From patchwork Tue Sep 8 16:59:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 249305 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4728710ilg; Tue, 8 Sep 2020 10:00:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwACsDlgGySA9NNj+R/VadJQeXAN6O/vHdIy/MoGBY8l5yZhgTl8HfWJU+8CwMDZuXOTFb+ X-Received: by 2002:a17:906:a1d7:: with SMTP id bx23mr27486294ejb.273.1599584420584; Tue, 08 Sep 2020 10:00:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599584420; cv=none; d=google.com; s=arc-20160816; b=C3DAl/P9ZaYDh4tb73So8IP/uNtSzozF46Fx+fjBC6USULviwAkKpAUhqz1/qIvoK+ bg4DPYOT8we2jJ2uITULlmsKh4lYmsaS/BqbGrILKuZjLefnc2GgpJm4EAhh0ynJ2rA3 oIiKgvbABGCA4FJAo6+XCpHx1nOzTbnSMDp+Uy6/pX9ABOgXOIqcljKKl9edV65SL8Fo C3sTqa0/42G7+ZfUz6zSuADzrsA95/yYYTEBxyZdO5eTcEH8DeX/3rbVncGZyWZaTxV1 mBhyrI3aaEViRLGn9KoPnEy7AQVDkcGCXe45rZ0TZ2LeaRBQU67WKoWuUnJeu7iwp3/Z qxUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=QZWuH3KY1sKtXDptWtQX4dYKsXnLQg4YPCavbKV70cg=; b=RqsMKNeZWvOCZeDEhk6WAboGZ8VigOuQ8q89OaL4NmpgHvCvUnvteWoytOQSRAMg4+ PuXUK6V13/dQ5E4SNedy4yojfmjIMMPJRp+b4SQkwWYdwe4KXTwSKG3QtGth7ZfPFZO4 Ss/NzOv/O6T/TLbIGl4I10hcancLfV0/jsllkjUWAPAEL+s5t8HYFp85AIz24Swhwq08 uqBSMQ8Qg1fF6aKlB7cISh0JNaqtWufz196pmP3tpG4fndWLsAFIHa15GXa5s/z8GbgK BgXPQEe+C/9FvjAhCmFbwiQD+ROhtXtR6GSw5LUI/vmmFZ1uLbiKzhZOIMA0S6S/dLw5 m52A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=R0j7oOiO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e3si12601357edj.131.2020.09.08.10.00.20; Tue, 08 Sep 2020 10:00:20 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=R0j7oOiO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731881AbgIHRAO (ORCPT + 6 others); Tue, 8 Sep 2020 13:00:14 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:47806 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731849AbgIHRAG (ORCPT ); Tue, 8 Sep 2020 13:00:06 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 088H032E003661; Tue, 8 Sep 2020 12:00:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599584403; bh=QZWuH3KY1sKtXDptWtQX4dYKsXnLQg4YPCavbKV70cg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=R0j7oOiOfAoeyB0UIzudIgJZHTQLHX+xtRRaWEcnlm/hbhdS/iE0prF/3nfi2MTfL YsRbuSqbgE0AYDsSmR69F0g1HGsVOphG2IfdJFByh20oNezTLqdE47+qxJ2SHo0Kkf qzLu7qdO9j7RBd+M/gORqsTYfCAIp3NiTNsV+dTg= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 088H02FC048821 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Sep 2020 12:00:03 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Sep 2020 12:00:01 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Sep 2020 12:00:01 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 088H00bs031667; Tue, 8 Sep 2020 12:00:01 -0500 From: Grygorii Strashko To: Peter Ujfalusi , Tero Kristo , Rob Herring , Nishanth Menon , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Grygorii Strashko Subject: [PATCH v2 1/4] arm64: dts: ti: k3-j7200: add DMA support Date: Tue, 8 Sep 2020 19:59:39 +0300 Message-ID: <20200908165942.32368-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908165942.32368-1-grygorii.strashko@ti.com> References: <20200908165942.32368-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Peter Ujfalusi Add the intr, inta, ringacc and udmap nodes for main and mcu NAVSS. Signed-off-by: Peter Ujfalusi Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 44 +++++++++++++ 2 files changed, 105 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 70c8f7e941fb..cc4ff380a7bc 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -45,6 +45,31 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id = <199>; + + main_navss_intr: interrupt-controller1 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <213>; + ti,interrupt-ranges = <0 64 64>, + <64 448 64>, + <128 672 64>; + }; + + main_udmass_inta: interrupt-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x0 0x33d00000 0x0 0x100000>; + interrupt-controller; + interrupt-parent = <&main_navss_intr>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <209>; + ti,interrupt-ranges = <0 0 256>; + }; secure_proxy_main: mailbox@32c00000 { compatible = "ti,am654-secure-proxy"; @@ -56,6 +81,42 @@ interrupt-names = "rx_011"; interrupts = ; }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <211>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <212>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; }; main_pmx0: pinmux@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 670e4c7cd9fe..9ecb7e0c9cf7 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -81,4 +81,48 @@ clocks = <&k3_clks 149 2>; clock-names = "fclk"; }; + + cbass_mcu_navss: navss@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + dma-ranges; + ti,sci-dev-id = <232>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <235>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <236>; + ti,ringacc = <&mcu_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; }; From patchwork Tue Sep 8 16:59:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 249308 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4730073ilg; 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[23.128.96.18]) by mx.google.com with ESMTP id d12si7341804ejj.237.2020.09.08.10.01.48; Tue, 08 Sep 2020 10:01:48 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ia4CnDqc; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731946AbgIHRAU (ORCPT + 6 others); Tue, 8 Sep 2020 13:00:20 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54858 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731843AbgIHRAM (ORCPT ); Tue, 8 Sep 2020 13:00:12 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 088H09L0044873; Tue, 8 Sep 2020 12:00:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599584409; bh=uXZMCP36lOtJZX1b2XkDr6j9kDkZTjkNJiSHuJFdBJs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ia4CnDqcIX6sj3iaKAVh5DGFks7W9LnxsOhJrTu0F3X6dN+t1BYeFG08uGCza96t4 I3wCJcfIysf03yF7SGTUH4hufmi7XHVQWnjJmf7tqCoaJQDvY6XagUkwFEbdDsOoS2 o5QFAnCTVu3raAUKaYutCOfcgxlrI/ZdSMCm9a1o= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 088H09iC115505; Tue, 8 Sep 2020 12:00:09 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Sep 2020 12:00:09 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Sep 2020 12:00:09 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 088H078A033059; Tue, 8 Sep 2020 12:00:08 -0500 From: Grygorii Strashko To: Peter Ujfalusi , Tero Kristo , Rob Herring , Nishanth Menon , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Grygorii Strashko Subject: [PATCH v2 2/4] arm64: dts: ti: k3-j7200-main: add main navss cpts node Date: Tue, 8 Sep 2020 19:59:40 +0300 Message-ID: <20200908165942.32368-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908165942.32368-1-grygorii.strashko@ti.com> References: <20200908165942.32368-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index cc4ff380a7bc..822c062e25c8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -117,6 +117,18 @@ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x310d0000 0x0 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 201 1>; + clock-names = "cpts"; + interrupts-extended = <&main_navss_intr 391>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; }; main_pmx0: pinmux@11c000 { From patchwork Tue Sep 8 16:59:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 249306 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4728795ilg; Tue, 8 Sep 2020 10:00:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwL6476OfbJqcekfsVMbHMEbAn2D5/sjNYEnKI+hMxB4f8+e1uXkOgxU0zlVDd4DPvJAfco X-Received: by 2002:aa7:dcc6:: with SMTP id w6mr15747972edu.10.1599584426501; Tue, 08 Sep 2020 10:00:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599584426; cv=none; d=google.com; s=arc-20160816; b=G1NMn2UdXnDYdAR5E3l4yoN45i/cnWpknRJS0kdNH2Eeu8N0pwjM/e+NgIvoK/F98/ Zw8scYDtmz3b9zkb4oVWyzlhZRlP860tJ7YzoGPWq8/Gj2+ecBXXYr7u04xMSMsE/XUn FcPMVfNM1uENab+j56To8WvzAwJ+M6uwpLFYa9/JjOb3McYulyev/eHCPKKKYdc+KsAH PrRK3w3NS1rfjHmIJKN1v8f33oAFIasEQ4aGes9cH7KyqlluvLZ1NATKGicXCrfzLHEl foLlPAGGaajJbA1tMDBqE1uPhHTmLOGVXg4+lvJKf3/uJRArAKtFnB4SIRgkVvcOBX1d /d6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=PKOejH6vx5nLOnIDQFUSZ/d82lIDZbEh+49+G1IcozA=; b=dV2n9WhjtdMkMQubcxF6bMwkNKZMh1du10Rc+oxfAJzrW0NhH3CZEa2As09NBZiJOO /yiwtv1o02C7GP5FbzLpfdB1YTau3AuZcNWNMxQTxbHfauqsWrcrHtU8pvNG/GKYJfvw HW2m/OcH4SX8Zm1dHpsZvvgC8y9e8khntEvDGkhi3cxLKXsG4zKe1yil+YxuJMOyOQAu 8UnVIJbXrMxaPxFGgTjOpb2TfXcKPLdrUN0cvhpDcWlUiLq4JUmlNQaZnGSD7c3dQAQG a419OZWRijdt3S7A6kdFuMQu8g1r9omCiNQQifoHykRKf0PTFqaNyb1vZsl5iCH/QUgT Rt4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=E8nFWq2A; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Grygorii Strashko --- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 9ecb7e0c9cf7..06cd6a80a499 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,20 @@ }; }; + mcu_conf: syscon@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + }; + chipid@43000014 { compatible = "ti,am654-chipid"; reg = <0x0 0x43000014 0x0 0x4>; @@ -125,4 +139,64 @@ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; }; From patchwork Tue Sep 8 16:59:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 249307 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4729656ilg; Tue, 8 Sep 2020 10:01:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzOhUl/mXzcWjn8MyeWmcC8lYyxRilF4CptpvvGtZyWd9yXAM1wy8L95oSfIW1E1btjPX6i X-Received: by 2002:a17:906:1484:: with SMTP id x4mr26364300ejc.81.1599584481457; Tue, 08 Sep 2020 10:01:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599584481; cv=none; d=google.com; s=arc-20160816; b=SAHvusDB7+nOWEDxc3djVuT09VoOHPlU5UFo4TVHe/i+KTKzFek8suY1XMuJc1FlXB xymQmT4hQ92w3EG3GDlYeugf/uOMmaQ0X12itQhy2x6VyzvotQtf1cCYhd9sSqlt+TL4 VXj6jd7FnDvWqbuZI1bX3fdnUKpw8ULYpmbFo2Plr72JD90E1xstZXilCYlTxpxFo57z d8O0fvaJb2xTYn5MOgSGuWa63tSCW0cW1JUyo1luhzGYU63RNS5OgfRWopvsEyyPPgrj 5rf36pM+VcPp+I4WtbZWr/OeBUV134hUq8AGKqn+1ti24M8dmIyHcAxss4AXCMsVRF7R fo1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=FmjuH099uiCn3rXvAwwFQmzrrjb4VVYs4/lLE60Nv/I=; b=BeyBd4sNuZeIP2spUoDYRlrmkQ7VeVxxbAd4Z7XnklA5/eJrint6szghXq5jh86eBm jrH3dDzMQRFmSH/zD2RLebJnHOKyjF2+Wvnm1M1RjQh71xCT5eZCGo5mhHUHFgKI/OUw 1I9wW6y14eZAtIKlDDc/8XhMmUOxilw4wUvnZtWfDIY/gYOHcx3Q4NoifgEsvmfq6KSN I/xjNyWBEH1rhruNApPYNBEvPU75juU+yB2VzNPb0kkh/5TJuY9ANFo2HjpMAK5dokiu ioOMY/qan/fdvluyxj6ZBWn9ny3XVzmjy4FCBBfFzIIDyctYcbmmfvO8BuzrBGa6EX8D yHdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wLd1vszn; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id by6si11778519edb.31.2020.09.08.10.01.21; Tue, 08 Sep 2020 10:01:21 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wLd1vszn; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731897AbgIHRBQ (ORCPT + 6 others); Tue, 8 Sep 2020 13:01:16 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54954 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731640AbgIHRAW (ORCPT ); Tue, 8 Sep 2020 13:00:22 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 088H0Jwn045048; Tue, 8 Sep 2020 12:00:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599584419; bh=FmjuH099uiCn3rXvAwwFQmzrrjb4VVYs4/lLE60Nv/I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wLd1vsznDaoSAfqoAKw5uf4m8BsVf2wTtxENbY85IvdHhy9iJwcg3Hv6Bepb7NXjl /uq8HIrmP1KPzWtr40fG/QeXFsDjLr5mZRkRAeBElplLmVZSlSTC95fq+qlZW54PGW OlLSd2PGepNC5PzLf0uOjXSNbszcjJBgo/qngars= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 088H0J4g082815 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Sep 2020 12:00:19 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Sep 2020 12:00:19 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Sep 2020 12:00:19 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 088H0Iwq112786; Tue, 8 Sep 2020 12:00:18 -0500 From: Grygorii Strashko To: Peter Ujfalusi , Tero Kristo , Rob Herring , Nishanth Menon , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Grygorii Strashko Subject: [PATCH v2 4/4] arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs Date: Tue, 8 Sep 2020 19:59:42 +0300 Message-ID: <20200908165942.32368-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908165942.32368-1-grygorii.strashko@ti.com> References: <20200908165942.32368-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko --- .../dts/ti/k3-j7200-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e27069317c4e..f7e6b9b5ef5f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include / { chosen { @@ -14,6 +15,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -62,3 +89,21 @@ /* UART not brought out */ status = "disabled"; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +};