From patchwork Sat Sep 26 13:02:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 292659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9170C47420 for ; Sat, 26 Sep 2020 13:02:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A1490206D4 for ; Sat, 26 Sep 2020 13:02:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VkaBAj6H" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728680AbgIZNCc (ORCPT ); Sat, 26 Sep 2020 09:02:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725208AbgIZNCb (ORCPT ); Sat, 26 Sep 2020 09:02:31 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58944C0613CE; Sat, 26 Sep 2020 06:02:31 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id k15so6823919wrn.10; Sat, 26 Sep 2020 06:02:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w1nHgSXiyRX1I7vLuG0jsc7c+HKkk/aWCdpprslY+FI=; b=VkaBAj6HCVaUKP50urEs6yPeDxX7uIvgYksBmrWBSf9BzZ++ZMTfyfarLfnIsyLsCb 44CrG7EiYZBQ2/xGWON0F5lrgmnOyywgWBx7FQSt3TYRFIzfE0HYZAfd9BCpI5ohcdi4 zcY6GmsVdGZQFbmu7kObSVTTC6Qk96iS7cND6BSWuFBpRBSLwBCsuPevadSQnNP5E+7Y vDct0w1C+3hU1EcRMJvZpscTPG3AET+pdtRJnVwKbi82mq1Xu1iEwpBE8vNa79vVxB2x tFXf5IlhjuLTR3UFZJwUiV0ghfwQN85AYLOc6iRMX1Pth3PINL0dQK/uzUZWzizBUwsi z90A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w1nHgSXiyRX1I7vLuG0jsc7c+HKkk/aWCdpprslY+FI=; b=kxLRbk9nyCucuFE2hC4uDKcf2fhbPbddNgppmzup7hR86dzoGTmlmAcHqp/A32kHrH /vNtEx7f3akiNYEtbGhd24SUsR4SBHG+zxQZryJbAgjFg/JaRj4YFcQTaplcWhidmssn aXwJAYdAVnFBuoH2oqwzJrCtCpmLXr3SP0qQtnNo2pKd4cADihIV1aCL5XVH26fWwy9t cd0CiZvVAdBUwS2jOhG1rlRy08UFPSc/PzKX27RzFsa0phC8CvEUIZmKJrUm0cA7EUH2 VI+Oadae6CjgELvIyYINp3HK2vLQXNwZKQr6lOwpqgiLPAaeg59dqSBN0JnjwwPCNsFy cOPw== X-Gm-Message-State: AOAM531BuTvGyMiMGN7upfdLvw0RgbQMgh36CrcSTmeadEak9G1EwjEa SH/ZH/r1hC5nAZj9Lmeak+Q= X-Google-Smtp-Source: ABdhPJwRRjjnq4BXKs+TCa/1HoKstgR181NpFmZ8bfn0I1tKyCsqL0sdiPihqYdoiED2L5VcZV3DZA== X-Received: by 2002:adf:f203:: with SMTP id p3mr9568911wro.339.1601125349876; Sat, 26 Sep 2020 06:02:29 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id f14sm7137738wrt.53.2020.09.26.06.02.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:02:29 -0700 (PDT) From: kholk11@gmail.com To: agross@kernel.org Cc: bjorn.andersson@linaro.org, sboyd@kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical Date: Sat, 26 Sep 2020 15:02:22 +0200 Message-Id: <20200926130225.13733-2-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130225.13733-1-kholk11@gmail.com> References: <20200926130225.13733-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Similarly to MSM8998, any access to the MMSS depends on this clock. Gating it will crash the system when RPMCC inits mmssnoc_axi_rpm_clk. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/qcom/gcc-sdm660.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index f0b47b7d50ca..93ac77628bec 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -1684,6 +1684,12 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_noc_cfg_ahb_clk", .ops = &clk_branch2_ops, + /* + * Any access to mmss depends on this clock. + * Gating this clock has been shown to crash the system + * when mmssnoc_axi_rpm_clk is inited in rpmcc. + */ + .flags = CLK_IS_CRITICAL, }, }, }; From patchwork Sat Sep 26 13:02:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 292658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0D08C4727E for ; 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Sat, 26 Sep 2020 06:02:30 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id f14sm7137738wrt.53.2020.09.26.06.02.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:02:30 -0700 (PDT) From: kholk11@gmail.com To: agross@kernel.org Cc: bjorn.andersson@linaro.org, sboyd@kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical Date: Sat, 26 Sep 2020 15:02:23 +0200 Message-Id: <20200926130225.13733-3-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130225.13733-1-kholk11@gmail.com> References: <20200926130225.13733-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno This clock is critical for any access to the GPU: gating it will crash the system when the GPU has been initialized (so, you cannot gate it unless you deinit the Adreno completely). So, to achieve a working state with GPU on, set the CLK_IS_CRITICAL flag to this clock. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/qcom/gcc-sdm660.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 93ac77628bec..7b1c8d1f6388 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -1571,6 +1571,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_cfg_ahb_clk", .ops = &clk_branch2_ops, + .flags = CLK_IS_CRITICAL, }, }, }; From patchwork Sat Sep 26 13:02:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 250059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E877C2D0A8 for ; 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Sat, 26 Sep 2020 06:02:31 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id f14sm7137738wrt.53.2020.09.26.06.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:02:31 -0700 (PDT) From: kholk11@gmail.com To: agross@kernel.org Cc: bjorn.andersson@linaro.org, sboyd@kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers Date: Sat, 26 Sep 2020 15:02:24 +0200 Message-Id: <20200926130225.13733-4-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130225.13733-1-kholk11@gmail.com> References: <20200926130225.13733-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno The function clk_gfx3d_determine_rate is selecting different PLLs to manage the GFX3D clock source in a special way: this one needs to be ping-pong'ed on different PLLs to ensure stability during frequency switching (set a PLL rate, let it stabilize, switch the RCG to the new PLL) and fast frequency transitions. This technique is currently being used in the MSM8996 SoC and the function was assuming that the parents were always at a specific index in the parents list, which is TRUE, if we use this only on the MSM8996 MMCC. Unfortunately, MSM8996 is not the only SoC that needs to ping-pong the graphics RCG, so choices are: 1. Make new special ops just to hardcode *again* other indexes, creating code duplication for (imo) no reason; or 2. Generalize this function, so that it becomes usable for a range of SoCs with slightly different ping-pong configuration. In this commit, the second road was taken: define a new "special" struct clk_rcg2_gfx3d, containing the ordered list of parents to ping-pong the graphics clock on, and the "regular" rcg2 clock structure in order to generalize the clk_gfx3d_determine_rate function and make it working for other SoCs. As for the function itself it is left with the assumption that we need to ping-pong over three parents. The reasons for this are: 1. The initial model was MSM8996, which has 3 parents for the graphics clock pingpong; 2. The other example that was taken into consideration is the SDM630/636/660 SoC gpu clock controller, which is ping-ponging over two dynamic clocked and one fixed clock PLL. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/qcom/clk-rcg.h | 9 ++++++ drivers/clk/qcom/clk-rcg2.c | 56 ++++++++++++++++++++++++------------- 2 files changed, 45 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 86d2b8b90173..99efcc7f8d88 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -153,6 +153,15 @@ struct clk_rcg2 { #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) +struct clk_rcg2_gfx3d { + u8 div; + struct clk_rcg2 rcg; + struct clk_hw **hws; +}; + +#define to_clk_rcg2_gfx3d(_hw) \ + container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg) + extern const struct clk_ops clk_rcg2_ops; extern const struct clk_ops clk_rcg2_floor_ops; extern const struct clk_ops clk_edp_pixel_ops; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 357159fe85b5..cebdacc188aa 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -728,40 +728,49 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_rate_request parent_req = { }; - struct clk_hw *p2, *p8, *p9, *xo; - unsigned long p9_rate; + struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw); + struct clk_hw *xo; + unsigned long request, p0_rate; int ret; + /* + * This function does ping-pong the RCG between PLLs: if we don't + * have at least one fixed PLL and two variable ones, + * then it's not going to work correctly. + */ + if (unlikely(cgfx->hws[0] == NULL || cgfx->hws[1] == NULL || + cgfx->hws[2] == NULL)) + return -EINVAL; + xo = clk_hw_get_parent_by_index(hw, 0); if (req->rate == clk_hw_get_rate(xo)) { req->best_parent_hw = xo; return 0; } - p9 = clk_hw_get_parent_by_index(hw, 2); - p2 = clk_hw_get_parent_by_index(hw, 3); - p8 = clk_hw_get_parent_by_index(hw, 4); + request = req->rate; + if (cgfx->div > 1) + parent_req.rate = request = request * cgfx->div; - /* PLL9 is a fixed rate PLL */ - p9_rate = clk_hw_get_rate(p9); + /* This has to be a fixed rate PLL */ + p0_rate = clk_hw_get_rate(cgfx->hws[0]); - parent_req.rate = req->rate = min(req->rate, p9_rate); - if (req->rate == p9_rate) { - req->rate = req->best_parent_rate = p9_rate; - req->best_parent_hw = p9; + if (request == p0_rate) { + req->rate = req->best_parent_rate = p0_rate; + req->best_parent_hw = cgfx->hws[0]; return 0; } - if (req->best_parent_hw == p9) { + if (req->best_parent_hw == cgfx->hws[0]) { /* Are we going back to a previously used rate? */ - if (clk_hw_get_rate(p8) == req->rate) - req->best_parent_hw = p8; + if (clk_hw_get_rate(cgfx->hws[2]) == request) + req->best_parent_hw = cgfx->hws[2]; else - req->best_parent_hw = p2; - } else if (req->best_parent_hw == p8) { - req->best_parent_hw = p2; + req->best_parent_hw = cgfx->hws[1]; + } else if (req->best_parent_hw == cgfx->hws[2]) { + req->best_parent_hw = cgfx->hws[1]; } else { - req->best_parent_hw = p8; + req->best_parent_hw = cgfx->hws[2]; } ret = __clk_determine_rate(req->best_parent_hw, &parent_req); @@ -770,18 +779,25 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw, req->rate = req->best_parent_rate = parent_req.rate; + if (cgfx->div > 1) + do_div(req->rate, cgfx->div); + return 0; } static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index) { - struct clk_rcg2 *rcg = to_clk_rcg2(hw); + struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw); + struct clk_rcg2 *rcg = &cgfx->rcg; u32 cfg; int ret; - /* Just mux it, we don't use the division or m/n hardware */ cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; + /* On some targets, the GFX3D RCG may need to divide PLL frequency */ + if (cgfx->div > 1) + cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT; + ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); if (ret) return ret; From patchwork Sat Sep 26 13:02:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 250058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65B69C47420 for ; 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Sat, 26 Sep 2020 06:02:32 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id f14sm7137738wrt.53.2020.09.26.06.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:02:32 -0700 (PDT) From: kholk11@gmail.com To: agross@kernel.org Cc: bjorn.andersson@linaro.org, sboyd@kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d Date: Sat, 26 Sep 2020 15:02:25 +0200 Message-Id: <20200926130225.13733-5-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130225.13733-1-kholk11@gmail.com> References: <20200926130225.13733-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno In commit 8c5dc88b064d the gfx3d ping-pong ops (clk_gfx3d_ops) were generalized in order to be able to reuse the same ops for more than just one clock for one SoC: follow the change here in the MSM8996 MMCC. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/qcom/mmcc-msm8996.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 3b3aac07fb2d..24843e4f2599 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -528,16 +528,23 @@ static struct clk_rcg2 maxi_clk_src = { }, }; -static struct clk_rcg2 gfx3d_clk_src = { - .cmd_rcgr = 0x4000, - .hid_width = 5, - .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gfx3d_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, - .num_parents = 6, - .ops = &clk_gfx3d_ops, - .flags = CLK_SET_RATE_PARENT, +static struct clk_rcg2_gfx3d gfx3d_clk_src = { + .rcg = { + .cmd_rcgr = 0x4000, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gfx3d_clk_src", + .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, + .num_parents = 6, + .ops = &clk_gfx3d_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, + .hws = (struct clk_hw*[]) { + &mmpll9.clkr.hw, + &mmpll2.clkr.hw, + &mmpll8.clkr.hw }, }; @@ -3089,7 +3096,7 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { [AHB_CLK_SRC] = &ahb_clk_src.clkr, [AXI_CLK_SRC] = &axi_clk_src.clkr, [MAXI_CLK_SRC] = &maxi_clk_src.clkr, - [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, + [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr, [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, [ISENSE_CLK_SRC] = &isense_clk_src.clkr, [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,