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Wed, 11 Oct 2017 10:25:20 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 1/5] clk: samsung: Instantiate Exynos4412 ISP clocks only when available Date: Wed, 11 Oct 2017 11:25:11 +0200 Message-id: <20171011092515.1698-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171011092515.1698-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBIsWRmVeSWpSXmKPExsWy7djP87qNj+9GGuzs4rHYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mrf/nMBWcUqw41LibrYHxuEwXIyeHhICJxP6tC5ggbDGJC/fWs3UxcnEI CSxllLj5t4MFwvnMKPGx7z8bTMfv83vBbCGBZYwSZ/pkIIoamCQu3DnECpJgEzCU6HrbBVYk IuAg8fnTa0aQImaBNiaJswf2g+0TFoiVWPp3JVgRi4CqxLFJDewgNq+AjcT926/YIbbJS7xf cJ8RxOYUsJV49aIN7D4JgQ42iZNfVrFCFLlIrJh5E+o8YYlXx7dANctIXJ7czQJh9zNKNLVq Q9gzGCXOveWFsK0lDh+/CDaHWYBPYtK26cxdjBxAcV6JjjYhiBIPiT8NS6DGOEocuraLBeL7 CYwSKx/aTGCUXsDIsIpRJLW0ODc9tdhYrzgxt7g0L10vOT93EyMwPk//O/5pB+PXE1aHGAU4 GJV4eC/U340UYk0sK67MPcQowcGsJMJ77gZQiDclsbIqtSg/vqg0J7X4EKM0B4uSOK9tVFuk kEB6YklqdmpqQWoRTJaJg1OqgTE6rf3Ajf3mJ75mzMq86n1UxXHPkU1KAfahc7h+xf+Y9VJz WlSDj1jNia0PXHdtdD6kt/Wu/ofld3NvtuVFJxU0tOSfP59/aMfr9l29RafmX+p5bMN+qpOD 15I1Yp3Z02yH7wc5J5pcfbPQOH29TkSizM/LrN8rZT4+N9Mz/xpQyZi/ZOU0QWclluKMREMt 5qLiRACSo+nnywIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnluLIzCtJLcpLzFFi42I5/e/4Nd2Gx3cjDbY/NbDYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mrf/nMBWcUqw41LibrYHxuEwXIyeHhICJxO/ze9kgbDGJC/fWA9lcHEIC SxglblyfywzhNDFJLN54kwWkik3AUKLrbRdYh4iAg8TnT68ZQYqYBTqYJPbsfQiWEBaIlVj6 dyWYzSKgKnFsUgM7iM0rYCNx//Yrdoh18hLvF9xnBLE5BWwlXr1oA6sXAqp5vm0b2wRG3gWM DKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECg2nbsZ9bdjB2vQs+xCjAwajEwytw/U6kEGti WXFl7iFGCQ5mJRHeczfuRgrxpiRWVqUW5ccXleakFh9ilOZgURLn7d2zOlJIID2xJDU7NbUg tQgmy8TBKdXAOHnaWYdKK+fZ/hFmVYInrs6y/7pkQVBsfJHNtybNpBVym8y2fnqZXaZsd9N1 /qkNgjvabN5/fdzwZsXZ/zbt81nurthxlUk68dUqlbB8iTt5dambOpuyp8jzKu6/cFTjwC7+ KadXzHi+fGe0j4NUwmOPj9fqufiX/epib81ibQnmSDmoPUPmjRJLcUaioRZzUXEiACttcXci AgAA X-CMS-MailID: 20171011092520eucas1p2a86dcd52a7c0c4b329563e5eaad3fd76 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171011092520eucas1p2a86dcd52a7c0c4b329563e5eaad3fd76 X-RootMTR: 20171011092520eucas1p2a86dcd52a7c0c4b329563e5eaad3fd76 References: <20171011092515.1698-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Istatiate those clocks only when provided clock registers resource covers those registers. This is a preparation for adding a separate clock driver for ISP clocks, which will be intergated with power domain using runtime PM feature. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..bdd68247e054 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -822,6 +822,12 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), + DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), + DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), + DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), +}; + +static struct samsung_div_clock exynos4x12_isp_div_clks[] = { DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, @@ -831,9 +837,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { 4, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3, CLK_GET_RATE_NOCACHE, 0), - DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), - DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), - DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), }; /* list of gate clocks supported in all exynos4 soc's */ @@ -1132,6 +1135,13 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 0, 0), GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 0, 0), + GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), + GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), + GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, + 0), +}; + +static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, @@ -1184,10 +1194,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), - GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), - GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, - 0), }; static const struct samsung_clock_alias exynos4_aliases[] __initconst = { @@ -1522,6 +1528,8 @@ static void __init exynos4_clk_init(struct device_node *np, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { + struct resource res; + samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); samsung_clk_register_div(ctx, exynos4x12_div_clks, @@ -1533,6 +1541,15 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_fixed_factor(ctx, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); + + of_address_to_resource(np, 0, &res); + if (resource_size(&res) > 0x18000) { + samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, + ARRAY_SIZE(exynos4x12_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, + ARRAY_SIZE(exynos4x12_isp_gate_clks)); + } + if (of_machine_is_compatible("samsung,exynos4412")) { exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, From patchwork Wed Oct 11 09:25:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 115526 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp531568qgn; Wed, 11 Oct 2017 02:25:29 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCxzFoe0xmmIllxEDUw2306fA8O8R3t2f3RoIfyVUrYxJFFkDYOt0JBs4LDNQa38le9jXTK X-Received: by 10.101.81.198 with SMTP id i6mr14911722pgq.228.1507713929281; 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Wed, 11 Oct 2017 10:25:21 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 3/5] clk: samsung: Add a separate driver for Exynos4412 ISP clocks Date: Wed, 11 Oct 2017 11:25:13 +0200 Message-id: <20171011092515.1698-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171011092515.1698-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOIsWRmVeSWpSXmKPExsWy7djP87pNj+9GGjy4zWKxccZ6VovrX56z Wky6P4HF4vz5DewWH3vusVrMOL+PyWLtkbvsFofftLM6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZq2a+Zyn4altx5+cytgbGCyZdjBwcEgImElPaOLoYOYFMMYkL99azdTFy cQgJLGWUmNh4hQXC+cwose/wWzaIKhOJ6w3LWEFsIYFljBKbn5dAFDUwSbz6dZQJJMEmYCjR 9bYLrEFEwEHi86fXjCBFzAJtTBJnD+wHKxIWCJfY9nIBmM0ioCpxu2slO4jNK2Aj0byonxli m7zE+wX3GUFsTgFbiVcv2qCu6GGTOH5aGcJ2kZgx7wsLhC0s8er4FnYIW0bi8uRuqHg/o0RT qzaEPYNR4txbXgjbWuLw8Ytg3zAL8ElM2jadGRIsvBIdbUIQJR4SDx8vYISwHSU+ntzPDPHw BEaJZfcOMU9glF7AyLCKUSS1tDg3PbXYRK84Mbe4NC9dLzk/dxMjMDpP/zv+ZQfj4mNWhxgF OBiVeHgFrt+JFGJNLCuuzD3EKMHBrCTCe+7G3Ugh3pTEyqrUovz4otKc1OJDjNIcLErivLZR bZFCAumJJanZqakFqUUwWSYOTqkGRla52VveZ5xQlK6tDrdyfqP3rbWQUW1O1RKdcNf0zdeX vkn7kr3/AufP54ENekJdRxSl2d/ylp1zEFAJc2d2trxtduIXv3LU1/7lV9sKn7GuWBvptLBd 893VxIfLzm3TPvx2Vtib+1/XR165v9XnjImMj8KRmwtWtdV0ZSU9TgpPXepol/f6qRJLcUai oRZzUXEiADuxo3LKAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjluLIzCtJLcpLzFFi42I5/e/4Nd3Gx3cjDeauVbPYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MVTPfsxR8ta2483MZWwPjBZMuRk4OCQETiesNy1ghbDGJC/fWs3UxcnEI CSxhlDh8aQGU08QksfLPBmaQKjYBQ4mut11sILaIgIPE50+vGUGKmAU6mCT27H0IlODgEBYI lzhyLwSkhkVAVeJ210p2EJtXwEaieVE/M8Q2eYn3C+4zgticArYSr160gc0UAqp5vm0b2wRG 3gWMDKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECQ2nbsZ9bdjB2vQs+xCjAwajEwytw/U6k EGtiWXFl7iFGCQ5mJRHeczfuRgrxpiRWVqUW5ccXleakFh9ilOZgURLn7d2zOlJIID2xJDU7 NbUgtQgmy8TBKdXAKHF+zbrdpw3Kz2w6zNR/XUTKx/9t25+O5a3Ti5Q45s1T6Oz1OMPlnrfF zOXdhnzVe/9KuOVnVjyTbBafGXXU8xnnzJ67cVddn+cLbDJ5ljmhYtn07Ye4S+L+Ll5q82/m gtR3BgmuB79YbVh630c/nOHTF9bZBWcUL/AxyBx5bTMxruityPEtiUosxRmJhlrMRcWJAKMP 5rMhAgAA X-CMS-MailID: 20171011092521eucas1p29aeadc2a63aea49b985b6827022a1b09 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171011092521eucas1p29aeadc2a63aea49b985b6827022a1b09 X-RootMTR: 20171011092521eucas1p29aeadc2a63aea49b985b6827022a1b09 References: <20171011092515.1698-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Because those registers are also located in a different memory region than the main clock controller, support for them can be provided by a separate clock controller. This in turn allows to almost seamlessly make it aware of the power domain using recently introduced runtime PM support for clocks. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos4412-isp.c | 179 +++++++++++++++++++++++++++++++ 2 files changed, 180 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos4412-isp.c -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 7afc21dc374e..8a67a3bb6803 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o +obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4412-isp.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c new file mode 100644 index 000000000000..d5f1ccb36300 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos4412-isp.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * Author: Marek Szyprowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos4412 ISP module. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +/* Exynos4x12 specific registers, which belong to ISP power domain */ +#define E4X12_DIV_ISP0 0x0300 +#define E4X12_DIV_ISP1 0x0304 +#define E4X12_GATE_ISP0 0x0800 +#define E4X12_GATE_ISP1 0x0804 + +/* + * Support for CMU save/restore across system suspends + */ +static struct samsung_clk_reg_dump *exynos4x12_save_isp; + +static const unsigned long exynos4x12_clk_isp_save[] __initconst = { + E4X12_DIV_ISP0, + E4X12_DIV_ISP1, + E4X12_GATE_ISP0, + E4X12_GATE_ISP1, +}; + +PNAME(mout_user_aclk400_mcuisp_p4x12) = { "fin_pll", "div_aclk400_mcuisp", }; + +static struct samsung_div_clock exynos4x12_isp_div_clks[] = { + DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3), + DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3), + DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", + E4X12_DIV_ISP1, 4, 3), + DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", + E4X12_DIV_ISP1, 8, 3), + DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), +}; + +static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { + GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0), + GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0), + GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0), + GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0), + GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0), + GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0), + GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0), + GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0), + GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0), + GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0), + GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, + 0, 0), + GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, + 0, 0), + GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, + 0, 0), + GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, + 0, 0), + GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, + 0, 0), + GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, + 0, 0), + GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, + 0, 0), + GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, + 0, 0), + GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, + 0, 0), + GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0), + GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0), + GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, + 0, 0), + GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, + 0, 0), + GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, + 0, 0), + GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, + 0, 0), + GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, + 0, 0), +}; + +static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev) +{ + struct samsung_clk_provider *ctx = dev_get_drvdata(dev); + + samsung_clk_save(ctx->reg_base, exynos4x12_save_isp, + ARRAY_SIZE(exynos4x12_clk_isp_save)); + return 0; +} + +static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev) +{ + struct samsung_clk_provider *ctx = dev_get_drvdata(dev); + + samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp, + ARRAY_SIZE(exynos4x12_clk_isp_save)); + return 0; +} + +static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev) +{ + struct samsung_clk_provider *ctx; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct resource *res; + void __iomem *reg_base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(reg_base)) { + dev_err(dev, "failed to map registers\n"); + return PTR_ERR(reg_base); + } + + exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save, + ARRAY_SIZE(exynos4x12_clk_isp_save)); + if (!exynos4x12_save_isp) + return -ENOMEM; + + ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS); + ctx->dev = dev; + + platform_set_drvdata(pdev, ctx); + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, + ARRAY_SIZE(exynos4x12_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, + ARRAY_SIZE(exynos4x12_isp_gate_clks)); + + samsung_clk_of_add_provider(np, ctx); + pm_runtime_put(dev); + + return 0; +} + +static const struct of_device_id exynos4x12_isp_clk_of_match[] = { + { .compatible = "samsung,exynos4412-isp-clock", }, + { }, +}; + +static const struct dev_pm_ops exynos4x12_isp_pm_ops = { + SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend, + exynos4x12_isp_clk_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver exynos4x12_isp_clk_driver __refdata = { + .driver = { + .name = "exynos4x12-isp-clk", + .of_match_table = exynos4x12_isp_clk_of_match, + .suppress_bind_attrs = true, + .pm = &exynos4x12_isp_pm_ops, + }, + .probe = exynos4x12_isp_clk_probe, +}; + +static int __init exynos4x12_isp_clk_init(void) +{ + return platform_driver_register(&exynos4x12_isp_clk_driver); +} +core_initcall(exynos4x12_isp_clk_init); From patchwork Wed Oct 11 09:25:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 115529 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp531643qgn; Wed, 11 Oct 2017 02:25:34 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDsQHdHz3eiYRvLtXgJHAAQuMW35JqDm5O11egTkDXPYbTpgmhsc2XaGRDm6+CS0yQoJCF/ X-Received: by 10.84.194.226 with SMTP id h89mr15001716pld.54.1507713934405; Wed, 11 Oct 2017 02:25:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507713934; cv=none; d=google.com; s=arc-20160816; b=RNukBzbTBugIGVkzX5j0rxg/NSw8MqJQ8Dg7BcxWYNylx2WxipQmotwWUGnByPExBD n/fBNZvar/kjFMOE4mKIGQAugQ5r/is+VZMod58J7G+L1bU23QlCw07QggRmQuL4KylG hNrWyfo0Luf06uC45fefFh4YD2664yeId24zvZoQrEVrpV3feLX3sgJn0ZGOgBoUnBKP yzP4wkKFEYyyPGISlnDQaSjoampyfIsFcGB1dm/RIs/o3f+Y8o9OzI5rsJH0RAMNfCaU fWENMH5gsAWuODNftjRPis3IhMFSm94fcBdGrca8rba6fQxgYAJrx3TpYfBmGDPKiq6p rx3A== ARC-Message-Signature: i=1; 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Wed, 11 Oct 2017 10:25:22 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 4/5] ARM: dts: exynos: Add Exynos4412 ISP clock controller Date: Wed, 11 Oct 2017 11:25:14 +0200 Message-id: <20171011092515.1698-5-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171011092515.1698-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRmVeSWpSXmKPExsWy7djPc7pNj+9GGvQ/l7HYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mp6f+Mhcc1avYs7yDpYFxjkoXIyeHhICJxO/1V5ggbDGJC/fWs3UxcnEI CSxjlPi09xczhPOZUWLTo5UsMB1Pjr1mhas6deo0O4TTwCTx48sGVpAqNgFDia63XWwgtoiA g8TnT68ZQYqYBdqYJM4e2A+0kINDWMBf4sx+dZAaFgFVib9NW8E28ArYSFzbcI0RYpu8xPsF 98FsTgFbiVcv2sDukxDoYZP41TMJqshFomvVZqgnhCVeHd/CDmHLSHR2HISK9zNKNLVqQ9gz GCXOveWFsK0lDh+/CHY0swCfxKRt05lBbpMQ4JXoaBOCKPGQWH/lKBuE7Shx6vFVRoiHJzBK LFx7iHkCo/QCRoZVjCKppcW56anFhnrFibnFpXnpesn5uZsYgRF6+t/x9zsYnzaHHGIU4GBU 4uEVuH4nUog1say4MvcQowQHs5II77kbdyOFeFMSK6tSi/Lji0pzUosPMUpzsCiJ89pGtUUK CaQnlqRmp6YWpBbBZJk4OKUaGEXNu4Kff5QvFPe50sF3l93L139ma1rrzGpJo4Su2xxZ5nnf z2z5dCxr0xz5K3deb3qhepmbdXKdcZ/cK1P+4/e0ZS/OFlzlMC/p+9/1K+3i9rarBMV+yEou Fer5UXl02jNO71fHpp9u9TBZvZlPXv8fxzKnJW4iP7czHo+QcX4kcn2upuY0QyWW4oxEQy3m ouJEAGW2EafMAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnluLIzCtJLcpLzFFi42I5/e/4Nd2mx3cjDeZvZbLYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mp6f+Mhcc1avYs7yDpYFxjkoXIyeHhICJxJNjr1khbDGJC/fWs3UxcnEI CSxhlHjQ9RHKaWKSWPPyHQtIFZuAoUTX2y42EFtEwEHi86fXjCBFzAIdTBJ79j4ESwgL+Eps ubOcGcRmEVCV+Nu0FayZV8BG4tqGa4wQ6+Ql3i+4D2ZzCthKvHrRBtYrBFTzfNs2tgmMvAsY GVYxiqSWFuem5xYb6hUn5haX5qXrJefnbmIEBtO2Yz8372C8tDH4EKMAB6MSD6/A9TuRQqyJ ZcWVuYcYJTiYlUR4z924GynEm5JYWZValB9fVJqTWnyIUZqDRUmct3fP6kghgfTEktTs1NSC 1CKYLBMHp1QDY960g+0tabEyjjOW5Dx2eMN+/TizkQbrDYsJR0OL83WkTwasbN5ednqtz6wq kaU1notjWNTy/968vM9tmuUsJeOWyiTBR//K7rG+uXjhprdKBpfjY7ftc89pvsvRPHjpl1Dw 48sfbvPOElJXXnr7/h73E1c0tpz2Zb1fbRV6ks+u//yRNYvTFymxFGckGmoxFxUnAgC2LoRE IgIAAA== X-CMS-MailID: 20171011092522eucas1p13c442dd9daa51e610618b39ee436e100 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171011092522eucas1p13c442dd9daa51e610618b39ee436e100 X-RootMTR: 20171011092522eucas1p13c442dd9daa51e610618b39ee436e100 References: <20171011092515.1698-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos4412 ISP clock controller is located in the SOC area, which belongs to ISP power domain. This patch instantiates a separate clock driver for those clocks, updates all clients of ISP clocks and ensures that the driver is properly integrated in ISP power domin. This finally solves all the mysterious freezes in accessing ISP clocks when ISP power domain is disabled. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos4412.dtsi | 71 ++++++++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 27 deletions(-) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7ff03a7e8fb9..2a2f1e596672 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -191,10 +191,19 @@ clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x20000>; + reg = <0x10030000 0x18000>; #clock-cells = <1>; }; + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; @@ -257,7 +266,7 @@ reg = <0x12390000 0x1000>; interrupts = ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite0>; status = "disabled"; @@ -268,7 +277,7 @@ reg = <0x123A0000 0x1000>; interrupts = ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite1>; status = "disabled"; @@ -280,29 +289,35 @@ interrupts = , ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>, - <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, - <&clock CLK_PPMUISPMX>, + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, - <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, - <&clock CLK_PWM_ISP>, - <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, - <&clock CLK_DIV_MCUISP0>, - <&clock CLK_DIV_MCUISP1>, - <&clock CLK_UART_ISP_SCLK>, - <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, + <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK400_MCUISP>; + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "mpll", "isp", + "ppmuispmx", "isp", "drc", "fd", "mcuisp", "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "uart", "aclk200", - "div_aclk200", "aclk400mcuisp", - "div_aclk400mcuisp"; + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; iommu-names = "isp", "drc", "fd", "mcuctl"; @@ -318,7 +333,7 @@ i2c1_isp: i2c-isp@12140000 { compatible = "samsung,exynos4212-i2c-isp"; reg = <0x12140000 0x100>; - clocks = <&clock CLK_I2C1_ISP>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; clock-names = "i2c_isp"; #address-cells = <1>; #size-cells = <0>; @@ -355,7 +370,7 @@ interrupts = <16 2>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISP>; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; #iommu-cells = <0>; }; @@ -366,7 +381,7 @@ interrupts = <16 3>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_DRC>; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; #iommu-cells = <0>; }; @@ -377,7 +392,7 @@ interrupts = <16 4>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FD>; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; #iommu-cells = <0>; }; @@ -388,7 +403,7 @@ interrupts = <16 5>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISPCX>; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; #iommu-cells = <0>; }; @@ -399,7 +414,8 @@ interrupts = <16 0>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; #iommu-cells = <0>; }; @@ -410,7 +426,8 @@ interrupts = <16 1>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; #iommu-cells = <0>; }; From patchwork Wed Oct 11 09:25:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 115531 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp531695qgn; Wed, 11 Oct 2017 02:25:37 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBC/wGwKLOtWQB3Blb87CbDeejzhLabhttW5+Slb8ETfY2IpXyK8gyxwVh4n/woIUqPV4ur X-Received: by 10.159.234.10 with SMTP id be10mr3080214plb.386.1507713937168; Wed, 11 Oct 2017 02:25:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507713937; cv=none; d=google.com; s=arc-20160816; b=iWDwAIQK9WacpldtaxdU8tmnAfcHvXbCq81DPgL787+6j8iK1VbsjeO6cZIuQU8sde UmewJH+lK2ihGXcqTh3lbaN8TLaniB247ACZ/wJRHsz6g0cRNWDP7lJDH95EmDvl9DdH pVZP/+lGya7dPwmOP1RR6qW66czRK7U0EMtW/O32qUf0CKsoHZxFR7pY9UAjUYy7fsru pFbF5DUk+kfc808SNF97vQklLIr1vS0z3pw2eD0hGDRK0j/Yl/fx9UWXt1Ki/rBmcUoB X90oBeWKTJLYq9B855GKK8qCfcHC01vHbOgraweJhvJFSPPgtevDWALiWaghHsOM15UF 1ieA== ARC-Message-Signature: i=1; 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Wed, 11 Oct 2017 10:25:22 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 5/5] clk: samsung: Remove obsolete code for Exynos4412 ISP clocks Date: Wed, 11 Oct 2017 11:25:15 +0200 Message-id: <20171011092515.1698-6-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171011092515.1698-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsWy7djP87pNj+9GGhz9bGqxccZ6VovrX56z Wky6P4HF4vz5DewWH3vusVrMOL+PyWLtkbvsFofftLM6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZfVMamQuOOlVMen6IvYHxrEUXIyeHhICJxJ3vF1kgbDGJC/fWs3UxcnEI CSxllLj89yg7hPOZUWLNkhlsMB0nHzQzQSSWMUrMa3vODOE0MEn8+LKBFaSKTcBQouttF1iH iICDxOdPrxlBipgF2pgkzh7YzwSSEBYIk1hyeTXYchYBVYkPx56CNfAK2Ej8OruTGWKdvMT7 BfcZQWxOAVuJVy/awA6UEOhgk/jzcRUrRJGLxN4bqxghbGGJV8e3sEPYMhKXJ3dDfdfPKNHU qg1hz2CUOPeWF8K2ljh8/CLYHGYBPolJ26YDLeYAivNKdLQJQZR4SLzZcAzqHkeJ59uvMEJ8 PIFR4vjHQ2wTGKUXMDKsYhRJLS3OTU8tNtErTswtLs1L10vOz93ECIzR0/+Of9nBuPiY1SFG AQ5GJR5eget3IoVYE8uKK3MPMUpwMCuJ8J67cTdSiDclsbIqtSg/vqg0J7X4EKM0B4uSOK9t VFukkEB6YklqdmpqQWoRTJaJg1OqgbGrdCfPRtuS1XknjQr7uHONXmf0STpq/AlZYuh38O3v iBfagS8V5lwo2vj6RcmWzCMJ2ZGvHL7VR/pUyq5s4+P23DW5a1XYkmuM/Xkxt1P6nafvuP1c mDut/0vVvU+7KlNVJKfqmMjWlgucTH4o8pCvZ9nZbz9jFslMj1DRWhpgqOShlaT1RYmlOCPR UIu5qDgRAPBr6x7NAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnluLIzCtJLcpLzFFi42I5/e/4Nd2mx3cjDbZMlrbYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MvimNzAVHnSomPT/E3sB41qKLkZNDQsBE4uSDZiYIW0ziwr31bF2MXBxC AksYJfbcfM8I4TQxSax5+Y4FpIpNwFCi620XG4gtIuAg8fnTa7AiZoEOJok9ex+CJYQFwiQ+ /fwINpZFQFXiw7GnYHFeARuJX2d3MkOsk5d4v+A+I4jNKWAr8epFG1iNEFDN823b2CYw8i5g ZFjFKJJaWpybnltspFecmFtcmpeul5yfu4kRGEzbjv3csoOx613wIUYBDkYlHl6B63cihVgT y4orcw8xSnAwK4nwnrtxN1KINyWxsiq1KD++qDQntfgQozQHi5I4b++e1ZFCAumJJanZqakF qUUwWSYOTqkGxpk2BjaCqRFxh5ov8ZdE3zDUVq5+HjDPRaVmZ/1NdjenLT+W6XqsnXK1+3p+ dMy/DvcNfMILi3e6nM7gtv3Xz/KoWmTHweP5/W1lx542cZy4Exm0+cjZuYvO7Oz7ctngxOQf 1x2k5V7M7lr8K3DGwaeT5qi3C7lEHg8snVh5MqvqxqvbnFeckpVYijMSDbWYi4oTAYzs+FAi AgAA X-CMS-MailID: 20171011092522eucas1p2804557c3fa5b2314911ac6038b3fccd1 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171011092522eucas1p2804557c3fa5b2314911ac6038b3fccd1 X-RootMTR: 20171011092522eucas1p2804557c3fa5b2314911ac6038b3fccd1 References: <20171011092515.1698-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock driver, so support for them in Exynos4-clk driver can be removed. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 81 ------------------------------------- include/dt-bindings/clock/exynos4.h | 30 -------------- 2 files changed, 111 deletions(-) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index bdd68247e054..69649dc6a9cf 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -123,10 +123,6 @@ #define CLKOUT_CMU_CPU 0x14a00 #define PWR_CTRL1 0x15020 #define E4X12_PWR_CTRL2 0x15024 -#define E4X12_DIV_ISP0 0x18300 -#define E4X12_DIV_ISP1 0x18304 -#define E4X12_GATE_ISP0 0x18800 -#define E4X12_GATE_ISP1 0x18804 /* Below definitions are used for PWR_CTRL settings */ #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) @@ -827,18 +823,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), }; -static struct samsung_div_clock exynos4x12_isp_div_clks[] = { - DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, - CLK_GET_RATE_NOCACHE, 0), - DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, - CLK_GET_RATE_NOCACHE, 0), - DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), - DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, - 4, 3, CLK_GET_RATE_NOCACHE, 0), - DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, - 8, 3, CLK_GET_RATE_NOCACHE, 0), -}; - /* list of gate clocks supported in all exynos4 soc's */ static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { /* @@ -1141,61 +1125,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 0), }; -static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { - GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), -}; - static const struct samsung_clock_alias exynos4_aliases[] __initconst = { ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), ALIAS(CLK_ARM_CLK, NULL, "armclk"), @@ -1528,8 +1457,6 @@ static void __init exynos4_clk_init(struct device_node *np, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { - struct resource res; - samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); samsung_clk_register_div(ctx, exynos4x12_div_clks, @@ -1542,14 +1469,6 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); - of_address_to_resource(np, 0, &res); - if (resource_size(&res) > 0x18000) { - samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, - ARRAY_SIZE(exynos4x12_isp_div_clks)); - samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, - ARRAY_SIZE(exynos4x12_isp_gate_clks)); - } - if (of_machine_is_compatible("samsung,exynos4412")) { exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index e9f9d400c322..f59ea85d77bd 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -190,32 +190,6 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 -#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ -#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ -#define CLK_PPMUISPX 355 /* Exynos4x12 only */ -#define CLK_PPMUISPMX 356 /* Exynos4x12 only */ -#define CLK_FIMC_ISP 357 /* Exynos4x12 only */ -#define CLK_FIMC_DRC 358 /* Exynos4x12 only */ -#define CLK_FIMC_FD 359 /* Exynos4x12 only */ -#define CLK_MCUISP 360 /* Exynos4x12 only */ -#define CLK_GICISP 361 /* Exynos4x12 only */ -#define CLK_SMMU_ISP 362 /* Exynos4x12 only */ -#define CLK_SMMU_DRC 363 /* Exynos4x12 only */ -#define CLK_SMMU_FD 364 /* Exynos4x12 only */ -#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ -#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ -#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ -#define CLK_MPWM_ISP 368 /* Exynos4x12 only */ -#define CLK_I2C0_ISP 369 /* Exynos4x12 only */ -#define CLK_I2C1_ISP 370 /* Exynos4x12 only */ -#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ -#define CLK_PWM_ISP 372 /* Exynos4x12 only */ -#define CLK_WDT_ISP 373 /* Exynos4x12 only */ -#define CLK_UART_ISP 374 /* Exynos4x12 only */ -#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ -#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ -#define CLK_SPI0_ISP 377 /* Exynos4x12 only */ -#define CLK_SPI1_ISP 378 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ @@ -257,10 +231,6 @@ #define CLK_PPMUACP 415 /* div clocks */ -#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ -#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ #define CLK_DIV_ACP 456