From patchwork Fri Sep 18 06:29:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 250175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94448C43466 for ; Fri, 18 Sep 2020 06:30:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5DF1921734 for ; Fri, 18 Sep 2020 06:30:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600410627; bh=IQhmDb9Gvirr9W7TU/bGaxVy/Wzg/SI9mkPG47dyJY0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=pv70nVcWsGY67AerFshDjX8Rk99XLr2zzPlBftCXMZ43j6G7tkBJJlG5Kuj9H1i22 83KIlrJ7JACphx/j5kLaj5+hziqAx57ih9OXEnPpegNvHTGwzX0yxHwrKDP2A9c4Pb HUOrzZCvO3OGr7OFl/+hlnVIGLkckLPrh4fqvQl0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726412AbgIRGaW (ORCPT ); Fri, 18 Sep 2020 02:30:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:33214 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726402AbgIRGaV (ORCPT ); Fri, 18 Sep 2020 02:30:21 -0400 Received: from localhost.localdomain (unknown [136.185.124.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7D42B2100A; Fri, 18 Sep 2020 06:30:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600410620; bh=IQhmDb9Gvirr9W7TU/bGaxVy/Wzg/SI9mkPG47dyJY0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mIiIVX25MRM14GAKz6rgjg1AHEg7VMtBhzzpalo1LPrRncpqxS/ozdPcV5GMCgfUK zdPhdT/PWBrjzoR94cYXGy1WxenfMOPfqIH78Kt43nhNajSKY94KVwHbXw4e1Y5cTi amXL+v5Sbq6CYIu8Gnxgo0Q9q0XhnPK8A5qSiqqs= From: Vinod Koul To: dmaengine@vger.kernel.org Cc: Vinod Koul , Rob Herring , Bjorn Andersson , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Ujfalusi Subject: [PATCH v2 1/3] dt-bindings: dmaengine: Document qcom, gpi dma binding Date: Fri, 18 Sep 2020 11:59:53 +0530 Message-Id: <20200918062955.2095156-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200918062955.2095156-1-vkoul@kernel.org> References: <20200918062955.2095156-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree binding documentation for GPI DMA controller implemented on Qualcomm SoCs Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/qcom,gpi.yaml | 86 +++++++++++++++++++ include/dt-bindings/dma/qcom-gpi.h | 11 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/qcom,gpi.yaml create mode 100644 include/dt-bindings/dma/qcom-gpi.h diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml new file mode 100644 index 000000000000..82f404bc8745 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc GPI DMA controller + +maintainers: + - Vinod Koul + +description: | + QCOM GPI DMA controller provides DMA capabilities for + peripheral buses such as I2C, UART, and SPI. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - qcom,gpi-dma + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt lines for each GPII instance + maxItems: 13 + + "#dma-cells": + const: 3 + description: > + DMA clients must use the format described in dma.txt, giving a phandle + to the DMA controller plus the following 3 integer cells: + - channel: if set to 0xffffffff, any available channel will be allocated + for the client. Otherwise, the exact channel specified will be used. + - seid: serial id of the client as defined in the SoC documentation. + - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h + + iommus: + maxItems: 1 + + dma-channels: + maxItems: 1 + + dma-channel-mask: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - iommus + - dma-channels + - dma-channel-mask + +examples: + - | + #include + #include + gpi_dma0: dma-controller@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <3>; + reg = <0x00800000 0x60000>; + iommus = <&apps_smmu 0x0016 0x0>; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + +... diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h new file mode 100644 index 000000000000..71f79eb7614c --- /dev/null +++ b/include/dt-bindings/dma/qcom-gpi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2020, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ +#define __DT_BINDINGS_DMA_QCOM_GPI_H__ + +#define QCOM_GPI_SPI 1 +#define QCOM_GPI_UART 2 +#define QCOM_GPI_I2C 3 + +#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ From patchwork Fri Sep 18 06:29:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 292772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64EAAC43464 for ; Fri, 18 Sep 2020 06:30:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1AC84206B6 for ; Fri, 18 Sep 2020 06:30:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600410633; bh=+e+IoK54qWZAhooHnoOb+SkccNGfKNqvzSHWUZVBsF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=kdCEfieTQ30l346PzN2cyOfZfG9ppHWma7auW38lFky6czuTNI5WoQWjz80mDNEh3 0ZF93UZM+ILpdARw0M7FDk1zKuo7Do/a2FyZeioz29R17B0f8moNyY3TiVVvtxGIl2 FUDw/lXu2Fk+O+fxemfffP0iVyVg7cifS3vOR7hQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726437AbgIRGa3 (ORCPT ); Fri, 18 Sep 2020 02:30:29 -0400 Received: from mail.kernel.org ([198.145.29.99]:33322 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726327AbgIRGaZ (ORCPT ); Fri, 18 Sep 2020 02:30:25 -0400 Received: from localhost.localdomain (unknown [136.185.124.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7C0E021534; Fri, 18 Sep 2020 06:30:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600410624; bh=+e+IoK54qWZAhooHnoOb+SkccNGfKNqvzSHWUZVBsF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rz2vEuuh8wJA5hH04sBlqBHc7a8+ygfS/eJcj/ibJiRT2ZIunUlTBCr0TW/XtZAoG c84aRC6/p8K6V1WzUPxTz6uTQmaqzPi+N+K6OwxvjoLk8WEgY5SdbW6+JMqqqMgFtg CzQOeFCfxhcTWb35yawbH3azOXR0EwMUPxL06GDE= From: Vinod Koul To: dmaengine@vger.kernel.org Cc: Vinod Koul , Rob Herring , Bjorn Andersson , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Ujfalusi Subject: [PATCH v2 2/3] dmaengine: add peripheral configuration Date: Fri, 18 Sep 2020 11:59:54 +0530 Message-Id: <20200918062955.2095156-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200918062955.2095156-1-vkoul@kernel.org> References: <20200918062955.2095156-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some complex dmaengine controllers have capability to program the peripheral device, so pass on the peripheral configuration as part of dma_slave_config Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 90 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 6fbd5c99e30c..89e0fe8e0b1c 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -380,6 +380,93 @@ enum dma_slave_buswidth { DMA_SLAVE_BUSWIDTH_64_BYTES = 64, }; +/** + * enum spi_transfer_cmd - spi transfer commands + */ +enum spi_transfer_cmd { + SPI_TX = 1, + SPI_RX, + SPI_DUPLEX, +}; + +/** + * struct dmaengine_spi_config - spi config for peripheral + * + * @loopback_en: spi loopback enable when set + * @clock_pol: clock polarity + * @data_pol: data polarity + * @pack_en: process tx/rx buffers as packed + * @word_len: spi word length + * @clk_div: source clock divider + * @clk_src: serial clock + * @cmd: spi cmd + * @cs: chip select toggle + */ +struct dmaengine_spi_config { + u8 loopback_en; + u8 clock_pol; + u8 data_pol; + u8 pack_en; + u8 word_len; + u32 clk_div; + u32 clk_src; + u8 fragmentation; + enum spi_transfer_cmd cmd; + u8 cs; +}; + +enum i2c_op { + I2C_WRITE = 1, + I2C_READ, +}; + +/** + * struct dmaengine_i2c_config - i2c config for peripheral + * + * @pack_enable: process tx/rx buffers as packed + * @cycle_count: clock cycles to be sent + * @high_count: high period of clock + * @low_count: low period of clock + * @clk_div: source clock divider + * @addr: i2c bus address + * @stretch: stretch the clock at eot + * @op: i2c cmd + */ +struct dmaengine_i2c_config { + u8 pack_enable; + u8 cycle_count; + u8 high_count; + u8 low_count; + u16 clk_div; + u8 addr; + u8 stretch; + enum i2c_op op; +}; + +enum dmaengine_peripheral { + DMAENGINE_PERIPHERAL_SPI = 1, + DMAENGINE_PERIPHERAL_UART = 2, + DMAENGINE_PERIPHERAL_I2C = 3, + DMAENGINE_PERIPHERAL_LAST = DMAENGINE_PERIPHERAL_I2C, +}; + +/** + * struct dmaengine_peripheral_config - peripheral configuration for + * dmaengine peripherals + * + * @peripheral: type of peripheral to DMA to/from + * @set_config: set peripheral config + * @rx_len: receive length for buffer + * @spi: peripheral config for spi + * @i2c: peripheral config for i2c + */ +struct dmaengine_peripheral_config { + enum dmaengine_peripheral peripheral; + u8 set_config; + u32 rx_len; + struct dmaengine_spi_config spi; + struct dmaengine_i2c_config i2c; +}; /** * struct dma_slave_config - dma slave channel runtime config * @direction: whether the data shall go in or out on this slave @@ -418,6 +505,8 @@ enum dma_slave_buswidth { * @slave_id: Slave requester id. Only valid for slave channels. The dma * slave peripheral will have unique id as dma requester which need to be * pass as slave config. + * @peripheral: peripheral configuration for programming peripheral for + * dmaengine transfer * * This struct is passed in as configuration data to a DMA engine * in order to set up a certain channel for DMA transport at runtime. @@ -443,6 +532,7 @@ struct dma_slave_config { u32 dst_port_window_size; bool device_fc; unsigned int slave_id; + struct dmaengine_peripheral_config *peripheral; }; /**