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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:11 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:42 +0200 Message-Id: <1507736449-6073-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Add an implementation of EFI_RNG_PROTOCOL so that the OS loader has access to entropy for KASLR and other purposes (i.e., seeding the OS's entropy pool very early on). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 4 + Platform/Marvell/Armada/Armada70x0.fdf | 1 + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c | 254 ++++++++++++++++++++ Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf | 47 ++++ Platform/Marvell/Marvell.dec | 3 + 5 files changed, 309 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index 1aa485c..ec24d76 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -364,6 +364,9 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 + # TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform @@ -400,6 +403,7 @@ Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf Platform/Marvell/Drivers/Spi/MvSpiDxe.inf Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf # Network support MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf index 933c3ed..a94a9ff 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -113,6 +113,7 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c INF Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf INF Platform/Marvell/Drivers/Spi/MvSpiDxe.inf INF Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + INF Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf # Network support INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c new file mode 100644 index 0000000..dca6dcc --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c @@ -0,0 +1,254 @@ +/** @file + + This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG + + Copyright (C) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +#include + +#define TRNG_OUTPUT_REG mTrngBaseAddress +#define TRNG_OUTPUT_SIZE 0x10 + +#define TRNG_STATUS_REG (mTrngBaseAddress + 0x10) +#define TRNG_STATUS_READY BIT0 + +#define TRNG_INTACK_REG (mTrngBaseAddress + 0x10) +#define TRNG_INTACK_READY BIT0 + +#define TRNG_CONTROL_REG (mTrngBaseAddress + 0x14) +#define TRNG_CONTROL_REG_ENABLE BIT10 + +#define TRNG_CONFIG_REG (mTrngBaseAddress + 0x18) +#define __MIN_REFILL_SHIFT 0 +#define __MAX_REFILL_SHIFT 16 +#define TRNG_CONFIG_MIN_REFILL_CYCLES (0x05 << __MIN_REFILL_SHIFT) +#define TRNG_CONFIG_MAX_REFILL_CYCLES (0x22 << __MAX_REFILL_SHIFT) + +#define TRNG_FRODETUNE_REG (mTrngBaseAddress + 0x24) +#define TRNG_FRODETUNE_MASK 0x0 + +#define TRNG_FROENABLE_REG (mTrngBaseAddress + 0x20) +#define TRNG_FROENABLE_MASK 0xffffff + +#define TRNG_MAX_RETRIES 20 + +STATIC EFI_PHYSICAL_ADDRESS mTrngBaseAddress; + +/** + Returns information about the random number generation implementation. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in,out] RNGAlgorithmListSize On input, the size in bytes of + RNGAlgorithmList. + On output with a return code of + EFI_SUCCESS, the size in bytes of the + data returned in RNGAlgorithmList. On + output with a return code of + EFI_BUFFER_TOO_SMALL, the size of + RNGAlgorithmList required to obtain the + list. + @param[out] RNGAlgorithmList A caller-allocated memory buffer filled + by the driver with one EFI_RNG_ALGORITHM + element for each supported RNG algorithm. + The list must not change across multiple + calls to the same driver. The first + algorithm in the list is the default + algorithm for the driver. + + @retval EFI_SUCCESS The RNG algorithm list was returned + successfully. + @retval EFI_UNSUPPORTED The services is not supported by this + driver. + @retval EFI_DEVICE_ERROR The list of algorithms could not be + retrieved due to a hardware or firmware + error. + @retval EFI_INVALID_PARAMETER One or more of the parameters are + incorrect. + @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small + to hold the result. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetInfo ( + IN EFI_RNG_PROTOCOL *This, + IN OUT UINTN *RNGAlgorithmListSize, + OUT EFI_RNG_ALGORITHM *RNGAlgorithmList + ) +{ + if (This == NULL || RNGAlgorithmListSize == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) { + *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM); + return EFI_BUFFER_TOO_SMALL; + } + + if (RNGAlgorithmList == NULL) { + return EFI_INVALID_PARAMETER; + } + + *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM); + CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetTrngData ( + IN UINTN Length, + OUT UINT8 *Bits + ) +{ + UINTN Tries; + UINT32 Buf[TRNG_OUTPUT_SIZE / sizeof (UINT32)]; + UINTN Index; + + for (Tries = 0; Tries < TRNG_MAX_RETRIES; Tries++) { + if (MmioRead32 (TRNG_STATUS_REG) & TRNG_STATUS_READY) { + for (Index = 0; Index < ARRAY_SIZE (Buf); Index++) { + Buf[Index] = MmioRead32 (TRNG_OUTPUT_REG + Index * sizeof (UINT32)); + } + CopyMem (Bits, Buf, Length); + MmioWrite32 (TRNG_INTACK_REG, TRNG_INTACK_READY); + + return EFI_SUCCESS; + } + gBS->Stall (10); + } + return EFI_DEVICE_ERROR; +} + +/** + Produces and returns an RNG value using either the default or specified RNG + algorithm. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that + identifies the RNG algorithm to use. May + be NULL in which case the function will + use its default RNG algorithm. + @param[in] RNGValueLength The length in bytes of the memory buffer + pointed to by RNGValue. The driver shall + return exactly this numbers of bytes. + @param[out] RNGValue A caller-allocated memory buffer filled + by the driver with the resulting RNG + value. + + @retval EFI_SUCCESS The RNG value was returned successfully. + @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm + is not supported by this driver. + @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due + to a hardware or firmware error. + @retval EFI_NOT_READY There is not enough random data available + to satisfy the length requested by + RNGValueLength. + @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is + zero. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetRNG ( + IN EFI_RNG_PROTOCOL *This, + IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL + IN UINTN RNGValueLength, + OUT UINT8 *RNGValue + ) +{ + UINTN Length; + EFI_STATUS Status; + + if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // We only support the raw algorithm, so reject requests for anything else + // + if (RNGAlgorithm != NULL && + !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) { + return EFI_UNSUPPORTED; + } + + do { + Length = MIN (RNGValueLength, TRNG_OUTPUT_SIZE); + Status = GetTrngData (Length, RNGValue); + if (EFI_ERROR (Status)) { + return Status; + } + + RNGValue += Length; + RNGValueLength -= Length; + } while (RNGValueLength > 0); + + return EFI_SUCCESS; +} + +STATIC EFI_RNG_PROTOCOL mArmada70x0RngProtocol = { + Armada70x0RngGetInfo, + Armada70x0RngGetRNG +}; + +// +// Entry point of this driver. +// +EFI_STATUS +EFIAPI +Armada70x0RngDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mTrngBaseAddress = PcdGet64 (PcdEip76TrngBaseAddress); + + // + // Disable the TRNG before updating its configuration + // + MmioAnd32 (TRNG_CONTROL_REG, ~TRNG_CONTROL_REG_ENABLE); + + // + // Configure the internal conditioning parameters of the TRNG + // + MmioWrite32 (TRNG_CONFIG_REG, TRNG_CONFIG_MIN_REFILL_CYCLES | + TRNG_CONFIG_MAX_REFILL_CYCLES); + + // + // Configure the FROs + // + MmioWrite32 (TRNG_FRODETUNE_REG, TRNG_FRODETUNE_MASK); + MmioWrite32 (TRNG_FROENABLE_REG, TRNG_FROENABLE_MASK); + + // + // Enable the TRNG + // + MmioOr32 (TRNG_CONTROL_REG, TRNG_CONTROL_REG_ENABLE); + + return SystemTable->BootServices->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiRngProtocolGuid, + &mArmada70x0RngProtocol, + NULL + ); +} diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf new file mode 100644 index 0000000..189ffc5 --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf @@ -0,0 +1,47 @@ +## @file +# This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG +# +# Copyright (C) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Armada70x0RngDxe + FILE_GUID = dd87096a-cae5-4328-bec1-2ddb755f2e08 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = Armada70x0RngDxeEntryPoint + +[Sources] + Armada70x0RngDxe.c + +[Packages] + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + BaseMemoryLib + IoLib + PcdLib + UefiDriverEntryPoint + +[Pcd] + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress + +[Protocols] + gEfiRngProtocolGuid ## PRODUCES + +[Guids] + gEfiRngAlgorithmRaw + +[Depex] + TRUE diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index e7d7c2c..78f5e53 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -195,6 +195,9 @@ #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 +#TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 + [Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} From patchwork Wed Oct 11 15:40:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 115569 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp757816edb; Wed, 11 Oct 2017 08:41:23 -0700 (PDT) X-Received: by 10.98.144.142 with SMTP id q14mr13104pfk.303.1507736482907; Wed, 11 Oct 2017 08:41:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507736482; cv=none; d=google.com; s=arc-20160816; b=aEU0AZ9gbj6svAyO4LB0g8awFbxOTaBKVm3zs4Xj/bb04wJZsYkFcZk6HNzpbRSqP/ ttrIfiNZJdWkSLZpvtQuc/9hCj/59344hnp2Ks9xTcfq25kJ9qY7g1rVS4k3YaFhuyqO kSEL73AR49PUATk7gky1uTeJbI4cb6Mzz+OdGD7gUvx9sX6prQncpzClkw0G3DBkPHt+ Nge9kkZ+2z1wfe4Mx7Jai8772/E2YhsFdiqnDffL2XaGtdkGkzpIRoVHkyCa16P8u5Ig aGCRDAtIZkoPrXpdOgt/sybkFay2UbThF0gYthst9tJ/AOqaQOWWaIE3gEKNRnMFO+/a SxFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=MqOL2WRTPAWUT3ceSu1vl/pnqOCc4Ki5A7KReYnWim4=; b=VLdK8/FuzBGEKCvUaYp6eoFEyJfsDJ1D09kXJjSFmsOwGc80UHzJr+JpC433tRMvGr lxWrP7IyUUHzt54Qri6KSKKDvYgDnWoKdx1wktGnUUh2Kx/iplqoQuwepNlRBRp0ETZS 3pgnNTQ8jFDvNsXFMIBynFK5UrJovpU+pfuVTxZ7I6BfG5gEgLnZWMFmSzywAIbCgsZn 1/yuAOu3gf33Ijj3CKlZCk1mOgpleF9TlfqDCgAE0B6FLnRQmgjgVgCOSO2Wsm1aHMT5 U7Ko/wJHIdKjdGutrLJ2tO7wUedvOmheVNiYJc7jn1s7PRdfVtaQ1+VRfmw7Km1F9sF9 cv0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=zncG20QV; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:13 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:43 +0200 Message-Id: <1507736449-6073-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/8] Marvell/Armada: Increase preallocated memory region size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel In order to prevent fragmentation of the UEFI memory map, increase the sizes of the preallocated regions. Note that this does not increase the memory footprint of UEFI, it just modifies it allocation policy to keep similar region types together. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index ec24d76..56d8941 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -341,10 +341,10 @@ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|35000 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 From patchwork Wed Oct 11 15:40:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 115570 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp757923edb; Wed, 11 Oct 2017 08:41:30 -0700 (PDT) X-Received: by 10.159.198.70 with SMTP id y6mr12576plt.334.1507736490611; Wed, 11 Oct 2017 08:41:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507736490; cv=none; d=google.com; s=arc-20160816; b=zSn7jLGaz+AFEm5DZ54/pmzVsaJhVQmvcT0fITaVPdEC5dKf/GBK3TDjrcOcre71w5 fDmhMQS6Tf1ur71bL6ayzADlLDm+7+6sqBLR9qBGDOha1wF6Q2c+0uLiE1w9cFB4zhXo qOeOlr/YLTjYlkT+Mmr060yj657W9or+pzCBlvvhzzmDqE1tataEyRkuSR8ck6DLb5Xi seUZ204L2LAe0THn3xpj/h1m/+qcutWW1JXzNNQUbFaABS0SzZ0uZ+mcGBQXUrML9I8v S+BpMVWb3w4mg27XmdWOYbwylz7a6i3CCb4hQE1S+atA6L0yFOiu7ClH9IaPy2XnaAaA x1FA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=yFHtYOHyyuW/GoqqE/eEgh0dfzV2uEzPzi5sHSnYakw=; b=kZ81OqWarStrm9umydgc56v+5u55WEicmnJ2LGtXW/WGBs3u+iu/sP8je3wpPbv/vC Er2mejEmcTF4FuHEOkKjwvLRUayQM6QFV5+n6HWk6ZZ4wZKA5xRZvFMEdqHK8BpeS1MK 1H+O9NEEOqsY0EvRIx5jOHKqQBg7fSN2ocV3vGzQg/pp5kiQIcFEU0agJuar7yvNaE8h 6k84fMi8z5c0b3N2zXlWpBD3aIhsQB7IucomfQDPHULoWZdVYfPMEZzaXQLbPxZfmc9c qXnyHcwoQbxcvQ4IAM+w3embmy6qZC3aEUqqrfTwGAZ+jKGYr7WDblv0ylAZjfe94ya4 vj3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=cCTueOPl; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:16 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:45 +0200 Message-Id: <1507736449-6073-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 4/8] Marvell/Armada: Add support from DRAM remapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel The Armada 70x0/80x0 DRAM controller allows a single window of DRAM to be remapped to another location in the physical address space. This allows us to free up some memory in the 32-bit addressable region for peripheral MMIO and PCI MMIO32 and CONFIG spaces. This patch adjusts memory blocks to the configuration done in ATF. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 15 +++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3 + Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 60 ++++++++++++++++---- Platform/Marvell/Marvell.dec | 13 +++++ 4 files changed, 81 insertions(+), 10 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S index 72f8cfc..c5be1a9 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S @@ -17,6 +17,21 @@ ASM_FUNC(ArmPlatformPeiBootAction) mov x29, xzr + + .if FixedPcdGet64 (PcdSystemMemoryBase) != 0 + .err PcdSystemMemoryBase should be 0x0 on this platform! + .endif + + .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapTarget) + // + // Use the low range for UEFI itself. The remaining memory will be mapped + // and added to the GCD map later. + // + adr x0, mSystemMemoryEnd + MOV64 (x1, FixedPcdGet32 (PcdDramRemapTarget) - 1) + str x1, [x0] + .endif + ret //UINTN diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2e198c3..838a670 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -67,5 +67,8 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore + gMarvellTokenSpaceGuid.PcdDramRemapSize + gMarvellTokenSpaceGuid.PcdDramRemapTarget + [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 74c9956..2cb2e15 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include #include #include +#include #include // The total number of descriptors, including the final "end-of-table" descriptor. @@ -44,6 +45,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED +STATIC ARM_MEMORY_REGION_DESCRIPTOR VirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS]; + /** Return the Virtual Memory Map of your platform @@ -59,20 +62,41 @@ ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap ) { - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; UINTN Index = 0; + UINT64 MemSize; + UINT64 MemLowSize; + UINT64 MemHighStart; + UINT64 MemHighSize; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; ASSERT (VirtualMemoryMap != NULL); - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); - if (VirtualMemoryTable == NULL) { - return; - } + MemSize = FixedPcdGet64 (PcdSystemMemorySize); + MemLowSize = MIN (FixedPcdGet64 (PcdDramRemapTarget), MemSize); + MemHighStart = (UINT64)FixedPcdGet64 (PcdDramRemapTarget) + + FixedPcdGet32 (PcdDramRemapSize); + MemHighSize = MemSize - MemLowSize; + + ResourceAttributes = ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdSystemMemoryBase), + MemLowSize + ); // DDR - VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = MemLowSize; VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; // Configuration space 0xF000_0000 - 0xFFFF_FFFF @@ -81,13 +105,29 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = 0x10000000; VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + if (MemSize > MemLowSize) { + // + // If we have more than MemLowSize worth of DRAM, the remainder will be + // mapped at the top of the remapped window. + // + VirtualMemoryTable[++Index].PhysicalBase = MemHighStart; + VirtualMemoryTable[Index].VirtualBase = MemHighStart; + VirtualMemoryTable[Index].Length = MemHighSize; + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemHighStart, + MemHighSize + ); + } + // End of Table VirtualMemoryTable[++Index].PhysicalBase = 0; VirtualMemoryTable[Index].VirtualBase = 0; VirtualMemoryTable[Index].Length = 0; VirtualMemoryTable[Index].Attributes = 0; - ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - *VirtualMemoryMap = VirtualMemoryTable; } diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 434d6cb..db1c7fa 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -194,6 +194,19 @@ #TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 + # + # DRAM remapping controls. + # On the 70x0/80x0 SOCs, the DRAM is mapped at 0x0, and could be up to + # 16 GB in size. To allow for 32-bit addressable MMIO peripherals or PCI + # windows, a single window of up to 4 GB in size can be remapped elsewhere. + # So let's define a 1 GB window at 0xC000000 by default: this is the minimum + # alignment that Linux can map optimally (i.e., it's section shift is 30 bits) + # and gives us an additional 768 MB (on top of the 256 MB platform MMIO window + # at 0xF0000000) for the PCI MMIO32 and CONFIG spaces. + # + gMarvellTokenSpaceGuid.PcdDramRemapSize|0x40000000|UINT32|0x50000004 + gMarvellTokenSpaceGuid.PcdDramRemapTarget|0xC0000000|UINT32|0x50000003 + [Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} From patchwork Wed Oct 11 15:40:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 115571 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp757961edb; Wed, 11 Oct 2017 08:41:34 -0700 (PDT) X-Received: by 10.98.70.78 with SMTP id t75mr54836pfa.6.1507736494325; Wed, 11 Oct 2017 08:41:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507736494; cv=none; d=google.com; s=arc-20160816; b=tyJVCc5zbf+Hog94K8ktBoSjDmVEOIXTCL1Da6+GXyKDSCoW6TAiJ/wytQHeAHuGEl b22BEkZLMVh45CBdh0jPGHL/2PNIx8AmkWTGx95cGTK6g9aUtzSJ2ZyZuGgbEOGdHKIV Opra2LGZfV3SQeNSA/ldwRp6xYjuxJqKh6Viv/V1iCKPR2y2mtEzAxcG1h5uthfO50A+ IzKcqav/72oapFTDlKGCDQPBo7fFIVIrCNYqCGLqFXOXG0fyTriafu+KmcSIQeBgWGWW DehWTCxpqHIvmqjBrCHbjKcg+XhjQwOHNshH86z4V8AHVEbfXAut1z8Tv+yEwRrh8SXX y6SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=LSe3uWTjbpEcaR5HhT05flVpkPi6zkvDKkIMoj18nYo=; b=g5lCg1QuF3AJvQq+eFmw60EcrrnHbg3BdNHLVuDpmfQkgPRzjijRp1tKe+H2kKd+Dr 7FobVqyUGPdPIdEH7IZQ5kIm6DKVGk+qEcwmYDmUaWrTHVJuk7DK/kebqupkV2ks4SS+ Q2g+d1QuC74GHYhYqXAyGg62iutE4In24ml8NtXtMnIJepeaoCSgwdYW0Qw8dnDZy8RG CbNzHO9e3fY0YntSV7R+H9XeIfrlWwij2jebDcQoKMwxWhIuDLeaqGAYAvrR9ey5Fb5F WgG1DFJ49Hn0WJmmivYSv7kVMSaOsTm48XryuahUWY55iBHNX/UJQzlw0Rb3FEJspvCi OXqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=c7WahB++; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:17 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:46 +0200 Message-Id: <1507736449-6073-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 5/8] Marvell/Armada: Add MemoryInitPeiLib that reserves secure region X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel The default MemoryInitPeiLib implementation insists on reserving the region occupied by our own FV, while this is not necessary at all (the compressed payload is uncompressed elsewhere, so the moment we enter DXE core, we don't care about the FV contents in memory) So clone MemoryInitPeiLib and modify it to suit our needs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 6 +- Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c | 158 ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf | 46 ++++++ Platform/Marvell/Marvell.dec | 8 + 4 files changed, 217 insertions(+), 1 deletion(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index 56d8941..b0a8240 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -153,7 +153,7 @@ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf [LibraryClasses.common.SEC, LibraryClasses.common.PEIM] - MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + MemoryInitPeiLib|Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf [LibraryClasses.common.DXE_CORE] @@ -364,6 +364,10 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 + # Secure region reservation + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000 + # TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c new file mode 100644 index 0000000..53119f4 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c @@ -0,0 +1,158 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2017, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + + VOID *TranslationTableBase; + UINTN TranslationTableSize; + RETURN_STATUS Status; + + Status = ArmConfigureMmu (MemoryTable, + &TranslationTableBase, + &TranslationTableSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } +} + +/*++ + +Routine Description: + + + +Arguments: + + FileHandle - Handle of the file being invoked. + PeiServices - Describes the list of possible PEI Services. + +Returns: + + Status - EFI_SUCCESS if the boot mode could be set + +--*/ +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINT64 ResourceLength; + EFI_PEI_HOB_POINTERS NextHob; + EFI_PHYSICAL_ADDRESS SecureTop; + EFI_PHYSICAL_ADDRESS ResourceTop; + + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + SecureTop = (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase) + + FixedPcdGet32 (PcdSecureRegionSize); + + // + // Search for System Memory Hob that covers the secure firmware, + // and punch a hole in it + // + for (NextHob.Raw = GetHobList (); + NextHob.Raw != NULL; + NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, + NextHob.Raw)) { + + if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && + (FixedPcdGet64 (PcdSecureRegionBase) >= NextHob.ResourceDescriptor->PhysicalStart) && + (SecureTop <= NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength)) + { + ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute; + ResourceLength = NextHob.ResourceDescriptor->ResourceLength; + ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength; + + if (FixedPcdGet64 (PcdSecureRegionBase) == NextHob.ResourceDescriptor->PhysicalStart) { + // + // This region starts right at the start of the reserved region, so we + // can simply move its start pointer and reduce its length by the same + // value + // + NextHob.ResourceDescriptor->PhysicalStart += FixedPcdGet32 (PcdSecureRegionSize); + NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize); + + } else if ((NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength) == SecureTop) { + + // + // This region ends right at the end of the reserved region, so we + // can simply reduce its length by the size of the region. + // + NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize); + + } else { + // + // This region covers the reserved region. So split it into two regions, + // each one touching the reserved region at either end, but not covering + // it. + // + NextHob.ResourceDescriptor->ResourceLength = FixedPcdGet64 (PcdSecureRegionBase) - + NextHob.ResourceDescriptor->PhysicalStart; + + // Create the System Memory HOB for the remaining region (top of the FD) + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + SecureTop, + ResourceTop - SecureTop); + } + + // + // Reserve the memory space occupied by the secure firmware + // + BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED, + 0, + FixedPcdGet64 (PcdSecureRegionBase), + FixedPcdGet32 (PcdSecureRegionSize)); + + break; + } + NextHob.Raw = GET_NEXT_HOB (NextHob); + } + + // Build Memory Allocation Hob + InitMmu (MemoryTable); + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf new file mode 100644 index 0000000..ebaed01 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf @@ -0,0 +1,46 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Armada70x0MemoryInitPeiLib + FILE_GUID = abc4e8a7-89a7-4aea-92bc-0e9421c4a473 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM + +[Sources] + Armada70x0MemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + ArmPlatformLib + DebugLib + HobLib + ArmMmuLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdSecureRegionBase + gMarvellTokenSpaceGuid.PcdSecureRegionSize diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index db1c7fa..63ea071 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -207,6 +207,14 @@ gMarvellTokenSpaceGuid.PcdDramRemapSize|0x40000000|UINT32|0x50000004 gMarvellTokenSpaceGuid.PcdDramRemapTarget|0xC0000000|UINT32|0x50000003 + # + # The secure firmware may occupy a DRAM region that is accessible by the + # normal world. These PCDs describe such a region, which will be converted + # to 'reserved' memory before DXE is entered. + # + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x0|UINT64|0x50000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001 + [Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} From patchwork Wed Oct 11 15:40:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 115572 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp758065edb; Wed, 11 Oct 2017 08:41:43 -0700 (PDT) X-Received: by 10.84.197.35 with SMTP id m32mr14357pld.306.1507736502960; Wed, 11 Oct 2017 08:41:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507736502; cv=none; d=google.com; s=arc-20160816; b=HFx6rtSL/mq0fGumoBhIvEG1JzkoX9Tun2S5n1xzfbiHZMn92yAT32eqDtDjmWJEa9 j3VHQlZNb8Rdg+1MoqTjSk68GuzrdfuJ4YL4WZ2XHuRdfHrFS2RZWwqSH5pMi5yfszpl 8ZXczbH8kN54lDgUoC0NxYLOtYkN5lY7tHE0Bh/TZ860JCVGU7p1vrPl0xzp2AecJBB6 xHNF5JAjc/N/098Jtwy9lbCkH2UOJ8//lBB81C+rmMG2sN2rVzlPN03I9HU9lMsl870C UsRUDoRkODImIBY7kp5HincMkVCRWZDCXToKfW/3F1L4GvQ/6kwk3ro7ckEbqgBXSOSw QC9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=PTCjifxySsbvFu2xrSOjkSjDpBr5jUv94NyXxWz6sZE=; b=WWGtbP6AwgeKzBm+Nmfi86+dMV8WmJlz9HZvGyuIafdoS1byMMdHiclbE25ZJZ3j1H TNBBu/3tvd+CvTDYYL0V6d/jKPRl+LFtAYF0PxCETCOxzqjAr2CBjNyxqZ3Q7k7HAvNi n1EYM/BERkvCm/HViIG4gr0boxeskY/ESWm8FlAibXR890j8Pff1pvBS+3Iq37uEwpQC 9SBemZBbp+qY9yyer5A6mNRshMdVlEgUAOlHeR5VSitqLEEgwyBSB2EsXvFDPh3cOtC5 WrvivpMIHcoDnXS5Qt//0kZPDvqwPH21XyJh5q1d8zFSA6sf18F4c5k8U7252BKX5tXy o4Rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=ILUWpjxV; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:21 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:48 +0200 Message-Id: <1507736449-6073-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 7/8] Marvell/Armada: Armada70x0Lib: Add support for 32-bit ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Add an ARM implementation of ArmPlatformHelper.S. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S | 77 ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3 + 2 files changed, 80 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S new file mode 100644 index 0000000..21459e5 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S @@ -0,0 +1,77 @@ +//Based on ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHelper.S +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// Copyright (c) 2016, Marvell. All rights reserved. +// Copyright (c) 2017, Linaro Limited. All rights reserved. +// +// This program and the accompanying materials are licensed and made available +// under the terms and conditions of the BSD License which accompanies this +// distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +// + +#include +#include + +#define CCU_MC_BASE 0xF0001700 +#define CCU_MC_RCR_OFFSET 0x0 +#define CCU_MC_RCR_REMAP_EN BIT0 +#define CCU_MC_RCR_REMAP_SIZE(Size) (((Size) - 1) ^ (SIZE_1MB - 1)) + +#define CCU_MC_RSBR_OFFSET 0x4 +#define CCU_MC_RSBR_SOURCE_BASE(Base) (((Base) >> 20) << 10) +#define CCU_MC_RTBR_OFFSET 0x8 +#define CCU_MC_RTBR_TARGET_BASE(Base) (((Base) >> 20) << 10) + +ASM_FUNC(ArmPlatformPeiBootAction) + .if FixedPcdGet64 (PcdSystemMemoryBase) != 0 + .err PcdSystemMemoryBase should be 0x0 on this platform! + .endif + + .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapTarget) + // + // Use the low range for UEFI itself. The remaining memory will be mapped + // and added to the GCD map later. + // + ADRL (r0, mSystemMemoryEnd) + MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1) + mov r3, #0 + strd r2, r3, [r0] + .endif + + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (r0, FixedPcdGet32(PcdArmPrimaryCore)) + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and r0, r0, r1 + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 838a670..0dabd4b 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -60,6 +60,9 @@ [Sources.AArch64] AArch64/ArmPlatformHelper.S +[Sources.ARM] + ARM/ArmPlatformHelper.S + [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize From patchwork Wed Oct 11 15:40:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 115573 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp758123edb; Wed, 11 Oct 2017 08:41:47 -0700 (PDT) X-Received: by 10.99.124.91 with SMTP id l27mr32385pgn.49.1507736507229; Wed, 11 Oct 2017 08:41:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507736507; cv=none; d=google.com; s=arc-20160816; b=JnJJ6ydzgR8iV8oCc+bdz6PnRqu1fFGYRDJEHBa63dPD52h+rpkMPkIRXWkq0+qJJ/ tNDFaU6ZQIsv6td2udfxqK7Q4cQzngiBOJWSgjghutjN9dlEghscr0ilcr1fwsvnTXJt cVpyzKJyF+Eg+jyNocrqqNyTgMRstGynvRndb8PlhCeIvCMa2HXCmRLY10I2EI0xA6Hq wVARNMhDHUJdWmrENms1tywvNWTAGdelhGiPyP7kNh+TTV1PZokwYoIXjEOgYuPCfbxK JSQYDfPi05No3/QR1+O0Zz15ImU0+OfJxh00ncjdALHhVK4wX0VhEutLQi0d09nSD7OL XKlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=1rDCMQhhB8QFp5B0D/tBrHo3ppTHkC1d720KAUr6O14=; b=Oo3n+Oyeo48s3TlkSUfy5iYMvzPVO6st5svDeKHWm6eiRqAS6/iH3nx6aAc5iGDAHN XU9cojUEIDmdpcs8HvHTMOPPy1OEPML2nvVPPJbC4eHaJNkG50YEsYRCO+GKg44FCFjc P0/vCCQWL8Z33oHlWy/LjpSG9/SR/093ZvVT7hhqXb87HgEPhAXJcXgbExTDfLLU9ot/ 2imdy/1H/bcLNMkE93d4BxFtq4/QE+qkHq48G7JmPebfSiCNGkiMQT/1jX442mYXSRTw triXiCll5vNVGlRCyJdwjhPoC3F2TKCscMArArC31UCwoPiKQeii9j063pMEWko2+oNv iq4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=QvYEUJRF; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:22 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:49 +0200 Message-Id: <1507736449-6073-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 8/8] Marvell/Armada: Add 32-bit ARM support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Update the included components and library classes to make this platform build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 3 +-- Platform/Marvell/Armada/Armada70x0.dsc | 4 ++-- Platform/Marvell/Armada/Armada70x0.fdf | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index b0a8240..b9fc384 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -132,7 +132,6 @@ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf -[LibraryClasses.AARCH64] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf @@ -362,7 +361,7 @@ # ARM Pcds gArmTokenSpaceGuid.PcdSystemMemoryBase|0 gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 - gArmTokenSpaceGuid.PcdArmScr|0x531 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 # Secure region reservation gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc index 946c93e..0396e8e 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -39,8 +39,8 @@ PLATFORM_GUID = f837e231-cfc7-4f56-9a0f-5b218d746ae3 PLATFORM_VERSION = 0.1 DSC_SPECIFICATION = 0x00010005 - OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES = AARCH64 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES = AARCH64|ARM BUILD_TARGETS = DEBUG|RELEASE SKUID_IDENTIFIER = DEFAULT FLASH_DEFINITION = Platform/Marvell/Armada/Armada70x0.fdf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf index a94a9ff..ec2c368 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -237,7 +237,7 @@ READ_LOCK_STATUS = TRUE # ############################################################################ -[Rule.AARCH64.SEC] +[Rule.Common.SEC] FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED { TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi }