From patchwork Thu Oct 12 19:48:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 115667 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2308804qgn; Thu, 12 Oct 2017 12:49:12 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCiTB8r+UpyzyufxD/9bqqPSJWAWnH5XWIUL0djzrTX7y5x+cKeQQxJ6UrgP2CnvJCeZg0I X-Received: by 10.84.173.228 with SMTP id p91mr1116627plb.264.1507837752349; Thu, 12 Oct 2017 12:49:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507837752; cv=none; d=google.com; s=arc-20160816; b=X1EF2KHwxdkR6gKs0asmWmP8+HMVMibI7uDf1L7xcT2zm8ae/YuxBPYEd+lCTdMQpG OSf3EnoBkzMKlal8tcBFnBCUR2NA80piIp7YI/AfyJcSIFa317Wg86K56vlWatD96RFX ohgz9ekyFkrmCAliwWrwAo0v6TsZ3vS4fKc2mzidDWMfkG99po8Gd8/0iv3davNjKg3q LKFeexuYv7yuNLxiqgwuHlv/3+mG5XUgEMcXTEZVUMyZTRd2AddVLE9uvyWAnNuqxgqK 02O2VfvTE0kLUBI4CI01xkc9VmuG0u6njh2h2efwW030qAcL9u1G35Yi3Ahmy0Aq1+Iz Ap0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=DCrO9JEcH4er05GmWX83Ix9uMcocCHaWaRThO0sNIUI=; b=hBXy4b/Lm5bwSLWpgZ+9a8Pg219ZtDAq0gvPBgNDQIg0od5WOiPxo2/Pu3jGNcZ9mC SujDb6Rwi//ugXpQdbEIQq/lYBL80emDIPjKOt7+J87xVLNoYOjxRpFvOJvEbchT5/+6 XLbpO+KGlxXtcJjf+OIztRrG/k0cAk6v6FzaUrzHto4s4qejwJzUD3KjilFJzt/8O+1c heaDWlkgAXwkeNKoV5Ah/pkpMhB7TZY0ZE67tRZx4Ec9b/EEnU5x9IU0p4WOLHFYwXoq DuPwTFZaWEV4SWPkC8lSPjkATpeHOJ1DM07UVgpyoCnKKpstLtBJFWckBIUxQ5nLitcv E9Zw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g1si11757006pgc.3.2017.10.12.12.49.12; Thu, 12 Oct 2017 12:49:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754506AbdJLTtJ (ORCPT + 27 others); Thu, 12 Oct 2017 15:49:09 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51622 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751348AbdJLTtF (ORCPT ); Thu, 12 Oct 2017 15:49:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 76EB615BE; Thu, 12 Oct 2017 12:49:05 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9ABE83F58C; Thu, 12 Oct 2017 12:49:04 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, Jeremy Linton Subject: [PATCH v3 1/7] ACPI/PPTT: Add Processor Properties Topology Table parsing Date: Thu, 12 Oct 2017 14:48:50 -0500 Message-Id: <20171012194856.13844-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171012194856.13844-1-jeremy.linton@arm.com> References: <20171012194856.13844-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ACPI 6.2 adds a new table, which describes how processing units are related to each other in tree like fashion. Caches are also sprinkled throughout the tree and describe the properties of the caches in relation to other caches and processing units. Add the code to parse the cache hierarchy and report the total number of levels of cache for a given core using acpi_find_last_cache_level() as well as fill out the individual cores cache information with cache_setup_acpi() once the cpu_cacheinfo structure has been populated by the arch specific code. Further, report peers in the topology using setup_acpi_cpu_topology() to report a unique ID for each processing unit at a given level in the tree. These unique id's can then be used to match related processing units which exist as threads, COD (clusters on die), within a given package, etc. Signed-off-by: Jeremy Linton --- drivers/acpi/pptt.c | 485 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 485 insertions(+) create mode 100644 drivers/acpi/pptt.c 2.13.5 diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c new file mode 100644 index 000000000000..c86715fed4a7 --- /dev/null +++ b/drivers/acpi/pptt.c @@ -0,1 +1,485 @@ +/* + * Copyright (C) 2017, ARM + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * This file implements parsing of Processor Properties Topology Table (PPTT) + * which is optionally used to describe the processor and cache topology. + * Due to the relative pointers used throughout the table, this doesn't + * leverage the existing subtable parsing in the kernel. + */ +#define pr_fmt(fmt) "ACPI PPTT: " fmt + +#include +#include +#include + +/* + * Given the PPTT table, find and verify that the subtable entry + * is located within the table + */ +static struct acpi_subtable_header *fetch_pptt_subtable( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + struct acpi_subtable_header *entry; + + /* there isn't a subtable at reference 0 */ + if (!pptt_ref) + return NULL; + + if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) + return NULL; + + entry = (struct acpi_subtable_header *)((u8 *)table_hdr + pptt_ref); + + if (pptt_ref + entry->length > table_hdr->length) + return NULL; + + return entry; +} + +static struct acpi_pptt_processor *fetch_pptt_node( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_processor *)fetch_pptt_subtable(table_hdr, pptt_ref); +} + +static struct acpi_pptt_cache *fetch_pptt_cache( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_cache *)fetch_pptt_subtable(table_hdr, pptt_ref); +} + +static struct acpi_subtable_header *acpi_get_pptt_resource( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *node, int resource) +{ + u32 ref; + + if (resource >= node->number_of_priv_resources) + return NULL; + + ref = *(u32 *)((u8 *)node + sizeof(struct acpi_pptt_processor) + + sizeof(u32) * resource); + + return fetch_pptt_subtable(table_hdr, ref); +} + +/* + * given a pptt resource, verify that it is a cache node, then walk + * down each level of caches, counting how many levels are found + * as well as checking the cache type (icache, dcache, unified). If a + * level & type match, then we set found, and continue the search. + * Once the entire cache branch has been walked return its max + * depth. + */ +static int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr, + int local_level, + struct acpi_subtable_header *res, + struct acpi_pptt_cache **found, + int level, int type) +{ + struct acpi_pptt_cache *cache; + + if (res->type != ACPI_PPTT_TYPE_CACHE) + return 0; + + cache = (struct acpi_pptt_cache *) res; + while (cache) { + local_level++; + + if ((local_level == level) && + (cache->flags & ACPI_PPTT_CACHE_TYPE_VALID) && + ((cache->attributes & ACPI_PPTT_MASK_CACHE_TYPE) == type)) { + if (*found != NULL) + pr_err("Found duplicate cache level/type unable to determine uniqueness\n"); + + pr_debug("Found cache @ level %d\n", level); + *found = cache; + /* + * continue looking at this node's resource list + * to verify that we don't find a duplicate + * cache node. + */ + } + cache = fetch_pptt_cache(table_hdr, cache->next_level_of_cache); + } + return local_level; +} + +/* + * Given a CPU node look for cache levels that exist at this level, and then + * for each cache node, count how many levels exist below (logically above) it. + * If a level and type are specified, and we find that level/type, abort + * processing and return the acpi_pptt_cache structure. + */ +static struct acpi_pptt_cache *acpi_find_cache_level( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node, + int *starting_level, int level, int type) +{ + struct acpi_subtable_header *res; + int number_of_levels = *starting_level; + int resource = 0; + struct acpi_pptt_cache *ret = NULL; + int local_level; + + /* walk down from the processor node */ + while ((res = acpi_get_pptt_resource(table_hdr, cpu_node, resource))) { + resource++; + + local_level = acpi_pptt_walk_cache(table_hdr, *starting_level, + res, &ret, level, type); + /* + * we are looking for the max depth. Since its potentially + * possible for a given node to have resources with differing + * depths verify that the depth we have found is the largest. + */ + if (number_of_levels < local_level) + number_of_levels = local_level; + } + if (number_of_levels > *starting_level) + *starting_level = number_of_levels; + + return ret; +} + +/* + * given a processor node containing a processing unit, walk into it and count + * how many levels exist solely for it, and then walk up each level until we hit + * the root node (ignore the package level because it may be possible to have + * caches that exist across packages). Count the number of cache levels that + * exist at each level on the way up. + */ +static int acpi_process_node(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node) +{ + int total_levels = 0; + + do { + acpi_find_cache_level(table_hdr, cpu_node, &total_levels, 0, 0); + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } while (cpu_node); + + return total_levels; +} + +/* determine if the given node is a leaf node */ +static int acpi_pptt_leaf_node(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *node) +{ + struct acpi_subtable_header *entry; + unsigned long table_end; + u32 node_entry; + struct acpi_pptt_processor *cpu_node; + + table_end = (unsigned long)table_hdr + table_hdr->length; + node_entry = (u32)((u8 *)node - (u8 *)table_hdr); + entry = (struct acpi_subtable_header *)((u8 *)table_hdr + + sizeof(struct acpi_table_pptt)); + + while (((unsigned long)entry) + sizeof(struct acpi_subtable_header) < table_end) { + cpu_node = (struct acpi_pptt_processor *)entry; + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) && + (cpu_node->parent == node_entry)) + return 0; + entry = (struct acpi_subtable_header *)((u8 *)entry + entry->length); + } + return 1; +} + +/* + * Find the subtable entry describing the provided processor + */ +static struct acpi_pptt_processor *acpi_find_processor_node( + struct acpi_table_header *table_hdr, + u32 acpi_cpu_id) +{ + struct acpi_subtable_header *entry; + unsigned long table_end; + struct acpi_pptt_processor *cpu_node; + + table_end = (unsigned long)table_hdr + table_hdr->length; + entry = (struct acpi_subtable_header *)((u8 *)table_hdr + + sizeof(struct acpi_table_pptt)); + + /* find the processor structure associated with this cpuid */ + while (((unsigned long)entry) + sizeof(struct acpi_subtable_header) < table_end) { + cpu_node = (struct acpi_pptt_processor *)entry; + + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) && + acpi_pptt_leaf_node(table_hdr, cpu_node)) { + pr_debug("checking phy_cpu_id %d against acpi id %d\n", + acpi_cpu_id, cpu_node->acpi_processor_id); + if (acpi_cpu_id == cpu_node->acpi_processor_id) { + /* found the correct entry */ + pr_debug("match found!\n"); + return (struct acpi_pptt_processor *)entry; + } + } + + if (entry->length == 0) { + pr_err("Invalid zero length subtable\n"); + break; + } + entry = (struct acpi_subtable_header *) + ((u8 *)entry + entry->length); + } + + return NULL; +} + +/* + * Given a acpi_pptt_processor node, walk up until we identify the + * package that the node is associated with or we run out of levels + * to request. + */ +static struct acpi_pptt_processor *acpi_find_processor_package_id( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu, + int level) +{ + struct acpi_pptt_processor *prev_node; + + while (cpu && level && !(cpu->flags & ACPI_PPTT_PHYSICAL_PACKAGE)) { + pr_debug("level %d\n", level); + prev_node = fetch_pptt_node(table_hdr, cpu->parent); + if (prev_node == NULL) + break; + cpu = prev_node; + level--; + } + return cpu; +} + +static int acpi_parse_pptt(struct acpi_table_header *table_hdr, u32 acpi_cpu_id) +{ + int number_of_levels = 0; + struct acpi_pptt_processor *cpu; + + cpu = acpi_find_processor_node(table_hdr, acpi_cpu_id); + if (cpu) + number_of_levels = acpi_process_node(table_hdr, cpu); + + return number_of_levels; +} + +#define ACPI_6_2_CACHE_TYPE_DATA (0x0) +#define ACPI_6_2_CACHE_TYPE_INSTR (1<<2) +#define ACPI_6_2_CACHE_TYPE_UNIFIED (1<<3) +#define ACPI_6_2_CACHE_POLICY_WB (0x0) +#define ACPI_6_2_CACHE_POLICY_WT (1<<4) +#define ACPI_6_2_CACHE_READ_ALLOCATE (0x0) +#define ACPI_6_2_CACHE_WRITE_ALLOCATE (0x01) +#define ACPI_6_2_CACHE_RW_ALLOCATE (0x02) + +static u8 acpi_cache_type(enum cache_type type) +{ + switch (type) { + case CACHE_TYPE_DATA: + pr_debug("Looking for data cache\n"); + return ACPI_6_2_CACHE_TYPE_DATA; + case CACHE_TYPE_INST: + pr_debug("Looking for instruction cache\n"); + return ACPI_6_2_CACHE_TYPE_INSTR; + default: + pr_debug("Unknown cache type, assume unified\n"); + case CACHE_TYPE_UNIFIED: + pr_debug("Looking for unified cache\n"); + return ACPI_6_2_CACHE_TYPE_UNIFIED; + } +} + +/* find the ACPI node describing the cache type/level for the given CPU */ +static struct acpi_pptt_cache *acpi_find_cache_node( + struct acpi_table_header *table_hdr, u32 acpi_cpu_id, + enum cache_type type, unsigned int level, + struct acpi_pptt_processor **node) +{ + int total_levels = 0; + struct acpi_pptt_cache *found = NULL; + struct acpi_pptt_processor *cpu_node; + u8 acpi_type = acpi_cache_type(type); + + pr_debug("Looking for CPU %d's level %d cache type %d\n", + acpi_cpu_id, level, acpi_type); + + cpu_node = acpi_find_processor_node(table_hdr, acpi_cpu_id); + if (!cpu_node) + return NULL; + + do { + found = acpi_find_cache_level(table_hdr, cpu_node, &total_levels, level, acpi_type); + *node = cpu_node; + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } while ((cpu_node) && (!found)); + + return found; +} + +int acpi_find_last_cache_level(unsigned int cpu) +{ + u32 acpi_cpu_id; + struct acpi_table_header *table; + int number_of_levels = 0; + acpi_status status; + + pr_debug("Cache Setup find last level cpu=%d\n", cpu); + + acpi_cpu_id = acpi_cpu_get_madt_gicc(cpu)->uid; + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + } else { + number_of_levels = acpi_parse_pptt(table, acpi_cpu_id); + acpi_put_table(table); + } + pr_debug("Cache Setup find last level level=%d\n", number_of_levels); + + return number_of_levels; +} + +/* + * The ACPI spec implies that the fields in the cache structures are used to + * extend and correct the information probed from the hardware. In the case + * of arm64 the CCSIDR probing has been removed because it might be incorrect. + */ +static void update_cache_properties(struct cacheinfo *this_leaf, + struct acpi_pptt_cache *found_cache, + struct acpi_pptt_processor *cpu_node) +{ + if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) + this_leaf->size = found_cache->size; + if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID) + this_leaf->coherency_line_size = found_cache->line_size; + if (found_cache->flags & ACPI_PPTT_NUMBER_OF_SETS_VALID) + this_leaf->number_of_sets = found_cache->number_of_sets; + if (found_cache->flags & ACPI_PPTT_ASSOCIATIVITY_VALID) + this_leaf->ways_of_associativity = found_cache->associativity; + if (found_cache->flags & ACPI_PPTT_WRITE_POLICY_VALID) + switch (found_cache->attributes & ACPI_PPTT_MASK_WRITE_POLICY) { + case ACPI_6_2_CACHE_POLICY_WT: + this_leaf->attributes = CACHE_WRITE_THROUGH; + break; + case ACPI_6_2_CACHE_POLICY_WB: + this_leaf->attributes = CACHE_WRITE_BACK; + break; + default: + pr_err("Unknown ACPI cache policy %d\n", + found_cache->attributes & ACPI_PPTT_MASK_WRITE_POLICY); + } + if (found_cache->flags & ACPI_PPTT_ALLOCATION_TYPE_VALID) + switch (found_cache->attributes & ACPI_PPTT_MASK_ALLOCATION_TYPE) { + case ACPI_6_2_CACHE_READ_ALLOCATE: + this_leaf->attributes |= CACHE_READ_ALLOCATE; + break; + case ACPI_6_2_CACHE_WRITE_ALLOCATE: + this_leaf->attributes |= CACHE_WRITE_ALLOCATE; + break; + case ACPI_6_2_CACHE_RW_ALLOCATE: + this_leaf->attributes |= + CACHE_READ_ALLOCATE|CACHE_WRITE_ALLOCATE; + break; + default: + pr_err("Unknown ACPI cache allocation policy %d\n", + found_cache->attributes & ACPI_PPTT_MASK_ALLOCATION_TYPE); + } +} + +static void cache_setup_acpi_cpu(struct acpi_table_header *table, + unsigned int cpu) +{ + struct acpi_pptt_cache *found_cache; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + u32 acpi_cpu_id = acpi_cpu_get_madt_gicc(cpu)->uid; + struct cacheinfo *this_leaf; + unsigned int index = 0; + struct acpi_pptt_processor *cpu_node = NULL; + + while (index < get_cpu_cacheinfo(cpu)->num_leaves) { + this_leaf = this_cpu_ci->info_list + index; + found_cache = acpi_find_cache_node(table, acpi_cpu_id, + this_leaf->type, + this_leaf->level, + &cpu_node); + pr_debug("found = %p %p\n", found_cache, cpu_node); + if (found_cache) + update_cache_properties(this_leaf, + found_cache, + cpu_node); + + index++; + } +} + +static int topology_setup_acpi_cpu(struct acpi_table_header *table, + unsigned int cpu, int level) +{ + struct acpi_pptt_processor *cpu_node; + u32 acpi_cpu_id = acpi_cpu_get_madt_gicc(cpu)->uid; + + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); + if (cpu_node) { + cpu_node = acpi_find_processor_package_id(table, cpu_node, level); + /* Only the first level has a guaranteed id */ + if (level == 0) + return cpu_node->acpi_processor_id; + return (int)((u8 *)cpu_node - (u8 *)table); + } + pr_err_once("PPTT table found, but unable to locate core for %d\n", + cpu); + return -ENOENT; +} + +/* + * simply assign a ACPI cache entry to each known CPU cache entry + * determining which entries are shared is done later. + */ +int cache_setup_acpi(unsigned int cpu) +{ + struct acpi_table_header *table; + acpi_status status; + + pr_debug("Cache Setup ACPI cpu %d\n", cpu); + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + return -ENOENT; + } + + cache_setup_acpi_cpu(table, cpu); + acpi_put_table(table); + + return status; +} + +/* + * Determine a topology unique ID for each thread/core/cluster/socket/etc. + * This ID can then be used to group peers. + */ +int setup_acpi_cpu_topology(unsigned int cpu, int level) +{ + struct acpi_table_header *table; + acpi_status status; + int retval; + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cpu topology may be inaccurate\n"); + return -ENOENT; + } + retval = topology_setup_acpi_cpu(table, cpu, level); + pr_debug("Topology Setup ACPI cpu %d, level %d ret = %d\n", + cpu, level, retval); + acpi_put_table(table); + + return retval; +} -- From patchwork Thu Oct 12 19:48:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 115673 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2309872qgn; Thu, 12 Oct 2017 12:50:41 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCaT6kWhGSNj8RWf0oH2MgALVmELqFVI9Q1z9W4o12dwzybOwEEp9LqkY8KV2wTE10g3lU7 X-Received: by 10.101.65.11 with SMTP id w11mr1086955pgp.207.1507837841855; Thu, 12 Oct 2017 12:50:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507837841; cv=none; d=google.com; s=arc-20160816; b=bgzlsM1lXe9Fte7+qpffBf++sPXTw/x1aIGVwWGYNNAdZT8BiJ5EMc3aos/DHISR+O BbXVDb/UTveB/TuKDeuewMAYj0An/m5Z2uOc788NoeZqxrITX3mwUaKQ3JWlNAV+Dk6B 5uqAarOojGvbdycEXkByz6TbVLtuRlDR09pItFoxHtQJBy1poTVElSjIQrqSAFhjBuYs mLbtZQzfJX35K3hgIABiATJ3BvrBngc+ob0VQogAZRs9kEo/T70TbUZZpWsj23ZKn8Iw AgBT9XDXsaSDlEZsCT4gNRyfb8zAYIgSII96OVpr7HzAyOj44UxFWOpBVagKtUcUvmuo YJ6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; 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[209.132.180.67]) by mx.google.com with ESMTP id h91si8792036pld.3.2017.10.12.12.50.41; Thu, 12 Oct 2017 12:50:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754161AbdJLTuj (ORCPT + 27 others); Thu, 12 Oct 2017 15:50:39 -0400 Received: from foss.arm.com ([217.140.101.70]:51644 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753174AbdJLTtH (ORCPT ); Thu, 12 Oct 2017 15:49:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1374C1610; Thu, 12 Oct 2017 12:49:07 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 373303F58C; Thu, 12 Oct 2017 12:49:06 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, Jeremy Linton Subject: [PATCH v3 2/7] ACPI: Enable PPTT support on ARM64 Date: Thu, 12 Oct 2017 14:48:51 -0500 Message-Id: <20171012194856.13844-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171012194856.13844-1-jeremy.linton@arm.com> References: <20171012194856.13844-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that we have a PPTT parser, in preparation for its use on arm64, lets build it. Signed-off-by: Jeremy Linton --- arch/arm64/Kconfig | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/arm64/Kconfig | 3 +++ 3 files changed, 5 insertions(+) -- 2.13.5 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..68c9d1289735 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -7,6 +7,7 @@ config ARM64 select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ACPI_MCFG if ACPI select ACPI_SPCR_TABLE if ACPI + select ACPI_PPTT if ACPI select ARCH_CLOCKSOURCE_DATA select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEVMEM_IS_ALLOWED diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 90265ab4437a..c92a0c937551 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_ACPI_BGRT) += bgrt.o obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_acpi.o obj-$(CONFIG_ACPI_SPCR_TABLE) += spcr.o obj-$(CONFIG_ACPI_DEBUGGER_USER) += acpi_dbg.o +obj-$(CONFIG_ACPI_PPTT) += pptt.o # processor has its own "processor." module_param namespace processor-y := processor_driver.o diff --git a/drivers/acpi/arm64/Kconfig b/drivers/acpi/arm64/Kconfig index 5a6f80fce0d6..74b855a669ea 100644 --- a/drivers/acpi/arm64/Kconfig +++ b/drivers/acpi/arm64/Kconfig @@ -7,3 +7,6 @@ config ACPI_IORT config ACPI_GTDT bool + +config ACPI_PPTT + bool \ No newline at end of file From patchwork Thu Oct 12 19:48:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 115668 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2308917qgn; Thu, 12 Oct 2017 12:49:22 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAYqxK7jP/po3raMAT/482t6Th0DAhITkE/UOSZR7ZHtmySss9CZtFpYJMp2LZMf5yZoQX1 X-Received: by 10.101.72.199 with SMTP id o7mr1100544pgs.450.1507837761915; Thu, 12 Oct 2017 12:49:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507837761; cv=none; d=google.com; s=arc-20160816; b=Y0Bkw0ECrNjdpaQxZalk0enPmlAh5zfOKSWAZqbbdTj/peOPFMX3ji8zVChPZlQYTV VLKxaEF/cuwX9/HEZ4SbgabDl801n+G6ZZdRRUrQ3ET4TWSyL3CTv0LRjrt8FgcjZyXg CPFcNlhtm8Ny7wxvjyGRtrUW1kcw74ybx02Q6usBn/RlwEpvQlqWRrWJVw6VE2g/nqFo aKaAnzFzTCFw4wzF5W3kjeSS1t/wolUlCSfIGVjwiim8sWUPynluIRm0lN1Zis4KDvUk z5dvTsgqiN9Kda9KrwbSk+0/yXMjaeBgPqozofNk7PQqGNGZ0lgBK8x0kal7QjpCdcoa 2vIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=ec4HI2UkCxRxYbbxGksjxK5br9qEOZ1exeVky+4NOGk=; b=Xg6NWbR4qAI8b24ixc/GzPj6zYgVfhItvfX27S2GsBVE0GEY1hpUwqlvyCVnLYfpM2 z81d4UFLR81GoY6h4EvLbu99toqMEn/BVN+rO/w9nEolNhvV8iFAWN+d1ACaluLacBgS bLXuJkYfDSxY55JJNBAL7zaCDIJWEQXqMAqgbev2LpgVOmAXOMgIGXjCv1qz+FFPFbsJ 3GlwzW5zAN6E5NtNtcQutDmWk9hiiZ2eqB2Cqy7Pr01dwBGdthY3THN21CTL51AjOeHA MMI4uttceNPYraAZc6ZfSrWYtGXN6OjTAbSWXw17P84ZJ4zhq5iDzjIiGBSeyTovdzls M7BQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d22si13296385pli.461.2017.10.12.12.49.21; Thu, 12 Oct 2017 12:49:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754604AbdJLTtU (ORCPT + 27 others); Thu, 12 Oct 2017 15:49:20 -0400 Received: from foss.arm.com ([217.140.101.70]:51650 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753209AbdJLTtR (ORCPT ); Thu, 12 Oct 2017 15:49:17 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00C4E164F; Thu, 12 Oct 2017 12:49:17 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 247993F58C; Thu, 12 Oct 2017 12:49:16 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, Jeremy Linton Subject: [PATCH v3 3/7] drivers: base: cacheinfo: arm64: Add support for ACPI based firmware tables Date: Thu, 12 Oct 2017 14:48:52 -0500 Message-Id: <20171012194856.13844-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171012194856.13844-1-jeremy.linton@arm.com> References: <20171012194856.13844-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The /sys cache entries should support ACPI/PPTT generated cache topology information. Lets detect ACPI systems and call an arch specific cache_setup_acpi() routine to update the hardware probed cache topology. For arm64, if ACPI is enabled, determine the max number of cache levels and populate them using a PPTT table if one is available. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cacheinfo.c | 23 ++++++++++++++++++----- drivers/acpi/pptt.c | 1 + drivers/base/cacheinfo.c | 17 +++++++++++------ include/linux/cacheinfo.h | 11 +++++++++-- 4 files changed, 39 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 380f2e2fbed5..2e2cf0d312ba 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -17,6 +17,7 @@ * along with this program. If not, see . */ +#include #include #include @@ -44,9 +45,17 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, this_leaf->type = type; } +#ifndef CONFIG_ACPI +int acpi_find_last_cache_level(unsigned int cpu) +{ + /*ACPI kernels should be built with PPTT support*/ + return 0; +} +#endif + static int __init_cache_level(unsigned int cpu) { - unsigned int ctype, level, leaves, of_level; + unsigned int ctype, level, leaves, fw_level; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { @@ -59,15 +68,19 @@ static int __init_cache_level(unsigned int cpu) leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; } - of_level = of_find_last_cache_level(cpu); - if (level < of_level) { + if (acpi_disabled) + fw_level = of_find_last_cache_level(cpu); + else + fw_level = acpi_find_last_cache_level(cpu); + + if (level < fw_level) { /* * some external caches not specified in CLIDR_EL1 * the information may be available in the device tree * only unified external caches are considered here */ - leaves += (of_level - level); - level = of_level; + leaves += (fw_level - level); + level = fw_level; } this_cpu_ci->num_levels = level; diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index c86715fed4a7..b5c6de37e328 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -355,6 +355,7 @@ static void update_cache_properties(struct cacheinfo *this_leaf, struct acpi_pptt_cache *found_cache, struct acpi_pptt_processor *cpu_node) { + this_leaf->firmware_node = cpu_node; if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) this_leaf->size = found_cache->size; if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index eb3af2739537..8eca279e50d1 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -86,7 +86,7 @@ static int cache_setup_of_node(unsigned int cpu) static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, struct cacheinfo *sib_leaf) { - return sib_leaf->of_node == this_leaf->of_node; + return sib_leaf->firmware_node == this_leaf->firmware_node; } /* OF properties to query for a given cache type */ @@ -215,6 +215,11 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, } #endif +int __weak cache_setup_acpi(unsigned int cpu) +{ + return -ENOTSUPP; +} + static int cache_shared_cpu_map_setup(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); @@ -225,11 +230,11 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) if (this_cpu_ci->cpu_map_populated) return 0; - if (of_have_populated_dt()) + if (!acpi_disabled) + ret = cache_setup_acpi(cpu); + else if (of_have_populated_dt()) ret = cache_setup_of_node(cpu); - else if (!acpi_disabled) - /* No cache property/hierarchy support yet in ACPI */ - ret = -ENOTSUPP; + if (ret) return ret; @@ -286,7 +291,7 @@ static void cache_shared_cpu_map_remove(unsigned int cpu) static void cache_override_properties(unsigned int cpu) { - if (of_have_populated_dt()) + if (acpi_disabled && of_have_populated_dt()) return cache_of_override_properties(cpu); } diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 6a524bf6a06d..d1e9b8e01981 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -36,6 +36,9 @@ enum cache_type { * @of_node: if devicetree is used, this represents either the cpu node in * case there's no explicit cache node or the cache node itself in the * device tree + * @firmware_node: Shared with of_node. When not using DT, this may contain + * pointers to other firmware based values. Particularly ACPI/PPTT + * unique values. * @disable_sysfs: indicates whether this node is visible to the user via * sysfs or not * @priv: pointer to any private data structure specific to particular @@ -64,8 +67,10 @@ struct cacheinfo { #define CACHE_ALLOCATE_POLICY_MASK \ (CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE) #define CACHE_ID BIT(4) - - struct device_node *of_node; + union { + struct device_node *of_node; + void *firmware_node; + }; bool disable_sysfs; void *priv; }; @@ -98,6 +103,8 @@ int func(unsigned int cpu) \ struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); int init_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); +int cache_setup_acpi(unsigned int cpu); +int acpi_find_last_cache_level(unsigned int cpu); const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf); From patchwork Thu Oct 12 19:48:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 115669 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2308990qgn; Thu, 12 Oct 2017 12:49:28 -0700 (PDT) X-Google-Smtp-Source: AOwi7QB+Ke6I9+fO0xfZjV2Ojrbr48mvUXYhsUNNa1XKHmNsN0Wtel84Q15jp/NWJKOgceRr+BIt X-Received: by 10.98.163.2 with SMTP id s2mr3173754pfe.242.1507837768183; Thu, 12 Oct 2017 12:49:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507837768; cv=none; d=google.com; s=arc-20160816; b=ry10MDvCcACXJysKUnnIvBlrBDAjQ/5YNWKWZ/XVWjKnk1UJpU14y8U1AX+1i2rZXn v3SH976jyhBu1j7Oc/1NErK7BBstoPXl5+Fv5fQIjghOqxHhxhvgjoFRX+SOBFzRLf68 52/CEF0CHpj4i6iT/6wke/QdfqWxb+DoN++cSe0MDVSTdWo7NElgeIVQKjqTt/0pfOoQ Fruf7oNBIQCOWRRyil9hw8sAnIRW2/IRctWIS1+jCk6bOiqoH1QOk2sR5bCpTjBxpCtn zb1vtDSiTrzXy6/1vAeIbLJjad4UROm1ShdoWnASvh+hZ5SBZHdATgvCZHQFcEEpj+pp 1eSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=2DUxrQvIEYwcW5SywAUOMliWBoVDhYzTqt5ltCgScdM=; b=vCGKT9zHG7XH8X+eM0+s40IFadskBSVshhztIGcZWhJJ7rJBko83SjIpC4sJOirp8x /wk4AfOAELnSB7y8CJe3ycDMNv/+G39bR/ec9xEcOQagN33K9RxmaqbieOjJ7nSDQlAW AJDqSYma+Ko0y6ndvIXGwK+yrOhOcnK2P+NOUKX2yYOV/uFgpseA5CY2xJPkBHLg8qha /ghDrAQAn6e2I4MTritXNYGlbe0CdMBkoOQfZ8CrLoMhpgThtxVt+NbTQGQGObRYD7Up LDKvqmvA+CknQQdFeHi71FrvrWmRh15HawopWA4rlgKFfOeAmOHiqLIFCWImUfuV6MHf 2YRA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a61si12664083plc.255.2017.10.12.12.49.27; Thu, 12 Oct 2017 12:49:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755433AbdJLTt0 (ORCPT + 27 others); Thu, 12 Oct 2017 15:49:26 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51676 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752065AbdJLTtX (ORCPT ); Thu, 12 Oct 2017 15:49:23 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF68A1650; Thu, 12 Oct 2017 12:49:22 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D343D3F58C; Thu, 12 Oct 2017 12:49:21 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, Jeremy Linton Subject: [PATCH v3 4/7] Topology: Add cluster on die macros and arm64 decoding Date: Thu, 12 Oct 2017 14:48:53 -0500 Message-Id: <20171012194856.13844-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171012194856.13844-1-jeremy.linton@arm.com> References: <20171012194856.13844-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Many modern machines have cluster on die (COD) non-uniformity as well as the traditional multi-socket architectures. Reusing the multi-socket or NUMA on die concepts for these (as arm64 does) breaks down when presented with actual multi-socket/COD machines. Similar, problems are also visible on some x86 machines so it seems appropriate to start abstracting and making these topologies visible. To start a topology_cod_id() macro is added which defaults to returning the same information as topology_physical_package_id(). Moving forward we can start to spit out the differences. For arm64, an additional package_id is added to the cpu_topology array. Initially this will be equal to the cluster_id as well. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/topology.h | 4 +++- arch/arm64/kernel/topology.c | 8 ++++++-- include/linux/topology.h | 3 +++ 3 files changed, 12 insertions(+), 3 deletions(-) -- 2.13.5 diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 8b57339823e9..bd7517960d39 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -7,13 +7,15 @@ struct cpu_topology { int thread_id; int core_id; int cluster_id; + int package_id; cpumask_t thread_sibling; cpumask_t core_sibling; }; extern struct cpu_topology cpu_topology[NR_CPUS]; -#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) +#define topology_physical_package_id(cpu) (cpu_topology[cpu].package_id) +#define topology_cod_id(cpu) (cpu_topology[cpu].cluster_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 8d48b233e6ce..9147e5b6326d 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -67,6 +67,8 @@ static int __init parse_core(struct device_node *core, int cluster_id, leaf = false; cpu = get_cpu_for_node(t); if (cpu >= 0) { + /* maintain DT cluster == package behavior */ + cpu_topology[cpu].package_id = cluster_id; cpu_topology[cpu].cluster_id = cluster_id; cpu_topology[cpu].core_id = core_id; cpu_topology[cpu].thread_id = i; @@ -88,7 +90,7 @@ static int __init parse_core(struct device_node *core, int cluster_id, core); return -EINVAL; } - + cpu_topology[cpu].package_id = cluster_id; cpu_topology[cpu].cluster_id = cluster_id; cpu_topology[cpu].core_id = core_id; } else if (leaf) { @@ -228,7 +230,7 @@ static void update_siblings_masks(unsigned int cpuid) for_each_possible_cpu(cpu) { cpu_topo = &cpu_topology[cpu]; - if (cpuid_topo->cluster_id != cpu_topo->cluster_id) + if (cpuid_topo->package_id != cpu_topo->package_id) continue; cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); @@ -273,6 +275,7 @@ void store_cpu_topology(unsigned int cpuid) MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16; } + cpuid_topo->package_id = cpuid_topo->cluster_id; pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", cpuid, cpuid_topo->cluster_id, cpuid_topo->core_id, @@ -292,6 +295,7 @@ static void __init reset_cpu_topology(void) cpu_topo->thread_id = -1; cpu_topo->core_id = 0; cpu_topo->cluster_id = -1; + cpu_topo->package_id = -1; cpumask_clear(&cpu_topo->core_sibling); cpumask_set_cpu(cpu, &cpu_topo->core_sibling); diff --git a/include/linux/topology.h b/include/linux/topology.h index cb0775e1ee4b..4660749a7303 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -184,6 +184,9 @@ static inline int cpu_to_mem(int cpu) #ifndef topology_physical_package_id #define topology_physical_package_id(cpu) ((void)(cpu), -1) #endif +#ifndef topology_cod_id /* cluster on die */ +#define topology_cod_id(cpu) topology_physical_package_id(cpu) +#endif #ifndef topology_core_id #define topology_core_id(cpu) ((void)(cpu), 0) #endif From patchwork Thu Oct 12 19:48:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 115670 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2309097qgn; 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[209.132.180.67]) by mx.google.com with ESMTP id p14si11682716pgq.601.2017.10.12.12.49.35; Thu, 12 Oct 2017 12:49:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755729AbdJLTtc (ORCPT + 27 others); Thu, 12 Oct 2017 15:49:32 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51696 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755307AbdJLTtZ (ORCPT ); Thu, 12 Oct 2017 15:49:25 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 80B0A1435; Thu, 12 Oct 2017 12:49:25 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A465F3F58C; Thu, 12 Oct 2017 12:49:24 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, Jeremy Linton Subject: [PATCH v3 5/7] arm64: Fixup users of topology_physical_package_id Date: Thu, 12 Oct 2017 14:48:54 -0500 Message-Id: <20171012194856.13844-6-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171012194856.13844-1-jeremy.linton@arm.com> References: <20171012194856.13844-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are a few arm64 specific users (cpufreq, psci, etc) which really want the cluster rather than the topology_physical_package_id(). Lets convert those users to topology_cod_id(). That way when we start differentiating the socket/cluster they will continue to behave correctly. Signed-off-by: Jeremy Linton --- drivers/cpufreq/arm_big_little.c | 2 +- drivers/firmware/psci_checker.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.13.5 diff --git a/drivers/cpufreq/arm_big_little.c b/drivers/cpufreq/arm_big_little.c index 17504129fd77..6ee69b3820de 100644 --- a/drivers/cpufreq/arm_big_little.c +++ b/drivers/cpufreq/arm_big_little.c @@ -72,7 +72,7 @@ static struct mutex cluster_lock[MAX_CLUSTERS]; static inline int raw_cpu_to_cluster(int cpu) { - return topology_physical_package_id(cpu); + return topology_cod_id(cpu); } static inline int cpu_to_cluster(int cpu) diff --git a/drivers/firmware/psci_checker.c b/drivers/firmware/psci_checker.c index 6523ce962865..a9465f5d344a 100644 --- a/drivers/firmware/psci_checker.c +++ b/drivers/firmware/psci_checker.c @@ -202,7 +202,7 @@ static int hotplug_tests(void) */ for (i = 0; i < nb_cluster; ++i) { int cluster_id = - topology_physical_package_id(cpumask_any(clusters[i])); + topology_cod_id(cpumask_any(clusters[i])); ssize_t len = cpumap_print_to_pagebuf(true, page_buf, clusters[i]); /* Remove trailing newline. */ From patchwork Thu Oct 12 19:48:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 115671 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2309234qgn; Thu, 12 Oct 2017 12:49:47 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAJn9a5TgDEcCvIzmwlGBr7sm3k4mCC3aZAIeRfJ8+gyvBQ8f40NIwCGOiHf/y8cyHuKavC X-Received: by 10.84.233.197 with SMTP id m5mr1057160pln.305.1507837787113; Thu, 12 Oct 2017 12:49:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507837787; cv=none; d=google.com; s=arc-20160816; b=Zs3/w+6oPHY18mWAGg40FznTw/Wys/foXdoPkE33h1xrw1OCkmDimEJvXwMhveUUaW 8eQZHJORxOUoNnoWl+bQUIU6c92hnts6F1obeqJ6hQtoRAl/uyCLW5pvf0JiZu+A10ic v1lBhDRa/igUU5hB05aIpy+4siTQqdqTNa5wcjfj0EWpsZrDKqeHIUE2Yaz90TJnh2lJ Lyguy6eux5Bb2GsoiWAAI145Yo38WiXuaT0rNt/tRQQZBY4TcHsHPXP/PEWxyQO8nHqN zdaaxgra4FfZZlbq+s1Zhp20jq0ngcHrF7E3KreOlFg/K9wot3H6R+Em7Zc3ApqudEuB M2jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=hmALH7v4njla2pm6RLzqxTBrjEqNrU7DCaQblOQ7gpQ=; b=jroFdVwfyBrqBUTKS4Cw9cqokiq9wOaXiTPVCgrQljspPDXRt8cZaZqJMkP0+BHM5A GfSMe8hIrDewzCROBd3a4qcIn6dbWaASOk8Y8xG+kPcesXG6P9ZOkAWqpISeLUzAosaA LVGttJKwo4kPdeC8YzT01PKmf5UPQ7YtQCkELaQ/XwH+mj1tG3UuiVNAE1tEzE6xtJ3s 2N7/Ectpq/ZrYirg8Zahsz2OSY1EezV6wzTuve4B6rdu5GCOXDNH7Pg7zJU7RIYUia4R 4i/3PQfMjJQGe3jve8mCXUoB4gQAuqP6EJrqG89ru+VroTdh9yt9wDRbeU6VZhAQtw9g FEcw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g10si10361944pgp.397.2017.10.12.12.49.46; Thu, 12 Oct 2017 12:49:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755614AbdJLTtb (ORCPT + 27 others); Thu, 12 Oct 2017 15:49:31 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51712 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755434AbdJLTt2 (ORCPT ); Thu, 12 Oct 2017 15:49:28 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 392D815BE; Thu, 12 Oct 2017 12:49:28 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5C7223F58C; Thu, 12 Oct 2017 12:49:27 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, Jeremy Linton Subject: [PATCH v3 6/7] arm64: topology: Enable ACPI/PPTT based CPU topology. Date: Thu, 12 Oct 2017 14:48:55 -0500 Message-Id: <20171012194856.13844-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171012194856.13844-1-jeremy.linton@arm.com> References: <20171012194856.13844-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Propagate the topology information from the PPTT tree to the cpu_topology array. We can get the thread id, core_id and cluster_id by assuming certain levels of the PPTT tree correspond to those concepts. The package_id is flagged in the tree and can be found by passing an arbitrary large level to setup_acpi_cpu_topology() which terminates its search when it finds an ACPI node flagged as the physical package. If the tree doesn't contain enough levels to represent all of thread/core/cod/package then the package id will be used for the missing levels. Since server/ACPI machines are more likely to be multisocket and NUMA, this patch also modifies the default clusters=sockets behavior for ACPI machines to sockets=sockets. DT machines continue to represent sockets as clusters. For ACPI machines, this results in a more normalized view of the topology. Cluster level scheduler decisions are still being made due to the "MC" level in the scheduler which has knowledge of cache sharing domains. This code is loosely based on a combination of code from: Xiongfeng Wang John Garry Jeffrey Hugo Signed-off-by: Jeremy Linton --- arch/arm64/kernel/topology.c | 54 +++++++++++++++++++++++++++++++++++++++++++- include/linux/topology.h | 1 + 2 files changed, 54 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 9147e5b6326d..42f3e7f28b2b 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -11,6 +11,7 @@ * for more details. */ +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -304,6 +306,54 @@ static void __init reset_cpu_topology(void) } } +#ifdef CONFIG_ACPI +/* + * Propagate the topology information of the processor_topology_node tree to the + * cpu_topology array. + */ +static int __init parse_acpi_topology(void) +{ + u64 is_threaded; + int cpu; + int topology_id; + /* set a large depth, to hit ACPI_PPTT_PHYSICAL_PACKAGE if one exists */ + const int max_topo = 0xFF; + + is_threaded = read_cpuid_mpidr() & MPIDR_MT_BITMASK; + + for_each_possible_cpu(cpu) { + topology_id = setup_acpi_cpu_topology(cpu, 0); + if (topology_id < 0) + return topology_id; + + if (is_threaded) { + cpu_topology[cpu].thread_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, 1); + cpu_topology[cpu].core_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, 2); + cpu_topology[cpu].cluster_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, max_topo); + cpu_topology[cpu].package_id = topology_id; + } else { + cpu_topology[cpu].thread_id = -1; + cpu_topology[cpu].core_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, 1); + cpu_topology[cpu].cluster_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, max_topo); + cpu_topology[cpu].package_id = topology_id; + } + } + return 0; +} + +#else +static int __init parse_acpi_topology(void) +{ + /*ACPI kernels should be built with PPTT support*/ + return -EINVAL; +} +#endif + void __init init_cpu_topology(void) { reset_cpu_topology(); @@ -312,6 +362,8 @@ void __init init_cpu_topology(void) * Discard anything that was parsed if we hit an error so we * don't use partial information. */ - if (of_have_populated_dt() && parse_dt_topology()) + if ((!acpi_disabled) && parse_acpi_topology()) + reset_cpu_topology(); + else if (of_have_populated_dt() && parse_dt_topology()) reset_cpu_topology(); } diff --git a/include/linux/topology.h b/include/linux/topology.h index 4660749a7303..cbf2fb13bf92 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -43,6 +43,7 @@ if (nr_cpus_node(node)) int arch_update_cpu_topology(void); +int setup_acpi_cpu_topology(unsigned int cpu, int level); /* Conform to ACPI 2.0 SLIT distance definitions */ #define LOCAL_DISTANCE 10 From patchwork Thu Oct 12 19:48:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 115672 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2309247qgn; Thu, 12 Oct 2017 12:49:48 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDtXQZ3iXmR1KFoNcsuvj4bmuzPd65z5c6zLTvdw/Ou9gvAtA4YANM/emjT01TAsdrPGP/U X-Received: by 10.101.81.198 with SMTP id i6mr1081683pgq.228.1507837788506; Thu, 12 Oct 2017 12:49:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507837788; cv=none; d=google.com; s=arc-20160816; b=R9K+NTsSJKM4KcmiE4ZLKhz0kn3VFl25hVaBr68gBoYdelVFawewjj4DjFJsu7PeRW fN8F+iy3N7LeeqaR3thrU1cpUYjW84MT1UVCe5j6QdRDjI2Wq+Zm9d5J4EFiNKTln30X gqzJ9w+G2k2EuFhU8eLT4sKZWmxi69JRlkqGZ2swGXGC+IWLqOWWLlMC8tLNU7jcDjBO 42uWt/X6sTDnfBOOlIsHE49HP7Zi7+Eqwikjt3xDiU2tMgVGz4qwQOa3jBiGZtmSCX2S W5fEJpZlZQRiobQj1+5OPxxh8Bhe73vDRWc8kbjouyNaqOEQ4dRTIqY2/biv9CgDn1fc je4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=rQ6PbTotcufi47WSUYPynWHFZfLY3uf3S6xAx7p/+68=; b=Z3bgGBdC/xAmxeh4IKUxZBHcp4X+8N934Wb9oMy80cisPK93/MAjNDgtRRLhVKshZK uaEAR1y9CQ/AKkxoDeVwD9JcfRBP/pAUY+MmWKDjs48ODhQPpj49QnPCIxT8GCIRWHoF sBTpWUyL0tnQv5eh1Fj1yMu2M9ai/vIKAAj9oUDqRRuhNDW0s9zrPRzR91DEgeu3l5sl Ww0FmSAOXGnrWsX3oPLc7BmA0/YCvbAEPH+FKcVLZHMQqutu2vEGZeJ8RgWc2AfR7SKA 4bD6d142oDLlbFcmlsXyljkjsSfKs5rx0NZ9pcCigCWGpmXvWUKEQgXYt6Tcp3xnD+Z6 PkKQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z1si11920326pgc.781.2017.10.12.12.49.48; Thu, 12 Oct 2017 12:49:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756000AbdJLTtq (ORCPT + 27 others); Thu, 12 Oct 2017 15:49:46 -0400 Received: from foss.arm.com ([217.140.101.70]:51752 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755605AbdJLTtb (ORCPT ); Thu, 12 Oct 2017 15:49:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1695C1610; Thu, 12 Oct 2017 12:49:31 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 311C83F58C; Thu, 12 Oct 2017 12:49:30 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, Jeremy Linton Subject: [PATCH v3 7/7] ACPI: Add PPTT to injectable table list Date: Thu, 12 Oct 2017 14:48:56 -0500 Message-Id: <20171012194856.13844-8-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171012194856.13844-1-jeremy.linton@arm.com> References: <20171012194856.13844-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add ACPI_SIG_PPTT to the table so initrd's can override the system topology. Suggested-by: Geoffrey Blake Signed-off-by: Jeremy Linton --- drivers/acpi/tables.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 80ce2a7d224b..6d254450115b 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -456,7 +456,8 @@ static const char * const table_sigs[] = { ACPI_SIG_SLIC, ACPI_SIG_SPCR, ACPI_SIG_SPMI, ACPI_SIG_TCPA, ACPI_SIG_UEFI, ACPI_SIG_WAET, ACPI_SIG_WDAT, ACPI_SIG_WDDT, ACPI_SIG_WDRT, ACPI_SIG_DSDT, ACPI_SIG_FADT, ACPI_SIG_PSDT, - ACPI_SIG_RSDT, ACPI_SIG_XSDT, ACPI_SIG_SSDT, NULL }; + ACPI_SIG_RSDT, ACPI_SIG_XSDT, ACPI_SIG_SSDT, ACPI_SIG_PPTT, + NULL }; #define ACPI_HEADER_SIZE sizeof(struct acpi_table_header)