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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a7sm1626682pgt.39.2017.10.13.03.40.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Oct 2017 03:40:36 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Fri, 13 Oct 2017 16:10:30 +0530 Message-Id: <1507891231-4386-1-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: Andre Przywara , Julien Grall , Stefano Stabellini Subject: [Xen-devel] [PATCH 26/27 v12] arm/xen: vpl011: Fix the slow early console SBSA UART output X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The early console output uses pl011_early_write() to write data. This function waits for BUSY bit to get cleared before writing the next byte. In the SBSA UART emulation logic, the BUSY bit was set as soon one byte was written in the FIFO and it remained set until the FIFO was emptied. This meant that the output was delayed as each character needed the BUSY to get cleared. Since the SBSA UART is getting emulated in Xen using ring buffers, it ensures that once the data is enqueued in the FIFO, it will be received by xenconsole so it is safe to set the BUSY bit only when FIFO becomes full. This will ensure that pl011_early_write() is not delayed unduly to write the data. Signed-off-by: Bhupinder Thakur --- CC: Julien Grall CC: Andre Przywara CC: Stefano Stabellini xen/arch/arm/vpl011.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index f7ddccb..0b07436 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -159,9 +159,15 @@ static void vpl011_write_data(struct domain *d, uint8_t data) { vpl011->uartfr |= TXFF; vpl011->uartris &= ~TXI; - } - vpl011->uartfr |= BUSY; + /* + * This bit is set only when FIFO becomes full. This ensures that + * the SBSA UART driver can write the early console data as fast as + * possible, without waiting for the BUSY bit to get cleared before + * writing each byte. + */ + vpl011->uartfr |= BUSY; + } vpl011->uartfr &= ~TXFE; @@ -371,11 +377,16 @@ static void vpl011_data_avail(struct domain *d) { vpl011->uartfr &= ~TXFF; vpl011->uartris |= TXI; + + /* + * Clear the BUSY bit as soon as space becomes available + * so that the SBSA UART driver can start writing more data + * without any further delay. + */ + vpl011->uartfr &= ~BUSY; + if ( out_ring_qsize == 0 ) - { - vpl011->uartfr &= ~BUSY; vpl011->uartfr |= TXFE; - } } vpl011_update_interrupt_status(d); From patchwork Fri Oct 13 10:40:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupinder Thakur X-Patchwork-Id: 115749 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp572763qgn; Fri, 13 Oct 2017 03:42:27 -0700 (PDT) X-Received: by 10.107.69.7 with SMTP id s7mr1145545ioa.108.1507891347320; Fri, 13 Oct 2017 03:42:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507891347; cv=none; d=google.com; s=arc-20160816; b=qVPhpKUeJB4uEIRl35lOQYkklhQZVnaymHmYvQJR2T32WxkZYNvPcyWte8FLkbc0hY FysOZJoGkOLO3MRegGjRMyKYmqwn9KsFtP/0bW4yeZmtry2Wf8s/dYoLokVhRX7tMn+Q QOZhqlrTZKlmD+o38OIkGVL2y6tNdGWJZZF+5vLvQwLvTt3cmIZs1pwm8ozBL5O4QKjB B7HgM6pamNH4mjV60+5FhQdOcThpv7IUzawb91nBGnkb3D3i3rT/AZ4N6vLdXuJnyfd2 IL+zDiMjsMREp8WFRnMkp8qY9WiPu0SoaSkisljBqoKN8RKi9T22vOeR/sAKuikCo0vz BR1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=dTCL7zNzmXn8TYeyN7JBcApEZXzs/8G7P4jAYfcM2JA=; b=a0i5VyJBInFsECqDcl7pyVcLqNBTTUmrZjNZJInIuYiVxf8Pe8d6VSuK1DOErTmIpX Nk8psh7SP8HrO87n903qnQYcZpO5o9S5RJZwV2tTXCQh8WF8Xnrm9d64kYvbyadSRzPM IUdtcwJ+KxZ4pNktYlogSlN4OgiI7GacX4qb4zJv9ItrG2CKtEMvvh7jl+XB/UhwZbyv MtacUNWOu7puGyw/9bEj8etDir+G6oCvmKdHkAUYscb8RxAbBGMLNG4t96s5IQ3TccLr e2fJvzBvIyb4t20Zr5fg8RDyltAFu2sMRPwmdhtzfv2KrlR8Y7OM9p7P5hW0y/DX/5ov svLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=e0+9QwOu; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a7sm1626682pgt.39.2017.10.13.03.40.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Oct 2017 03:40:39 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Fri, 13 Oct 2017 16:10:31 +0530 Message-Id: <1507891231-4386-2-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507891231-4386-1-git-send-email-bhupinder.thakur@linaro.org> References: <1507891231-4386-1-git-send-email-bhupinder.thakur@linaro.org> Cc: Andre Przywara , Julien Grall , Stefano Stabellini , Dave Martin Subject: [Xen-devel] [PATCH 27/27 v12] arm/xen: vpl011: Correct the logic for asserting/de-asserting SBSA UART TX interrupt X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" This patch fixes the issue observed when pl011 patches were tested on the junos hardware by Andre/Julien. It was observed that when large output is generated such as on running 'find /', output was getting truncated intermittently due to OUT ring buffer getting full. This issue was due to the fact that the SBSA UART driver expects that when a TX interrupt is asserted then the FIFO queue should be atleast half empty and that it can write N bytes in the FIFO, where N is half the FIFO queue size, without the bytes getting dropped due to FIFO getting full. The SBSA UART emulation logic was asserting the TX interrupt as soon as any space became available in the FIFO and the SBSA UART driver tried to write more data (upto 16 bytes) in the FIFO expecting that there is enough space available leading to dropped bytes. The SBSA spec [1] does not specify when the TX interrupt should be asserted or de-asserted. Due to lack of clarity on the expected behavior, it is assumed for now that TX interrupt should be asserted only when the FIFO goes half empty. TBD: Once the SBSA spec is updated with the expected behavior, the implementation will be modified to align with the spec requirement. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0183f/DDI0183.pdf Signed-off-by: Bhupinder Thakur --- CC: Julien Grall CC: Andre Przywara CC: Stefano Stabellini CC: Dave Martin Changes since v11: - Add a build assert to check that ring buffer size is more than minimum rx fif size of 32 - Added a comment to explain why threshold based logic is not implemented for rx fifo - Moved calls to vpl011_update_interrupt_status() near where TXI/RXI status bit is set Changes since v8: - Used variables fifo_level/fifo_threshold for more clarity - Added a new macro SBSA_UART_FIFO_SIZE instead of using a magic number - Renamed ring_qsize variables to fifo_level for consistency xen/arch/arm/vpl011.c | 113 ++++++++++++++++++++++++++++++------------- xen/include/asm-arm/vpl011.h | 2 + 2 files changed, 82 insertions(+), 33 deletions(-) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 0b07436..adf1711 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -93,24 +93,27 @@ static uint8_t vpl011_read_data(struct domain *d) */ if ( xencons_queued(in_prod, in_cons, sizeof(intf->in)) > 0 ) { + unsigned int fifo_level; + data = intf->in[xencons_mask(in_cons, sizeof(intf->in))]; in_cons += 1; smp_mb(); intf->in_cons = in_cons; + + fifo_level = xencons_queued(in_prod, in_cons, sizeof(intf->in)); + + if ( fifo_level == 0 ) + { + vpl011->uartfr |= RXFE; + vpl011->uartris &= ~RXI; + vpl011_update_interrupt_status(d); + } } else gprintk(XENLOG_ERR, "vpl011: Unexpected IN ring buffer empty\n"); - if ( xencons_queued(in_prod, in_cons, sizeof(intf->in)) == 0 ) - { - vpl011->uartfr |= RXFE; - vpl011->uartris &= ~RXI; - } - vpl011->uartfr &= ~RXFF; - vpl011_update_interrupt_status(d); - VPL011_UNLOCK(d, flags); /* @@ -122,6 +125,26 @@ static uint8_t vpl011_read_data(struct domain *d) return data; } +static void vpl011_update_tx_fifo_status(struct vpl011 *vpl011, + unsigned int fifo_level) +{ + struct xencons_interface *intf = vpl011->ring_buf; + unsigned int fifo_threshold; + + BUILD_BUG_ON(sizeof (intf->out) < SBSA_UART_FIFO_SIZE); + + /* + * Set the TXI bit only when there is space for fifo_size/2 bytes which + * is the trigger level for asserting/de-assterting the TX interrupt. + */ + fifo_threshold = sizeof(intf->out) - SBSA_UART_FIFO_SIZE/2; + + if ( fifo_level <= fifo_threshold ) + vpl011->uartris |= TXI; + else + vpl011->uartris &= ~TXI; +} + static void vpl011_write_data(struct domain *d, uint8_t data) { unsigned long flags; @@ -146,33 +169,37 @@ static void vpl011_write_data(struct domain *d, uint8_t data) if ( xencons_queued(out_prod, out_cons, sizeof(intf->out)) != sizeof (intf->out) ) { + unsigned int fifo_level; + intf->out[xencons_mask(out_prod, sizeof(intf->out))] = data; out_prod += 1; smp_wmb(); intf->out_prod = out_prod; - } - else - gprintk(XENLOG_ERR, "vpl011: Unexpected OUT ring buffer full\n"); - if ( xencons_queued(out_prod, out_cons, sizeof(intf->out)) == - sizeof (intf->out) ) - { - vpl011->uartfr |= TXFF; - vpl011->uartris &= ~TXI; + fifo_level = xencons_queued(out_prod, out_cons, sizeof(intf->out)); - /* - * This bit is set only when FIFO becomes full. This ensures that - * the SBSA UART driver can write the early console data as fast as - * possible, without waiting for the BUSY bit to get cleared before - * writing each byte. - */ - vpl011->uartfr |= BUSY; + if ( fifo_level == sizeof (intf->out) ) + { + vpl011->uartfr |= TXFF; + + /* + * This bit is set only when FIFO becomes full. This ensures that + * the SBSA UART driver can write the early console data as fast as + * possible, without waiting for the BUSY bit to get cleared before + * writing each byte. + */ + vpl011->uartfr |= BUSY; + } + + vpl011_update_tx_fifo_status(vpl011, fifo_level); + + vpl011_update_interrupt_status(d); } + else + gprintk(XENLOG_ERR, "vpl011: Unexpected OUT ring buffer full\n"); vpl011->uartfr &= ~TXFE; - vpl011_update_interrupt_status(d); - VPL011_UNLOCK(d, flags); /* @@ -344,7 +371,7 @@ static void vpl011_data_avail(struct domain *d) struct vpl011 *vpl011 = &d->arch.vpl011; struct xencons_interface *intf = vpl011->ring_buf; XENCONS_RING_IDX in_cons, in_prod, out_cons, out_prod; - XENCONS_RING_IDX in_ring_qsize, out_ring_qsize; + XENCONS_RING_IDX in_fifo_level, out_fifo_level; VPL011_LOCK(d, flags); @@ -355,28 +382,46 @@ static void vpl011_data_avail(struct domain *d) smp_rmb(); - in_ring_qsize = xencons_queued(in_prod, + in_fifo_level = xencons_queued(in_prod, in_cons, sizeof(intf->in)); - out_ring_qsize = xencons_queued(out_prod, + out_fifo_level = xencons_queued(out_prod, out_cons, sizeof(intf->out)); /* Update the uart rx state if the buffer is not empty. */ - if ( in_ring_qsize != 0 ) + if ( in_fifo_level != 0 ) { vpl011->uartfr &= ~RXFE; - if ( in_ring_qsize == sizeof(intf->in) ) + + if ( in_fifo_level == sizeof(intf->in) ) vpl011->uartfr |= RXFF; + + /* + * Currently, the RXI bit is getting set even if there is a single + * byte of data in the rx fifo. Ideally, the RXI bit should be set + * only if the rx fifo level reaches the threshold. + * + * However, since currently RX timeout interrupt is not + * implemented as there is not enough clarity in the SBSA spec, + * the guest may keep waiting for an interrupt to read more + * data. To ensure that guest reads all the data without + * any delay, the RXI interrupt is raised if there is RX data + * available without checking whether fifo level has reached + * the threshold. + * + * TBD: Once there is more clarity in the SBSA spec on whether RX + * timeout interrupt needs to be implemented, the RXI interrupt + * will be raised only when rx fifo level reaches the threshold. + */ vpl011->uartris |= RXI; } /* Update the uart tx state if the buffer is not full. */ - if ( out_ring_qsize != sizeof(intf->out) ) + if ( out_fifo_level != sizeof(intf->out) ) { vpl011->uartfr &= ~TXFF; - vpl011->uartris |= TXI; /* * Clear the BUSY bit as soon as space becomes available @@ -385,7 +430,9 @@ static void vpl011_data_avail(struct domain *d) */ vpl011->uartfr &= ~BUSY; - if ( out_ring_qsize == 0 ) + vpl011_update_tx_fifo_status(vpl011, out_fifo_level); + + if ( out_fifo_level == 0 ) vpl011->uartfr |= TXFE; } diff --git a/xen/include/asm-arm/vpl011.h b/xen/include/asm-arm/vpl011.h index 1b583da..db95ff8 100644 --- a/xen/include/asm-arm/vpl011.h +++ b/xen/include/asm-arm/vpl011.h @@ -28,6 +28,8 @@ #define VPL011_LOCK(d,flags) spin_lock_irqsave(&(d)->arch.vpl011.lock, flags) #define VPL011_UNLOCK(d,flags) spin_unlock_irqrestore(&(d)->arch.vpl011.lock, flags) +#define SBSA_UART_FIFO_SIZE 32 + struct vpl011 { void *ring_buf; struct page_info *ring_page;