From patchwork Mon Aug 17 01:46:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 253727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71103C433DF for ; Mon, 17 Aug 2020 01:53:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 481ED208E4 for ; Mon, 17 Aug 2020 01:53:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726583AbgHQBxE (ORCPT ); Sun, 16 Aug 2020 21:53:04 -0400 Received: from mo-csw-fb1516.securemx.jp ([210.130.202.172]:40022 "EHLO mo-csw-fb.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726340AbgHQBxE (ORCPT ); Sun, 16 Aug 2020 21:53:04 -0400 X-Greylist: delayed 356 seconds by postgrey-1.27 at vger.kernel.org; Sun, 16 Aug 2020 21:53:02 EDT Received: by mo-csw-fb.securemx.jp (mx-mo-csw-fb1516) id 07H1l8W8018748; Mon, 17 Aug 2020 10:47:08 +0900 Received: by mo-csw.securemx.jp (mx-mo-csw1516) id 07H1kr12014348; Mon, 17 Aug 2020 10:46:53 +0900 X-Iguazu-Qid: 34tMSeeoSi6C1n0IS4 X-Iguazu-QSIG: v=2; s=0; t=1597628813; q=34tMSeeoSi6C1n0IS4; m=O1HMk+y3T+4H2GN7jTiGHwiRJStCDWJbUBAdptc8e5s= Received: from imx2.toshiba.co.jp (imx2.toshiba.co.jp [106.186.93.51]) by relay.securemx.jp (mx-mr1513) id 07H1kqV3028136; Mon, 17 Aug 2020 10:46:52 +0900 Received: from enc01.localdomain ([106.186.93.100]) by imx2.toshiba.co.jp with ESMTP id 07H1kqJU002041; Mon, 17 Aug 2020 10:46:52 +0900 (JST) Received: from hop001.toshiba.co.jp ([133.199.164.63]) by enc01.localdomain with ESMTP id 07H1kpAx024066; Mon, 17 Aug 2020 10:46:51 +0900 From: Nobuhiro Iwamatsu To: Rob Herring , Linus Walleij , Catalin Marinas , Will Deacon Cc: punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Nobuhiro Iwamatsu Subject: [PATCH 5/8] arm64: visconti: Add initial support for Toshiba Visconti platform Date: Mon, 17 Aug 2020 10:46:29 +0900 X-TSB-HOP: ON Message-Id: <20200817014632.595898-6-nobuhiro1.iwamatsu@toshiba.co.jp> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> References: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the initial device tree files for Toshiba Visconti platform. For starters, the only SoC supported will be Visconti5 TMPV7708. https://toshiba.semicon-storage.com/ap-en/semiconductor/product/image-recognition-processors-visconti.html Signed-off-by: Nobuhiro Iwamatsu --- arch/arm64/Kconfig.platforms | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8dd05b2a925c..a9181e074e9e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -280,6 +280,13 @@ config ARCH_VEXPRESS This enables support for the ARMv8 software model (Versatile Express). +config ARCH_VISCONTI + bool "Toshiba Visconti SoC Family" + select PINCTRL + select PINCTRL_VISCONTI + help + This enables support for Toshiba Visconti SoCs Family. + config ARCH_VULCAN def_bool n From patchwork Mon Aug 17 01:46:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 253726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24940C433E1 for ; Mon, 17 Aug 2020 01:59:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0A6CC207FF for ; Mon, 17 Aug 2020 01:59:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726408AbgHQB7T (ORCPT ); Sun, 16 Aug 2020 21:59:19 -0400 Received: from mo-csw-fb1515.securemx.jp ([210.130.202.171]:49248 "EHLO mo-csw-fb.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726340AbgHQB7S (ORCPT ); Sun, 16 Aug 2020 21:59:18 -0400 Received: by mo-csw-fb.securemx.jp (mx-mo-csw-fb1515) id 07H1l9VB030355; Mon, 17 Aug 2020 10:47:09 +0900 Received: by mo-csw.securemx.jp (mx-mo-csw1514) id 07H1ksru003694; Mon, 17 Aug 2020 10:46:54 +0900 X-Iguazu-Qid: 34tMXyHquHoSQpSrfn X-Iguazu-QSIG: v=2; s=0; t=1597628814; q=34tMXyHquHoSQpSrfn; m=Dtp2XqsXjPz89Bhjdj7MHK1GNzLImtmcqumWTmOMpr8= Received: from imx12.toshiba.co.jp (imx12.toshiba.co.jp [61.202.160.132]) by relay.securemx.jp (mx-mr1510) id 07H1krVE008490; Mon, 17 Aug 2020 10:46:53 +0900 Received: from enc03.toshiba.co.jp ([106.186.93.13]) by imx12.toshiba.co.jp with ESMTP id 07H1krGl001678; Mon, 17 Aug 2020 10:46:53 +0900 (JST) Received: from hop101.toshiba.co.jp ([133.199.85.107]) by enc03.toshiba.co.jp with ESMTP id 07H1kqAk023843; Mon, 17 Aug 2020 10:46:53 +0900 From: Nobuhiro Iwamatsu To: Rob Herring , Linus Walleij , Catalin Marinas , Will Deacon Cc: punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Nobuhiro Iwamatsu Subject: [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board Date: Mon, 17 Aug 2020 10:46:30 +0900 X-TSB-HOP: ON Message-Id: <20200817014632.595898-7-nobuhiro1.iwamatsu@toshiba.co.jp> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> References: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add basic support for the Visconti TMPV7708 SoC peripherals - - CPU - CA53 x 4 and 2 cluster. - not support PSCI, currently only spin-table is supported. - Interrupt controller (ARM Generic Interrupt Controller) - Timer (ARM architected timer) - UART (ARM PL011 UART controller) - SPI (ARM PL022 SPI controller) - I2C (Synopsys DesignWare APB I2C Controller) - Pin control (Visconti specific) Signed-off-by: Nobuhiro Iwamatsu --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/toshiba/Makefile | 2 + .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 44 ++ arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 ++++++++++++++++++ .../arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 +++++ 5 files changed, 530 insertions(+) create mode 100644 arch/arm64/boot/dts/toshiba/Makefile create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f19b762c008d..c58bdab675ea 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -26,5 +26,6 @@ subdir-y += socionext subdir-y += sprd subdir-y += synaptics subdir-y += ti +subdir-y += toshiba subdir-y += xilinx subdir-y += zte diff --git a/arch/arm64/boot/dts/toshiba/Makefile b/arch/arm64/boot/dts/toshiba/Makefile new file mode 100644 index 000000000000..8cd460d5b68e --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts new file mode 100644 index 000000000000..a883d3ab1858 --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree File for TMPV7708 RM main board + * + * (C) Copyright 2020, Toshiba Corporation. + * (C) Copyright 2020, Nobuhiro Iwamatsu + */ + +/dts-v1/; + +#include "tmpv7708.dtsi" + +/ { + model = "Toshiba TMPV7708 RM main board"; + compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "earlycon=pl011,0x28200000"; + stdout-path = "serial0:115200n8"; + }; + + /* 768MB memory */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x30000000>; + }; +}; + +&uart0 { + status = "okay"; + clocks = <&uart_clk>; + clock-names = "apb_pclk"; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; + clock-names = "apb_pclk"; +}; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi new file mode 100644 index 000000000000..f78ebb707aa4 --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for the TMPV7708 + * + * (C) Copyright 2018 - 2020, Toshiba Corporation. + * (C) Copyright 2020, Nobuhiro Iwamatsu + * + */ + +#include +#include + +/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ + +/ { + compatible = "toshiba,tmpv7708"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x00>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x01>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x02>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x03>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x100>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x101>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x102>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x103>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + always-on; + interrupts = + , + , + , + ; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller@24001000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x24001000 0 0x1000>, + <0 0x24002000 0 0x2000>, + <0 0x24004000 0 0x2000>, + <0 0x24006000 0 0x2000>; + }; + + pmux: pmux@24190000 { + compatible = "toshiba,tmpv7708-pinctrl"; + reg = <0 0x24190000 0 0x10000>; + }; + + uart0: serial@28200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28200000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart_0>; + status = "disabled"; + }; + + uart1: serial@28201000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28201000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart_1>; + status = "disabled"; + }; + + uart2: serial@28202000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28202000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart_2>; + status = "disabled"; + }; + + uart3: serial@28203000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28203000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart_3>; + status = "disabled"; + }; + + i2c0: i2c@28030000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28030000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@28031000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28031000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@28032000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28032000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_2>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@28033000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28033000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_3>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@28034000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28034000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@28035000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28035000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_5>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@28036000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28036000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_6>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@28037000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28037000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_7>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@28038000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28038000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_8>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@28140000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28140000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi_0>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@28141000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28141000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi_1>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@28142000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28142000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi_2>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@28143000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28143000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi_3>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@28144000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28144000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi_4>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@28145000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28145000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi_5>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@28146000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28146000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi_6>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; + +#include "tmpv7708_pins.dtsi" diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi new file mode 100644 index 000000000000..fb630f51cfe2 --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&pmux { + spi_0: spi_0 { + function = "spi0"; + groups = "spi0_grp"; + }; + spi_1: spi_1 { + function = "spi1"; + groups = "spi1_grp"; + }; + spi_2: spi_2 { + function = "spi2"; + groups = "spi2_grp"; + }; + spi_3: spi_3 { + function = "spi3"; + groups = "spi3_grp"; + }; + spi_4: spi_4 { + function = "spi4"; + groups = "spi4_grp"; + }; + spi_5: spi_5 { + function = "spi5"; + groups = "spi5_grp"; + }; + spi_6: spi_6 { + function = "spi6"; + groups = "spi6_grp"; + }; + uart_0: uart_0 { + function = "uart0"; + groups = "uart0_grp"; + }; + uart_1: uart_1 { + function = "uart1"; + groups = "uart1_grp"; + }; + uart_2: uart_2 { + function = "uart2"; + groups = "uart2_grp"; + }; + uart_3: uart_3 { + function = "uart3"; + groups = "uart3_grp"; + }; + i2c_0: i2c_0 { + function = "i2c0"; + groups = "i2c0_grp"; + bias-pull-up; + }; + i2c_1: i2c_1 { + function = "i2c1"; + groups = "i2c1_grp"; + bias-pull-up; + }; + i2c_2: i2c_2 { + function = "i2c2"; + groups = "i2c2_grp"; + bias-pull-up; + }; + i2c_3: i2c_3 { + function = "i2c3"; + groups = "i2c3_grp"; + bias-pull-up; + }; + i2c_4: i2c_4 { + function = "i2c4"; + groups = "i2c4_grp"; + bias-pull-up; + }; + i2c_5: i2c_5 { + function = "i2c5"; + groups = "i2c5_grp"; + bias-pull-up; + }; + i2c_6: i2c_6 { + function = "i2c6"; + groups = "i2c6_grp"; + bias-pull-up; + }; + i2c_7: i2c_7 { + function = "i2c7"; + groups = "i2c7_grp"; + bias-pull-up; + }; + i2c_8: i2c_8 { + function = "i2c8"; + groups = "i2c8_grp"; + bias-pull-up; + }; +}; From patchwork Mon Aug 17 01:46:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 253724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FE58C433E1 for ; Mon, 17 Aug 2020 02:21:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B5D8208B3 for ; Mon, 17 Aug 2020 02:21:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726792AbgHQCVS (ORCPT ); Sun, 16 Aug 2020 22:21:18 -0400 Received: from mo-csw-fb1514.securemx.jp ([210.130.202.170]:60842 "EHLO mo-csw-fb.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726721AbgHQCVS (ORCPT ); Sun, 16 Aug 2020 22:21:18 -0400 Received: by mo-csw-fb.securemx.jp (mx-mo-csw-fb1514) id 07H1l81b024184; Mon, 17 Aug 2020 10:47:08 +0900 Received: by mo-csw.securemx.jp (mx-mo-csw1516) id 07H1ktob014415; Mon, 17 Aug 2020 10:46:55 +0900 X-Iguazu-Qid: 34tKNrBeFZDrgOHFHl X-Iguazu-QSIG: v=2; s=0; t=1597628815; q=34tKNrBeFZDrgOHFHl; m=mZtFY5xQ0LIQRE3feks4YvyMEmqcK0Vl5rc1pvgS8+U= Received: from imx12.toshiba.co.jp (imx12.toshiba.co.jp [61.202.160.132]) by relay.securemx.jp (mx-mr1513) id 07H1ksbL028225; Mon, 17 Aug 2020 10:46:54 +0900 Received: from enc03.toshiba.co.jp ([106.186.93.13]) by imx12.toshiba.co.jp with ESMTP id 07H1ksUQ001683; Mon, 17 Aug 2020 10:46:54 +0900 (JST) Received: from hop101.toshiba.co.jp ([133.199.85.107]) by enc03.toshiba.co.jp with ESMTP id 07H1krJM023852; Mon, 17 Aug 2020 10:46:53 +0900 From: Nobuhiro Iwamatsu To: Rob Herring , Linus Walleij , Catalin Marinas , Will Deacon Cc: punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Nobuhiro Iwamatsu Subject: [PATCH 7/8] MAINTAINERS: Add information for Toshiba Visconti ARM SoCs Date: Mon, 17 Aug 2020 10:46:31 +0900 X-TSB-HOP: ON Message-Id: <20200817014632.595898-8-nobuhiro1.iwamatsu@toshiba.co.jp> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> References: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add information about Toshiba Visconti ARM SoCs to MAINTAINERS. Signed-off-by: Nobuhiro Iwamatsu --- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4e2698cc7e23..6080196045ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2612,6 +2612,17 @@ M: Dmitry Eremin-Solenikov M: Dirk Opfer S: Maintained +ARM/TOSHIBA VISCONTI ARCHITECTURE +M: Nobuhiro Iwamatsu +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git +F: Documentation/devicetree/bindings/arm/toshiba.yaml +F: Documentation/devicetree/bindings/pinctrl/toshiba,tmpv7700-pinctrl.yaml +F: arch/arm64/boot/dts/toshiba/ +F: drivers/pinctrl/visconti/ +N: visconti + ARM/UNIPHIER ARCHITECTURE M: Masahiro Yamada L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) From patchwork Mon Aug 17 01:46:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 253723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCBE3C433E1 for ; Mon, 17 Aug 2020 02:23:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C81422087D for ; Mon, 17 Aug 2020 02:23:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726830AbgHQCXX (ORCPT ); Sun, 16 Aug 2020 22:23:23 -0400 Received: from mo-csw-fb1116.securemx.jp ([210.130.202.175]:59776 "EHLO mo-csw-fb.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726631AbgHQCXW (ORCPT ); Sun, 16 Aug 2020 22:23:22 -0400 Received: by mo-csw-fb.securemx.jp (mx-mo-csw-fb1116) id 07H1lE7e001561; Mon, 17 Aug 2020 10:47:14 +0900 Received: by mo-csw.securemx.jp (mx-mo-csw1116) id 07H1kvB2025628; Mon, 17 Aug 2020 10:46:57 +0900 X-Iguazu-Qid: 2wGqm8lBoX80FbIIin X-Iguazu-QSIG: v=2; s=0; t=1597628817; q=2wGqm8lBoX80FbIIin; m=/A+tqHrUCgHLQ3BawaUweDUm0W3W8GXHqhKi+Rydehg= Received: from imx12.toshiba.co.jp (imx12.toshiba.co.jp [61.202.160.132]) by relay.securemx.jp (mx-mr1110) id 07H1kuEU007342; Mon, 17 Aug 2020 10:46:56 +0900 Received: from enc03.toshiba.co.jp ([106.186.93.13]) by imx12.toshiba.co.jp with ESMTP id 07H1kuVN001713; Mon, 17 Aug 2020 10:46:56 +0900 (JST) Received: from hop101.toshiba.co.jp ([133.199.85.107]) by enc03.toshiba.co.jp with ESMTP id 07H1ktKw023906; Mon, 17 Aug 2020 10:46:55 +0900 From: Nobuhiro Iwamatsu To: Rob Herring , Linus Walleij , Catalin Marinas , Will Deacon Cc: punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Nobuhiro Iwamatsu Subject: [PATCH 8/8] arm64: defconfig: Enable configs for Toshiba Visconti Date: Mon, 17 Aug 2020 10:46:32 +0900 X-TSB-HOP: ON Message-Id: <20200817014632.595898-9-nobuhiro1.iwamatsu@toshiba.co.jp> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> References: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable support for the Toshiba Visconti SoCs. Signed-off-by: Nobuhiro Iwamatsu --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2ca7ba69c318..7e547812b9d5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -57,6 +57,7 @@ CONFIG_ARCH_THUNDER=y CONFIG_ARCH_THUNDER2=y CONFIG_ARCH_UNIPHIER=y CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_VISCONTI=y CONFIG_ARCH_XGENE=y CONFIG_ARCH_ZX=y CONFIG_ARCH_ZYNQMP=y