From patchwork Fri Oct 20 13:48:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 116495 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1715171qgn; Fri, 20 Oct 2017 06:50:23 -0700 (PDT) X-Received: by 10.84.205.70 with SMTP id o6mr4327491plh.350.1508507423580; Fri, 20 Oct 2017 06:50:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508507423; cv=none; d=google.com; s=arc-20160816; b=f4t8uwww0dpWef0UTkOiusqXPy4cQSupNQNbHbea9lpAV53VmuPGHSnh69ezTDOFyx KC3jw9OhVa4UQ/AjY4UsaObtVXk77THuIePXmeRGCNYxPEffWvj9dGsavs5CXx7pzVun gon/xePB+ndo3EFyu5J30ID3p0bf3Twe4z0c+r/6bJcccflqDuF1PrwDdyiap0GIU2wd FDoLhPKhekXDP7g99vL/KDFfI/rqceAe/J1fIsLDz3wiVGChyltWau7j1p5KN2KLcf8w qnv2pK8q7u4SQ6IqTWpYyYplwbN1GwGUiVlQqmaVzg5mwVPGNacYId2AXXFxJjXjrzci lNSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=mwbHEsT6NpAINH03kPMlYofQ0DZQne3tvAsXxqRKykg=; b=iEOdmPN4kFfbR/MQFBkX3hzXXnlsaGJ8wZTW+ZtZeRqTijGb5qMCWVaV0BT6cp2G5S GyrWhvyYILpv3SXWiKwYnBA5PYw4ABfbWVYzxno5p/DLV59A234XCSzG9EutW+sjsPhY MiphXgxiD30xAo5jbK3hBO8UCemLsKxSjXWL6fvtvxWhGm0/Q/0klmWfjJzxrcsys5tW xlnybh5oTCsU1i0ooWi4SvLCmpMCEjK2uWDEPwBvl8NTunfAC1OwL4pc3UKnLqBF7yBL YRJjfO4gjH8ahNbRlx1Yr5+T+iqJEwBiOOFlOkR4GG0gWpWpQRalIs2cqlyE38wb346q veRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RkZWWloX; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o7si752035pgr.606.2017.10.20.06.50.23; Fri, 20 Oct 2017 06:50:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RkZWWloX; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751589AbdJTNuW (ORCPT + 6 others); Fri, 20 Oct 2017 09:50:22 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:47366 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751582AbdJTNuW (ORCPT ); Fri, 20 Oct 2017 09:50:22 -0400 Received: by mail-lf0-f65.google.com with SMTP id k40so13281245lfi.4 for ; Fri, 20 Oct 2017 06:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=N17B4inzRvduutMgIhfzt6sP9wDhe8s21QSeEkkQg2I=; b=RkZWWloXKtZIE18yICXWLBaBUdK7Buy7+QMGyJ/7jw45KADoy7JayD6TzKim6871uY CSA9LtKKxjz9lTvCpCnsRXsC5HvgthhY4837ExsQiG3boxuTzXzCh6mZGnDNfMStaXRM rZyVBMK31jK6GmBlmZyi/LUdQX3zVZb06FQj8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=N17B4inzRvduutMgIhfzt6sP9wDhe8s21QSeEkkQg2I=; b=VLNAnRO5347t/ZwoUOm+wCWExy6aIEu81maADC98e4ghlw+Osx9MkhKBahFwTH866K 7cHVayrWQxFMjnJw68rkk9vitLgHt5sSrSC3TGc+jdMFcredanDzpnef4LMIIAgCAj+N ELTraLjLdjfmZrDeThQZWFcdMYt2I2t1BQmok1GYZuu+nUWiEtgvwsZyT+ihsvicKSpX c2CYwhRceM59nmdsWU79TERljWw4lPioAo3bprsXaubXsJZ+lciWEs6cy+uhvf0dSIIw eaaxWS1YajUadW/55zROS5b4B+YypquqZgmroRKw/lZnNfl+ST9ULmVT0PwjPWHkh6ab prOw== X-Gm-Message-State: AMCzsaVdtcZF7g5vvVwmapJkP3KBBluKLkkvkf3vJDIFHmKpQkywJhJS zuXVZpXPjaCI8TK5uqr0oPf9a9VocRQ= X-Google-Smtp-Source: ABhQp+QYYKxuMhAEUWAiYPAykSNmrX5QXbSXgzscXBdRD4tJBM/vsJDAPKZHZD72tZzEyqzPNDGIeg== X-Received: by 10.25.215.142 with SMTP id q14mr2137148lfi.25.1508507420572; Fri, 20 Oct 2017 06:50:20 -0700 (PDT) Received: from localhost.localdomain (c-5f7c71d5.014-348-6c756e10.cust.bredbandsbolaget.se. [213.113.124.95]) by smtp.gmail.com with ESMTPSA id u19sm200260lfc.89.2017.10.20.06.50.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Oct 2017 06:50:19 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Gregory Fong , Florian Fainelli Subject: [PATCH] gpio: brcmstb: Do not use gc->pin2mask() Date: Fri, 20 Oct 2017 15:48:17 +0200 Message-Id: <20171020134817.28040-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.6 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pin2mask() accessor only shuffles BIT ORDER in big endian systems, i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or bit 15 or bit 31 or so. The brcmstb only uses big endian BYTE ORDER which will be taken car of by the ->write_reg() callback. Just use BIT(offset) to assign the bit. Cc: Gregory Fong Cc: Florian Fainelli Signed-off-by: Linus Walleij --- drivers/gpio/gpio-brcmstb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Gregory Fong Reviewed-by: Florian Fainelli diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index 27e92e57adae..9b8fcca7ad17 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -20,6 +20,7 @@ #include #include #include +#include #define GIO_BANK_SIZE 0x20 #define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00) @@ -68,16 +69,15 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, { struct gpio_chip *gc = &bank->gc; struct brcmstb_gpio_priv *priv = bank->parent_priv; - u32 mask = gc->pin2mask(gc, offset); u32 imask; unsigned long flags; spin_lock_irqsave(&gc->bgpio_lock, flags); imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); if (enable) - imask |= mask; + imask |= BIT(offset); else - imask &= ~mask; + imask &= ~BIT(offset); gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); spin_unlock_irqrestore(&gc->bgpio_lock, flags); }