From patchwork Tue Aug 18 15:46:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 262354 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FF7CC433DF for ; Tue, 18 Aug 2020 15:58:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB14C2224D for ; Tue, 18 Aug 2020 15:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728324AbgHRP55 (ORCPT ); Tue, 18 Aug 2020 11:57:57 -0400 Received: from mga06.intel.com ([134.134.136.31]:18981 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728095AbgHRPqx (ORCPT ); Tue, 18 Aug 2020 11:46:53 -0400 IronPort-SDR: A4sR7TVJ2xfvtamT0mdAqY2FpaqpuA5RO50jHZOen6OPrEyuVkI1A8//e/0ZQOKGl9Tl7bod8s eFnsE+ZsOR2A== X-IronPort-AV: E=McAfee;i="6000,8403,9716"; a="216462274" X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="216462274" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 08:46:50 -0700 IronPort-SDR: 50FV8DT7Peb1MIJh8FWOPhZ0N2ZO8CKZ1Wa2q6d1vabfdfTCCwi1ZzkE0y8m+yWGozvmNp6835 KvxMYWN4zrtw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="400530198" Received: from pg-nxl3.altera.com ([10.142.129.93]) by fmsmga001.fm.intel.com with ESMTP; 18 Aug 2020 08:46:44 -0700 From: "Ooi, Joyce" To: "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Dalon Westergreen Subject: [PATCH v6 01/10] net: eth: altera: tse_start_xmit ignores tx_buffer call response Date: Tue, 18 Aug 2020 23:46:04 +0800 Message-Id: <20200818154613.148921-2-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200818154613.148921-1-joyce.ooi@intel.com> References: <20200818154613.148921-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen The return from tx_buffer call in tse_start_xmit is inapropriately ignored. tse_buffer calls should return 0 for success or NETDEV_TX_BUSY. tse_start_xmit should return not report a successful transmit when the tse_buffer call returns an error condition. In addition to the above, the msgdma and sgdma do not return the same value on success or failure. The sgdma_tx_buffer returned 0 on failure and a positive number of transmitted packets on success. Given that it only ever sends 1 packet, this made no sense. The msgdma implementation msgdma_tx_buffer returns 0 on success. -> Don't ignore the return from tse_buffer calls -> Fix sgdma tse_buffer call to return 0 on success and NETDEV_TX_BUSY on failure. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi Reviewed-by: Thor Thayer --- v2: no change v3: queue is stopped before returning NETDEV_TX_BUSY v4: no change v5: no change v6: no change --- drivers/net/ethernet/altera/altera_sgdma.c | 19 ++++++++++++------- drivers/net/ethernet/altera/altera_tse_main.c | 4 +++- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/altera/altera_sgdma.c b/drivers/net/ethernet/altera/altera_sgdma.c index db97170da8c7..fe6276c7e4a3 100644 --- a/drivers/net/ethernet/altera/altera_sgdma.c +++ b/drivers/net/ethernet/altera/altera_sgdma.c @@ -4,6 +4,7 @@ */ #include +#include #include "altera_utils.h" #include "altera_tse.h" #include "altera_sgdmahw.h" @@ -159,10 +160,11 @@ void sgdma_clear_txirq(struct altera_tse_private *priv) SGDMA_CTRLREG_CLRINT); } -/* transmits buffer through SGDMA. Returns number of buffers - * transmitted, 0 if not possible. - * - * tx_lock is held by the caller +/* transmits buffer through SGDMA. + * original behavior returned the number of transmitted packets (always 1) & + * returned 0 on error. This differs from the msgdma. the calling function + * will now actually look at the code, so from now, 0 is good and return + * NETDEV_TX_BUSY when busy. */ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer) { @@ -173,8 +175,11 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer) struct sgdma_descrip __iomem *ndesc = &descbase[1]; /* wait 'til the tx sgdma is ready for the next transmit request */ - if (sgdma_txbusy(priv)) - return 0; + if (sgdma_txbusy(priv)) { + if (!netif_queue_stopped(priv->dev)) + netif_stop_queue(priv->dev); + return NETDEV_TX_BUSY; + } sgdma_setup_descrip(cdesc, /* current descriptor */ ndesc, /* next descriptor */ @@ -191,7 +196,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer) /* enqueue the request to the pending transmit queue */ queue_tx(priv, buffer); - return 1; + return 0; } diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index 907125abef2c..ec2b36e05c3f 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -595,7 +595,9 @@ static netdev_tx_t tse_start_xmit(struct sk_buff *skb, struct net_device *dev) buffer->dma_addr = dma_addr; buffer->len = nopaged_len; - priv->dmaops->tx_buffer(priv, buffer); + ret = priv->dmaops->tx_buffer(priv, buffer); + if (ret) + goto out; skb_tx_timestamp(skb); From patchwork Tue Aug 18 15:46:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 262360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22A6DC433DF for ; Tue, 18 Aug 2020 15:47:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E58872245C for ; Tue, 18 Aug 2020 15:47:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728214AbgHRPrp (ORCPT ); Tue, 18 Aug 2020 11:47:45 -0400 Received: from mga04.intel.com ([192.55.52.120]:8521 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728153AbgHRPrM (ORCPT ); Tue, 18 Aug 2020 11:47:12 -0400 IronPort-SDR: LDzOuy/P6ioik2EGMnuyeHlqLnzZMZQzmjGtcbZeaPC/XeTbt6DPsb5qfGTdRGsKxzOkmRLiKI Lox1xo0o0SVg== X-IronPort-AV: E=McAfee;i="6000,8403,9716"; a="152345542" X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="152345542" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 08:47:11 -0700 IronPort-SDR: 5qv3GD2RoO6VHR6djUlkpNAv06/Wj5U/JiCgJZEspJjW3l6OVL/WMe016Qj9YG7Oi/j/3KwWgM AMgU3O1Bn/9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="400530251" Received: from pg-nxl3.altera.com ([10.142.129.93]) by fmsmga001.fm.intel.com with ESMTP; 18 Aug 2020 08:47:09 -0700 From: "Ooi, Joyce" To: "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Dalon Westergreen Subject: [PATCH v6 03/10] net: eth: altera: fix altera_dmaops declaration Date: Tue, 18 Aug 2020 23:46:06 +0800 Message-Id: <20200818154613.148921-4-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200818154613.148921-1-joyce.ooi@intel.com> References: <20200818154613.148921-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen The declaration of struct altera_dmaops does not have identifier names. Add identifier names to confrom with required coding styles. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi Reviewed-by: Thor Thayer --- v2: no change v3: no change v4: no change v5: no change v6: no change --- drivers/net/ethernet/altera/altera_tse.h | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h index f17acfb579a0..7d0c98fc103e 100644 --- a/drivers/net/ethernet/altera/altera_tse.h +++ b/drivers/net/ethernet/altera/altera_tse.h @@ -385,20 +385,22 @@ struct altera_tse_private; struct altera_dmaops { int altera_dtype; int dmamask; - void (*reset_dma)(struct altera_tse_private *); - void (*enable_txirq)(struct altera_tse_private *); - void (*enable_rxirq)(struct altera_tse_private *); - void (*disable_txirq)(struct altera_tse_private *); - void (*disable_rxirq)(struct altera_tse_private *); - void (*clear_txirq)(struct altera_tse_private *); - void (*clear_rxirq)(struct altera_tse_private *); - int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *); - u32 (*tx_completions)(struct altera_tse_private *); - void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *); - u32 (*get_rx_status)(struct altera_tse_private *); - int (*init_dma)(struct altera_tse_private *); - void (*uninit_dma)(struct altera_tse_private *); - void (*start_rxdma)(struct altera_tse_private *); + void (*reset_dma)(struct altera_tse_private *priv); + void (*enable_txirq)(struct altera_tse_private *priv); + void (*enable_rxirq)(struct altera_tse_private *priv); + void (*disable_txirq)(struct altera_tse_private *priv); + void (*disable_rxirq)(struct altera_tse_private *priv); + void (*clear_txirq)(struct altera_tse_private *priv); + void (*clear_rxirq)(struct altera_tse_private *priv); + int (*tx_buffer)(struct altera_tse_private *priv, + struct tse_buffer *buffer); + u32 (*tx_completions)(struct altera_tse_private *priv); + void (*add_rx_desc)(struct altera_tse_private *priv, + struct tse_buffer *buffer); + u32 (*get_rx_status)(struct altera_tse_private *priv); + int (*init_dma)(struct altera_tse_private *priv); + void (*uninit_dma)(struct altera_tse_private *priv); + void (*start_rxdma)(struct altera_tse_private *priv); }; /* This structure is private to each device. From patchwork Tue Aug 18 15:46:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 262356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95AFDC433DF for ; Tue, 18 Aug 2020 15:56:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E84220829 for ; Tue, 18 Aug 2020 15:56:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728254AbgHRP4U (ORCPT ); Tue, 18 Aug 2020 11:56:20 -0400 Received: from mga11.intel.com ([192.55.52.93]:35749 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728183AbgHRPrS (ORCPT ); Tue, 18 Aug 2020 11:47:18 -0400 IronPort-SDR: vL9FBaH0TqzJ0GQ11erL/qDWNu9Gl8TR5nz21tju0VQIm3AwwVgBUukPSIDWhddBmSi9LHVFUz yQLkUoymPlUw== X-IronPort-AV: E=McAfee;i="6000,8403,9716"; a="152563263" X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="152563263" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 08:47:18 -0700 IronPort-SDR: V2LwCJFKDxgzQb5hV91A5IeYw3Ero92nPQ+4CXQK6uEQjJ72/c3Ds8RnGIRtPtb0AlwJEGbUzw 4zaYKZhNRABg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="400530265" Received: from pg-nxl3.altera.com ([10.142.129.93]) by fmsmga001.fm.intel.com with ESMTP; 18 Aug 2020 08:47:15 -0700 From: "Ooi, Joyce" To: "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Dalon Westergreen Subject: [PATCH v6 04/10] net: eth: altera: add optional function to start tx dma Date: Tue, 18 Aug 2020 23:46:07 +0800 Message-Id: <20200818154613.148921-5-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200818154613.148921-1-joyce.ooi@intel.com> References: <20200818154613.148921-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen Allow for optional start up of tx dma if the start_txdma function is defined in altera_dmaops. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi Reviewed-by: Thor Thayer --- v2: no change v3: no change v4: no change v5: no change v6: no change --- drivers/net/ethernet/altera/altera_tse.h | 1 + drivers/net/ethernet/altera/altera_tse_main.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h index 7d0c98fc103e..26c5541fda27 100644 --- a/drivers/net/ethernet/altera/altera_tse.h +++ b/drivers/net/ethernet/altera/altera_tse.h @@ -401,6 +401,7 @@ struct altera_dmaops { int (*init_dma)(struct altera_tse_private *priv); void (*uninit_dma)(struct altera_tse_private *priv); void (*start_rxdma)(struct altera_tse_private *priv); + void (*start_txdma)(struct altera_tse_private *priv); }; /* This structure is private to each device. diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index a3749ffdcac9..0a724e4d2c8c 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -1244,6 +1244,9 @@ static int tse_open(struct net_device *dev) priv->dmaops->start_rxdma(priv); + if (priv->dmaops->start_txdma) + priv->dmaops->start_txdma(priv); + /* Start MAC Rx/Tx */ spin_lock(&priv->mac_cfg_lock); tse_set_mac(priv, true); @@ -1646,6 +1649,7 @@ static const struct altera_dmaops altera_dtype_sgdma = { .init_dma = sgdma_initialize, .uninit_dma = sgdma_uninitialize, .start_rxdma = sgdma_start_rxdma, + .start_txdma = NULL, }; static const struct altera_dmaops altera_dtype_msgdma = { @@ -1665,6 +1669,7 @@ static const struct altera_dmaops altera_dtype_msgdma = { .init_dma = msgdma_initialize, .uninit_dma = msgdma_uninitialize, .start_rxdma = msgdma_start_rxdma, + .start_txdma = NULL, }; static const struct of_device_id altera_tse_ids[] = { From patchwork Tue Aug 18 15:46:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 262357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C6CCC433E1 for ; Tue, 18 Aug 2020 15:56:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 417DA2080C for ; Tue, 18 Aug 2020 15:56:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728176AbgHRPzf (ORCPT ); Tue, 18 Aug 2020 11:55:35 -0400 Received: from mga09.intel.com ([134.134.136.24]:39885 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728210AbgHRPri (ORCPT ); Tue, 18 Aug 2020 11:47:38 -0400 IronPort-SDR: rDMOk/EgOz/1XM2qkGmleF0OyI3qUiXBP88RDOIKtEw/QtejbNjAMjboSFQ3ZquN66cwvZFU4g VkagzmHKY3Lw== X-IronPort-AV: E=McAfee;i="6000,8403,9716"; a="156017134" X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="156017134" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 08:47:35 -0700 IronPort-SDR: TcIsAB+pVGQaCeqERlAM3HnJHmp7wiLle5NwrakfWRkudd+ExkSb79C5BJY4R49Q0DJcISIAyn BL4+VzrRe0vA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="400530346" Received: from pg-nxl3.altera.com ([10.142.129.93]) by fmsmga001.fm.intel.com with ESMTP; 18 Aug 2020 08:47:32 -0700 From: "Ooi, Joyce" To: "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen Subject: [PATCH v6 06/10] net: eth: altera: Add missing identifier names to function declarations Date: Tue, 18 Aug 2020 23:46:09 +0800 Message-Id: <20200818154613.148921-7-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200818154613.148921-1-joyce.ooi@intel.com> References: <20200818154613.148921-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen The sgdma and msgdma header files included function declarations without identifier names for pointers. Add appropriate identifier names. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi Reviewed-by: Thor Thayer --- v2: this patch is added in patch version 2 v3: no change v4: no change v5: no change v6: no change --- drivers/net/ethernet/altera/altera_msgdma.h | 30 ++++++++++++++------------- drivers/net/ethernet/altera/altera_sgdma.h | 32 +++++++++++++++-------------- 2 files changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/altera/altera_msgdma.h b/drivers/net/ethernet/altera/altera_msgdma.h index 9813fbfff4d3..23f5b2a13898 100644 --- a/drivers/net/ethernet/altera/altera_msgdma.h +++ b/drivers/net/ethernet/altera/altera_msgdma.h @@ -6,19 +6,21 @@ #ifndef __ALTERA_MSGDMA_H__ #define __ALTERA_MSGDMA_H__ -void msgdma_reset(struct altera_tse_private *); -void msgdma_enable_txirq(struct altera_tse_private *); -void msgdma_enable_rxirq(struct altera_tse_private *); -void msgdma_disable_rxirq(struct altera_tse_private *); -void msgdma_disable_txirq(struct altera_tse_private *); -void msgdma_clear_rxirq(struct altera_tse_private *); -void msgdma_clear_txirq(struct altera_tse_private *); -u32 msgdma_tx_completions(struct altera_tse_private *); -void msgdma_add_rx_desc(struct altera_tse_private *, struct tse_buffer *); -int msgdma_tx_buffer(struct altera_tse_private *, struct tse_buffer *); -u32 msgdma_rx_status(struct altera_tse_private *); -int msgdma_initialize(struct altera_tse_private *); -void msgdma_uninitialize(struct altera_tse_private *); -void msgdma_start_rxdma(struct altera_tse_private *); +void msgdma_reset(struct altera_tse_private *priv); +void msgdma_enable_txirq(struct altera_tse_private *priv); +void msgdma_enable_rxirq(struct altera_tse_private *priv); +void msgdma_disable_rxirq(struct altera_tse_private *priv); +void msgdma_disable_txirq(struct altera_tse_private *priv); +void msgdma_clear_rxirq(struct altera_tse_private *priv); +void msgdma_clear_txirq(struct altera_tse_private *priv); +u32 msgdma_tx_completions(struct altera_tse_private *priv); +void msgdma_add_rx_desc(struct altera_tse_private *priv, + struct tse_buffer *buffer); +int msgdma_tx_buffer(struct altera_tse_private *priv, + struct tse_buffer *buffer); +u32 msgdma_rx_status(struct altera_tse_private *priv); +int msgdma_initialize(struct altera_tse_private *priv); +void msgdma_uninitialize(struct altera_tse_private *priv); +void msgdma_start_rxdma(struct altera_tse_private *priv); #endif /* __ALTERA_MSGDMA_H__ */ diff --git a/drivers/net/ethernet/altera/altera_sgdma.h b/drivers/net/ethernet/altera/altera_sgdma.h index 08afe1c9994f..3fb201417820 100644 --- a/drivers/net/ethernet/altera/altera_sgdma.h +++ b/drivers/net/ethernet/altera/altera_sgdma.h @@ -6,20 +6,22 @@ #ifndef __ALTERA_SGDMA_H__ #define __ALTERA_SGDMA_H__ -void sgdma_reset(struct altera_tse_private *); -void sgdma_enable_txirq(struct altera_tse_private *); -void sgdma_enable_rxirq(struct altera_tse_private *); -void sgdma_disable_rxirq(struct altera_tse_private *); -void sgdma_disable_txirq(struct altera_tse_private *); -void sgdma_clear_rxirq(struct altera_tse_private *); -void sgdma_clear_txirq(struct altera_tse_private *); -int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *); -u32 sgdma_tx_completions(struct altera_tse_private *); -void sgdma_add_rx_desc(struct altera_tse_private *priv, struct tse_buffer *); -void sgdma_status(struct altera_tse_private *); -u32 sgdma_rx_status(struct altera_tse_private *); -int sgdma_initialize(struct altera_tse_private *); -void sgdma_uninitialize(struct altera_tse_private *); -void sgdma_start_rxdma(struct altera_tse_private *); +void sgdma_reset(struct altera_tse_private *priv); +void sgdma_enable_txirq(struct altera_tse_private *priv); +void sgdma_enable_rxirq(struct altera_tse_private *priv); +void sgdma_disable_rxirq(struct altera_tse_private *priv); +void sgdma_disable_txirq(struct altera_tse_private *priv); +void sgdma_clear_rxirq(struct altera_tse_private *priv); +void sgdma_clear_txirq(struct altera_tse_private *priv); +int sgdma_tx_buffer(struct altera_tse_private *priv, + struct tse_buffer *buffer); +u32 sgdma_tx_completions(struct altera_tse_private *priv); +void sgdma_add_rx_desc(struct altera_tse_private *priv, + struct tse_buffer *buffer); +void sgdma_status(struct altera_tse_private *priv); +u32 sgdma_rx_status(struct altera_tse_private *priv); +int sgdma_initialize(struct altera_tse_private *priv); +void sgdma_uninitialize(struct altera_tse_private *priv); +void sgdma_start_rxdma(struct altera_tse_private *priv); #endif /* __ALTERA_SGDMA_H__ */ From patchwork Tue Aug 18 15:46:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 262358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5760C433DF for ; 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d="scan'208";a="400530409" Received: from pg-nxl3.altera.com ([10.142.129.93]) by fmsmga001.fm.intel.com with ESMTP; 18 Aug 2020 08:47:56 -0700 From: "Ooi, Joyce" To: "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Dalon Westergreen Subject: [PATCH v6 09/10] net: eth: altera: add msgdma prefetcher Date: Tue, 18 Aug 2020 23:46:12 +0800 Message-Id: <20200818154613.148921-10-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200818154613.148921-1-joyce.ooi@intel.com> References: <20200818154613.148921-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen Add support for the mSGDMA prefetcher. The prefetcher adds support for a linked list of descriptors in system memory. The prefetcher feeds these to the mSGDMA dispatcher. The prefetcher is configured to poll for the next descriptor in the list to be owned by hardware, then pass the descriptor to the dispatcher. It will then poll the next descriptor until it is owned by hardware. The dispatcher responses are written back to the appropriate descriptor, and the owned by hardware bit is cleared. The driver sets up a linked list twice the tx and rx ring sizes, with the last descriptor pointing back to the first. This ensures that the ring of descriptors will always have inactive descriptors preventing the prefetcher from looping over and reusing descriptors inappropriately. The prefetcher will continuously loop over these descriptors. The driver modifies descriptors as required to update the skb address and length as well as the owned by hardware bit. In addition to the above, the mSGDMA prefetcher can be used to handle rx and tx timestamps coming from the ethernet ip. These can be included in the prefetcher response in the descriptor. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi --- v2: minor fixes and suggested edits v3: queue is stopped before returning NETDEV_TX_BUSY v4: fix build warnings v5: hardcode poll_freq instead of reading from device tree and some minor edits v6: no change --- drivers/net/ethernet/altera/Makefile | 2 +- .../net/ethernet/altera/altera_msgdma_prefetcher.c | 431 +++++++++++++++++++++ .../net/ethernet/altera/altera_msgdma_prefetcher.h | 30 ++ .../ethernet/altera/altera_msgdmahw_prefetcher.h | 87 +++++ drivers/net/ethernet/altera/altera_tse.h | 14 + drivers/net/ethernet/altera/altera_tse_main.c | 40 ++ 6 files changed, 603 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.c create mode 100644 drivers/net/ethernet/altera/altera_msgdma_prefetcher.h create mode 100644 drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h diff --git a/drivers/net/ethernet/altera/Makefile b/drivers/net/ethernet/altera/Makefile index fc2e460926b3..4834e972e906 100644 --- a/drivers/net/ethernet/altera/Makefile +++ b/drivers/net/ethernet/altera/Makefile @@ -6,4 +6,4 @@ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \ altera_msgdma.o altera_sgdma.o altera_utils.o \ - intel_fpga_tod.o + intel_fpga_tod.o altera_msgdma_prefetcher.o diff --git a/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c new file mode 100644 index 000000000000..518f6e04b23b --- /dev/null +++ b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0 +/* MSGDMA Prefetcher driver for Altera ethernet devices + * + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * Author(s): + * Dalon Westergreen + */ + +#include +#include +#include +#include "altera_tse.h" +#include "altera_msgdma.h" +#include "altera_msgdmahw.h" +#include "altera_msgdma_prefetcher.h" +#include "altera_msgdmahw_prefetcher.h" +#include "altera_utils.h" + +int msgdma_pref_initialize(struct altera_tse_private *priv) +{ + struct msgdma_pref_extended_desc *rx_descs; + struct msgdma_pref_extended_desc *tx_descs; + dma_addr_t rx_descsphys; + dma_addr_t tx_descsphys; + int i; + + priv->pref_rxdescphys = (dma_addr_t)0; + priv->pref_txdescphys = (dma_addr_t)0; + + /* we need to allocate more pref descriptors than ringsize to + * prevent all of the descriptors being owned by hw. To do this + * we just allocate twice ring_size descriptors. + * rx_ring_size = priv->rx_ring_size * 2 + * tx_ring_size = priv->tx_ring_size * 2 + */ + + /* The prefetcher requires the descriptors to be aligned to the + * descriptor read/write master's data width which worst case is + * 512 bits. Currently we DO NOT CHECK THIS and only support 32-bit + * prefetcher masters. + */ + + /* allocate memory for rx descriptors */ + priv->pref_rxdesc = + dma_alloc_coherent(priv->device, + sizeof(struct msgdma_pref_extended_desc) + * priv->rx_ring_size * 2, + &priv->pref_rxdescphys, GFP_KERNEL); + + if (!priv->pref_rxdesc) + goto err_rx; + + /* allocate memory for tx descriptors */ + priv->pref_txdesc = + dma_alloc_coherent(priv->device, + sizeof(struct msgdma_pref_extended_desc) + * priv->tx_ring_size * 2, + &priv->pref_txdescphys, GFP_KERNEL); + + if (!priv->pref_txdesc) + goto err_tx; + + /* setup base descriptor ring for tx & rx */ + rx_descs = (struct msgdma_pref_extended_desc *)priv->pref_rxdesc; + tx_descs = (struct msgdma_pref_extended_desc *)priv->pref_txdesc; + tx_descsphys = priv->pref_txdescphys; + rx_descsphys = priv->pref_rxdescphys; + + /* setup RX descriptors */ + priv->pref_rx_prod = 0; + for (i = 0; i < priv->rx_ring_size * 2; i++) { + rx_descsphys = priv->pref_rxdescphys + + (((i + 1) % (priv->rx_ring_size * 2)) * + sizeof(struct msgdma_pref_extended_desc)); + rx_descs[i].next_desc_lo = lower_32_bits(rx_descsphys); + rx_descs[i].next_desc_hi = upper_32_bits(rx_descsphys); + rx_descs[i].stride = MSGDMA_DESC_RX_STRIDE; + /* burst set to 0 so it defaults to max configured */ + /* set seq number to desc number */ + rx_descs[i].burst_seq_num = i; + } + + /* setup TX descriptors */ + for (i = 0; i < priv->tx_ring_size * 2; i++) { + tx_descsphys = priv->pref_txdescphys + + (((i + 1) % (priv->tx_ring_size * 2)) * + sizeof(struct msgdma_pref_extended_desc)); + tx_descs[i].next_desc_lo = lower_32_bits(tx_descsphys); + tx_descs[i].next_desc_hi = upper_32_bits(tx_descsphys); + tx_descs[i].stride = MSGDMA_DESC_TX_STRIDE; + /* burst set to 0 so it defaults to max configured */ + /* set seq number to desc number */ + tx_descs[i].burst_seq_num = i; + } + + if (netif_msg_ifup(priv)) + netdev_info(priv->dev, "%s: RX Desc mem at 0x%llx\n", __func__, + priv->pref_rxdescphys); + + if (netif_msg_ifup(priv)) + netdev_info(priv->dev, "%s: TX Desc mem at 0x%llx\n", __func__, + priv->pref_txdescphys); + + return 0; + +err_tx: + dma_free_coherent(priv->device, + sizeof(struct msgdma_pref_extended_desc) + * priv->rx_ring_size * 2, + priv->pref_rxdesc, priv->pref_rxdescphys); +err_rx: + return -ENOMEM; +} + +void msgdma_pref_uninitialize(struct altera_tse_private *priv) +{ + if (priv->pref_rxdesc) + dma_free_coherent(priv->device, + sizeof(struct msgdma_pref_extended_desc) + * priv->rx_ring_size * 2, + priv->pref_rxdesc, priv->pref_rxdescphys); + + if (priv->pref_txdesc) + dma_free_coherent(priv->device, + sizeof(struct msgdma_pref_extended_desc) + * priv->tx_ring_size * 2, + priv->pref_txdesc, priv->pref_txdescphys); +} + +void msgdma_pref_enable_txirq(struct altera_tse_private *priv) +{ + tse_set_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_GLOBAL_INTR); +} + +void msgdma_pref_disable_txirq(struct altera_tse_private *priv) +{ + tse_clear_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_GLOBAL_INTR); +} + +void msgdma_pref_clear_txirq(struct altera_tse_private *priv) +{ + csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr, + msgdma_pref_csroffs(status)); +} + +void msgdma_pref_enable_rxirq(struct altera_tse_private *priv) +{ + tse_set_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_GLOBAL_INTR); +} + +void msgdma_pref_disable_rxirq(struct altera_tse_private *priv) +{ + tse_clear_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_GLOBAL_INTR); +} + +void msgdma_pref_clear_rxirq(struct altera_tse_private *priv) +{ + csrwr32(MSGDMA_PREF_STAT_IRQ, priv->rx_pref_csr, + msgdma_pref_csroffs(status)); +} + +static u64 timestamp_to_ns(struct msgdma_pref_extended_desc *desc) +{ + u64 ns = 0; + u64 second; + u32 tmp; + + tmp = desc->timestamp_96b[0] >> 16; + tmp |= (desc->timestamp_96b[1] << 16); + + second = desc->timestamp_96b[2]; + second <<= 16; + second |= ((desc->timestamp_96b[1] & 0xffff0000) >> 16); + + ns = second * NSEC_PER_SEC + tmp; + + return ns; +} + +/* Setup TX descriptor + * -> this should never be called when a descriptor isn't available + */ + +netdev_tx_t msgdma_pref_tx_buffer(struct altera_tse_private *priv, + struct tse_buffer *buffer) +{ + struct msgdma_pref_extended_desc *tx_descs = priv->pref_txdesc; + u32 desc_entry = priv->tx_prod % (priv->tx_ring_size * 2); + + /* if for some reason the descriptor is still owned by hardware */ + if (unlikely(tx_descs[desc_entry].desc_control + & MSGDMA_PREF_DESC_CTL_OWNED_BY_HW)) { + if (!netif_queue_stopped(priv->dev)) + netif_stop_queue(priv->dev); + return NETDEV_TX_BUSY; + } + + /* write descriptor entries */ + tx_descs[desc_entry].len = buffer->len; + tx_descs[desc_entry].read_addr_lo = lower_32_bits(buffer->dma_addr); + tx_descs[desc_entry].read_addr_hi = upper_32_bits(buffer->dma_addr); + + /* set the control bits and set owned by hw */ + tx_descs[desc_entry].desc_control = (MSGDMA_DESC_CTL_TX_SINGLE + | MSGDMA_PREF_DESC_CTL_OWNED_BY_HW); + + if (netif_msg_tx_queued(priv)) + netdev_info(priv->dev, "%s: cons: %d prod: %d", + __func__, priv->tx_cons, priv->tx_prod); + + return NETDEV_TX_OK; +} + +u32 msgdma_pref_tx_completions(struct altera_tse_private *priv) +{ + u32 desc_ringsize = priv->tx_ring_size * 2; + struct skb_shared_hwtstamps shhwtstamp; + struct msgdma_pref_extended_desc *cur; + u32 ringsize = priv->tx_ring_size; + struct tse_buffer *tx_buff; + u32 cons = priv->tx_cons; + u32 ready = 0; + u32 control; + u64 ns = 0; + int i; + + if (netif_msg_tx_done(priv)) + for (i = 0; i < desc_ringsize; i++) + netdev_info(priv->dev, "%s: desc: %d control 0x%x\n", + __func__, i, + priv->pref_txdesc[i].desc_control); + + cur = &priv->pref_txdesc[cons % desc_ringsize]; + control = cur->desc_control; + tx_buff = &priv->tx_ring[cons % ringsize]; + + while (!(control & MSGDMA_PREF_DESC_CTL_OWNED_BY_HW) && + (priv->tx_prod != (cons + ready)) && control) { + if (skb_shinfo(tx_buff->skb)->tx_flags & SKBTX_IN_PROGRESS) { + /* Timestamping is enabled, pass timestamp back */ + ns = timestamp_to_ns(cur); + memset(&shhwtstamp, 0, + sizeof(struct skb_shared_hwtstamps)); + shhwtstamp.hwtstamp = ns_to_ktime(ns); + skb_tstamp_tx(tx_buff->skb, &shhwtstamp); + } + + if (netif_msg_tx_done(priv)) + netdev_info(priv->dev, "%s: cur: %d ts: %lld ns\n", + __func__, + ((cons + ready) % desc_ringsize), ns); + + /* clear data */ + cur->desc_control = 0; + cur->timestamp_96b[0] = 0; + cur->timestamp_96b[1] = 0; + cur->timestamp_96b[2] = 0; + + ready++; + cur = &priv->pref_txdesc[(cons + ready) % desc_ringsize]; + tx_buff = &priv->tx_ring[(cons + ready) % ringsize]; + control = cur->desc_control; + } + + return ready; +} + +void msgdma_pref_reset(struct altera_tse_private *priv) +{ + int counter; + + /* turn off polling */ + tse_clear_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_DESC_POLL_EN); + tse_clear_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_DESC_POLL_EN); + + /* Reset the RX Prefetcher */ + csrwr32(MSGDMA_PREF_STAT_IRQ, priv->rx_pref_csr, + msgdma_pref_csroffs(status)); + csrwr32(MSGDMA_PREF_CTL_RESET, priv->rx_pref_csr, + msgdma_pref_csroffs(control)); + + counter = 0; + while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { + if (tse_bit_is_clear(priv->rx_pref_csr, + msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_RESET)) + break; + udelay(1); + } + + if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) + netif_warn(priv, drv, priv->dev, + "TSE Rx Prefetcher reset bit never cleared!\n"); + + /* Reset the TX Prefetcher */ + csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr, + msgdma_pref_csroffs(status)); + csrwr32(MSGDMA_PREF_CTL_RESET, priv->tx_pref_csr, + msgdma_pref_csroffs(control)); + + counter = 0; + while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { + if (tse_bit_is_clear(priv->tx_pref_csr, + msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_RESET)) + break; + udelay(1); + } + + if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) + netif_warn(priv, drv, priv->dev, + "TSE Tx Prefetcher reset bit never cleared!\n"); + + /* clear all status bits */ + csrwr32(MSGDMA_PREF_STAT_IRQ, priv->tx_pref_csr, + msgdma_pref_csroffs(status)); + + /* Reset mSGDMA dispatchers*/ + msgdma_reset(priv); +} + +/* Setup the RX and TX prefetchers to poll the descriptor chain */ +void msgdma_pref_start_rxdma(struct altera_tse_private *priv) +{ + csrwr32(priv->rx_poll_freq, priv->rx_pref_csr, + msgdma_pref_csroffs(desc_poll_freq)); + csrwr32(lower_32_bits(priv->pref_rxdescphys), priv->rx_pref_csr, + msgdma_pref_csroffs(next_desc_lo)); + csrwr32(upper_32_bits(priv->pref_rxdescphys), priv->rx_pref_csr, + msgdma_pref_csroffs(next_desc_hi)); + tse_set_bit(priv->rx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_DESC_POLL_EN | MSGDMA_PREF_CTL_RUN); +} + +void msgdma_pref_start_txdma(struct altera_tse_private *priv) +{ + csrwr32(priv->tx_poll_freq, priv->tx_pref_csr, + msgdma_pref_csroffs(desc_poll_freq)); + csrwr32(lower_32_bits(priv->pref_txdescphys), priv->tx_pref_csr, + msgdma_pref_csroffs(next_desc_lo)); + csrwr32(upper_32_bits(priv->pref_txdescphys), priv->tx_pref_csr, + msgdma_pref_csroffs(next_desc_hi)); + tse_set_bit(priv->tx_pref_csr, msgdma_pref_csroffs(control), + MSGDMA_PREF_CTL_DESC_POLL_EN | MSGDMA_PREF_CTL_RUN); +} + +/* Add MSGDMA Prefetcher Descriptor to descriptor list + * -> This should never be called when a descriptor isn't available + */ +void msgdma_pref_add_rx_desc(struct altera_tse_private *priv, + struct tse_buffer *rxbuffer) +{ + struct msgdma_pref_extended_desc *rx_descs = priv->pref_rxdesc; + u32 desc_entry = priv->pref_rx_prod % (priv->rx_ring_size * 2); + + /* write descriptor entries */ + rx_descs[desc_entry].len = priv->rx_dma_buf_sz; + rx_descs[desc_entry].write_addr_lo = lower_32_bits(rxbuffer->dma_addr); + rx_descs[desc_entry].write_addr_hi = upper_32_bits(rxbuffer->dma_addr); + + /* set the control bits and set owned by hw */ + rx_descs[desc_entry].desc_control = (MSGDMA_DESC_CTL_END_ON_EOP + | MSGDMA_DESC_CTL_END_ON_LEN + | MSGDMA_DESC_CTL_TR_COMP_IRQ + | MSGDMA_DESC_CTL_EARLY_IRQ + | MSGDMA_DESC_CTL_TR_ERR_IRQ + | MSGDMA_DESC_CTL_GO + | MSGDMA_PREF_DESC_CTL_OWNED_BY_HW); + + /* we need to keep a separate one for rx as RX_DESCRIPTORS are + * pre-configured at startup + */ + priv->pref_rx_prod++; + + if (netif_msg_rx_status(priv)) { + netdev_info(priv->dev, "%s: desc: %d buf: %d control 0x%x\n", + __func__, desc_entry, + priv->rx_prod % priv->rx_ring_size, + priv->pref_rxdesc[desc_entry].desc_control); + } +} + +u32 msgdma_pref_rx_status(struct altera_tse_private *priv) +{ + struct msgdma_pref_extended_desc *rx_descs = priv->pref_rxdesc; + u32 desc_entry = priv->rx_prod % (priv->rx_ring_size * 2); + u32 entry = priv->rx_cons % priv->rx_ring_size; + struct skb_shared_hwtstamps *shhwtstamp = NULL; + struct tse_buffer *rx_buff = priv->rx_ring; + u32 rxstatus = 0; + u32 pktlength; + u32 pktstatus; + u64 ns = 0; + + /* if the current entry is not owned by hardware, process it */ + if (!(rx_descs[desc_entry].desc_control + & MSGDMA_PREF_DESC_CTL_OWNED_BY_HW) && + rx_descs[desc_entry].desc_control) { + pktlength = rx_descs[desc_entry].bytes_transferred; + pktstatus = rx_descs[desc_entry].desc_status; + rxstatus = pktstatus; + rxstatus = rxstatus << 16; + rxstatus |= (pktlength & 0xffff); + + /* get the timestamp */ + if (priv->hwts_rx_en) { + ns = timestamp_to_ns(&rx_descs[desc_entry]); + shhwtstamp = skb_hwtstamps(rx_buff[entry].skb); + memset(shhwtstamp, 0, + sizeof(struct skb_shared_hwtstamps)); + shhwtstamp->hwtstamp = ns_to_ktime(ns); + } + + /* clear data */ + rx_descs[desc_entry].desc_control = 0; + rx_descs[desc_entry].timestamp_96b[0] = 0; + rx_descs[desc_entry].timestamp_96b[1] = 0; + rx_descs[desc_entry].timestamp_96b[2] = 0; + + if (netif_msg_rx_status(priv)) + netdev_info(priv->dev, "%s: desc: %d buf: %d ts: %lld ns", + __func__, desc_entry, entry, ns); + } + return rxstatus; +} diff --git a/drivers/net/ethernet/altera/altera_msgdma_prefetcher.h b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.h new file mode 100644 index 000000000000..6507c2805a05 --- /dev/null +++ b/drivers/net/ethernet/altera/altera_msgdma_prefetcher.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* MSGDMA Prefetcher driver for Altera ethernet devices + * + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * Author(s): + * Dalon Westergreen + */ + +#ifndef __ALTERA_PREF_MSGDMA_H__ +#define __ALTERA_PREF_MSGDMA_H__ + +void msgdma_pref_reset(struct altera_tse_private *priv); +void msgdma_pref_enable_txirq(struct altera_tse_private *priv); +void msgdma_pref_enable_rxirq(struct altera_tse_private *priv); +void msgdma_pref_disable_rxirq(struct altera_tse_private *priv); +void msgdma_pref_disable_txirq(struct altera_tse_private *priv); +void msgdma_pref_clear_rxirq(struct altera_tse_private *priv); +void msgdma_pref_clear_txirq(struct altera_tse_private *priv); +u32 msgdma_pref_tx_completions(struct altera_tse_private *priv); +void msgdma_pref_add_rx_desc(struct altera_tse_private *priv, + struct tse_buffer *buffer); +netdev_tx_t msgdma_pref_tx_buffer(struct altera_tse_private *priv, + struct tse_buffer *buffer); +u32 msgdma_pref_rx_status(struct altera_tse_private *priv); +int msgdma_pref_initialize(struct altera_tse_private *priv); +void msgdma_pref_uninitialize(struct altera_tse_private *priv); +void msgdma_pref_start_rxdma(struct altera_tse_private *priv); +void msgdma_pref_start_txdma(struct altera_tse_private *priv); + +#endif /* __ALTERA_PREF_MSGDMA_H__ */ diff --git a/drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h b/drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h new file mode 100644 index 000000000000..efda31e491ca --- /dev/null +++ b/drivers/net/ethernet/altera/altera_msgdmahw_prefetcher.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* MSGDMA Prefetcher driver for Altera ethernet devices + * + * Copyright (C) 2020 Intel Corporation. + * Contributors: + * Dalon Westergreen + * Thomas Chou + * Ian Abbott + * Yuriy Kozlov + * Tobias Klauser + * Andriy Smolskyy + * Roman Bulgakov + * Dmytro Mytarchuk + * Matthew Gerlach + */ + +#ifndef __ALTERA_MSGDMAHW_PREFETCHER_H__ +#define __ALTERA_MSGDMAHW_PREFETCHER_H__ + +/* mSGDMA prefetcher extended prefectcher descriptor format + */ +struct msgdma_pref_extended_desc { + /* data buffer source address low bits */ + u32 read_addr_lo; + /* data buffer destination address low bits */ + u32 write_addr_lo; + /* the number of bytes to transfer */ + u32 len; + /* next descriptor low address */ + u32 next_desc_lo; + /* number of bytes transferred */ + u32 bytes_transferred; + u32 desc_status; + u32 reserved_18; + /* bit 31:24 write burst */ + /* bit 23:16 read burst */ + /* bit 15:0 sequence number */ + u32 burst_seq_num; + /* bit 31:16 write stride */ + /* bit 15:0 read stride */ + u32 stride; + /* data buffer source address high bits */ + u32 read_addr_hi; + /* data buffer destination address high bits */ + u32 write_addr_hi; + /* next descriptor high address */ + u32 next_desc_hi; + /* prefetcher mod now writes these reserved bits*/ + /* Response bits [191:160] */ + u32 timestamp_96b[3]; + /* desc_control */ + u32 desc_control; +}; + +/* mSGDMA Prefetcher Descriptor Status bits */ +#define MSGDMA_PREF_DESC_STAT_STOPPED_ON_EARLY BIT(8) +#define MSGDMA_PREF_DESC_STAT_MASK 0xFF + +/* mSGDMA Prefetcher Descriptor Control bits */ +/* bit 31 and bits 29-0 are the same as the normal dispatcher ctl flags */ +#define MSGDMA_PREF_DESC_CTL_OWNED_BY_HW BIT(30) + +/* mSGDMA Prefetcher CSR */ +struct msgdma_prefetcher_csr { + u32 control; + u32 next_desc_lo; + u32 next_desc_hi; + u32 desc_poll_freq; + u32 status; +}; + +/* mSGDMA Prefetcher Control */ +#define MSGDMA_PREF_CTL_PARK BIT(4) +#define MSGDMA_PREF_CTL_GLOBAL_INTR BIT(3) +#define MSGDMA_PREF_CTL_RESET BIT(2) +#define MSGDMA_PREF_CTL_DESC_POLL_EN BIT(1) +#define MSGDMA_PREF_CTL_RUN BIT(0) + +#define MSGDMA_PREF_POLL_FREQ_MASK 0xFFFF + +/* mSGDMA Prefetcher Status */ +#define MSGDMA_PREF_STAT_IRQ BIT(0) + +#define msgdma_pref_csroffs(a) (offsetof(struct msgdma_prefetcher_csr, a)) +#define msgdma_pref_descroffs(a) (offsetof(struct msgdma_pref_extended_desc, a)) + +#endif /* __ALTERA_MSGDMAHW_PREFETCHER_H__*/ diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h index 87faecee80d2..c966b8768ed5 100644 --- a/drivers/net/ethernet/altera/altera_tse.h +++ b/drivers/net/ethernet/altera/altera_tse.h @@ -382,6 +382,7 @@ struct altera_tse_private; #define ALTERA_DTYPE_SGDMA 1 #define ALTERA_DTYPE_MSGDMA 2 +#define ALTERA_DTYPE_MSGDMA_PREF 3 /* standard DMA interface for SGDMA and MSGDMA */ struct altera_dmaops { @@ -434,6 +435,19 @@ struct altera_tse_private { void __iomem *tx_dma_csr; void __iomem *tx_dma_desc; + /* mSGDMA Rx Prefecher address space */ + void __iomem *rx_pref_csr; + struct msgdma_pref_extended_desc *pref_rxdesc; + dma_addr_t pref_rxdescphys; + u32 pref_rx_prod; + + /* mSGDMA Tx Prefecher address space */ + void __iomem *tx_pref_csr; + struct msgdma_pref_extended_desc *pref_txdesc; + dma_addr_t pref_txdescphys; + u32 rx_poll_freq; + u32 tx_poll_freq; + /* Rx buffers queue */ struct tse_buffer *rx_ring; u32 rx_cons; diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index acf9f5044c96..1cce8b2005f4 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -44,6 +44,7 @@ #include "altera_sgdma.h" #include "altera_msgdma.h" #include "intel_fpga_tod.h" +#include "altera_msgdma_prefetcher.h" static atomic_t instance_count = ATOMIC_INIT(~0); /* Module parameters */ @@ -1496,6 +1497,23 @@ static int altera_tse_probe(struct platform_device *pdev) priv->rxdescmem = resource_size(dma_res); priv->rxdescmem_busaddr = dma_res->start; + } else if (priv->dmaops && + priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA_PREF) { + /* mSGDMA Rx Prefetcher address space */ + ret = request_and_map(pdev, "rx_pref", &dma_res, + &priv->rx_pref_csr); + if (ret) + goto err_free_netdev; + + /* mSGDMA Tx Prefetcher address space */ + ret = request_and_map(pdev, "tx_pref", &dma_res, + &priv->tx_pref_csr); + if (ret) + goto err_free_netdev; + + priv->rx_poll_freq = 128; + priv->tx_poll_freq = 128; + } else { goto err_free_netdev; } @@ -1753,7 +1771,29 @@ static const struct altera_dmaops altera_dtype_msgdma = { .start_txdma = NULL, }; +static const struct altera_dmaops altera_dtype_prefetcher = { + .altera_dtype = ALTERA_DTYPE_MSGDMA_PREF, + .dmamask = 64, + .reset_dma = msgdma_pref_reset, + .enable_txirq = msgdma_pref_enable_txirq, + .enable_rxirq = msgdma_pref_enable_rxirq, + .disable_txirq = msgdma_pref_disable_txirq, + .disable_rxirq = msgdma_pref_disable_rxirq, + .clear_txirq = msgdma_pref_clear_txirq, + .clear_rxirq = msgdma_pref_clear_rxirq, + .tx_buffer = msgdma_pref_tx_buffer, + .tx_completions = msgdma_pref_tx_completions, + .add_rx_desc = msgdma_pref_add_rx_desc, + .get_rx_status = msgdma_pref_rx_status, + .init_dma = msgdma_pref_initialize, + .uninit_dma = msgdma_pref_uninitialize, + .start_rxdma = msgdma_pref_start_rxdma, + .start_txdma = msgdma_pref_start_txdma, +}; + static const struct of_device_id altera_tse_ids[] = { + { .compatible = "altr,tse-msgdma-2.0", + .data = &altera_dtype_prefetcher, }, { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, }, { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, }, { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, }, From patchwork Tue Aug 18 15:46:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 262359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3575FC433E1 for ; Tue, 18 Aug 2020 15:48:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE5A320897 for ; Tue, 18 Aug 2020 15:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728261AbgHRPsx (ORCPT ); Tue, 18 Aug 2020 11:48:53 -0400 Received: from mga14.intel.com ([192.55.52.115]:41763 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728240AbgHRPsU (ORCPT ); Tue, 18 Aug 2020 11:48:20 -0400 IronPort-SDR: sR6D3MpIZelbM6yclzF6ZdW8hDarCnm8z5qnEzitlnlXAOKasBa6RK14RNZXzK0gGlXI7zcnRx cEJjPPbfxfsw== X-IronPort-AV: E=McAfee;i="6000,8403,9716"; a="154194593" X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="154194593" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 08:48:08 -0700 IronPort-SDR: kZZ2AcB8IdQK7Yv26NjXFc0QfUWmTFCRMPNXvfbXsEHUVSTb2unZHo+IsuXOe0r6OCY4/JVrzx 4XRaPBgvjfdw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="400530454" Received: from pg-nxl3.altera.com ([10.142.129.93]) by fmsmga001.fm.intel.com with ESMTP; 18 Aug 2020 08:48:05 -0700 From: "Ooi, Joyce" To: "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Dalon Westergreen , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v6 10/10] net: eth: altera: update devicetree bindings documentation Date: Tue, 18 Aug 2020 23:46:13 +0800 Message-Id: <20200818154613.148921-11-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200818154613.148921-1-joyce.ooi@intel.com> References: <20200818154613.148921-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen Update devicetree bindings documentation to include msgdma prefetcher and ptp bindings. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi Reviewed-by: Rob Herring --- v2: no change v3: no change v4: no change v5: no change v6: no change --- .../devicetree/bindings/net/altera_tse.txt | 103 +++++++++++++++++---- 1 file changed, 84 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt index 0b7d4d3758ea..2f2d12603907 100644 --- a/Documentation/devicetree/bindings/net/altera_tse.txt +++ b/Documentation/devicetree/bindings/net/altera_tse.txt @@ -2,53 +2,86 @@ Required properties: - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should - be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE. + be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE, + and "altr,tse-msgdma-2.0" for MSGDMA with prefetcher based + implementations. ALTR is supported for legacy device trees, but is deprecated. altr should be used for all new designs. - reg: Address and length of the register set for the device. It contains the information of registers in the same order as described by reg-names - reg-names: Should contain the reg names - "control_port": MAC configuration space region - "tx_csr": xDMA Tx dispatcher control and status space region - "tx_desc": MSGDMA Tx dispatcher descriptor space region - "rx_csr" : xDMA Rx dispatcher control and status space region - "rx_desc": MSGDMA Rx dispatcher descriptor space region - "rx_resp": MSGDMA Rx dispatcher response space region - "s1": SGDMA descriptor memory - interrupts: Should contain the TSE interrupts and it's mode. - interrupt-names: Should contain the interrupt names - "rx_irq": xDMA Rx dispatcher interrupt - "tx_irq": xDMA Tx dispatcher interrupt + "rx_irq": DMA Rx dispatcher interrupt + "tx_irq": DMA Tx dispatcher interrupt - rx-fifo-depth: MAC receive FIFO buffer depth in bytes - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes - phy-mode: See ethernet.txt in the same directory. - phy-handle: See ethernet.txt in the same directory. - phy-addr: See ethernet.txt in the same directory. A configuration should include phy-handle or phy-addr. -- altr,has-supplementary-unicast: - If present, TSE supports additional unicast addresses. - Otherwise additional unicast addresses are not supported. -- altr,has-hash-multicast-filter: - If present, TSE supports a hash based multicast filter. - Otherwise, hash-based multicast filtering is not supported. - - mdio device tree subnode: When the TSE has a phy connected to its local mdio, there must be device tree subnode with the following required properties: - - compatible: Must be "altr,tse-mdio". - #address-cells: Must be <1>. - #size-cells: Must be <0>. For each phy on the mdio bus, there must be a node with the following fields: - - reg: phy id used to communicate to phy. - device_type: Must be "ethernet-phy". The MAC address will be determined using the optional properties defined in ethernet.txt. +- altr,has-supplementary-unicast: + If present, TSE supports additional unicast addresses. + Otherwise additional unicast addresses are not supported. +- altr,has-hash-multicast-filter: + If present, TSE supports a hash based multicast filter. + Otherwise, hash-based multicast filtering is not supported. +- altr,has-ptp: + If present, TSE supports 1588 timestamping. Currently only + supported with the msgdma prefetcher. +- altr,tx-poll-cnt: + Optional cycle count for Tx prefetcher to poll descriptor + list. If not present, defaults to 128, which at 125MHz is + roughly 1usec. Only for "altr,tse-msgdma-2.0". +- altr,rx-poll-cnt: + Optional cycle count for Tx prefetcher to poll descriptor + list. If not present, defaults to 128, which at 125MHz is + roughly 1usec. Only for "altr,tse-msgdma-2.0". + +Required registers by compatibility string: + - "altr,tse-1.0" + "control_port": MAC configuration space region + "tx_csr": DMA Tx dispatcher control and status space region + "rx_csr" : DMA Rx dispatcher control and status space region + "s1": DMA descriptor memory + + - "altr,tse-msgdma-1.0" + "control_port": MAC configuration space region + "tx_csr": DMA Tx dispatcher control and status space region + "tx_desc": DMA Tx dispatcher descriptor space region + "rx_csr" : DMA Rx dispatcher control and status space region + "rx_desc": DMA Rx dispatcher descriptor space region + "rx_resp": DMA Rx dispatcher response space region + + - "altr,tse-msgdma-2.0" + "control_port": MAC configuration space region + "tx_csr": DMA Tx dispatcher control and status space region + "tx_pref": DMA Tx prefetcher configuration space region + "rx_csr" : DMA Rx dispatcher control and status space region + "rx_pref": DMA Rx prefetcher configuration space region + "tod_ctrl": Time of Day Control register only required when + timestamping support is enabled. Timestamping is + only supported with the msgdma-2.0 implementation. + +Optional properties: +- local-mac-address: See ethernet.txt in the same directory. +- max-frame-size: See ethernet.txt in the same directory. + Example: tse_sub_0_eth_tse_0: ethernet@1,00000000 { @@ -86,6 +119,11 @@ Example: device_type = "ethernet-phy"; }; + phy2: ethernet-phy@2 { + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; }; @@ -111,3 +149,30 @@ Example: altr,has-hash-multicast-filter; phy-handle = <&phy1>; }; + + + tse_sub_2_eth_tse_0: ethernet@1,00002000 { + compatible = "altr,tse-msgdma-2.0"; + reg = <0x00000001 0x00002000 0x00000400>, + <0x00000001 0x00002400 0x00000020>, + <0x00000001 0x00002420 0x00000020>, + <0x00000001 0x00002440 0x00000020>, + <0x00000001 0x00002460 0x00000020>, + <0x00000001 0x00002480 0x00000040>; + reg-names = "control_port", "rx_csr", "rx_pref","tx_csr", "tx_pref", "tod_ctrl"; + interrupt-parent = <&hps_0_arm_gic_0>; + interrupts = <0 45 4>, <0 44 4>; + interrupt-names = "rx_irq", "tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + address-bits = <48>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "sgmii"; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + altr,has-ptp; + altr,tx-poll-cnt = <128>; + altr,rx-poll-cnt = <32>; + phy-handle = <&phy2>; + };