From patchwork Tue Oct 24 15:51:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116963 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5915067qgn; Tue, 24 Oct 2017 08:07:33 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SVetEu9QNaktiz3+OoCnbh1SL+qVcnPtbTw1g4tY5x3mVbOL+NTKKj+sSSbgbBplj9Lp9k X-Received: by 10.101.69.74 with SMTP id x10mr15038972pgr.294.1508857653856; Tue, 24 Oct 2017 08:07:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857653; cv=none; d=google.com; s=arc-20160816; b=biOkFXpVyREzzJ35BRxCLAVZ3Zw299jGesT0AEb3Li1IcK/hgTnfY1mz6at1gNf8lc WJQ112se9cdRJhKhyUn4ushGNIHVUMP1FuZA+TSoGPA1kWWd4WVI6qziKpobj3snJXP8 2VufBjwWxQ66Hsq8W74AJCl4nbRHWhdeWLQrmKql/C3eZYIabChxezCmImFOXdnMP61t I27J8/d6l0dug8+W4AVK/ug6ULjYtg4NbhpACVAlJhlkEmif71Qc9XG9eboj4E1mWbFg m7ishxbYlDnoozP/j4O5Uu3zWoA2c4phap3v7rkpuVs8yXVFERs28/4sZj/5hkqUGEeV 1p2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=2M2yNGnX9cftpytvY1miHogAdzl4SoLju96q61an7j4=; b=bgzsVe0EOI2oHVkJkO2leHubmskKazLA3q7q8efd/sPAPb1Vpu1ssTr/79WM/ahIhz 5zzSwd7VELdMZRTfWgxpxOi1QuwLfmFPR9WFm6e/SdKv5ysOfrKBvbcofyGXJ4R/3Eow CbQ0bAgoogy5ZTxLAPmT1vzBw6+JqujUsbMs1WGIcF+o9pK28oIxC/8Knx+Ey+jAzuzI 7ogtuvoq0a7Wr2n136t/Cr+rSS2wrgns/GdklsW+qxTZWCxPKoyZVYXlOBKLnHHEpDzW NHfhiUAAa+p+7QYDLATsyTS19iJb6fL9A4x/aqEKb4cgN0H4g50r+/gam1tYcHixeB0t LglA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b187si336900pfg.335.2017.10.24.08.07.33; Tue, 24 Oct 2017 08:07:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932416AbdJXPHc (ORCPT + 27 others); Tue, 24 Oct 2017 11:07:32 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50507 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751343AbdJXPF2 (ORCPT ); Tue, 24 Oct 2017 11:05:28 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id D8FD8A0941C46; Tue, 24 Oct 2017 23:05:22 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:15 +0800 From: John Garry To: , CC: , , , , Xiang Chen , John Garry Subject: [PATCH 01/19] scsi: hisi_sas: delete get_ncq_tag_v3_hw() Date: Tue, 24 Oct 2017 23:51:31 +0800 Message-ID: <1508860309-212397-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen We already relocated hisi_sas_get_ncq_tag() into common file main.c, so delete get_ncq_tag_v3_hw() and use hisi_sas_get_ncq_tag() instead. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 2e5fa97..d60501f 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -988,20 +988,6 @@ static int prep_smp_v3_hw(struct hisi_hba *hisi_hba, return rc; } -static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag) -{ - struct ata_queued_cmd *qc = task->uldd_task; - - if (qc) { - if (qc->tf.command == ATA_CMD_FPDMA_WRITE || - qc->tf.command == ATA_CMD_FPDMA_READ) { - *tag = qc->tag; - return 1; - } - } - return 0; -} - static int prep_ata_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { @@ -1050,7 +1036,7 @@ static int prep_ata_v3_hw(struct hisi_hba *hisi_hba, hdr->dw1 = cpu_to_le32(dw1); /* dw2 */ - if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) { + if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; } From patchwork Tue Oct 24 15:51:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116956 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5913176qgn; Tue, 24 Oct 2017 08:06:00 -0700 (PDT) X-Google-Smtp-Source: ABhQp+R4TjSy6Nqh5YqEVx4auRoFfCpjRioYEf/wqC1fwT+oTtxODo+oFB+DKO8laGXVmXh0rDsp X-Received: by 10.101.92.66 with SMTP id v2mr12414341pgr.151.1508857560642; Tue, 24 Oct 2017 08:06:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857560; cv=none; d=google.com; s=arc-20160816; b=A4X7xO2SIg2V+mFb0ejYm0HvdRNKt1mqzRUyFGTal0lFTgtTc7SHb8fs+Li95cDjbq WFL6HhCEd1xChSKybk/WMCWWpb334J9DUJPGDVIf/WoSA1nIZei0Mmrom81ZAcyDmwOJ em0nqsX3jgWhrIq5fJ+qtavU7yZN5zr1nADtG1dCLPr+ZurXjO8lj6mpT+oqNID7tMfQ tiUHoyh0LThys+qMVXogucS64OTy98dV0fjnxabIlTgoDlso7xcCYS+HBnDmQuLxCgex ZT/oK2cqRvf3HOUE5KQine3gkdI7l+4JyAVw03uApN/qgay6sQ6zKZg8PTVcP90OwP2U fN/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=j/6MfGOsat2pDSCP3t6PtjIyNjBdnOR5aYMiu3uJQGE=; b=GJISxKEKomYp4KbqQX1LBmH/Xga1Ppj6Dj/mDo+UtqPNqloe7HlrpBlExzmJsFXCK8 gdoqn0jWzNvvObo/qhfzEkalaTfRqef546EHThTXdTo0KmFfWuuTJvYsOs8I55OMK66H p8MubF32HkrYlvYKf5JPsqiv9/AlxBhN+0LQlcirvGGABfEomFFKPjyqXFYsMIzd0qUz vENhJ4GcrGYjyf1H3777h5fiJb/DGiIEDCLdfP5xpcceqXQeb97bvoFLr6vkRvMouLea 73tap+XEH16aaLx1FYIeXr6Wrd7ibv4r/mZgg8LWtReS5/kbtH0Ji5VJoPrRiEbW5Q+I y3OA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m68si323969pfm.585.2017.10.24.08.06.00; Tue, 24 Oct 2017 08:06:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751854AbdJXPF6 (ORCPT + 27 others); Tue, 24 Oct 2017 11:05:58 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50596 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932221AbdJXPFa (ORCPT ); Tue, 24 Oct 2017 11:05:30 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6C1AF50470BB4; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:15 +0800 From: John Garry To: , CC: , , , , Xiang Chen , John Garry Subject: [PATCH 02/19] scsi: hisi_sas: fix internal abort slot timeout bug Date: Tue, 24 Oct 2017 23:51:32 +0800 Message-ID: <1508860309-212397-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen When an internal abort times out in hisi_sas_internal_task_abort(), goto the exit label in and not go through the other task status checks. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 9e29902..0eb9174 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1469,6 +1469,7 @@ static int hisi_sas_query_task(struct sas_task *task) if (slot) slot->task = NULL; dev_err(dev, "internal task abort: timeout.\n"); + goto exit; } } From patchwork Tue Oct 24 15:51:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116960 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5914097qgn; Tue, 24 Oct 2017 08:06:44 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SIA3ViRUwfmtnmKP0vdhksjzcO55ZAIrY39jAA33DS3Spa2Kh9iHjQBTaJ2GlAU1dtHEdm X-Received: by 10.84.241.129 with SMTP id b1mr13509480pll.103.1508857604731; Tue, 24 Oct 2017 08:06:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857604; cv=none; d=google.com; s=arc-20160816; b=rn63VHc1mu1JBBWzs0yfcuQAd6i+a/89wolQIXJjm98GSppOk5yVNJ8YMQSNAlnWj/ surU7RVWg0eOeRzfN4lSng8KFuJR3LGtzol3MvV6kkqHxFYCFfF5z27KW9CdrOvj5xZ/ qlvyZDI9ulQjqxedo4v5UJIwE9A9zFiSGmNaoF90mqiXq5jmXa+CnzUoWgH1/HcZTbGC S4y2lkRbnB8Q4oWI0LxvmzQvQ0+avKb4CTw3J0oKw9vYQ+XEWd3DppWyWEnGqOahPsIs nwa+Pao4tj/d0g6jz7Al7iLa0EzyjWoVUXI1w8M0eIuftZBZz4AgDvZ0yG22wQ/PEnye 94Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=LWAIM4b75llGqP9qNTry68T/lgapfSrlMMcGs4Xqbgg=; b=vajqPdKWup8obh7aeYzsppJYRvu9nbIIruTqwmQNjd/8KQ8a3aLyzKMB6pT7lN9Ms7 Ax/rx4uu2U3eP0j/zpZHCmp1Vc5LrauRO0Nu03I5H2B2MKE4psfaGsCdx6TCM8w5LMsU VbhmSvDnwixxk+uJ811vin8C3eK5C2Kqk/6obGQQlaun8eOqn+zokMBENm4gTuFSFpAB qmug3iQ0uEse03aJtndiN0DRF80kvyRD/YsOiK/jukvZxPTmCpGqkZb7ZWiWt6maSpP1 S2bMBjcM97uNqmTncEjYB9IRD+9ReLaf+nEcQ6JBrWTkIIwT3zXwUC0VofG446ftNFSy LWkw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n10si262866plp.150.2017.10.24.08.06.44; Tue, 24 Oct 2017 08:06:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932379AbdJXPGn (ORCPT + 27 others); Tue, 24 Oct 2017 11:06:43 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50580 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751705AbdJXPF3 (ORCPT ); Tue, 24 Oct 2017 11:05:29 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 5D72D4404433C; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:15 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 03/19] scsi: hisi_sas: use spin_lock_irqsave() for hisi_hba.lock Date: Tue, 24 Oct 2017 23:51:33 +0800 Message-ID: <1508860309-212397-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan We used spin_lock() to grab hisi_hba.lock in two places where spin_lock_irqsave() should be used, as hisi_hba.lock can be taken in interrupt context. This patch is to fix this. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 5 +++-- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 0eb9174..e038bdf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -505,9 +505,10 @@ static struct hisi_sas_device *hisi_sas_alloc_dev(struct domain_device *device) { struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); struct hisi_sas_device *sas_dev = NULL; + unsigned long flags; int i; - spin_lock(&hisi_hba->lock); + spin_lock_irqsave(&hisi_hba->lock, flags); for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) { if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { int queue = i % hisi_hba->queue_count; @@ -524,7 +525,7 @@ static struct hisi_sas_device *hisi_sas_alloc_dev(struct domain_device *device) break; } } - spin_unlock(&hisi_hba->lock); + spin_unlock_irqrestore(&hisi_hba->lock, flags); return sas_dev; } diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 779af97..73d12ff 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -843,8 +843,9 @@ hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) struct hisi_sas_device *sas_dev = NULL; int i, sata_dev = dev_is_sata(device); int sata_idx = -1; + unsigned long flags; - spin_lock(&hisi_hba->lock); + spin_lock_irqsave(&hisi_hba->lock, flags); if (sata_dev) if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx)) @@ -874,7 +875,7 @@ hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) } out: - spin_unlock(&hisi_hba->lock); + spin_unlock_irqrestore(&hisi_hba->lock, flags); return sas_dev; } From patchwork Tue Oct 24 15:51:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116954 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5912652qgn; Tue, 24 Oct 2017 08:05:35 -0700 (PDT) X-Google-Smtp-Source: ABhQp+T9PVRfD4e26v4ZwcVO93pC+T8ZC9gPGPnU6diZB3xzNHbLlUstbaMkm+1MUD3RYcOBvLiR X-Received: by 10.101.71.197 with SMTP id f5mr14705922pgs.266.1508857535848; Tue, 24 Oct 2017 08:05:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857535; cv=none; d=google.com; s=arc-20160816; b=NleZWVAWi2Q+hA4aU9x1CIDSTsgPAZ4C4Jd9gbEp8QGfxzdDXwJ1y1zW208ZbumgYV YX01pRfoEgsJZH3e4XCjnfbgtYMHCz96KzmpITLaBnunZXF/1546uVz32MH6tzz52CT4 mm6gMb9qyKVWr2C8q7DAiPzzNH4IYRXAB5O2BkR72mYa7eeb+q5CWP5wpN9SsNgNoO7N siQ1ypCaUycIk8N1RQgx8NYg9b/Yuvd64N8m5Wga1/Wm9lo05Ebxn7xrAd3+ZWriNdv0 7A70IAZva7GU2Ud9TL9SssI0Thhp+M4xUZGO5LKqtOrlYF16y0ek4E13kA6RnpxYJo1r 4Xng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=zP1GPofjFAp1WAF8JbeMzRFQRQPocXQSvsCsTUcH8To=; b=MyGhP/JOoSmHO3ECXLYguIToIeRyTyxMy2+t03mHSksAiVVFfRflmFuJAXpps/w4Lk AXioaCKr2rHXi8drc3RLe6k5AULK9jG8WGpvq8eoRmz6qlQRLhApmqtEW1YtJ5vXgTmS hOGc4PqaezBL+MZ2fv3ycut+GrMUj9ABmGUjclmMKzHMTnch+bc6iZuzUX24quD7+7Zi fogvNwAHGjplS78BRY4/kFuKNb55IO+oouIt25tuFTyybVrlIDQYW/qC/dqUD4BFhIq3 RcxzM/B1TIkHTqX07AVkiNC9VmlhZUVqCGeYxzTtUueivIeU7MfYGcSIpF2H8Vmx1FiS N00A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f26si344004pff.119.2017.10.24.08.05.35; Tue, 24 Oct 2017 08:05:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932297AbdJXPFc (ORCPT + 27 others); Tue, 24 Oct 2017 11:05:32 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50516 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751354AbdJXPF1 (ORCPT ); Tue, 24 Oct 2017 11:05:27 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 015D2E98343FF; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:16 +0800 From: John Garry To: , CC: , , , , Xiang Chen , John Garry Subject: [PATCH 04/19] scsi: hisi_sas: grab hisi_hba.lock when processing slots Date: Tue, 24 Oct 2017 23:51:34 +0800 Message-ID: <1508860309-212397-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen When adding/removing slots from device list, we need to lock this operation with hisi_hba lock for safety. This patch adds missing instances of this. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 5 ++++- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 2 ++ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 ++ 3 files changed, 8 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index e038bdf..254af67 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -401,7 +401,9 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq goto err_out_buf; } + spin_lock_irqsave(&hisi_hba->lock, flags); list_add_tail(&slot->entry, &sas_dev->list); + spin_unlock_irqrestore(&hisi_hba->lock, flags); spin_lock_irqsave(&task->task_state_lock, flags); task->task_state_flags |= SAS_TASK_AT_INITIATOR; spin_unlock_irqrestore(&task->task_state_lock, flags); @@ -1387,8 +1389,9 @@ static int hisi_sas_query_task(struct sas_task *task) if (rc) goto err_out_buf; - + spin_lock_irqsave(&hisi_hba->lock, flags); list_add_tail(&slot->entry, &sas_dev->list); + spin_unlock_irqrestore(&hisi_hba->lock, flags); spin_lock_irqsave(&task->task_state_lock, flags); task->task_state_flags |= SAS_TASK_AT_INITIATOR; spin_unlock_irqrestore(&task->task_state_lock, flags); diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 73d12ff..3b2e5b5 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -2378,7 +2378,9 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, if (unlikely(aborted)) { ts->stat = SAS_ABORTED_TASK; + spin_lock_irqsave(&hisi_hba->lock, flags); hisi_sas_slot_task_free(hisi_hba, task, slot); + spin_unlock_irqrestore(&hisi_hba->lock, flags); return -1; } diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index d60501f..38eeba9 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1400,7 +1400,9 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) ts->resp = SAS_TASK_COMPLETE; if (unlikely(aborted)) { ts->stat = SAS_ABORTED_TASK; + spin_lock_irqsave(&hisi_hba->lock, flags); hisi_sas_slot_task_free(hisi_hba, task, slot); + spin_unlock_irqrestore(&hisi_hba->lock, flags); return -1; } From patchwork Tue Oct 24 15:51:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116961 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5914202qgn; Tue, 24 Oct 2017 08:06:50 -0700 (PDT) X-Google-Smtp-Source: ABhQp+STF663Fo3BrTkBW5gEAtJJofrFofbc+5LrG3WjrJjzonPvPNbLhzxwwem9PmcH951/9dbc X-Received: by 10.84.218.141 with SMTP id r13mr13126974pli.53.1508857610757; Tue, 24 Oct 2017 08:06:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857610; cv=none; d=google.com; s=arc-20160816; b=rtTiob4vf8aVdLnxGaQCis9w2lMGkJ6Lbb4QjLbQJ7aNRenByA5m1xD2Ph3ZX+Z4yt 6Vprr44BvQJ1QwkxEfOpmYLc3BzvH6s52thNEoeio5wCLTHFIL1PWQyoLD7uoxubgtWQ 5i/+gaWnQV+9U2Nx1aI+GHqcWG/mNjGq29rm6+72gpZROvcgpmXdAYSg32DhLcCCJcNa C4zC9VBH28Yg0JsYbpDVCThjjRUSsKGOrh6kN4JqTecuw6eyaUudimXoKvHfBnp97s8g +8SUE9L19rM+9klIjlcxVZYiQr63qhR4Iqnn48CIea9dM5JGYSjQKs+Sotxskn86yMAV RnJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=+UUTWczqS7awXgI8ugUMidgD0qTzpqxVyG4N1TpGFJ4=; b=SoChIjVaWnwK/3G8dOAhy7HoDL5DsQCSeWFQq1VR+GvSkbPNyijWKc3xac+EeW+lFN nSH+WrAxlFefRVxf9NvhJbrrT0Kxcv3YjtNeD4ZCJlFRVbSU9gYwrjuvGxHMsP2GPGrO T2uXFLlpLjp4mImybuOe+cT/lF6Z/AaoEqKlcMGPioSA70RLmOu1Adn5Tm7b94DvlvS3 RP7qPQcVZYID6nDlIc+0NFtJAIGsgowX9BnGnafgu327qXqFrusBOxQw1SVca6cVwsSI 6DTb5dzudPCOdC/dq0So0i3F5Ow+xkhwmao/55TXoVJrGsdQscXh4h8s+cp9J1qm5q0M 1utQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l6si310644pgo.198.2017.10.24.08.06.50; Tue, 24 Oct 2017 08:06:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932395AbdJXPGs (ORCPT + 27 others); Tue, 24 Oct 2017 11:06:48 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50576 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751637AbdJXPF3 (ORCPT ); Tue, 24 Oct 2017 11:05:29 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 3E9ED7084060F; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:17 +0800 From: John Garry To: , CC: , , , , Xiang Chen , John Garry Subject: [PATCH 06/19] scsi: hisi_sas: us start_phy in PHY_FUNC_LINK_RESET Date: Tue, 24 Oct 2017 23:51:36 +0800 Message-ID: <1508860309-212397-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen When a PHY_FUNC_LINK_RESET is issued, we need to fill the transport identify_frame to SAS controller before the PHYs are enabled. Without this, we may find that if a PHY which belonged to a wideport before the reset may generate a new port id. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 +- drivers/scsi/hisi_sas/hisi_sas_main.c | 2 +- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 2 +- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 2 +- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 07538cf..ea4b5d6 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -198,7 +198,7 @@ struct hisi_sas_hw { int (*slot_complete)(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot); void (*phys_init)(struct hisi_hba *hisi_hba); - void (*phy_enable)(struct hisi_hba *hisi_hba, int phy_no); + void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no); void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no); void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no); void (*get_events)(struct hisi_hba *hisi_hba, int phy_no); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index f49a131..88d90dc 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -765,7 +765,7 @@ static int hisi_sas_control_phy(struct asd_sas_phy *sas_phy, enum phy_func func, case PHY_FUNC_LINK_RESET: hisi_hba->hw->phy_disable(hisi_hba, phy_no); msleep(100); - hisi_hba->hw->phy_enable(hisi_hba, phy_no); + hisi_hba->hw->phy_start(hisi_hba, phy_no); break; case PHY_FUNC_DISABLE: diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c index 08eca20..00b5ee4 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c @@ -1857,7 +1857,7 @@ static int hisi_sas_v1_init(struct hisi_hba *hisi_hba) .start_delivery = start_delivery_v1_hw, .slot_complete = slot_complete_v1_hw, .phys_init = phys_init_v1_hw, - .phy_enable = enable_phy_v1_hw, + .phy_start = start_phy_v1_hw, .phy_disable = disable_phy_v1_hw, .phy_hard_reset = phy_hard_reset_v1_hw, .phy_set_linkrate = phy_set_linkrate_v1_hw, diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 3b2e5b5..50a0fc8 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -3463,7 +3463,7 @@ static int soft_reset_v2_hw(struct hisi_hba *hisi_hba) .start_delivery = start_delivery_v2_hw, .slot_complete = slot_complete_v2_hw, .phys_init = phys_init_v2_hw, - .phy_enable = enable_phy_v2_hw, + .phy_start = start_phy_v2_hw, .phy_disable = disable_phy_v2_hw, .phy_hard_reset = phy_hard_reset_v2_hw, .get_events = phy_get_events_v2_hw, diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index ac499e9..67ebd8f 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1781,7 +1781,7 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, .phys_init = phys_init_v3_hw, - .phy_enable = enable_phy_v3_hw, + .phy_start = start_phy_v3_hw, .phy_disable = disable_phy_v3_hw, .phy_hard_reset = phy_hard_reset_v3_hw, .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, From patchwork Tue Oct 24 15:51:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116955 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5912763qgn; Tue, 24 Oct 2017 08:05:41 -0700 (PDT) X-Google-Smtp-Source: ABhQp+S42Er8D3E90SFpgXWe/vbtEnELElO7dXyYV/AKRMWeYWxSdDbT9FxAqwbnY6HP9kRB761Q X-Received: by 10.159.208.5 with SMTP id a5mr13412721plp.436.1508857541450; Tue, 24 Oct 2017 08:05:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857541; cv=none; d=google.com; s=arc-20160816; b=c7Z4LYZ4yya5zTfmaceyaHbV7pnQFHXYM9qt1w9kt0Lbj3+nIFyi2nfn7gfATcK4yT vjU7aU1GZaeXOAWwNX0vujNcHp7N2GXYUJhTUXLrfTOgJvTSJM+9b9JLqX79HTv4wyZV UlX08atjAAeQq2mvZBHjmbYA53uO4DNLmeyAShiA8+DMCKHUzs1aH+ZWjSIvfIGEzK7s qF6fD9BV4+7CLmkCPsxaAOmJMdSTKjqSXs40vrETrrTTcmVaTSEUCpgUEchArTu7tquJ 4lSSc9NumiAah7Un905L1ta/lYT018qaVX6M/A3pcf5zlnkUEtkO6NVJClXexHxQ5yzg 3e0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=znGSUMCsslPLPaOESRHCC+54ePNDf8SM7Qfb/SswhPA=; b=gLmZWPrJwRBgHLMvip9TMV0r/wn8rMn8cEJMbe9AVZohxsU006oQ5DlqIIp4MVTd6O cz15TewwkahyVvWYHZO9eTh2MnJ+6RwccJpcAxYyCxLQdpy24MqQAeBkv2V4Viamx4cK sMDXXGBSbMEnjkjy39AVl4+f99v+wT2rJBTat3DFD9vNVBKn/m/gG9YbvZZbRZQYyctC ws01G0ITZII229AObmPSxj5SdaAxT42BgNTZybEfD99Z/37YamAPL2QSDu0sxtamZvtE 4jnlBLY3O5+K29jY1/t4FlucFmT0jW2Z/PS19kgLYDTVe+o4bD5youTZRvZbeqwjPGwR NRSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 78si324538pfi.520.2017.10.24.08.05.41; Tue, 24 Oct 2017 08:05:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932335AbdJXPFj (ORCPT + 27 others); Tue, 24 Oct 2017 11:05:39 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50597 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932206AbdJXPFb (ORCPT ); Tue, 24 Oct 2017 11:05:31 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7A0F63C483AC9; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:17 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 07/19] scsi: hisi_sas: fix NULL check in SMP abort task path Date: Tue, 24 Oct 2017 23:51:37 +0800 Message-ID: <1508860309-212397-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan This patch adds a NULL check of task->lldd_task before freeing the slot in SMP path. This is to guard against the scenario of the slot being freed during the from the preceding internal abort. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 88d90dc..2a209e1 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1161,7 +1161,7 @@ static int hisi_sas_abort_task(struct sas_task *task) rc = hisi_sas_internal_task_abort(hisi_hba, device, HISI_SAS_INT_ABT_CMD, tag); - if (rc == TMF_RESP_FUNC_FAILED) { + if (rc == TMF_RESP_FUNC_FAILED && task->lldd_task) { spin_lock_irqsave(&hisi_hba->lock, flags); hisi_sas_do_release_task(hisi_hba, task, slot); spin_unlock_irqrestore(&hisi_hba->lock, flags); From patchwork Tue Oct 24 15:51:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116958 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5913408qgn; Tue, 24 Oct 2017 08:06:11 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TfxxjyfBavKb+1KJsmEQaZ8uI5SsMZj64QCCpZd7DY4aI+LrjhMjuK8X0mov28LygdVt6B X-Received: by 10.98.159.23 with SMTP id g23mr16667265pfe.216.1508857571519; Tue, 24 Oct 2017 08:06:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857571; cv=none; d=google.com; s=arc-20160816; b=wee5MlZF93+7LtvLqqt3ACflZtzww+2EqANGxkztq3sXCff11k1Hsp+aDNHlyLwCFr GkjI6rUq9V3AWZJkhF7o6JxBJ31/tk8LYKb0H5b6eG7VO8ExBJRLyEY5uvsA8qO/eAG9 GNnh34VviKT8xKgWq7onvP64+pBC6HrDhEOJRQkqOag5RHSll6OMXidVGFnyOdowRyJq kOC96DBSOGAztOUNX9nUURkiy661qSTMEODbO1omqPqAMSuWyv0cd6B4TXmKoCi6ugkY ME+07LiMx7sFJToDSo9Sf/SMykzSqcNSQ3tgENo78+QNuNx2AgyCHFAwbQGiiUWWK0xs 3rlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=qpU0NVwF7vjNT/SKFyk6lcBZ9ETAHlYLGou8PqKaFtM=; b=VfFrg90i2lEsz//vcdgvsZ5yMa7Tst/7R581AONjDtuhsN9/mdysjuDRsQL2uE5n1x 7H+N/OYV8M1nX+EBpdsPBXBpoj85rW6qPGDrTqdAgv/IZrgAMDe7APQJIhFTEflleznc MGDwFUQVHc8Z2Sq9KXwEy2p24pes04ilMJKbcHV7hMKul6p/NpYJCSQrGML5fSdtyxr8 ySyotwGnlgH7hOWb4xi6fpuDi+SngVhKrrbAp5k9HTeahNWBYcNZ/ZWp6gDrFmhBUbBC smkaQ/iPjKXCwqzoGm/OT58klv8WiCfoJghKSJucT7LvwytKLlihPdvuXLw62UqlOMjq l4TA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m68si323969pfm.585.2017.10.24.08.06.11; Tue, 24 Oct 2017 08:06:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932354AbdJXPGJ (ORCPT + 27 others); Tue, 24 Oct 2017 11:06:09 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50575 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751670AbdJXPFa (ORCPT ); Tue, 24 Oct 2017 11:05:30 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 2DEBC84C6214E; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:18 +0800 From: John Garry To: , CC: , , , , Shiju Jose , John Garry Subject: [PATCH 09/19] scsi: hisi_sas: use array for v2 hw AXI errors Date: Tue, 24 Oct 2017 23:51:39 +0800 Message-ID: <1508860309-212397-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shiju Jose The code to print AXI errors in v2 hw driver is repetitive. This patch condenses the code by looping an array of errors. Also, a formatting error in one_bit_ecc_errors[] and multi_bit_ecc_errors[] is fixed. Signed-off-by: Shiju Jose Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 236 ++++++++++++++------------------- 2 files changed, 100 insertions(+), 137 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index ea4b5d6..d2d384b 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -96,6 +96,7 @@ struct hisi_sas_hw_error { int shift; const char *msg; int reg; + const struct hisi_sas_hw_error *sub; }; struct hisi_sas_phy { diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 50a0fc8..ee34f2e 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -406,80 +406,70 @@ struct hisi_sas_err_record_v2 { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF), .msk = HGC_DQE_ECC_1B_ADDR_MSK, .shift = HGC_DQE_ECC_1B_ADDR_OFF, - .msg = "hgc_dqe_acc1b_intr found: \ - Ram address is 0x%08X\n", + .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n", .reg = HGC_DQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF), .msk = HGC_IOST_ECC_1B_ADDR_MSK, .shift = HGC_IOST_ECC_1B_ADDR_OFF, - .msg = "hgc_iost_acc1b_intr found: \ - Ram address is 0x%08X\n", + .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n", .reg = HGC_IOST_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF), .msk = HGC_ITCT_ECC_1B_ADDR_MSK, .shift = HGC_ITCT_ECC_1B_ADDR_OFF, - .msg = "hgc_itct_acc1b_intr found: \ - Ram address is 0x%08X\n", + .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n", .reg = HGC_ITCT_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF), .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, - .msg = "hgc_iostl_acc1b_intr found: \ - memory address is 0x%08X\n", + .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF), .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, - .msg = "hgc_itctl_acc1b_intr found: \ - memory address is 0x%08X\n", + .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF), .msk = HGC_CQE_ECC_1B_ADDR_MSK, .shift = HGC_CQE_ECC_1B_ADDR_OFF, - .msg = "hgc_cqe_acc1b_intr found: \ - Ram address is 0x%08X\n", + .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n", .reg = HGC_CQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, - .msg = "rxm_mem0_acc1b_intr found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, - .msg = "rxm_mem1_acc1b_intr found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, - .msg = "rxm_mem2_acc1b_intr found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, - .msg = "rxm_mem3_acc1b_intr found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS15, }, }; @@ -489,80 +479,70 @@ struct hisi_sas_err_record_v2 { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), .msk = HGC_DQE_ECC_MB_ADDR_MSK, .shift = HGC_DQE_ECC_MB_ADDR_OFF, - .msg = "hgc_dqe_accbad_intr (0x%x) found: \ - Ram address is 0x%08X\n", + .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_DQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), .msk = HGC_IOST_ECC_MB_ADDR_MSK, .shift = HGC_IOST_ECC_MB_ADDR_OFF, - .msg = "hgc_iost_accbad_intr (0x%x) found: \ - Ram address is 0x%08X\n", + .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_IOST_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), .msk = HGC_ITCT_ECC_MB_ADDR_MSK, .shift = HGC_ITCT_ECC_MB_ADDR_OFF, - .msg = "hgc_itct_accbad_intr (0x%x) found: \ - Ram address is 0x%08X\n", + .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_ITCT_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, - .msg = "hgc_iostl_accbad_intr (0x%x) found: \ - memory address is 0x%08X\n", + .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, - .msg = "hgc_itctl_accbad_intr (0x%x) found: \ - memory address is 0x%08X\n", + .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), .msk = HGC_CQE_ECC_MB_ADDR_MSK, .shift = HGC_CQE_ECC_MB_ADDR_OFF, - .msg = "hgc_cqe_accbad_intr (0x%x) found: \ - Ram address is 0x%08X\n", + .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_CQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, - .msg = "rxm_mem0_accbad_intr (0x%x) found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, - .msg = "rxm_mem1_accbad_intr (0x%x) found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, - .msg = "rxm_mem2_accbad_intr (0x%x) found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, - .msg = "rxm_mem3_accbad_intr (0x%x) found: \ - memory address is 0x%08X\n", + .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS15, }, }; @@ -2956,25 +2936,58 @@ static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p) return IRQ_HANDLED; } -#define AXI_ERR_NR 8 -static const char axi_err_info[AXI_ERR_NR][32] = { - "IOST_AXI_W_ERR", - "IOST_AXI_R_ERR", - "ITCT_AXI_W_ERR", - "ITCT_AXI_R_ERR", - "SATA_AXI_W_ERR", - "SATA_AXI_R_ERR", - "DQE_AXI_R_ERR", - "CQE_AXI_W_ERR" +static const struct hisi_sas_hw_error axi_error[] = { + { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, + { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, + { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, + { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, + { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, + { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, + { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, + { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, + {}, +}; + +static const struct hisi_sas_hw_error fifo_error[] = { + { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, + { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, + { .msk = BIT(10), .msg = "GETDQE_FIFO" }, + { .msk = BIT(11), .msg = "CMDP_FIFO" }, + { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, + {}, }; -#define FIFO_ERR_NR 5 -static const char fifo_err_info[FIFO_ERR_NR][32] = { - "CQE_WINFO_FIFO", - "CQE_MSG_FIFIO", - "GETDQE_FIFO", - "CMDP_FIFO", - "AWTCTRL_FIFO" +static const struct hisi_sas_hw_error fatal_axi_errors[] = { + { + .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), + .msg = "write pointer and depth", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), + .msg = "iptt no match slot", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), + .msg = "read pointer and depth", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), + .reg = HGC_AXI_FIFO_ERR_INFO, + .sub = axi_error, + }, + { + .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), + .reg = HGC_AXI_FIFO_ERR_INFO, + .sub = fifo_error, + }, + { + .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), + .msg = "LM add/fetch list", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), + .msg = "SAS_HGC_ABT fetch LM list", + }, }; static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) @@ -2982,98 +2995,47 @@ static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) struct hisi_hba *hisi_hba = p; u32 irq_value, irq_msk, err_value; struct device *dev = hisi_hba->dev; + const struct hisi_sas_hw_error *axi_error; + int i; irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe); irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); - if (irq_value) { - if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) { - hisi_sas_write32(hisi_hba, ENT_INT_SRC3, - 1 << ENT_INT_SRC3_WP_DEPTH_OFF); - dev_warn(dev, "write pointer and depth error (0x%x) \ - found!\n", - irq_value); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } - if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) { - hisi_sas_write32(hisi_hba, ENT_INT_SRC3, - 1 << - ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF); - dev_warn(dev, "iptt no match slot error (0x%x) found!\n", - irq_value); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } - - if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF)) { - dev_warn(dev, "read pointer and depth error (0x%x) \ - found!\n", - irq_value); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } - - if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) { - int i; - - hisi_sas_write32(hisi_hba, ENT_INT_SRC3, - 1 << ENT_INT_SRC3_AXI_OFF); - err_value = hisi_sas_read32(hisi_hba, - HGC_AXI_FIFO_ERR_INFO); - - for (i = 0; i < AXI_ERR_NR; i++) { - if (err_value & BIT(i)) { - dev_warn(dev, "%s (0x%x) found!\n", - axi_err_info[i], irq_value); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } - } - } - - if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) { - int i; - - hisi_sas_write32(hisi_hba, ENT_INT_SRC3, - 1 << ENT_INT_SRC3_FIFO_OFF); - err_value = hisi_sas_read32(hisi_hba, - HGC_AXI_FIFO_ERR_INFO); + for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) { + axi_error = &fatal_axi_errors[i]; + if (!(irq_value & axi_error->irq_msk)) + continue; - for (i = 0; i < FIFO_ERR_NR; i++) { - if (err_value & BIT(AXI_ERR_NR + i)) { - dev_warn(dev, "%s (0x%x) found!\n", - fifo_err_info[i], irq_value); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + 1 << axi_error->shift); + if (axi_error->sub) { + const struct hisi_sas_hw_error *sub = axi_error->sub; + + err_value = hisi_sas_read32(hisi_hba, axi_error->reg); + for (; sub->msk || sub->msg; sub++) { + if (!(err_value & sub->msk)) + continue; + dev_warn(dev, "%s (0x%x) found!\n", + sub->msg, irq_value); + queue_work(hisi_hba->wq, &hisi_hba->rst_work); } - - } - - if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) { - hisi_sas_write32(hisi_hba, ENT_INT_SRC3, - 1 << ENT_INT_SRC3_LM_OFF); - dev_warn(dev, "LM add/fetch list error (0x%x) found!\n", - irq_value); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } - - if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) { - hisi_sas_write32(hisi_hba, ENT_INT_SRC3, - 1 << ENT_INT_SRC3_ABT_OFF); - dev_warn(dev, "SAS_HGC_ABT fetch LM list error (0x%x) found!\n", - irq_value); + } else { + dev_warn(dev, "%s (0x%x) found!\n", + axi_error->msg, irq_value); queue_work(hisi_hba->wq, &hisi_hba->rst_work); } + } - if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { - u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); - u32 dev_id = reg_val & ITCT_DEV_MSK; - struct hisi_sas_device *sas_dev = - &hisi_hba->devices[dev_id]; + if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { + u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); + u32 dev_id = reg_val & ITCT_DEV_MSK; + struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id]; - hisi_sas_write32(hisi_hba, ITCT_CLR, 0); - dev_dbg(dev, "clear ITCT ok\n"); - complete(sas_dev->completion); - } + hisi_sas_write32(hisi_hba, ITCT_CLR, 0); + dev_dbg(dev, "clear ITCT ok\n"); + complete(sas_dev->completion); } hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value); From patchwork Tue Oct 24 15:51:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116957 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5913275qgn; Tue, 24 Oct 2017 08:06:05 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Qvl8sAhr681gTLCa4sfie//C3kMiKewRH6RFhzTwrvJ/o/D2TEJGWUpAHGukXw/42xzURl X-Received: by 10.101.72.132 with SMTP id n4mr14982225pgs.245.1508857565030; Tue, 24 Oct 2017 08:06:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857565; cv=none; d=google.com; s=arc-20160816; b=dBK3iES5SukxbsHHRZ4lyIeAmjl8+kUqQdsbc1NIXXIV6sE1m62wfMRC7kInHyls9V lrp3KWeS4p2ClwDtjLaQg6uLqpSGRWa1zL5wb/X3V9DaIm9Z2MIE948Oy24BxHtVM0KV lzLBL8e+0RpnpD97h+fkPDEzoeX8K/IQHofnw04vI3Q08m45l/bqD0AwwK4SRodnD5iC +zuFWrOyKp5yM77HShGV058c5kIXlCO0mPQwHfBCOexHHfqokDBwSaBLMTkyhG5MzrVK UpuV35fOrz3ORIwIHnT25ZZJWE1OdZAz1RYJV7Q9o34gtknqSyQ/5T1XGhXmTcdKsMSC FhfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=bQuK/OuR/uCdnGKNEigd0FE8R7z9O+J3fL6aUVqz0Ys=; b=eT+V20pJIlSZHE+O4i0hxe+QC01pt5EAUwdO+RGDJUKPeYiwTAisUOjQytQR65aEFL F/hT/eQ8iQ9dOJ8V31qYgbH5i3IzeJofVj6QI9SN9lvJOtShEWCvb5CyJxwbkQmqFlS0 smDFNSPQp+mU6yZBsZw2AyVgy2sRDmyZyIoYES3mPj1EkJGVEs6+5wgnRyHaRUWjipnI 2ytZjoJ/mCCo2CvgHn0dp3KqlqqJmD+9cixf9Hk+Y6fJTZ9uqXpAncsTM7MPSo1x5pLQ hd2wtO1Lr/VP/vNSIVLHt2E9efcJl+n0AHa24hiWiYv2E1SKWUQ8zm6xSqBjY1aP/G5G zeDQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m68si323969pfm.585.2017.10.24.08.06.04; Tue, 24 Oct 2017 08:06:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751918AbdJXPGB (ORCPT + 27 others); Tue, 24 Oct 2017 11:06:01 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50579 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932178AbdJXPFa (ORCPT ); Tue, 24 Oct 2017 11:05:30 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 4D6C3697D88E4; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:18 +0800 From: John Garry To: , CC: , , , , Shiju Jose , John Garry Subject: [PATCH 10/19] scsi: hisi_sas: report ECC errors in v2 hw to userspace Date: Tue, 24 Oct 2017 23:51:40 +0800 Message-ID: <1508860309-212397-11-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shiju Jose This patch adds reporting ECC errors in the SAS V2 driver to userspace as non-standard trace events. rasdaemon can be used to read and log these ECC errors in userspace. Rasdaemon log for the SAS errors with the decoding sample: cpu 00:[ 70.025830] hisi_sas_v2_hw HISI0162:01: phy7, wait tx fifo need send break -0 [4204528] 0.000007: non_standard_event: 2017-09-06 11:14:49 +0000 Recoverable section type: daffd814-6eba-4d8c-8a91-bc9bbf4aa301 fru text: HISI0162:01 fru id: 00000000-0000-0000-0000-000000000000 length: 24 error: 00000000: 00000007 00000000 0000013c 00000000 00000010: 00000000 00000001 HISI HIP07: SAS error: [phy addr = 0x0x13c: single-bit ecc: error type = hgc_dqe ecc] cpu 00: -0 [4204552] 0.000007: non_standard_event: 2017-09-06 11:14:49 +0000 Fatal section type: daffd814-6eba-4d8c-8a91-bc9bbf4aa301 fru text: HISI0162:01 fru id: 00000000-0000-0000-0000-000000000000 length: 24 error: 00000000: 00000007 00000000 0000013c 00000000 00000010: 00000001 00000001 HISI HIP07: SAS error: [phy addr = 0x0x13c: multi-bit ecc: error type = hgc_dqe ecc] Signed-off-by: Shiju Jose Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 9 ++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 95 +++++++++++++++++++++++++++++++++- 2 files changed, 102 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index d2d384b..58bc69e 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -12,6 +12,7 @@ #ifndef _HISI_SAS_H_ #define _HISI_SAS_H_ +#include #include #include #include @@ -22,7 +23,9 @@ #include #include #include +#include #include +#include #include #include @@ -96,9 +99,15 @@ struct hisi_sas_hw_error { int shift; const char *msg; int reg; + u32 type; const struct hisi_sas_hw_error *sub; }; +enum hisi_sas_bit_err_type { + HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0, + HISI_SAS_ERR_MULTI_BIT_ECC = 0x1, +}; + struct hisi_sas_phy { struct hisi_hba *hisi_hba; struct hisi_sas_port *port; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index ee34f2e..0cf8244 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -379,6 +379,17 @@ #define HISI_SAS_FATAL_INT_NR 2 +#define HISI_SAS_ECC_ERR_HGC_DQE BIT(0) +#define HISI_SAS_ECC_ERR_HGC_IOST BIT(1) +#define HISI_SAS_ECC_ERR_HGC_ITCT BIT(2) +#define HISI_SAS_ECC_ERR_HGC_IOSTLIST BIT(3) +#define HISI_SAS_ECC_ERR_HGC_ITCTLIST BIT(4) +#define HISI_SAS_ECC_ERR_HGC_CQE BIT(5) +#define HISI_SAS_ECC_ERR_HGC_RXM_MEM0 BIT(6) +#define HISI_SAS_ECC_ERR_HGC_RXM_MEM1 BIT(7) +#define HISI_SAS_ECC_ERR_HGC_RXM_MEM2 BIT(8) +#define HISI_SAS_ECC_ERR_HGC_RXM_MEM3 BIT(9) + struct hisi_sas_complete_v2_hdr { __le32 dw0; __le32 dw1; @@ -401,6 +412,13 @@ struct hisi_sas_err_record_v2 { __le32 dma_rx_err_type; }; +struct hisi_sas_hw_err_info { + u64 validation_bits; + u64 physical_addr; + u32 mb_err; + u32 type; +}; + static const struct hisi_sas_hw_error one_bit_ecc_errors[] = { { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF), @@ -408,6 +426,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_DQE_ECC_1B_ADDR_OFF, .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n", .reg = HGC_DQE_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_DQE, }, { .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF), @@ -415,6 +434,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_IOST_ECC_1B_ADDR_OFF, .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n", .reg = HGC_IOST_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_IOST, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF), @@ -422,6 +442,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_ITCT_ECC_1B_ADDR_OFF, .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n", .reg = HGC_ITCT_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_ITCT, }, { .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF), @@ -429,6 +450,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, + .type = HISI_SAS_ECC_ERR_HGC_IOSTLIST, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF), @@ -436,6 +458,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, + .type = HISI_SAS_ECC_ERR_HGC_ITCTLIST, }, { .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF), @@ -443,6 +466,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_CQE_ECC_1B_ADDR_OFF, .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n", .reg = HGC_CQE_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_CQE, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF), @@ -450,6 +474,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM0, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF), @@ -457,6 +482,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM1, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF), @@ -464,6 +490,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM2, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF), @@ -471,6 +498,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS15, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM3, }, }; @@ -481,6 +509,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_DQE_ECC_MB_ADDR_OFF, .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_DQE_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_DQE, }, { .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), @@ -488,6 +517,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_IOST_ECC_MB_ADDR_OFF, .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_IOST_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_IOST, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), @@ -495,6 +525,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_ITCT_ECC_MB_ADDR_OFF, .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_ITCT_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_ITCT, }, { .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), @@ -502,6 +533,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, + .type = HISI_SAS_ECC_ERR_HGC_IOSTLIST, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), @@ -509,6 +541,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_LM_DFX_STATUS2, + .type = HISI_SAS_ECC_ERR_HGC_ITCTLIST, }, { .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), @@ -516,6 +549,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_CQE_ECC_MB_ADDR_OFF, .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n", .reg = HGC_CQE_ECC_ADDR, + .type = HISI_SAS_ECC_ERR_HGC_CQE, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), @@ -523,6 +557,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM0, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), @@ -530,6 +565,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM1, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), @@ -537,6 +573,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS14, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM2, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), @@ -544,6 +581,7 @@ struct hisi_sas_err_record_v2 { .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n", .reg = HGC_RXM_DFX_STATUS15, + .type = HISI_SAS_ECC_ERR_HGC_RXM_MEM3, }, }; @@ -702,6 +740,15 @@ enum { #define DIR_TO_DEVICE 2 #define DIR_RESERVED 3 +/* Vendor specific CPER SEC TYPE for HISI SAS Memory errors */ +#define CPER_SEC_TYPE_HISI_SAS \ + UUID_LE(0xDAFFD814, 0x6EBA, 0x4D8C, 0x8A, 0x91, 0xBC, 0x9B, \ + 0xBF, 0x4A, 0xA3, 0x01) + +#define HISI_SAS_VALID_PA BIT(0) +#define HISI_SAS_VALID_MB_ERR BIT(1) +#define HISI_SAS_VALID_ERR_TYPE BIT(2) + #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \ err_phase == 0x4 || err_phase == 0x8 ||\ err_phase == 0x6 || err_phase == 0xa) @@ -2882,6 +2929,17 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) const struct hisi_sas_hw_error *ecc_error; u32 val; int i; + struct hisi_sas_hw_err_info err_data; + bool trace_ns_event_enabled = trace_non_standard_event_enabled(); + + if (trace_ns_event_enabled) { + memset(&err_data, 0, sizeof(err_data)); + err_data.validation_bits = + HISI_SAS_VALID_PA | + HISI_SAS_VALID_MB_ERR | + HISI_SAS_VALID_ERR_TYPE; + err_data.mb_err = HISI_SAS_ERR_SINGLE_BIT_ECC; + } for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) { ecc_error = &one_bit_ecc_errors[i]; @@ -2889,7 +2947,18 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) val = hisi_sas_read32(hisi_hba, ecc_error->reg); val &= ecc_error->msk; val >>= ecc_error->shift; - dev_warn(dev, ecc_error->msg, val); + if (trace_ns_event_enabled) { + err_data.physical_addr = val; + err_data.type = ecc_error->type; + log_non_standard_event(&CPER_SEC_TYPE_HISI_SAS, + &NULL_UUID_LE, + dev_name(dev), + GHES_SEV_RECOVERABLE, + (const u8 *)&err_data, + sizeof(err_data)); + } else { + dev_warn(dev, ecc_error->msg, val); + } } } } @@ -2901,6 +2970,17 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, const struct hisi_sas_hw_error *ecc_error; u32 val; int i; + struct hisi_sas_hw_err_info err_data; + bool trace_ns_event_enabled = trace_non_standard_event_enabled(); + + if (trace_ns_event_enabled) { + memset(&err_data, 0, sizeof(err_data)); + err_data.validation_bits = + HISI_SAS_VALID_PA | + HISI_SAS_VALID_MB_ERR | + HISI_SAS_VALID_ERR_TYPE; + err_data.mb_err = HISI_SAS_ERR_MULTI_BIT_ECC; + } for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) { ecc_error = &multi_bit_ecc_errors[i]; @@ -2908,7 +2988,18 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, val = hisi_sas_read32(hisi_hba, ecc_error->reg); val &= ecc_error->msk; val >>= ecc_error->shift; - dev_warn(dev, ecc_error->msg, irq_value, val); + if (trace_ns_event_enabled) { + err_data.physical_addr = val; + err_data.type = ecc_error->type; + log_non_standard_event(&CPER_SEC_TYPE_HISI_SAS, + &NULL_UUID_LE, + dev_name(dev), + GHES_SEV_PANIC, + (const u8 *)&err_data, + sizeof(err_data)); + } else { + dev_warn(dev, ecc_error->msg, irq_value, val); + } queue_work(hisi_hba->wq, &hisi_hba->rst_work); } } From patchwork Tue Oct 24 15:51:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116969 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5917356qgn; Tue, 24 Oct 2017 08:09:33 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Rck3WTtNF/UCzbhcuR9OThRpzDXZBAXMfDaCL5EsoiWdFs0hp+I5m5dyjFRyGw3AeKPVZD X-Received: by 10.98.33.137 with SMTP id o9mr16975902pfj.33.1508857773655; Tue, 24 Oct 2017 08:09:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857773; cv=none; d=google.com; s=arc-20160816; b=h5z9fmk+cqNpYpwPb4m2dT226hy77cUoQZnsbvoXxCKI9KsjiFbCCBQX10sHO/sdsc /zf2RyCykqejc3LQb9JdxNDSRdZD6pDIP3Ml0X3ZHAaas4wT+OWgmAs/DaRQHSWGx1ng PqnIK7XvME0OlXilzNqtkqrz2ldDQQkzN94iG4E2dPubHtu7r1+YryG5/MbinUxDiCWi yEdiAUh1yWjYldFsrPFSrL6zns/8ZqJiAZhLLlfoJPGDL+TxNP/6L5pWNWqJNV4rlILv XNSYsb926iSSJK8ng1NIVLbe1OoA3F60CevS7eNh54qcHRkC6A9+4m+VZhZ2t+YlCaQe E4GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=1uCvQF26Vs6b4wMl/2S9qQKZnkEOqDaa0ab46GF1JpI=; b=H+Wugprztpqd25lG+mCN0at0b3q/OpQsEN/VfHEYdK2O4H3HvOkFcjmbTNshtcWitL mudbl5IM4MSUDGtO4SLZtEWqBfayIYkY7ASwr38VU26534Xz//5E8j31FrsMtNSWY5pI 4eNhVttVf5iyuotRpzZRxWSQ0cMN4FQKl3n0/WjLUXabykXmLC4BgOo/r0FJPa78WItP guofZ0VjSVeh5EVd2H+sCCv6batXyiSvTMpCpAjwQ7/3G0mPA3/dMoVPbEfU5dH4spr/ IwWE8/G46Et4wqLU+KwGuff4Xvo04qkuwAJQprhmNYoVriyl/FRKa74HRcD/RQp/Y7jq tYmg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 31si273917plj.299.2017.10.24.08.09.33; Tue, 24 Oct 2017 08:09:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751999AbdJXPJb (ORCPT + 27 others); Tue, 24 Oct 2017 11:09:31 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9047 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751757AbdJXPJR (ORCPT ); Tue, 24 Oct 2017 11:09:17 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29919; Tue, 24 Oct 2017 23:05:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:18 +0800 From: John Garry To: , CC: , , , , Shiju Jose , John Garry Subject: [PATCH 11/19] scsi: hisi_sas: report v2 hw AXI errors to userspace Date: Tue, 24 Oct 2017 23:51:41 +0800 Message-ID: <1508860309-212397-12-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.59EF56BA.0145, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 449a9d4b2d886eb4bf06ba82ea1b40f9 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shiju Jose This patch adds reporting of AXI errors in the SAS v2 hw driver to userspace as non-standard trace events. rasdaemon can be used to read and log these AXI errors in userspace. Signed-off-by: Shiju Jose Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 54 +++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 0cf8244..8626d9f 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -389,6 +389,13 @@ #define HISI_SAS_ECC_ERR_HGC_RXM_MEM1 BIT(7) #define HISI_SAS_ECC_ERR_HGC_RXM_MEM2 BIT(8) #define HISI_SAS_ECC_ERR_HGC_RXM_MEM3 BIT(9) +#define HISI_SAS_ERR_WP_DEPTH BIT(10) +#define HISI_SAS_ERR_IPTT_SLOT_NOMATCH BIT(11) +#define HISI_SAS_ERR_RP_DEPTH BIT(12) +#define HISI_SAS_ERR_AXI BIT(13) +#define HISI_SAS_ERR_FIFO BIT(14) +#define HISI_SAS_ERR_LM_ADD_FETCH_LIST BIT(15) +#define HISI_SAS_ERR_HGC_ABT_FETCH_LM BIT(16) struct hisi_sas_complete_v2_hdr { __le32 dw0; @@ -417,6 +424,7 @@ struct hisi_sas_hw_err_info { u64 physical_addr; u32 mb_err; u32 type; + u32 axi_err_info; }; static const struct hisi_sas_hw_error one_bit_ecc_errors[] = { @@ -748,6 +756,7 @@ enum { #define HISI_SAS_VALID_PA BIT(0) #define HISI_SAS_VALID_MB_ERR BIT(1) #define HISI_SAS_VALID_ERR_TYPE BIT(2) +#define HISI_SAS_VALID_AXI_ERR_INFO BIT(3) #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \ err_phase == 0x4 || err_phase == 0x8 ||\ @@ -3052,32 +3061,39 @@ static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p) { .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), .msg = "write pointer and depth", + .type = HISI_SAS_ERR_WP_DEPTH, }, { .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), .msg = "iptt no match slot", + .type = HISI_SAS_ERR_IPTT_SLOT_NOMATCH, }, { .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), .msg = "read pointer and depth", + .type = HISI_SAS_ERR_RP_DEPTH, }, { .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), .reg = HGC_AXI_FIFO_ERR_INFO, + .type = HISI_SAS_ERR_AXI, .sub = axi_error, }, { .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), .reg = HGC_AXI_FIFO_ERR_INFO, + .type = HISI_SAS_ERR_FIFO, .sub = fifo_error, }, { .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), .msg = "LM add/fetch list", + .type = HISI_SAS_ERR_LM_ADD_FETCH_LIST, }, { .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), .msg = "SAS_HGC_ABT fetch LM list", + .type = HISI_SAS_ERR_HGC_ABT_FETCH_LM, }, }; @@ -3088,12 +3104,17 @@ static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) struct device *dev = hisi_hba->dev; const struct hisi_sas_hw_error *axi_error; int i; + struct hisi_sas_hw_err_info err_data; + bool trace_ns_event_enabled = trace_non_standard_event_enabled(); irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe); irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + if (trace_ns_event_enabled) + memset(&err_data, 0, sizeof(err_data)); + for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) { axi_error = &fatal_axi_errors[i]; if (!(irq_value & axi_error->irq_msk)) @@ -3108,13 +3129,38 @@ static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) for (; sub->msk || sub->msg; sub++) { if (!(err_value & sub->msk)) continue; - dev_warn(dev, "%s (0x%x) found!\n", - sub->msg, irq_value); + if (trace_ns_event_enabled) { + err_data.validation_bits = + HISI_SAS_VALID_ERR_TYPE | + HISI_SAS_VALID_AXI_ERR_INFO; + err_data.type = axi_error->type; + err_data.axi_err_info = sub->msk; + log_non_standard_event( + &CPER_SEC_TYPE_HISI_SAS, + &NULL_UUID_LE, + dev_name(dev), + GHES_SEV_PANIC, + (const u8 *)&err_data, + sizeof(err_data)); + } else + dev_warn(dev, "%s (0x%x) found!\n", + sub->msg, irq_value); queue_work(hisi_hba->wq, &hisi_hba->rst_work); } } else { - dev_warn(dev, "%s (0x%x) found!\n", - axi_error->msg, irq_value); + if (trace_ns_event_enabled) { + err_data.validation_bits = + HISI_SAS_VALID_ERR_TYPE; + err_data.type = axi_error->type; + log_non_standard_event(&CPER_SEC_TYPE_HISI_SAS, + &NULL_UUID_LE, + dev_name(dev), + GHES_SEV_PANIC, + (const u8 *)&err_data, + sizeof(err_data)); + } else + dev_warn(dev, "%s (0x%x) found!\n", + axi_error->msg, irq_value); queue_work(hisi_hba->wq, &hisi_hba->rst_work); } } From patchwork Tue Oct 24 15:51:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116971 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5918491qgn; Tue, 24 Oct 2017 08:10:31 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QzhS2SaPYLpwUFd5a0qb9B0GnwJL8Qkcn8LXuyNhPAxTZXuTo853B4L2/9CFeMxCnjgD50 X-Received: by 10.159.254.14 with SMTP id r14mr7614338pls.72.1508857831881; Tue, 24 Oct 2017 08:10:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857831; cv=none; d=google.com; s=arc-20160816; b=GUFL2W1kV5T0e5yTr0KZqDzPdhPSclXy7isCMb0ykRrSXqYMHYnKmG2Ixp5czOw0k7 RRqra6Xu3Fvm1JG1+I2VAxM9M0+Vlm5Ko2LARiqMUwoqTrG1cj9QQwzuHSFZ6ZLSXqOj QoagPQTaOuUbrNCdqJAAufSVtKRQVjq/pW8ONFGvZy5L528pLC9tQ5mGlOCOcEP81ju+ ffj2RDx8m+dcFLn+pw7IB5CQL/+h+Drjocw7RRX6B2OjP+FI5/nBCx/iFP3xvirozly/ fvypbFAABeycnGTwN11JOMi15pdRuwU/yzjI+t5/lM2gTr9J5Qd0JddQb0cuiw3rW6Xj 97kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=qu95AVB43JmYiBCCXNfPJZsA6S/psYE7FZGgcDvCaU4=; b=Lfo2WaV+n5dnSZapvg3L9lkkrPQvKG01ECbWG2zyLAy9N6u1hI+lU/cQ9nrRH77G6z BeGvWuPXcSa8NJhgju8tV/Ls0irRQ1ZAH06QicXzFyOnKfVNum8xsNAN/avAp5ohd40g ICx5DbRI1qwYkZC1XXWUsFP36TlAxyJK0rCo9cIMKXxksGSyRP+1bdh982WQ8eNXQrTE k5RUC2yKttqM/gXXemhmyiQg06u7twTsYfya/V7RJMlQFYAOqj8KEdY+zF3vIwCTeEZP vE0k7DfNipfF1q1uST/zCvUSuezMOs9Xjodsa6RtNjitcfRNJJTE7MpGdcm6AmwYLeou 5T1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bd7si263577plb.694.2017.10.24.08.10.31; Tue, 24 Oct 2017 08:10:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932345AbdJXPK2 (ORCPT + 27 others); Tue, 24 Oct 2017 11:10:28 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9040 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751682AbdJXPIu (ORCPT ); Tue, 24 Oct 2017 11:08:50 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29918; Tue, 24 Oct 2017 23:05:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:19 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 12/19] scsi: hisi_sas: check PHY state in get_wideport_bitmap_v3_hw() Date: Tue, 24 Oct 2017 23:51:42 +0800 Message-ID: <1508860309-212397-13-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0204.59EF56BA.004C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a1442c8262fec7b2ef5d6bca430e909c Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan We should check register PHY_STATE when getting the bitmap of a wideport, as, if the PHY is not ready, the value of register PHY_PORT_NUM_MA is not valid. V2 hw has done this check, and v3 hw should do this check too. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 67ebd8f..c88e787 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -755,10 +755,12 @@ static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) { int i, bitmap = 0; u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); + u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); for (i = 0; i < hisi_hba->n_phy; i++) - if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) - bitmap |= 1 << i; + if (phy_state & BIT(i)) + if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) + bitmap |= BIT(i); return bitmap; } From patchwork Tue Oct 24 15:51:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116972 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5918558qgn; Tue, 24 Oct 2017 08:10:35 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SSRjQsaMiC1NuOV361X58rZmpRCp4RBWWTIH0N9OW1JmLi9blHztW/uSiitM6zZuOXD4w3 X-Received: by 10.159.194.6 with SMTP id x6mr13296752pln.359.1508857835355; Tue, 24 Oct 2017 08:10:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857835; cv=none; d=google.com; s=arc-20160816; b=CDrgBaVl7t1mToNYc6YSHFXBsvqlkA/VpBFG0jkqIbDfzp8hknhYQjHZeGGkzcGKAY XKyynAFlPgx+j+0IfDlucrmTWdo61S4bRzRXbbnuxyL67SIbdQs5VeiLoPCz6NOv6R5N j8tMnZ9tA6rsNkpzqcoaI7jn1BhtjHP/n2Yq5v0My7ZrtE4U6d1v47wlnleOlYKDbQBk IXYSOe7jrn1N4QNIIt6GV7qKLzqDBefs+YwXgbWddBpSt8n64e6bZYeaamh4w6NxHym0 Wyq19Ydn0rqNsDt3QVur/rs1FMWUp4T7xPk8gh9uYkFXSok2FjGHlyPs1ztQkpFAplT3 vr1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=wHbwnTP0pZz3gkJx3sFQ5Xrlan/GLsJRA7GcoF0nKE8=; b=szifYDHoI+85i5/YHjMumwhHu7emEFT2QR6wjoLlZQtpLF62N1ZgL/t0xB7AVq2fDp 5azEEipTmcn3G5fTUjusyzMnxJlvgwqdTgAwaHVdaf7I/WLc4xqd3coiSlR3Qrf6y/hF 7h6dlIBiA55m8sYTMIOHZsXmia89KRoxY6FDR24cjYx91fx56TKFgfSryHywq9jPwoCV I39v5A86JUzf0uEGKXNHix/wyaVNu1hFfqRsKbc8SImmLnlHam+DBWQoAbxFqnZ0u+7W kohA3fjP5C3GwgOlBVhyqEkO8tZUTnnidjTngC1P1nC4NelZ2SY9YxDVyMYwWqxoO/3p 7TdQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n5si344820pfn.150.2017.10.24.08.10.35; Tue, 24 Oct 2017 08:10:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932375AbdJXPKd (ORCPT + 27 others); Tue, 24 Oct 2017 11:10:33 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9042 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751691AbdJXPIt (ORCPT ); Tue, 24 Oct 2017 11:08:49 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29920; Tue, 24 Oct 2017 23:05:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:19 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 13/19] scsi: hisi_sas: init connect cfg register for v3 hw Date: Tue, 24 Oct 2017 23:51:43 +0800 Message-ID: <1508860309-212397-14-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0204.59EF56BA.0192, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a0bbd8151ffd9408ffb7d1b303209af6 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan Add initialization of register CON_CFG_DRIVER for v3 hw, to limit number of the times of setup connection. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 3 +++ 1 file changed, 3 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index c88e787..5fbd121 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -135,6 +135,7 @@ #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) #define STP_LINK_TIMER (PORT_BASE + 0x120) +#define CON_CFG_DRIVER (PORT_BASE + 0x130) #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) @@ -422,6 +423,8 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 0xa03e8); hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); + hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, + 0x2a0a80); } for (i = 0; i < hisi_hba->queue_count; i++) { /* Delivery queue */ From patchwork Tue Oct 24 15:51:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116970 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5918083qgn; Tue, 24 Oct 2017 08:10:10 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TOWwKfM+n7FqmJ3UP8NN4BwY0TtbQ9cgGzIztfYpfrN5IalB5M8W8CX4SegJs+NVL3cu1V X-Received: by 10.99.110.196 with SMTP id j187mr12817544pgc.393.1508857810451; Tue, 24 Oct 2017 08:10:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857810; cv=none; d=google.com; s=arc-20160816; b=Anhek1uL7bepm8ikMyiPz5tw4T851ri5XVje2MgQQf35KfKn2DUG288SAwkVig8xsQ el+V1vhTSPPe8e4g7mz4zKIYSf7XGVJr4ZIV8ixZWPl5nuK/TBsiUczBh8GhO1B3svi7 DcM/JbCG8zoGwjOE56tC8dm925abaALuhp7SedvKsU5eEeVPqYOIxfPelODVh2k+wijh HNBmeZqTrKkkLAp4yddrsqaMb2EOBj2Mj+0KoA2LcfPiEPzRSOUYv82EpaslEg9mxBuR gWzCEtDh05pboQO90fRb/J7ltLPnPhPVxEMRxRV9iPRRzpj29131YLJRZrSF+RRf0gF3 KjVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=QfQ+FPI7av7rdMdGVTX6afHxRrwX7LFNUe5jovh8/mo=; b=s5jihhVslpfpex6BGW982b/0ZG/Em1EFe7es+RCVuyyBslq1enSh0+UpGqRczu8IS/ BwQH8/GZzwL0MhZAa/uczH6rxPPnHGrcZbN38JeG9RloEzR1FcKbg1p5dA1FRut4EyfD j4D3v4LMIt2MwLU7q86rgfBESkV9odj3fzGBcCwPg0hB6yqzep21w5y175JtVf5elx8b zYCHPUOrpkZN/FjVh9SUp6QnDoLoodQuqQQpthibi3Zei21MDSv7rY/alu2UKqlCLW5A fBRSNARI9jls4UFr2WqMiBOlzWKdQrIMhC0gsyt5uKaVLx+FUnS8ujUIIellwO4SyUvD vxew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 125si328287pff.574.2017.10.24.08.10.10; Tue, 24 Oct 2017 08:10:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932317AbdJXPKJ (ORCPT + 27 others); Tue, 24 Oct 2017 11:10:09 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9041 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751750AbdJXPIw (ORCPT ); Tue, 24 Oct 2017 11:08:52 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29915; Tue, 24 Oct 2017 23:05:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:19 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 14/19] scsi: hisi_sas: add v3 hw DFX feature Date: Tue, 24 Oct 2017 23:51:44 +0800 Message-ID: <1508860309-212397-15-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.59EF56BA.0053, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: aa79d9f0b4e4f4506528f382178f94d0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan Realise get_events() to add DFX feature for v3 hw. Just like v2 hw, We support the following errors: - loss_of_dword_sync_count - invalid_dword_count - phy_reset_problem_count - running_disparity_error_count Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 5fbd121..818bd575 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -172,6 +172,10 @@ #define DMA_RX_STATUS (PORT_BASE + 0x2e8) #define DMA_RX_STATUS_BUSY_OFF 0 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) +#define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) +#define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) +#define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) +#define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) @@ -1742,6 +1746,31 @@ static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) return hisi_sas_read32(hisi_hba, PHY_STATE); } +static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; + struct asd_sas_phy *sas_phy = &phy->sas_phy; + struct sas_phy *sphy = sas_phy->phy; + u32 reg_value; + + /* loss dword sync */ + reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); + sphy->loss_of_dword_sync_count += reg_value; + + /* phy reset problem */ + reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); + sphy->phy_reset_problem_count += reg_value; + + /* invalid dword */ + reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); + sphy->invalid_dword_count += reg_value; + + /* disparity err */ + reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); + sphy->running_disparity_error_count += reg_value; + +} + static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; @@ -1794,6 +1823,7 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) .dereg_device = dereg_device_v3_hw, .soft_reset = soft_reset_v3_hw, .get_phys_state = get_phys_state_v3_hw, + .get_events = phy_get_events_v3_hw, }; static struct Scsi_Host * From patchwork Tue Oct 24 15:51:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116966 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5916849qgn; Tue, 24 Oct 2017 08:09:06 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SWFDOi3mXuwBL+Ea8Nkcn7afy88D80MZxC5qpvmU+oMIN/iDiR++U/gaKhcvXQGPdpX+YB X-Received: by 10.84.229.5 with SMTP id b5mr8360184plk.405.1508857746633; Tue, 24 Oct 2017 08:09:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857746; cv=none; d=google.com; s=arc-20160816; b=UGE4qTXpq+qOzIbDrtLzejiWbj+dbHFUc9s48DyCq++nzt1QIGQxDEci5L2gR5I+SN gggOYTAQgkbT1mny0PCuOk+iqaKSOYUBVI44jabUHFeWF3+igdcBcDDUveMNDfKpty2D eT4ZEBKo8msR5uArmNmL2FaW76DXHY/TWUaGIilv1Mkqv9mzlG7cHMorjSYPbE3i7uKb xTsgg8qBsYbphDGG4XGZWHqlSt/99V8q4c9hsyqmRLHa8SC7Q2AIIRG0K/xtG/y8WwoP x4QGkk6HNHFcRHvhh32ZNmlUB3GKCIz2ZPZJoCzmcqZvfQb9As/tsNJF37o0aG3MveIn 5ENw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rmUkAoLLLYHRsz5qRdhfa17c2NjKjuxg+9I80WlY0s8=; b=Mxm4nvNSUD9696z9uAodpJSsplirQDtLS8cLIiHL4ezsnkPsjceJDemG55+ZwlpS9c BZtRbza2EHidCjb02yfzlD3jHZIe17bC2Veh8KkL+veTmNta4tivVaRvEkkqcZNCo2BE SxvyEF6LamGYJGzXCjy/Kti2Y05+oXsIbMnUn0XurAn8FV4a0cH6DajCilZpyxdxn1qI u14rsTk86cgKIlOkRmzFfsVoh8O/M3u0qF3tBjCtR1d/JiGfFChLuNLEiv8onF0ga9Kj E/TLJFLyNVv479aizmVCOQMu+nBDfHRSbHhsLNL6EhzJOLJ97brR30q/rljz3UbIbBQS t9aQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q81si356780pfg.32.2017.10.24.08.09.06; Tue, 24 Oct 2017 08:09:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751964AbdJXPJD (ORCPT + 27 others); Tue, 24 Oct 2017 11:09:03 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9044 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbdJXPI5 (ORCPT ); Tue, 24 Oct 2017 11:08:57 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29926; Tue, 24 Oct 2017 23:05:31 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:20 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 15/19] scsi: hisi_sas: add hisi_hba.rst_work init for v3 hw Date: Tue, 24 Oct 2017 23:51:45 +0800 Message-ID: <1508860309-212397-16-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0208.59EF56BB.01A9, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b8755e3473696631e480efc50ede9111 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan Add init code of hisi_hba->rst_work for v3 hw. Because v3 hw also need it to recover controller when some hw errors occurs. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_main.c | 3 ++- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 58bc69e..00fefea 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -434,4 +434,5 @@ extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task, struct hisi_sas_slot *slot); extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba); +extern void hisi_sas_rst_work_handler(struct work_struct *work); #endif diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 6b4dabde..1d417a4 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1785,13 +1785,14 @@ void hisi_sas_free(struct hisi_hba *hisi_hba) } EXPORT_SYMBOL_GPL(hisi_sas_free); -static void hisi_sas_rst_work_handler(struct work_struct *work) +void hisi_sas_rst_work_handler(struct work_struct *work) { struct hisi_hba *hisi_hba = container_of(work, struct hisi_hba, rst_work); hisi_sas_controller_reset(hisi_hba); } +EXPORT_SYMBOL_GPL(hisi_sas_rst_work_handler); int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba) { diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 818bd575..1f8995b 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1840,6 +1840,7 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) } hisi_hba = shost_priv(shost); + INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); hisi_hba->hw = &hisi_sas_v3_hw; hisi_hba->pci_dev = pdev; hisi_hba->dev = dev; From patchwork Tue Oct 24 15:51:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116967 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5917019qgn; Tue, 24 Oct 2017 08:09:16 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Rn9P5zoZMuCLIQi3QO2s0V2bleGWhyUlFfPyTsniMayLUDQl9zWjvXhc+5Gd0kzD08dD8X X-Received: by 10.99.114.19 with SMTP id n19mr14880243pgc.356.1508857755988; Tue, 24 Oct 2017 08:09:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857755; cv=none; d=google.com; s=arc-20160816; b=ToBNM+HY4i+XNB5u6gvNjHBYo/D/AFA01j5dTsgWwp4bllM0hEjUXJwIv/FHh3/D4v vh1wJVJf4jxb0FkMHm+eBeMa0GUd8GhyeGOXRcP6x86NATZhVUOR8n2aiCgG9xRV7Zhf Aq7PyJ1lmpsZ4N380kMJ9/qy8hW9ytHdPUD7nuUt4sgLwojwPFa9oAnjkLLIRsz08Wh3 e0xgwp4G5uut1aXs5fNQMzYBeJSJ84H9POQ2aFyqGN2xuWrNG4SK4HUeh3qnaKDcrmIa pKtVJWrq3JP81qBHx8C5sjfJC4gR0P46GWReBzDxaBTOeXRM26JdN/QOrEH16c1ic/u9 6c+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Y3f/70WCSTr3Xkvkc0VkAIb1GrF1lIFPsP7yPL0BPN0=; b=ZUrIO2+M55+7Ikmv5Te2ORuXEgGu5bB+4aiB/I+R/4oGw4vEzPBOBqgqGGK4HM6i57 Eetm7GAHQq0Fsfo9vfg6YRFM70kCHCALl+H+S64Dbj5LtXCxBwJnYky7RUcoe/fb+2ex x2eCviFqeABZd4rpzQKN4arggYOHK3y4X518ewS4pHlUFpTs5JcIX9zX4gBFsoLddRgg ef3rHlG9gov7uSLS19N2znJFZ967lkkviwdvHOvPzxeQVuAmoW+jGfuFMYbEysT9/KPW fQOOJeJuYqkwm8ib710pop9qAxSjFYubzYF/obo/7L1WlREBq3VwxdFxCwyOUIXUZK69 KD+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c30si294953pgn.815.2017.10.24.08.09.15; Tue, 24 Oct 2017 08:09:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932215AbdJXPJO (ORCPT + 27 others); Tue, 24 Oct 2017 11:09:14 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9045 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751969AbdJXPJJ (ORCPT ); Tue, 24 Oct 2017 11:09:09 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29925; Tue, 24 Oct 2017 23:05:31 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:20 +0800 From: John Garry To: , CC: , , , , Xiang Chen , John Garry Subject: [PATCH 16/19] scsi: hisi_sas: fix a bug when free device for v3 hw Date: Tue, 24 Oct 2017 23:51:46 +0800 Message-ID: <1508860309-212397-17-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.59EF56BB.0061, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 121beb882c87e1daadb7504a4b33e160 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Use completion to wait on ITCT CLR interrupt finishing before processing other things when freeing a device. This is safer than the pre-existing process of polling the register. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 1f8995b..243fa1d 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -393,7 +393,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); - hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); @@ -582,35 +582,24 @@ static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, static void free_device_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { + DECLARE_COMPLETION_ONSTACK(completion); u64 dev_id = sas_dev->device_id; - struct device *dev = hisi_hba->dev; struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + sas_dev->completion = &completion; + /* clear the itct interrupt state */ if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) hisi_sas_write32(hisi_hba, ENT_INT_SRC3, ENT_INT_SRC3_ITC_INT_MSK); /* clear the itct table*/ - reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); - reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); + reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); - udelay(10); - reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); - if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { - dev_dbg(dev, "got clear ITCT done interrupt\n"); - - /* invalid the itct state*/ - memset(itct, 0, sizeof(struct hisi_sas_itct)); - hisi_sas_write32(hisi_hba, ENT_INT_SRC3, - ENT_INT_SRC3_ITC_INT_MSK); - - /* clear the itct */ - hisi_sas_write32(hisi_hba, ITCT_CLR, 0); - dev_dbg(dev, "clear ITCT ok\n"); - } + wait_for_completion(sas_dev->completion); + memset(itct, 0, sizeof(struct hisi_sas_itct)); } static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, From patchwork Tue Oct 24 15:51:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116965 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5916644qgn; Tue, 24 Oct 2017 08:08:55 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QrmgVLU9xGXG19iZCAB1Aus7W720Sxx5kkaN8bQvyMcWJBGzY8GC8Ov76yiY/1GoJWGt5E X-Received: by 10.98.105.199 with SMTP id e190mr16852746pfc.275.1508857735427; Tue, 24 Oct 2017 08:08:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857735; cv=none; d=google.com; s=arc-20160816; b=tPLF9o/4ysbJ929qZOsAbXeRazhxJOgDGIY17vEsNOUJDLA0NW2K6Uv5xJqe/h7gc7 GoH3gvXNDMkcy89+zEPWwOuIUJc0v6tL6yy41zdPl52Fd9U6D3bsXE4IlFptPRdkpnuM kLmdSPYJZRNFn1vVL1CmAEcdf9Dy/2wGqECL+XPEclkA5YI5QYe6WFDl1Senl0YKNHDh MHZaSdTwrThKY4C8ryFVymavMpHrWgXbfoood0Sp8CzKezergm4Bwq97qB5y1eGObjmn LtLWKKohv/afeRG+Nx72PoPW979/sa32JLryRJpLr7R0tiRn2Y0yFRrbWFZN49ygiF02 auRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rIfK5thYjiILQozM12DWaCQaZ/c34BgxGMqpiuuIlY4=; b=OzeKcm9itMjY6YvOYnbB9tus+kjEHM37zKTiaUcNsLwsrj8KcPp6bqKptud+AHOok9 ZARQ8cKHvsKuA2HzCrhxKoipRXThlnng0hhgDXrRJnOWB8Eube7ZDTnRzU5IR7Y0vcUQ yEACOPmYvWE7PRhVPtQhWEpvAaQrDiL/goPBE/DCvVU+xZzgML7IEeYrPCUw5PZiURqs qxM2IN2VJywUs2/QYC3jk9MxMV7IPceh8O95h8H5XUIYDHACMQP3G6D9ekiUQz+FIkkK CTPXnxoVIve9pw/t9567A/1/4sbrf8HiBGgl3DO8ybeuWmm5F6j2cIaMxud+nOAMbLEB HfQw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g8si273703plt.186.2017.10.24.08.08.55; Tue, 24 Oct 2017 08:08:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751917AbdJXPIw (ORCPT + 27 others); Tue, 24 Oct 2017 11:08:52 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9043 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbdJXPIr (ORCPT ); Tue, 24 Oct 2017 11:08:47 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29921; Tue, 24 Oct 2017 23:05:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:20 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 17/19] scsi: hisi_sas: complete all tasklets prior to host reset Date: Tue, 24 Oct 2017 23:51:47 +0800 Message-ID: <1508860309-212397-18-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.59EF56BA.012E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 48b47beb8ebb43b616191086e89ab7b5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan The CQ event is handled in tasklet context, and it could be delayed if the system loading is high. It is possible to run into some problems when executing a host reset when cq_tasklet_vx_hw() is being executed. So, prior to host reset, execute tasklet_kill() to ensure that all CQ tasklets are complete. Besides, as the function hisi_sas_wait_tasklets_done() is added to do tasklet_kill(), this patch refactors some code where tasklet_kill() is used. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_main.c | 11 +++++++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 8 ++------ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 3 ++- 4 files changed, 16 insertions(+), 7 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 00fefea..636cdf8 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -435,4 +435,5 @@ extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot); extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba); extern void hisi_sas_rst_work_handler(struct work_struct *work); +extern void hisi_sas_kill_tasklets(struct hisi_hba *hisi_hba); #endif diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 1d417a4..4cbb999 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1548,6 +1548,17 @@ void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy) } EXPORT_SYMBOL_GPL(hisi_sas_phy_down); +void hisi_sas_kill_tasklets(struct hisi_hba *hisi_hba) +{ + int i; + + for (i = 0; i < hisi_hba->queue_count; i++) { + struct hisi_sas_cq *cq = &hisi_hba->cq[i]; + + tasklet_kill(&cq->tasklet); + } +} +EXPORT_SYMBOL_GPL(hisi_sas_kill_tasklets); struct scsi_transport_template *hisi_sas_stt; EXPORT_SYMBOL_GPL(hisi_sas_stt); diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 8626d9f..433412a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -3512,6 +3512,7 @@ static int soft_reset_v2_hw(struct hisi_hba *hisi_hba) interrupt_disable_v2_hw(hisi_hba); hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); + hisi_sas_kill_tasklets(hisi_hba); hisi_sas_stop_phys(hisi_hba); @@ -3595,16 +3596,11 @@ static int hisi_sas_v2_remove(struct platform_device *pdev) { struct sas_ha_struct *sha = platform_get_drvdata(pdev); struct hisi_hba *hisi_hba = sha->lldd_ha; - int i; if (timer_pending(&hisi_hba->timer)) del_timer(&hisi_hba->timer); - for (i = 0; i < hisi_hba->queue_count; i++) { - struct hisi_sas_cq *cq = &hisi_hba->cq[i]; - - tasklet_kill(&cq->tasklet); - } + hisi_sas_kill_tasklets(hisi_hba); return hisi_sas_remove(pdev); } diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 243fa1d..18cc3b4 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1768,6 +1768,7 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) interrupt_disable_v3_hw(hisi_hba); hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); + hisi_sas_kill_tasklets(hisi_hba); hisi_sas_stop_phys(hisi_hba); @@ -1977,7 +1978,6 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) struct hisi_sas_cq *cq = &hisi_hba->cq[i]; free_irq(pci_irq_vector(pdev, i+16), cq); - tasklet_kill(&cq->tasklet); } pci_free_irq_vectors(pdev); } @@ -1993,6 +1993,7 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) sas_remove_host(sha->core.shost); hisi_sas_v3_destroy_irqs(pdev, hisi_hba); + hisi_sas_kill_tasklets(hisi_hba); pci_release_regions(pdev); pci_disable_device(pdev); hisi_sas_free(hisi_hba);