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X-Host: mariner.tdc.vzwcorp.com Received: from ohtwi1exh003.uswin.ad.vzwcorp.com ([10.144.218.45]) by eris.verizonwireless.com with ESMTP/TLS/AES128-SHA256; 25 Oct 2017 01:56:01 +0000 Received: from tbwexch06apd.uswin.ad.vzwcorp.com (153.114.162.30) by OHTWI1EXH003.uswin.ad.vzwcorp.com (10.144.218.45) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 24 Oct 2017 21:56:01 -0400 Received: from OMZP1LUMXCA20.uswin.ad.vzwcorp.com (144.8.22.198) by tbwexch06apd.uswin.ad.vzwcorp.com (153.114.162.30) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 24 Oct 2017 21:56:01 -0400 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) by OMZP1LUMXCA20.uswin.ad.vzwcorp.com (144.8.22.198) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 24 Oct 2017 20:55:58 -0500 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) by OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) with mapi id 15.00.1263.000; Tue, 24 Oct 2017 20:55:58 -0500 To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH AUTOSEL for 4.9 10/50] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks Thread-Topic: [PATCH AUTOSEL for 4.9 10/50] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks Thread-Index: AQHTTTRkRmqKpYKTVkOBvz/ox2XXlg== Date: Wed, 25 Oct 2017 01:55:54 +0000 Message-ID: <20171025015539.24525-10-alexander.levin@verizon.com> References: <20171025015539.24525-1-alexander.levin@verizon.com> In-Reply-To: <20171025015539.24525-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marek Szyprowski [ Upstream commit 5ccb58968bf7f46dbd128df88f71838a5a9750b8 ] Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki Signed-off-by: Sasha Levin --- drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- include/dt-bindings/clock/exynos5433.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) -- 2.11.0 diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index ea1608682d7f..2fe057326552 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -2559,8 +2559,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), /* PHY clocks from MIPI_DPHY0 */ - FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), - FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", + NULL, 0, 188000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", + NULL, 0, 100000000), /* PHY clocks from HDMI_PHY */ FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", NULL, 0, 300000000), diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 4fa6bb2136e3..be39d23e6a32 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -771,7 +771,10 @@ #define CLK_PCLK_DECON 113 -#define DISP_NR_CLK 114 +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 + +#define DISP_NR_CLK 116 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 From patchwork Wed Oct 25 01:55:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Levin, Alexander \(Sasha Levin\)" X-Patchwork-Id: 117003 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp320725qgn; Tue, 24 Oct 2017 18:57:48 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QcNdjFWBPEzBwWkxRwnrtYf+g2mxKO0QbcMZMbvGsgjh0AK9pDUy/WIOqrPsyEN3Uo/Aoq X-Received: by 10.84.235.201 with SMTP id m9mr471148plt.94.1508896667987; Tue, 24 Oct 2017 18:57:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508896667; cv=none; d=google.com; s=arc-20160816; b=E/OMySlRik3oDpZNdM85FUdyVxhWN8uNlKYtd+RxcvsHcwSFRIGYF21RQjylbpQYeS BUl164JL0CAfZLJzJwRg+mbG5CGSrh9pf23mKsTfX7NJ/MXkyxWZczaJ/Y7gJldpz3/i l1R2wEBc8izd6SvL0XlVMEsu8GJr7f4IQAwBF3K4gsXkkeSsDi5Y37JhH7ox94+Zro48 FNwpxOpH+7sCeQ2q5uoXh9mHg5pbJ9EwNLHI7NU8KvF0oqhOInLvGohfeKPM1Fqurj4A z9IRvticAB9qRops5KfwtSwG50gLpvuqYWgr7y5r0oLSWkQbUKMbcVn4fX2rXi+/zeKl 52Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:to:dkim-signature :dkim-signature:cc:from:dkim-signature:arc-authentication-results; bh=WnkqR8h0pkjSFcsBG8+2QXf3UNZ6uF0Jj726gKxTLJ0=; b=GUGxleP7vEodMgU4LWsbLnHSKJsHqxh7ym9YX5k8K+dhTWM44XUbeCB6XFqAoBuorN Pl+nVD96nYt8vYfopPDHgFsBZ1wo09/gWYRSUexuSAOeHZ/aLXDi2JdEwUI6fsebkTU6 I0FEwSU7HQRAIgZo+IO1kRK04SaX4VSoF8poizDOaY2IlyU8B8S41qF5K1M8xDzNba7B NJYLAI7+wCP6wllwX+r9CaSUPu4yL9MqibwxEt5dQv0EsuFK9Lyrbab55cjJK1k6LsUc Pd8pBWPGB8fTGp5uJ4aF1pF3GcRRzmrX/dqQV6phpWYJWHNF2hjYEwkO5hkNd1MzlRlE 00Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@verizon.com header.s=corp header.b=siopE1RC; dkim=fail header.i=@verizon.com header.s=corp header.b=LVmUH0uq; dkim=fail header.i=@verizon.com header.s=corp header.b=LVmUH0uq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=verizon.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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X-Host: mariner.tdc.vzwcorp.com Received: from ohtwi1exh001.uswin.ad.vzwcorp.com ([10.144.218.43]) by eris.verizonwireless.com with ESMTP/TLS/AES128-SHA256; 25 Oct 2017 01:56:04 +0000 Received: from tbwexch12apd.uswin.ad.vzwcorp.com (153.114.162.36) by OHTWI1EXH001.uswin.ad.vzwcorp.com (10.144.218.43) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 24 Oct 2017 21:56:04 -0400 Received: from OMZP1LUMXCA19.uswin.ad.vzwcorp.com (144.8.22.197) by tbwexch12apd.uswin.ad.vzwcorp.com (153.114.162.36) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 24 Oct 2017 21:56:04 -0400 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) by OMZP1LUMXCA19.uswin.ad.vzwcorp.com (144.8.22.197) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 24 Oct 2017 20:56:03 -0500 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) by OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) with mapi id 15.00.1263.000; Tue, 24 Oct 2017 20:56:03 -0500 To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH AUTOSEL for 4.9 18/50] arm64: dma-mapping: Only swizzle DMA ops for IOMMU_DOMAIN_DMA Thread-Topic: [PATCH AUTOSEL for 4.9 18/50] arm64: dma-mapping: Only swizzle DMA ops for IOMMU_DOMAIN_DMA Thread-Index: AQHTTTRlAW6RuxOz0kaTMEt7Kht5wA== Date: Wed, 25 Oct 2017 01:55:56 +0000 Message-ID: <20171025015539.24525-18-alexander.levin@verizon.com> References: <20171025015539.24525-1-alexander.levin@verizon.com> In-Reply-To: <20171025015539.24525-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon [ Upstream commit 4a8d8a14c0d08c2437cb80c05e88f6cc1ca3fb2c ] The arm64 DMA-mapping implementation sets the DMA ops to the IOMMU DMA ops if we detect that an IOMMU is present for the master and the DMA ranges are valid. In the case when the IOMMU domain for the device is not of type IOMMU_DOMAIN_DMA, then we have no business swizzling the ops, since we're not in control of the underlying address space. This patch leaves the DMA ops alone for masters attached to non-DMA IOMMU domains. Reviewed-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm64/mm/dma-mapping.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) -- 2.11.0 diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index b5bf46ce873b..cab3574ab7d9 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -836,14 +836,21 @@ static bool do_iommu_attach(struct device *dev, const struct iommu_ops *ops, * then the IOMMU core will have already configured a group for this * device, and allocated the default domain for that group. */ - if (!domain || iommu_dma_init_domain(domain, dma_base, size, dev)) { - pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n", - dev_name(dev)); - return false; + if (!domain) + goto out_err; + + if (domain->type == IOMMU_DOMAIN_DMA) { + if (iommu_dma_init_domain(domain, dma_base, size, dev)) + goto out_err; + + dev->archdata.dma_ops = &iommu_dma_ops; } - dev->archdata.dma_ops = &iommu_dma_ops; return true; +out_err: + pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n", + dev_name(dev)); + return false; } static void queue_iommu_attach(struct device *dev, const struct iommu_ops *ops,