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[198.145.21.10]) by mx.google.com with ESMTPS id b2si1403437pgr.511.2017.10.24.23.46.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Oct 2017 23:46:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=gvGTybLx; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B88A62034C089; Tue, 24 Oct 2017 23:43:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C195920347156 for ; Tue, 24 Oct 2017 23:43:01 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id a2so4502923lfh.11 for ; Tue, 24 Oct 2017 23:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qZ+h2MPyUS32AeRZekIxNmJznIldLjpejjkh+JDaO3Q=; b=gvGTybLxrxJy54mx1z1DB9af18hLaJUqohIFKPJWoB7ktirpCP/lVo3IiU4pFxBkuv NeKDHZCXZDDA5QCC1uvNsmblf+2qOQlwr6I0ICiegOE049jNAd6IWoTKGZ8W3Cq8yZGv Y17I6sDnA6F6z0JCJryDH2oThSYJG+DPR52qxMFbTSqhfFHBp1bHcMCcWE7vbeqatOOP AuafcEPghAvLqlrj5r+KZMuWR8iHlM9XPQ1x1gOL28N7moW0tXDlJsKaSJMqeCFhfchA 9de8ybcuW9YsB6GU9lLX0HuV8HbzMXliOEZ0WrWFqhfrmMg0fWwDGDz2B7k4MNfbYFvT U3vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qZ+h2MPyUS32AeRZekIxNmJznIldLjpejjkh+JDaO3Q=; b=mHbH01qDEOGTaiI2coQw++WAQ4QvUh82Y9lqZEHvcnq8vm7SeTmiwD0xikMr7yry8w XlR933mxlnZCXynlQ+Ubp/mhmF8Lp67H/mXFGfIUsQJIAwJZEOXAIxKHAQs39rN9qKhc 1B64SR39LZtXpSv1d90ntg0pSKSwIF3sWHZVibMfgIPk6R7uRid/k5ny3vn75QTH7x2+ p47LqRdOgRQEJUQ7ZtVmHj3m8dfRhUoYm9lZqA9jaWD/bX2JMwVcjtJg9fwp3K4UvRJY VLlkN/0r04D6dm7oxyPbtPOtDVbbKTuttKYGqMlD/XyVDkUKMbu7fhp3m7lrsWRcf+GE NXaQ== X-Gm-Message-State: AMCzsaUvT9Me6LoWVCAXlKB6phx1EyEjGP6agnm891GpoCxQuKnnwpzs tFNqp8jJjmhbQfH/LhxDS8m/dp+Hc6U= X-Received: by 10.46.9.197 with SMTP id 188mr7600424ljj.134.1508914004326; Tue, 24 Oct 2017 23:46:44 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:43 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:23 +0200 Message-Id: <1508913930-30886-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Add an implementation of EFI_RNG_PROTOCOL so that the OS loader has access to entropy for KASLR and other purposes (i.e., seeding the OS's entropy pool very early on). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 4 + Platform/Marvell/Armada/Armada70x0.fdf | 1 + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c | 255 ++++++++++++++++++++ Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf | 47 ++++ Platform/Marvell/Marvell.dec | 3 + 5 files changed, 310 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index 1aa485c..ec24d76 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -364,6 +364,9 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 + # TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform @@ -400,6 +403,7 @@ Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf Platform/Marvell/Drivers/Spi/MvSpiDxe.inf Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf # Network support MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf index 933c3ed..a94a9ff 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -113,6 +113,7 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c INF Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf INF Platform/Marvell/Drivers/Spi/MvSpiDxe.inf INF Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + INF Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf # Network support INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c new file mode 100644 index 0000000..014443d --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c @@ -0,0 +1,255 @@ +/** @file + + This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG + + Copyright (C) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +#include + +#define TRNG_OUTPUT_REG mTrngBaseAddress +#define TRNG_OUTPUT_SIZE 0x10 + +#define TRNG_STATUS_REG (mTrngBaseAddress + 0x10) +#define TRNG_STATUS_READY BIT0 + +#define TRNG_INTACK_REG (mTrngBaseAddress + 0x10) +#define TRNG_INTACK_READY BIT0 + +#define TRNG_CONTROL_REG (mTrngBaseAddress + 0x14) +#define TRNG_CONTROL_REG_ENABLE BIT10 + +#define TRNG_CONFIG_REG (mTrngBaseAddress + 0x18) +#define __MIN_REFILL_SHIFT 0 +#define __MAX_REFILL_SHIFT 16 +#define TRNG_CONFIG_MIN_REFILL_CYCLES (0x05 << __MIN_REFILL_SHIFT) +#define TRNG_CONFIG_MAX_REFILL_CYCLES (0x22 << __MAX_REFILL_SHIFT) + +#define TRNG_FRODETUNE_REG (mTrngBaseAddress + 0x24) +#define TRNG_FRODETUNE_MASK 0x0 + +#define TRNG_FROENABLE_REG (mTrngBaseAddress + 0x20) +#define TRNG_FROENABLE_MASK 0xffffff + +#define TRNG_MAX_RETRIES 20 + +STATIC EFI_PHYSICAL_ADDRESS mTrngBaseAddress; + +/** + Returns information about the random number generation implementation. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in,out] RNGAlgorithmListSize On input, the size in bytes of + RNGAlgorithmList. + On output with a return code of + EFI_SUCCESS, the size in bytes of the + data returned in RNGAlgorithmList. On + output with a return code of + EFI_BUFFER_TOO_SMALL, the size of + RNGAlgorithmList required to obtain the + list. + @param[out] RNGAlgorithmList A caller-allocated memory buffer filled + by the driver with one EFI_RNG_ALGORITHM + element for each supported RNG algorithm. + The list must not change across multiple + calls to the same driver. The first + algorithm in the list is the default + algorithm for the driver. + + @retval EFI_SUCCESS The RNG algorithm list was returned + successfully. + @retval EFI_UNSUPPORTED The services is not supported by this + driver. + @retval EFI_DEVICE_ERROR The list of algorithms could not be + retrieved due to a hardware or firmware + error. + @retval EFI_INVALID_PARAMETER One or more of the parameters are + incorrect. + @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small + to hold the result. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetInfo ( + IN EFI_RNG_PROTOCOL *This, + IN OUT UINTN *RNGAlgorithmListSize, + OUT EFI_RNG_ALGORITHM *RNGAlgorithmList + ) +{ + if (This == NULL || RNGAlgorithmListSize == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) { + *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM); + return EFI_BUFFER_TOO_SMALL; + } + + if (RNGAlgorithmList == NULL) { + return EFI_INVALID_PARAMETER; + } + + *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM); + CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetTrngData ( + IN UINTN Length, + OUT UINT8 *Bits + ) +{ + UINTN Tries; + UINT32 Buf[TRNG_OUTPUT_SIZE / sizeof (UINT32)]; + UINTN Index; + + for (Tries = 0; Tries < TRNG_MAX_RETRIES; Tries++) { + if (MmioRead32 (TRNG_STATUS_REG) & TRNG_STATUS_READY) { + for (Index = 0; Index < ARRAY_SIZE (Buf); Index++) { + Buf[Index] = MmioRead32 (TRNG_OUTPUT_REG + Index * sizeof (UINT32)); + } + CopyMem (Bits, Buf, Length); + MmioWrite32 (TRNG_INTACK_REG, TRNG_INTACK_READY); + + return EFI_SUCCESS; + } + // Wait for more TRNG data to arrive + gBS->Stall (10); + } + return EFI_DEVICE_ERROR; +} + +/** + Produces and returns an RNG value using either the default or specified RNG + algorithm. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that + identifies the RNG algorithm to use. May + be NULL in which case the function will + use its default RNG algorithm. + @param[in] RNGValueLength The length in bytes of the memory buffer + pointed to by RNGValue. The driver shall + return exactly this numbers of bytes. + @param[out] RNGValue A caller-allocated memory buffer filled + by the driver with the resulting RNG + value. + + @retval EFI_SUCCESS The RNG value was returned successfully. + @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm + is not supported by this driver. + @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due + to a hardware or firmware error. + @retval EFI_NOT_READY There is not enough random data available + to satisfy the length requested by + RNGValueLength. + @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is + zero. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetRNG ( + IN EFI_RNG_PROTOCOL *This, + IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL + IN UINTN RNGValueLength, + OUT UINT8 *RNGValue + ) +{ + UINTN Length; + EFI_STATUS Status; + + if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // We only support the raw algorithm, so reject requests for anything else + // + if (RNGAlgorithm != NULL && + !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) { + return EFI_UNSUPPORTED; + } + + do { + Length = MIN (RNGValueLength, TRNG_OUTPUT_SIZE); + Status = GetTrngData (Length, RNGValue); + if (EFI_ERROR (Status)) { + return Status; + } + + RNGValue += Length; + RNGValueLength -= Length; + } while (RNGValueLength > 0); + + return EFI_SUCCESS; +} + +STATIC EFI_RNG_PROTOCOL mArmada70x0RngProtocol = { + Armada70x0RngGetInfo, + Armada70x0RngGetRNG +}; + +// +// Entry point of this driver. +// +EFI_STATUS +EFIAPI +Armada70x0RngDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mTrngBaseAddress = PcdGet64 (PcdEip76TrngBaseAddress); + + // + // Disable the TRNG before updating its configuration + // + MmioAnd32 (TRNG_CONTROL_REG, ~TRNG_CONTROL_REG_ENABLE); + + // + // Configure the internal conditioning parameters of the TRNG + // + MmioWrite32 (TRNG_CONFIG_REG, TRNG_CONFIG_MIN_REFILL_CYCLES | + TRNG_CONFIG_MAX_REFILL_CYCLES); + + // + // Configure the FROs + // + MmioWrite32 (TRNG_FRODETUNE_REG, TRNG_FRODETUNE_MASK); + MmioWrite32 (TRNG_FROENABLE_REG, TRNG_FROENABLE_MASK); + + // + // Enable the TRNG + // + MmioOr32 (TRNG_CONTROL_REG, TRNG_CONTROL_REG_ENABLE); + + return SystemTable->BootServices->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiRngProtocolGuid, + &mArmada70x0RngProtocol, + NULL + ); +} diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf new file mode 100644 index 0000000..189ffc5 --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf @@ -0,0 +1,47 @@ +## @file +# This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG +# +# Copyright (C) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Armada70x0RngDxe + FILE_GUID = dd87096a-cae5-4328-bec1-2ddb755f2e08 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = Armada70x0RngDxeEntryPoint + +[Sources] + Armada70x0RngDxe.c + +[Packages] + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + BaseMemoryLib + IoLib + PcdLib + UefiDriverEntryPoint + +[Pcd] + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress + +[Protocols] + gEfiRngProtocolGuid ## PRODUCES + +[Guids] + gEfiRngAlgorithmRaw + +[Depex] + TRUE diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index e7d7c2c..78f5e53 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -195,6 +195,9 @@ #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 +#TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 + [Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} From patchwork Wed Oct 25 06:45:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 117019 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp509405qgn; Tue, 24 Oct 2017 23:46:51 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RG8AVYC+ww/vAQ8r/h32EBPdTwTKsMRIOOD/FCoH8fkNht/bUrDs7e4SR5Q8DPj+C/Mj27 X-Received: by 10.84.131.163 with SMTP id d32mr311527pld.73.1508914011270; Tue, 24 Oct 2017 23:46:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508914011; cv=none; d=google.com; s=arc-20160816; b=YZ85SJA8ezOk+dNGHfQOSDEGQolGk9qEnzfFPAR86yckOq7Mgs9ZIQaiIiUbMaku21 8zOx7mW1GQlO1coduhCmKt5SztVZPPWTXJRQKNd8ePp237QpUJ9F97alDzZlL2zKe1Za 3ogeQIXG9JGtSmvkUQDJZQF9e0QF1aUWfabRP5a+NJKFghzxTAFaEyPRnpGmeC4Vg5rP OOhxVJIUJcLYRTiqu9WDxWbl5AXPllK7OdrhvvGRtEYjL46k1cCmevoFIUi87a/xctAZ NDCR4yZv3Xb4YZibcvRtqCtKuEulxd4VaFpgOGbo2lnlHSD5wLy0r2chPzm3anYixz0I JRSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=bWMq1VNXPTNRRLIRezXCZgujGnDt4MylWDNzCzBZwKk=; b=zYejdwo+ERYKyVnKKAKy9dnsb7LBnv2FFsScOfhONDfI/Ne6M+by3C8ud9HeGGfVnS N1jKfGN3PUrkqRyGQLXptdKcpgI1gRif1YSTmxmXKKs/+w+N0ZKaWjBy+xu7RwCOaULu PQ18BePjCBGyBaWHVF5Z2UZVowztmg9LcBJ/Y2wOe0MCBrIBoWuJQY5c4aI9/uHCmnTa QD97nCFQ7Rvea2qSqhb3LhlgAGiXg+v1stzNJFr1wmWH4s0t23XgcudCB4YcQq2bdZo8 jvvhtfx+mc+Odl3EUqENemlYWhA28v52J2U6peB+G+8R0i+/huEKmUA5n5muvBW7aeWo uGMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=piFC+lMY; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:44 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:24 +0200 Message-Id: <1508913930-30886-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/8] Marvell/Armada: Increase preallocated memory region size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel In order to prevent fragmentation of the UEFI memory map, increase the sizes of the preallocated regions. Note that this does not increase the memory footprint of UEFI, it just modifies it allocation policy to keep similar region types together. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index ec24d76..56d8941 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -341,10 +341,10 @@ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|35000 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 From patchwork Wed Oct 25 06:45:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 117020 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp509485qgn; Tue, 24 Oct 2017 23:47:00 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TiUH4iYJc+6DXj216NZFZdiBz/KfB2MuKfYV/5QU6AkiL+XjVOERtKbra+N0WGF0Xgz6wg X-Received: by 10.98.160.90 with SMTP id r87mr1271635pfe.324.1508914020632; Tue, 24 Oct 2017 23:47:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508914020; cv=none; d=google.com; s=arc-20160816; b=JbTstU07uLyQqOaiBjgCOacHx2z8b6f7f2xgW9TPFcf6hCpEBRhGEzQziZJlkjegIz vUU9iN+8BKQzsJtO2hwRC/GM2XR7uD7NKLOlihoRW1iSmm0ldFPvVPKqEb5Nb7/reJ7c IO9/flKyJJz/gql1IVF6T4O7+UQ4AJsI/F/SRigc9Sj2ECfWXJ7Sp1CjBbFHp5vJAh1l zQ70MPL6vFaQm4xsJ17BJ3AK97/nLU7h6gH0XlYXXNRntPeHJMD/I8LlRKcEDN6YGpdg 31AlueoA/Hz6Ck8h2T+/X5Y/qJmMsxYThSqhHY8gp0mDLuoMlfzku5TMr209M0t8IULO u1nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=MC6h5ygRETql90vFYXZ3OmwZo5qICA8ZB5+kPdQalio=; b=w0nXjNw0AYBjcqdqcxbxfXLyu2TSwtMHp+CYg3YoI8BugFtwsTuWrB5aBppH9Ddgyi LM3l78C/6YQl6dXiYlq743hHP4jl8A7q2n0igzZMR93EbOgVh8K+Wd27wFT5YtRNTMj4 R/7UH7WQV/YsxzQuXp5TXcXV3/MEqC4r/2Mo5p85+sWiNjodw6AbcH6I79azlX2beLbF fd0ahIF82vvf+W93fx5cb15KAwvok8ATBqT/WZ00QfIlPec8S93c9kJpO8u9GQXEDtiV Bq+rAt4aHjn1RmCiO56xt9n7iozZmWogJ/KLReTkRIBP1OJg8GSVtW25dmgl0Kkc5jln fO5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=qkiG/9dZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:48 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:27 +0200 Message-Id: <1508913930-30886-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 5/8] Marvell/Armada: Add MemoryInitPeiLib that reserves secure region X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel The default MemoryInitPeiLib implementation insists on reserving the region occupied by our own FV, while this is not necessary at all (the compressed payload is uncompressed elsewhere, so the moment we enter DXE core, we don't care about the FV contents in memory) So clone MemoryInitPeiLib and modify it to suit our needs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 6 +- Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c | 158 ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf | 46 ++++++ Platform/Marvell/Marvell.dec | 8 + 4 files changed, 217 insertions(+), 1 deletion(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index 56d8941..b0a8240 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -153,7 +153,7 @@ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf [LibraryClasses.common.SEC, LibraryClasses.common.PEIM] - MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + MemoryInitPeiLib|Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf [LibraryClasses.common.DXE_CORE] @@ -364,6 +364,10 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 + # Secure region reservation + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000 + # TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c new file mode 100644 index 0000000..53119f4 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c @@ -0,0 +1,158 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2017, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + + VOID *TranslationTableBase; + UINTN TranslationTableSize; + RETURN_STATUS Status; + + Status = ArmConfigureMmu (MemoryTable, + &TranslationTableBase, + &TranslationTableSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } +} + +/*++ + +Routine Description: + + + +Arguments: + + FileHandle - Handle of the file being invoked. + PeiServices - Describes the list of possible PEI Services. + +Returns: + + Status - EFI_SUCCESS if the boot mode could be set + +--*/ +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINT64 ResourceLength; + EFI_PEI_HOB_POINTERS NextHob; + EFI_PHYSICAL_ADDRESS SecureTop; + EFI_PHYSICAL_ADDRESS ResourceTop; + + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + SecureTop = (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase) + + FixedPcdGet32 (PcdSecureRegionSize); + + // + // Search for System Memory Hob that covers the secure firmware, + // and punch a hole in it + // + for (NextHob.Raw = GetHobList (); + NextHob.Raw != NULL; + NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, + NextHob.Raw)) { + + if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && + (FixedPcdGet64 (PcdSecureRegionBase) >= NextHob.ResourceDescriptor->PhysicalStart) && + (SecureTop <= NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength)) + { + ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute; + ResourceLength = NextHob.ResourceDescriptor->ResourceLength; + ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength; + + if (FixedPcdGet64 (PcdSecureRegionBase) == NextHob.ResourceDescriptor->PhysicalStart) { + // + // This region starts right at the start of the reserved region, so we + // can simply move its start pointer and reduce its length by the same + // value + // + NextHob.ResourceDescriptor->PhysicalStart += FixedPcdGet32 (PcdSecureRegionSize); + NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize); + + } else if ((NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength) == SecureTop) { + + // + // This region ends right at the end of the reserved region, so we + // can simply reduce its length by the size of the region. + // + NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize); + + } else { + // + // This region covers the reserved region. So split it into two regions, + // each one touching the reserved region at either end, but not covering + // it. + // + NextHob.ResourceDescriptor->ResourceLength = FixedPcdGet64 (PcdSecureRegionBase) - + NextHob.ResourceDescriptor->PhysicalStart; + + // Create the System Memory HOB for the remaining region (top of the FD) + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + SecureTop, + ResourceTop - SecureTop); + } + + // + // Reserve the memory space occupied by the secure firmware + // + BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED, + 0, + FixedPcdGet64 (PcdSecureRegionBase), + FixedPcdGet32 (PcdSecureRegionSize)); + + break; + } + NextHob.Raw = GET_NEXT_HOB (NextHob); + } + + // Build Memory Allocation Hob + InitMmu (MemoryTable); + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf new file mode 100644 index 0000000..ebaed01 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf @@ -0,0 +1,46 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Armada70x0MemoryInitPeiLib + FILE_GUID = abc4e8a7-89a7-4aea-92bc-0e9421c4a473 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM + +[Sources] + Armada70x0MemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + ArmPlatformLib + DebugLib + HobLib + ArmMmuLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdSecureRegionBase + gMarvellTokenSpaceGuid.PcdSecureRegionSize diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 36a9d59..cd800c8 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -197,6 +197,14 @@ #Configuration space gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054 + # + # The secure firmware may occupy a DRAM region that is accessible by the + # normal world. These PCDs describe such a region, which will be converted + # to 'reserved' memory before DXE is entered. + # + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x0|UINT64|0x50000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001 + [Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} From patchwork Wed Oct 25 06:45:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 117021 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp509561qgn; Tue, 24 Oct 2017 23:47:08 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TiDwfA5KDIs751RC/Vl1nm3UzdDAUP6KZrXLD0GzvY40T2QhqwIipFYtaNMvZ2R8Mb/ni5 X-Received: by 10.99.4.133 with SMTP id 127mr1121772pge.72.1508914028189; Tue, 24 Oct 2017 23:47:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508914028; cv=none; d=google.com; s=arc-20160816; b=dvDJ2VpWAdk4qHynfnqYfr7jcx8zVy/Tb1Wuvn6hEszETNghv+51tnp9RPc/PTHBCb jgWkmf5InjFZIyvQQr8FrVm3Hp3sAH76k6z6KQTcac8BUQq1Vwqqpkp9s+NkN5Z6UDO9 32a97dTs+GgRkg6ZDV/sbsrpuW5N76GcQefjmPSMSbchfx9cE4/YBAgyIfrh8D4gSPlm wW5VTSrxaeyH56+QS4e+F6QJZ390jPCYhkgHrnkASg/SZeUXr7uRZkreUK+jl5bpb12N LTRSHDjqu+nrDq8a8/6rBsnlXKPRyusf2SY4WKNFWrkamw/n7dIZds2WOrFkm/2EQ9va yGQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=kjOKiqJqeI2RoJ4gwtAOdjf+S+7J8YroQwOGxANTTp4=; b=psVzfrHul4kstnpwtHq4lFEnvTly9+9KEUIhefsH1n8M4T+RgqbLcTSuG6Oa52IQHF nsUHR5/vvemz9CHTli8Y3j9V+2F1NNtBcg/RNQ4NJCoZoqpOazzUC+uZGlTcUHGLQhle ooX3LyAopk/RwzZfnjPmJvehRm/21CXtH6fvKiyoh1+VD7jVOM+vSmv4CUYOyn3pCJvy FNeb+iG4RK3rfFT1hHDzj4PF7QUWCl1P3wrdBio/dlpsBsT85O0VQUa9sTo4Fjh+9wuV RmEy5Fmw7nzEAz5CyDBpBq38xqZLg29v79xnFI1h5vSq8n4D0Q6ymIISTAaBRpgCfJzr io7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=PmT0Rlip; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:51 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:29 +0200 Message-Id: <1508913930-30886-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 7/8] Marvell/Armada: Armada70x0Lib: Add support for 32-bit ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Add an ARM implementation of ArmPlatformHelper.S. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S | 77 ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3 + 2 files changed, 80 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S new file mode 100644 index 0000000..21459e5 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S @@ -0,0 +1,77 @@ +//Based on ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHelper.S +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// Copyright (c) 2016, Marvell. All rights reserved. +// Copyright (c) 2017, Linaro Limited. All rights reserved. +// +// This program and the accompanying materials are licensed and made available +// under the terms and conditions of the BSD License which accompanies this +// distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +// + +#include +#include + +#define CCU_MC_BASE 0xF0001700 +#define CCU_MC_RCR_OFFSET 0x0 +#define CCU_MC_RCR_REMAP_EN BIT0 +#define CCU_MC_RCR_REMAP_SIZE(Size) (((Size) - 1) ^ (SIZE_1MB - 1)) + +#define CCU_MC_RSBR_OFFSET 0x4 +#define CCU_MC_RSBR_SOURCE_BASE(Base) (((Base) >> 20) << 10) +#define CCU_MC_RTBR_OFFSET 0x8 +#define CCU_MC_RTBR_TARGET_BASE(Base) (((Base) >> 20) << 10) + +ASM_FUNC(ArmPlatformPeiBootAction) + .if FixedPcdGet64 (PcdSystemMemoryBase) != 0 + .err PcdSystemMemoryBase should be 0x0 on this platform! + .endif + + .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapTarget) + // + // Use the low range for UEFI itself. The remaining memory will be mapped + // and added to the GCD map later. + // + ADRL (r0, mSystemMemoryEnd) + MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1) + mov r3, #0 + strd r2, r3, [r0] + .endif + + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (r0, FixedPcdGet32(PcdArmPrimaryCore)) + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and r0, r0, r1 + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2236d9f..71abdd4 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -60,6 +60,9 @@ [Sources.AArch64] AArch64/ArmPlatformHelper.S +[Sources.ARM] + ARM/ArmPlatformHelper.S + [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize From patchwork Wed Oct 25 06:45:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 117022 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp509615qgn; Tue, 24 Oct 2017 23:47:12 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TV3+L2FG3db173EgumYpaai3aAP9qKuTy3sPnGVNqsWe36hiyoC9zvzLHpBpngxDfAvAHu X-Received: by 10.98.189.9 with SMTP id a9mr1238414pff.323.1508914032441; Tue, 24 Oct 2017 23:47:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508914032; cv=none; d=google.com; s=arc-20160816; b=XywQ1kBirmMXMozeJo3RuswCnnbQ7F4lK9oWZdmM9YavKezR/cP393X+NF7PkjmjCH UpG807TrtZilPKI+3mlniM7IfoHbxXSG6aVfoVXYKDF8vCzZSX0c9jWA/2JQiXLs6cZY LGDlTkZetJQfDmrOXFFC29rnc3rCkxCUef21bV8x3e/3HljhT8O+90jNyMtfwb/PwZr+ nS2HuDPVmNSfrd7Sc4334LQtZwAiyofxfB7khh2OGTSV9GmlzuIR6fHwyXH9TZxBu5ZN RYPhgHRZsF3prLt8Tgp8NlcQnsw2nEaSryP9Q3ZWv60utOcGmlCMNNBNJcn2RM4xYyMd 4VTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=jmJoGzCyxfnuiy35lxwLYhTDvf3B2vwZZvuI2f2AlfA=; b=umjGDvbjYxfqtpTwfXxsaN+N/jwZf2InySo268m437sAAvq+p4LBPbe/8SLQ5V2fdB PbfVeLWTqfG4QuwsIVTg9KnR4BueFupIsafGPjVPzDDGbk7Kki/G3+wVyJmHl8AlGKDA bnG0KznXJHyfwOZI6bje/l1Fdh8gwktBsKXH0+F6sbajfQq1XbqZcyjVaDpiezO445B1 pCwAd3ppXieecclZed+8Jm+O3+19SmUTl+OauJjHz7AhGCa9GzvTeqjB2pvg1SvTxq0m sZrt8dh/fjsuIRAe0K5npyjveuDZo+Q8B3w64kvgAPX/QeO0PTM88HbT/Yuywxx+Fr/N ilzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=lg+y/Auk; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:30 +0200 Message-Id: <1508913930-30886-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 8/8] Marvell/Armada: Add 32-bit ARM support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Update the included components and library classes to make this platform build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 3 +-- Platform/Marvell/Armada/Armada70x0.dsc | 4 ++-- Platform/Marvell/Armada/Armada70x0.fdf | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index b0a8240..b9fc384 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -132,7 +132,6 @@ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf -[LibraryClasses.AARCH64] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf @@ -362,7 +361,7 @@ # ARM Pcds gArmTokenSpaceGuid.PcdSystemMemoryBase|0 gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 - gArmTokenSpaceGuid.PcdArmScr|0x531 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 # Secure region reservation gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc index 946c93e..0396e8e 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -39,8 +39,8 @@ PLATFORM_GUID = f837e231-cfc7-4f56-9a0f-5b218d746ae3 PLATFORM_VERSION = 0.1 DSC_SPECIFICATION = 0x00010005 - OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES = AARCH64 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES = AARCH64|ARM BUILD_TARGETS = DEBUG|RELEASE SKUID_IDENTIFIER = DEFAULT FLASH_DEFINITION = Platform/Marvell/Armada/Armada70x0.fdf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf index a94a9ff..ec2c368 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -237,7 +237,7 @@ READ_LOCK_STATUS = TRUE # ############################################################################ -[Rule.AARCH64.SEC] +[Rule.Common.SEC] FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED { TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi }