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Peter Anvin" , Jiri Olsa , Mark Rutland , Michael Petlan , Namhyung Kim , LKML , x86 , stable@vger.kernel.org Subject: [PATCH v2 2/7] perf/x86/amd: Fix sampling Large Increment per Cycle events Date: Tue, 8 Sep 2020 16:47:35 -0500 Message-Id: <20200908214740.18097-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200908214740.18097-1-kim.phillips@amd.com> References: <20200908214740.18097-1-kim.phillips@amd.com> X-ClientProxiedBy: DM5PR12CA0060.namprd12.prod.outlook.com (2603:10b6:3:103::22) To BN8PR12MB2946.namprd12.prod.outlook.com (2603:10b6:408:9d::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fritz.amd.com (165.204.77.11) by DM5PR12CA0060.namprd12.prod.outlook.com (2603:10b6:3:103::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Tue, 8 Sep 2020 21:48:17 +0000 X-Mailer: git-send-email 2.27.0 X-Originating-IP: [165.204.77.11] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7677255e-58eb-4a98-cddf-08d85440e6a4 X-MS-TrafficTypeDiagnostic: BN8PR12MB2882: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UHdFaXgkR1/DNQ6lqoxMgTeXXdACBhHTjnFthJKEQtDjO+oHevWSQdUw/2hcFsJ1Qbo21v2p0GoCasgkZALFMw0caFEoTcRZ31HEbZjOUBFlWnh2yjNm/+4DZRPlVG7XdTcUUNkFkRHE5LZsq3Qj8xhV9LVwm88x6vUWGj8h0+MgrYhZJwF2Li67VxfbKZXrXzK2TnGLsg0aR4pPwq1DZqbRSl6hZCGsC97f34lFRjdL/QrEwmiSLaizfae/EV0j/d9clquVD+fX8mfg5xmORwOuvUK5rtNYfoUXllyW8d99DE4ssuRMiZfheJM4WnU6aXyYQxKwYuhTz7zSpYVuAJUKEWGzFgKLSUuR0Pz1JWnmH+ny2c/J3iycW/MTc2aP4vAPcK2jytlH0IIIc/auMw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN8PR12MB2946.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(346002)(366004)(136003)(376002)(39860400002)(396003)(54906003)(52116002)(7696005)(4326008)(26005)(186003)(110136005)(66556008)(66476007)(66946007)(5660300002)(2906002)(1076003)(36756003)(86362001)(6666004)(966005)(316002)(16526019)(44832011)(6486002)(478600001)(2616005)(8936002)(956004)(8676002)(83380400001)(7416002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: 8VrGMdvs6MCVt35gA8f3ZYRYfpw++B0zqGQXEfyjVywxsi5cG39ycy0G1OjSKOH+R5K+06dOpUPXqEfWkFtjSdx98F9uiBZYYaoK0FVYXNcC+1307yHjXHUfaGnbuy4jNgJ8jfebexJWI3t/zo/PIgetpo+cKOlDFQyuWCrLUbF9Jk553iHWWgDMCsBSVb8QTN1uGD6a2hbnA0/5I8oOD/vzr7PMYDm1GcLi7fQ9ayJG2k8XRLQ/tRuYBFyoK/lPnImDlSsFSVOcohdDYtE6ye0LzGbitywMcE+McY0tDvxB8iISUZIAME0Wtsiez6CcKO+gXfJGENDa6M1X89P9MZeXfWRLMX/z5yCQaCGN5UUorvfwz0OHNKPH2e+E7/bxNNQvofVOxUMrM2YJaJHRutPnSTsWZBfQEgwZjpa9ku+HbGomvv1HMNgiMlAKbaSmyq6wQeHvQFYhFWCw5TA4hvV1yxVVxjOqJN2D8a806lBkM7uTbewrlURMgJdi/6B+fjMHzwP2JBFP8NIuek+1dVxBAmvTH1h0Ox+bpkXzQM9ceXfU8uIISgeA8zYTVLierBJ6vpvRp/n7zIMIrJezSKhL1MuIG81Cjs9JOiS7rkEENvadS91zu7VKp0E6J0rc1iR2Fn9f0whp4EYf5gUHPQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7677255e-58eb-4a98-cddf-08d85440e6a4 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB2946.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2020 21:48:19.9224 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gemmEf7IpNM4ii/q1eBq72V2P6OFuxftXa56OeqIk9Xu1bk4lDcTFo1CYSN26cPbIzJsjHhG+LorIRg4cf1NMQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2882 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Commit 5738891229a2 ("perf/x86/amd: Add support for Large Increment per Cycle Events") mistakenly zeroes the upper 16 bits of the count in set_period(). That's fine for counting with perf stat, but not sampling with perf record when only Large Increment events are being sampled. To enable sampling, we sign extend the upper 16 bits of the merged counter pair as described in the Family 17h PPRs: "Software wanting to preload a value to a merged counter pair writes the high-order 16-bit value to the low-order 16 bits of the odd counter and then writes the low-order 48-bit value to the even counter. Reading the even counter of the merged counter pair returns the full 64-bit value." Fixes: 5738891229a2 ("perf/x86/amd: Add support for Large Increment per Cycle Events") Signed-off-by: Kim Phillips Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: "H. Peter Anvin" Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: LKML Cc: x86 Cc: stable@vger.kernel.org --- v2: no changes. arch/x86/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 1cbf57dc2ac8..2fdc211e3e56 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1284,11 +1284,11 @@ int x86_perf_event_set_period(struct perf_event *event) wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); /* - * Clear the Merge event counter's upper 16 bits since + * Sign extend the Merge event counter's upper 16 bits since * we currently declare a 48-bit counter width */ if (is_counter_pair(hwc)) - wrmsrl(x86_pmu_event_addr(idx + 1), 0); + wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff); /* * Due to erratum on certan cpu we need From patchwork Tue Sep 8 21:47:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 309863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 432D6C433E2 for ; Tue, 8 Sep 2020 21:48:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DBC722137B for ; Tue, 8 Sep 2020 21:48:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="2mQ79EHC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729741AbgIHVsn (ORCPT ); Tue, 8 Sep 2020 17:48:43 -0400 Received: from mail-dm6nam12on2069.outbound.protection.outlook.com ([40.107.243.69]:56954 "EHLO NAM12-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726434AbgIHVsh (ORCPT ); Tue, 8 Sep 2020 17:48:37 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RpD5HnSkO5rIr567Xm+1wo9OR0Y7eDFonLBDz6n4SmhsCjglTE1gnRGKFwQd/NtBU9QvbXm57aAa1V/PEb9WSHMKNQrcASSOpI0YLehtR/9qOexX8QVF8Q5u7cTv3MMdxgS6dF4KAa5YvKu0Tu28bmuxU9gELROoLszLGU7Rxeell2NhOEBVlhV3wgDhM68VBsXZp4FaFUbLx91gjrC+sOK32E3vyf8r86w5TA3hnqXxv5KTNwgsrxX0BO/jVEF3HLYDSOyuyDb++RfThfJGWyDHxJqkjvqMejAdu/QS7u8HWf7TaFw5opPVJ75HSHT+nLHtfGQe5aBhF3z5Srpikw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5ggWot059eRVohE/cNcVAQIToD+p+Gj+HvAbFM8efco=; b=ZZqP8HHIR+QBpieBpVO8D0vDIJw2n7+2O6xDnqosIMNKOSSQKr42NrDFdne7ky0kgbP+ibd4rpmnSIrobOx4tTFgCwZNXFtUIgIYvDYEyC6jCwq/OEx84ioZl2Y3TBfFqDIfuJPpYXxYRZUq+aspz/qSB7JZ0iKcCi3oLShCwBf32xgm+AdrPlY8E2mv869mgf0Zdf/t87AUN7LusNf5IW9MC+9I0U4smBpgHcQNgnrLSJ6M2SAUjxqBo+J06VJxU+yQseywMxAyadRf1zZP7QnNDrxAfUz+VfvAIp126nz0WmIyBtlHHcKKyuMT29MEAKd+nmlYyeLvWdM75s43pw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5ggWot059eRVohE/cNcVAQIToD+p+Gj+HvAbFM8efco=; b=2mQ79EHCcAEWCC/MafsfEiV89HyMTC94RzNHhorXBf106U99unQKlMmAOerCCInHL1h3RRHt3Eh4eoeefOkNJZAsg6Ms3if7vhJh8T5nEBD9Lxq7zRCgXVkMj7+dFTVcQDFqiSUEZS8mDF77m7a0SoU8l2E8pztF5vDcQ7riYKU= Authentication-Results: alien8.de; dkim=none (message not signed) header.d=none; alien8.de; dmarc=none action=none header.from=amd.com; Received: from BN8PR12MB2946.namprd12.prod.outlook.com (2603:10b6:408:9d::13) by BN7PR12MB2593.namprd12.prod.outlook.com (2603:10b6:408:25::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16; Tue, 8 Sep 2020 21:48:34 +0000 Received: from BN8PR12MB2946.namprd12.prod.outlook.com ([fe80::a92d:18c0:971b:48e6]) by BN8PR12MB2946.namprd12.prod.outlook.com ([fe80::a92d:18c0:971b:48e6%6]) with mapi id 15.20.3348.019; Tue, 8 Sep 2020 21:48:34 +0000 From: Kim Phillips To: Borislav Petkov , Borislav Petkov , Peter Zijlstra , Ingo Molnar , Ingo Molnar , Thomas Gleixner , kim.phillips@amd.com Cc: Stephane Eranian , Alexander Shishkin , Arnaldo Carvalho de Melo , "H. Peter Anvin" , Jiri Olsa , Mark Rutland , Michael Petlan , Namhyung Kim , LKML , x86 , Stephane Eranian , stable@vger.kernel.org Subject: [PATCH v2 3/7] arch/x86/amd/ibs: Fix re-arming IBS Fetch Date: Tue, 8 Sep 2020 16:47:36 -0500 Message-Id: <20200908214740.18097-4-kim.phillips@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200908214740.18097-1-kim.phillips@amd.com> References: <20200908214740.18097-1-kim.phillips@amd.com> X-ClientProxiedBy: DM6PR07CA0067.namprd07.prod.outlook.com (2603:10b6:5:74::44) To BN8PR12MB2946.namprd12.prod.outlook.com (2603:10b6:408:9d::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fritz.amd.com (165.204.77.11) by DM6PR07CA0067.namprd07.prod.outlook.com (2603:10b6:5:74::44) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3348.16 via Frontend Transport; Tue, 8 Sep 2020 21:48:31 +0000 X-Mailer: git-send-email 2.27.0 X-Originating-IP: [165.204.77.11] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 5ddc8a2a-bc16-4e59-ebef-08d85440ef35 X-MS-TrafficTypeDiagnostic: BN7PR12MB2593: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fOJHb3DUFPhZJPOP7oV79gpKna7XPKQsZ2WWcanvoaL+yl6lgfzakhLOUJoPxhqOZvgCR6NLysF2CEwkqV/92iAZKFwllIzg2uKFO2f7nGwdJl4rsntK0M6HwPXJr6x1nH+F+v45elrzY9lJ5IiOWrCBJPn9Qswh6/KfwB7Dxj9vfreStaigAY9OOr3PEWuAttN2UJk038it9M5wy5VKmfbMlqcfgt5CIt5T4lg/k5EJnbGVLHccoNpe0AGQwLNFNQ5sIpqlAihSbu6eEHKyg64/KcsEISAncQh6ewhqSXAuTLG0RsOJh2mfH1bXX0O/JfE9/mYyGT4YBIdzrob1abX72WnE2XqmbS14PSBM26FWGVW004GbBojjKTd0y9xL0OhirebcioIjPK24zPtGWQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN8PR12MB2946.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(136003)(39860400002)(366004)(396003)(376002)(346002)(7696005)(52116002)(83380400001)(6486002)(44832011)(956004)(2616005)(86362001)(7416002)(478600001)(66476007)(66556008)(66946007)(186003)(26005)(8936002)(2906002)(4326008)(16526019)(8676002)(966005)(316002)(36756003)(5660300002)(54906003)(110136005)(1076003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: VUwDx0+kv0VTum36LMRktHL5c/bRJU7HgQLqVPsaHLLG63hABB+83adwptTlz0AAPCoCeqG42LL5TFu4SsmsEnxsC0GU6L0KqC7HifVFKqGXO7D/EuZUjuSPHay2C3EhPAUwLhTvqila4DGX406h6wKj/rg/vBA4Vr55bfvtS3sqWwv3wJLfGFI5k7MhWIBj8Qwzoc6fPPP+D479HsFmyKCEzGapZygpgD/ZSgAtuPMCSdellsmZA/+3hxpRX2g7btdK7JMsyMZXKzmlrvpOKQNusQiqgmknZDBJWNQqXg2Hl8EMpKywoqjZ7FE0ydR3nkBZ0kzwbVdakLEcQJ49/zYUzwU1dU3woYqky16HFxtGzDDdQOQdhfP1kWwMJ0skzxZEB3Zas36VYTHuGR3olioAuHCPcBEQmXMS8Vpewg77PgnGn6nE/CFQebfkK/3NGawvs58UBFoQ4EoML6KR9hv7n0Mlk8tBEnV6hmZAtDZnMCZtNi4Nu87VCFImb/AEMWD1nFaJBjAkNYc1ssCPxYQpN+bQ0OggLLU8hCaV1LnNPryHVtsIb+G87XLBf9VYI41h6kKqfuk+oQB1giOa7198qq0eumyJrbNc3nsCNF0esGggdCPK6QV2BGPisX0mqBoXaThUcLFszM0v5ScYaw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ddc8a2a-bc16-4e59-ebef-08d85440ef35 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB2946.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2020 21:48:34.3072 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: skdl5Emanwriwljim5HtfiXewesnYw8yt1o6DsqdvU1056Ei1mEYPzDbK4JiDeBc69P0LL5Yap51bVLFL6BKVA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2593 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Stephane Eranian found a bug in that IBS' current Fetch counter was not being reset when the driver would write the new value to clear it along with the enable bit set, and found that adding an MSR write that would first disable IBS Fetch would make IBS Fetch reset its current count. Indeed, the PPR for AMD Family 17h Model 31h B0 55803 Rev 0.54 - Sep 12, 2019 states "The periodic fetch counter is set to IbsFetchCnt [...] when IbsFetchEn is changed from 0 to 1." Explicitly set IbsFetchEn to 0 and then to 1 when re-enabling IBS Fetch, so the driver properly resets the internal counter to 0 and IBS Fetch starts counting again. A family 15h machine tested does not have this problem, and the extra wrmsr is also not needed on Family 19h, so only do the extra wrmsr on families 16h through 18h. Reported-by: Stephane Eranian Signed-off-by: Kim Phillips Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: "H. Peter Anvin" Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: LKML Cc: x86 Cc: stable@vger.kernel.org --- v2: constrained the extra wrmsr to Families 16h through 18h, inclusive. arch/x86/events/amd/ibs.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 26c36357c4c9..3eb9a55e998c 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -363,7 +363,14 @@ perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event, static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs, struct hw_perf_event *hwc, u64 config) { - wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask); + u64 _config = (hwc->config | config) & ~perf_ibs->enable_mask; + + /* On Fam17h, the periodic fetch counter is set when IbsFetchEn is changed from 0 to 1 */ + if (perf_ibs == &perf_ibs_fetch && boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18) + wrmsrl(hwc->config_base, _config); + + _config |= perf_ibs->enable_mask; + wrmsrl(hwc->config_base, _config); } /* From patchwork Tue Sep 8 21:47:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 264121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 943CEC433E2 for ; Tue, 8 Sep 2020 21:49:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A4CF2087C for ; Tue, 8 Sep 2020 21:49:00 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Peter Anvin" , Jiri Olsa , Mark Rutland , Michael Petlan , Namhyung Kim , LKML , x86 , stable@vger.kernel.org Subject: [PATCH v2 4/7] perf/x86/amd/ibs: Don't include randomized bits in get_ibs_op_count() Date: Tue, 8 Sep 2020 16:47:37 -0500 Message-Id: <20200908214740.18097-5-kim.phillips@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200908214740.18097-1-kim.phillips@amd.com> References: <20200908214740.18097-1-kim.phillips@amd.com> X-ClientProxiedBy: DM5PR13CA0069.namprd13.prod.outlook.com (2603:10b6:3:117::31) To BN8PR12MB2946.namprd12.prod.outlook.com (2603:10b6:408:9d::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fritz.amd.com (165.204.77.11) by DM5PR13CA0069.namprd13.prod.outlook.com (2603:10b6:3:117::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.7 via Frontend Transport; Tue, 8 Sep 2020 21:48:46 +0000 X-Mailer: git-send-email 2.27.0 X-Originating-IP: [165.204.77.11] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: ad25a55c-9c7a-4f03-537b-08d85440f78c X-MS-TrafficTypeDiagnostic: BN8PR12MB2881: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9Yt2uaTlUQemjqBUCXk6v5ga9stFooWecBULVRwZ3u7YCsDZpZVy59Gcf/iIXr55pElJDAmtLcZ6mWXVtX4YWRad2tj6W1aZtnD95kN7pPDtjf5nCdw4j7El8/w68qIuMfnG1/deTrJGs+4y6ADXwzjsJzs+YevQK2jb4Fo8wr6hK0g1rIGLvMsNx2qZofosC2hN+DLrVfhCxgJG+3OtiFGwGO5ihKUfleFbAvKTsUSYdAoZll8dY29vRreQz8fmiFEwm1DOUCmB0plH70piJ20QfFiCqK/jzbFxuyzDA7iaGcJ2zfhgTOPu4jESry7bG/fa47qlFlAXxVGIhVtMd9PZatd50HHGLUsOmKTpCfkChP/jP7JFQt21iB037cb1INbROJDe0bDrz1epINXFEA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN8PR12MB2946.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(39860400002)(346002)(396003)(136003)(376002)(366004)(2616005)(54906003)(110136005)(4326008)(6666004)(36756003)(8676002)(1076003)(966005)(66946007)(66476007)(44832011)(66556008)(6486002)(86362001)(7696005)(52116002)(83380400001)(956004)(316002)(186003)(7416002)(478600001)(26005)(8936002)(2906002)(16526019)(5660300002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: n77t1MM0o18mjARulMECDc02dY+nvPXqBVPEUZ6+iUKxTsCZHowISn/lx2Vvd0tQgLWFWCKwZfiQc7Uxoas2OTI6dRDuoF8PuMXEYho6RKF9A0Fy9CbKbZc/lT5gTuJkFioo2QrcjNqfc8rCGCuabtm7LXPYmrV5fWZhWJ1ydjHmOJ2U+vggKLNRzbYS32RX06Sl0//q7tweevj9b//fdzf0wTmQFOPt9OeYKwm/3beZYDzsdLcVZGwZuTtgdQrZzhzpBsThzL/tgxKX7H9cz9/8gSH9Wo/jvN44qBQb453cYmWpXPoPCtmuRMLU6CpfJhCvyILk5W8lV7iIy6MzAocTKKUcs1g7jB7+yQu/NryMmMbDAX8ycqG4KlCeHlmpQymS4Us3/jYxlAKBum8R//3pQDDx3ROFtBdmjVd49SUHgRjIHYOgptK8Ym9Kb+2V9nD0PlydNwdA19IevC034Uo7VXc788V+UqbNsqGnbl5TqnBcM98W7GLO8dIjL+0OvmuAlKiG4zUQ9BftVuwqz2TKqc9SYtMsKmj848abwd9TPQj8NVBzT4a1cP4tyXYdjOeZEd9cxGwdrPiTobIJ7f4HUZ0LALvbLNOB1cfTS+VxRzP4JJOx3u9VfO7Pp04eaE3dO6tog5BjimHNB9YmkQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ad25a55c-9c7a-4f03-537b-08d85440f78c X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB2946.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2020 21:48:48.2752 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jxLL7NNHF7jBWrom3NBGOm4Vr3AEpj2ndthPCFtbMKKURQaFXJ5+Fz1um+ogKURFgT6ukPVzmwR/sWkjy4VbaQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2881 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org get_ibs_op_count() adds hardware's current count (IbsOpCurCnt) bits to its count regardless of hardware's valid status. According to the PPR for AMD Family 17h Model 31h B0 55803 Rev 0.54, if the counter rolls over, valid status is set, and the lower 7 bits of IbsOpCurCnt are randomized by hardware. Don't include those bits in the driver's event count. Signed-off-by: Kim Phillips Fixes: 8b1e13638d46 ("perf/x86-ibs: Fix usage of IBS op current count") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: "H. Peter Anvin" Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: LKML Cc: x86 Cc: stable@vger.kernel.org --- v2: no changes. arch/x86/events/amd/ibs.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3eb9a55e998c..68776cc291a6 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -334,11 +334,15 @@ static u64 get_ibs_op_count(u64 config) { u64 count = 0; + /* + * If the internal 27-bit counter rolled over, the count is MaxCnt + * and the lower 7 bits of CurCnt are randomized. + * Otherwise CurCnt has the full 27-bit current counter value. + */ if (config & IBS_OP_VAL) - count += (config & IBS_OP_MAX_CNT) << 4; /* cnt rolled over */ - - if (ibs_caps & IBS_CAPS_RDWROPCNT) - count += (config & IBS_OP_CUR_CNT) >> 32; + count = (config & IBS_OP_MAX_CNT) << 4; + else if (ibs_caps & IBS_CAPS_RDWROPCNT) + count = (config & IBS_OP_CUR_CNT) >> 32; return count; }