From patchwork Sat Oct 28 13:37:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 117392 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp609181qgn; Sat, 28 Oct 2017 06:39:39 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QGMSOBh810yvaPdVPYdmn/EwFTGmXN4XHji0b/qGqZpv9EpG0QBK6UMGiKNIKvjkLf4/X4 X-Received: by 10.99.171.6 with SMTP id p6mr3134253pgf.30.1509197979399; Sat, 28 Oct 2017 06:39:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509197979; cv=none; d=google.com; s=arc-20160816; b=G6bZhfL5dxtkgGMIJ9wc5qJ7NKfeYtw3THfndk/ipyCXVCLRZHwDSFmScmwo8JJseq Oj/XjWjJ2TdhCPevJSjagLG6Hnh9NSG2pmZGYTu0h7GL+YY/nUxsXvdD53UPyAILawvv 2bbwE3uF9PZRhTk6QIEmJ4wBCayILhGC1coE1aCVIgc8LPhx8bL2Jw3102hgI8kzpSUs P/c4cLRYKffnvf3CDoJIpW5y5+PAy1WC793W/vfx90oKNSEtfHCzcY5wITE2g6HIchAs T3UMru55sPEaK/ISklVOZBkJQxj0FtRG9h43CUuCz7YhIXYNF7zqFJ1jaTSJ/fPMay51 4FSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=CRq0XfPDD4eE0tSadeVOHZ37bSIR5DjByvBdLkpgX/E=; b=C3/VzwE5H9VAOSx1zv8eJIWP/JNR1x+WvoqiVlpQmvWBacQMu4tTVajIquO/pPiSYd s94OcdvlF0LvZicWDxmSEMKi3xGtKHd8zc1c5/JsjSHQaAMnIZL1rB3R89jOyRHo3tkA qzYN5L1GxhlU7iZblHALPnSbhVGHE+BREAE71ODJ6/SgmD2kBUiVhhTm7CabLeeNPOYM xadxqYiMuwP+Xdw6w8QLbWbv7wbhQzwPWgQQifX4suy3VXJWEafe3fmwLfWnoFBEBE8b Ub21s/ImdIXWR9qzWSQI+VKEwhhtvRYPsuR3uM96s6b+tipfesLj3/M484Hwl1x0fyCC 9Jhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jyFuwb2n; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l185si372828pfc.43.2017.10.28.06.39.38; Sat, 28 Oct 2017 06:39:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jyFuwb2n; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751298AbdJ1Nji (ORCPT + 6 others); Sat, 28 Oct 2017 09:39:38 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:51232 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751199AbdJ1Njh (ORCPT ); Sat, 28 Oct 2017 09:39:37 -0400 Received: by mail-lf0-f67.google.com with SMTP id r129so10112155lff.8 for ; Sat, 28 Oct 2017 06:39:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=v6m4spjbgc8Ze6uOtfqGm/TfDLEOEvpD+AKxpf9NatY=; b=jyFuwb2nGdiObQ4OYTIBAi76HnwiJIR9SnkqjckrV5yzDqqOOBeQ01go99JeIQjNv4 8XMN0yN6JJ2/yhLHC9QKeYthc3zHB9WyYKZdeOLnCEsy4WMixdXH7Q1n/5/gddCT9WFT TW5DWreh+mqYySzx2AylWqoy5K5k3vZkIhHaU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=v6m4spjbgc8Ze6uOtfqGm/TfDLEOEvpD+AKxpf9NatY=; b=WqjrHTwZ3bKnU+p7iC7idKHV+/y1/Ct+uCkcnHTrVmcUr3xe5GrqnfBO1/Z7wJRJAd aTmjglgWIU34j6q4Gp6N3rFf7/FPGoO9M7ZScNSkIT1yKWzPqiWZdFZWhLqIOdEISj7d zzVr9n82TVFRGOBMHe/6gx0bJ7tkKWWUaAh+DRP3ld+1aJCG+Jclc8BytBLSXZLBsKsH NNyK3dHvB0dk8AmPQZ1PNvyhxvR50HGexarxYeNgZdJ5DYGmoQaeXypBxbOcXaLQU58y wiNlh8dV8lPupLc+QoLFuvAeyPJEJ5QBPIKYX3EjSUVavrOsIiHHZHojP6vvELNFAeeA l06g== X-Gm-Message-State: AMCzsaXkrc0WX37XIYaXSv75QkxJh8Avfxr0hiztBwncSwFw5xWBsgO7 TZFVfI4HTsJ+se7vzdFGYgmSeFAL3o4= X-Received: by 10.25.178.206 with SMTP id t75mr1260460lfk.228.1509197976009; Sat, 28 Oct 2017 06:39:36 -0700 (PDT) Received: from localhost.localdomain (c-567171d5.014-348-6c756e10.cust.bredbandsbolaget.se. [213.113.113.86]) by smtp.gmail.com with ESMTPSA id r23sm2447913lja.32.2017.10.28.06.39.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 28 Oct 2017 06:39:34 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org, Hans Ulli Kroll , Florian Fainelli Cc: Janos Laube , Paulius Zaleckas , linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 1/4] pinctrl: gemini: Add missing functions Date: Sat, 28 Oct 2017 15:37:16 +0200 Message-Id: <20171028133719.27528-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.6 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Some two functions were missing from the Gemini pin control driver. Noticed when trying to use ethernet. Fix it up by adding them. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-gemini.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Hans Ulli Kroll diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index 39e6221e7100..7ffd768c0e02 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -2074,6 +2074,16 @@ static const struct gemini_pmx_func gemini_pmx_functions[] = { .num_groups = ARRAY_SIZE(satagrps), }, { + .name = "usb", + .groups = usbgrps, + .num_groups = ARRAY_SIZE(usbgrps), + }, + { + .name = "gmii", + .groups = gmiigrps, + .num_groups = ARRAY_SIZE(gmiigrps), + }, + { .name = "pci", .groups = pcigrps, .num_groups = ARRAY_SIZE(pcigrps), From patchwork Sat Oct 28 13:37:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 117393 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp610550qgn; Sat, 28 Oct 2017 06:41:29 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RcDk8LwWCRpqY2aTCCk6nE1i8JJUuWPqkxyjRFAQrEFqTDQ4DMNDSRpTBZQ/uca6NQwJe1 X-Received: by 10.98.36.23 with SMTP id r23mr3452756pfj.256.1509198089410; Sat, 28 Oct 2017 06:41:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509198089; cv=none; d=google.com; s=arc-20160816; b=g+6Da9wEsFr+YFNTMIuAi+maUvz0QpH8tH9CD07b5mwC/7a5LcVIJyQqgDPMJPS8D3 WqTsmeCq5Bt6gp5Y1N8IUgOdgRnV2oEoovuQkIsODSLUKS9uxMJNPONc7xXA/EcuURSK nlZ5aYgGwoUEeMfTjvJht2lcfF+OWh4/X8tFlWH/PHOvjlyHzld8AEc9+5TEGbOysNhN Vk+8nkBmwc53fpC4vx2IgSQNQnbxD4aTI/mvfg6pdL2r6o0m4/WGDizJokBk8AWz90yb v0VTVAkLeeSH4ObHM77jn59VeNEe+hW0RlRcvDDmS1+/0uXD4sBPkFZFM7+j11WBZI1r 6Qnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=RARbn7H1rJkCMbxt2pSxYwT/FwuMMwbAjP/eo9iC1h8=; b=ErE15B3BXw9AJQIDeiXF+FHvbj22w6wUsqQRE3G1ri2g9VAp2te6q+I1bYwlWzbNs4 EzBDcapZDU+20zNSQ/x+IqQdHg/W/zgByNWLk7PPMrhdG3BpYlY1Tj4FmwRJK0UT14XP GRVxHnlNB8naSfhri5CfiTnXSDKsKth44U/2+LQRCyeiBfk/mKBE+oHYlgWCrJx2l9d2 dpLA9IUqJh+YRi1Xbmt6BYDb9DVdtEbCDtamRH+4LFE6noMfUNZkHvHKIVrDFBVi1vTj HNfqyFIZH25znTAlcXGmtB9w0EVkGdEtQK97/XItbMUKIF3XgqFetoOOMiXAeE/CdL6m 7hig== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gYJge6W5; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.113.86]) by smtp.gmail.com with ESMTPSA id r23sm2447913lja.32.2017.10.28.06.41.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 28 Oct 2017 06:41:25 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org, Hans Ulli Kroll , Florian Fainelli Cc: Janos Laube , Paulius Zaleckas , linux-arm-kernel@lists.infradead.org, Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 2/4] pinctrl: Add skew-delay pin config and bindings Date: Sat, 28 Oct 2017 15:37:17 +0200 Message-Id: <20171028133719.27528-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171028133719.27528-1-linus.walleij@linaro.org> References: <20171028133719.27528-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Some pin controllers (such as the Gemini) can control the expected clock skew and output delay on certain pins with a sub-nanosecond granularity. This is typically done by shunting in a number of double inverters in front of or behind the pin. Make it possible to configure this with a generic binding. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 4 ++++ drivers/pinctrl/pinconf-generic.c | 2 ++ include/linux/pinctrl/pinconf-generic.h | 5 +++++ 3 files changed, 11 insertions(+) -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Hans Ulli Kroll Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index 4483cc31e531..ad9bbbba36e9 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -271,6 +271,10 @@ output-high - set the pin to output mode with high level sleep-hardware-state - indicate this is sleep related state which will be programmed into the registers for the sleep state. slew-rate - set the slew rate +skew-delay - this affects the expected clock skew on input pins + and the delay before latching a value to an output + pin. Typically indicates how many double-inverters are + used to delay the signal. For example: diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 8eaa25c3384f..b4f7f8a458ea 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -49,6 +49,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), + PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true), }; static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, @@ -181,6 +182,7 @@ static const struct pinconf_generic_params dt_params[] = { { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, + { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, }; /** diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 5d8bc7f21c2a..ec6dadcc1fde 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -90,6 +90,10 @@ * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to * this parameter (on a custom format) tells the driver which alternative * slew rate to use. + * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs) + * or latch delay (on outputs) this parameter (in a custom format) + * specifies the clock skew or latch delay. It typically controls how + * many double inverters are put in front of the line. * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if * you need to pass in custom configurations to the pin controller, use * PIN_CONFIG_END+1 as the base offset. @@ -117,6 +121,7 @@ enum pin_config_param { PIN_CONFIG_POWER_SOURCE, PIN_CONFIG_SLEEP_HARDWARE_STATE, PIN_CONFIG_SLEW_RATE, + PIN_CONFIG_SKEW_DELAY, PIN_CONFIG_END = 0x7F, PIN_CONFIG_MAX = 0xFF, }; From patchwork Sat Oct 28 13:37:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 117394 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp610781qgn; Sat, 28 Oct 2017 06:41:47 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SXMZUvgsEn1fhlWlb8YiRZggqMdcdrxvzfPgIqXFUJJ6j0+1B7u8KT1XkXNIN7Y6aWD3BW X-Received: by 10.98.67.154 with SMTP id l26mr3502182pfi.212.1509198107754; Sat, 28 Oct 2017 06:41:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509198107; cv=none; d=google.com; s=arc-20160816; b=rehg9PS3l9FTuw1JLi87UO3/djVJ0m7naavH+/GdIgEsMrBo+DzwcrMeoIFwu+TO1s yBW42teS2h78ox7EsNmMb5VRgxf2xtJ6C8CXAyBEy4deGJAsfHDpWcjS8DGqoZnhAOLy 0EQ+gG4qfAlj+pAQJ8gNSeq0Wrvhhty8YRNCfOqtBgT9NG+PIsMwzRA8NwuqfLYO3LvE ALDLQ7Jpl43mM6545VN9Gr+o2f57YAWZmXqhnvs7ITUH1lNj+a8xf+87Fmj3IR3bZWf8 tvdd7IpNPwxNsvqK/W56KFhvnN4FcO7I8jLTDQSmY/yPKQBawzXpcwAodJEf3n+WT9TR zc+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lhpoxTfvQPCAVkPpaz8FL4DLsgzv8WXiJp+cxIKNJMY=; b=V4a2b5q6cSbn4g3RO/E9Dbyn4rkws46XrzglkP1Txli+yoFH/8B+7IlSTVwMPf8MsI 3cAcRZkhAvTK5wr9HpNwCl2+XDU8p+OLMQjH7Y3Sm4PVXL5S1VpxrY86vQHQyB/EnMQV OZ12jHnxxz7HHpkRdJ2s/cv1vhFVDJ1ZF30KXFRrLmuhKPDxZt+TNtBznYilShodrmnN io2tVMLVFFwzuJN2LgcRONgmkfLQOAfdEuIxZKSkTENRe6pYGOJE9tSfsZSudSrsJSWX 9RVZeyylfH0b+igQpdmxutA+QyLnG+AXw/pzNI8AhRB3OZTUttDNo6F3WXCIOREmKuU0 b+bA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aneD2eL5; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.113.86]) by smtp.gmail.com with ESMTPSA id r23sm2447913lja.32.2017.10.28.06.41.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 28 Oct 2017 06:41:43 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org, Hans Ulli Kroll , Florian Fainelli Cc: Janos Laube , Paulius Zaleckas , linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 3/4] pinctrl: gemini: Use generic DT parser Date: Sat, 28 Oct 2017 15:37:18 +0200 Message-Id: <20171028133719.27528-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171028133719.27528-1-linus.walleij@linaro.org> References: <20171028133719.27528-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We can just use the generic Device Tree parser code in this driver and save some code. Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/pinctrl-gemini.c | 66 +++------------------------------------- 2 files changed, 5 insertions(+), 62 deletions(-) -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Hans Ulli Kroll diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1778cf4f81c7..98b2d5dcbda7 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -151,6 +151,7 @@ config PINCTRL_GEMINI depends on ARCH_GEMINI default ARCH_GEMINI select PINMUX + select GENERIC_PINCONF select MFD_SYSCON config PINCTRL_MCP23S08 diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index 7ffd768c0e02..18fb5ff8a442 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -1918,73 +1920,13 @@ static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, " " DRIVER_NAME); } -static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, - unsigned int *reserved_maps, - unsigned int *num_maps) -{ - int ret; - const char *function = NULL; - const char *group; - struct property *prop; - - ret = of_property_read_string(np, "function", &function); - if (ret < 0) - return ret; - - ret = of_property_count_strings(np, "groups"); - if (ret < 0) - return ret; - - ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, - num_maps, ret); - if (ret < 0) - return ret; - - of_property_for_each_string(np, "groups", prop, group) { - ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, - num_maps, group, function); - if (ret < 0) - return ret; - pr_debug("ADDED FUNCTION %s <-> GROUP %s\n", - function, group); - } - - return 0; -} - -static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned int *num_maps) -{ - unsigned int reserved_maps = 0; - struct device_node *np; - int ret; - - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map, - &reserved_maps, num_maps); - if (ret < 0) { - pinctrl_utils_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -}; - static const struct pinctrl_ops gemini_pctrl_ops = { .get_groups_count = gemini_get_groups_count, .get_group_name = gemini_get_group_name, .get_group_pins = gemini_get_group_pins, .pin_dbg_show = gemini_pin_dbg_show, - .dt_node_to_map = gemini_pinctrl_dt_node_to_map, - .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, }; /** From patchwork Sat Oct 28 13:37:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 117395 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp610821qgn; Sat, 28 Oct 2017 06:41:51 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Rdbz2yO1ynJbu6si0ptxX3jZXF8Myv1NtHH6ooyx82uyBwDwjm0qiHJUo6SP7ktJM8oKhZ X-Received: by 10.99.51.11 with SMTP id z11mr3082917pgz.223.1509198111038; Sat, 28 Oct 2017 06:41:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509198111; cv=none; d=google.com; s=arc-20160816; b=ObBzd6k+jy7X4+8q37xZQzu3Qhqlv3NxeiJ2zfZUyc6HbC9IBuoHhLXmg4+13d4Y7L qtyCceljqYc1Ld1mZO8k6audV4l2H0pP07dB0pcrr1GUTRKbAhuGt25pKBCmZtGLIBmM D1zbm4iVEjT9I6uyYaV1jvcCz/UmFk/5ns7r01MShRCAD1SNHMTwiudMqeNyZSZknKUM cyh7sfxWlkNtkXHjtz9Qz3aOoenNkHH2HS+c0tJK8Qtk7F+hXfO3LQ7xbYD/gXT/buUy 9kVnp6AA2owhKm/GBTzE+9j+L2SJZDko5/EbiLiwkgTZ5CAxts8gt8FdEi0seWQvXkY9 ZbUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=2EClafLVJpQGnt5r9mvJIHNR5NM7ei7dHd+5IVVqjXc=; b=YYjzcCEDp6pVWbTZ0fv0qXt0o05TecPkfP+RP8GndOzUOH7LmF+DHzmk485uIalyjl EKG7h4XfGPPRWsbV/uexoe17wZq/WXCdS8I9Qm23sZbo96Pf+IIBk9xLcLN2tWA4uD/Y 4ul9Rr0/btVOCzhdJ35T6RujPO2QDT7q3vAL7vP+cYGVhODIWu38anHAGK2UzgcoobH8 tVsggbp4nWH2K6jYoMxKVMsQmP+ArnUCDImNPDU3ABJdfcj+l4odeIMUypFAO4E2EMPw xE82oK77EjeeqP+aPczWfdfBZVpfRi7uOwBqy7uXkT7CicUxW8MUopfxt8ISDM0aD0WB mJgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=g4oFoi3h; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.113.86]) by smtp.gmail.com with ESMTPSA id r23sm2447913lja.32.2017.10.28.06.41.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 28 Oct 2017 06:41:46 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org, Hans Ulli Kroll , Florian Fainelli Cc: Janos Laube , Paulius Zaleckas , linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 4/4] pinctrl: gemini: Implement clock skew/delay config Date: Sat, 28 Oct 2017 15:37:19 +0200 Message-Id: <20171028133719.27528-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171028133719.27528-1-linus.walleij@linaro.org> References: <20171028133719.27528-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Signed-off-by: Linus Walleij --- .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 10 +- drivers/pinctrl/pinctrl-gemini.c | 178 ++++++++++++++++++++- 2 files changed, 182 insertions(+), 6 deletions(-) -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Hans Ulli Kroll diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt index 61466c58faae..d857b67fab72 100644 --- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt @@ -9,8 +9,14 @@ The pin controller node must be a subnode of the system controller node. Required properties: - compatible: "cortina,gemini-pinctrl" -Subnodes of the pin controller contain pin control multiplexing set-up. -Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes. +Subnodes of the pin controller contain pin control multiplexing set-up +and pin configuration of individual pins. + +Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes +and generic pin config nodes. + +Supported configurations: +- skew-delay is supported on the Ethernet pins Example: diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index 18fb5ff8a442..bd6133f06759 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -24,6 +24,19 @@ #define DRIVER_NAME "pinctrl-gemini" /** + * struct gemini_pin_conf - information about configuring a pin + * @pin: the pin number + * @reg: config register + * @mask: the bits affecting the configuration of the pin + */ +struct gemini_pin_conf { + unsigned int pin; + u32 reg; + u32 mask; +}; + +/** + * struct gemini_pmx - state holder for the gemini pin controller * @dev: a pointer back to containing device * @virtbase: the offset to the controller in virtual memory * @map: regmap to access registers @@ -31,6 +44,8 @@ * @is_3516: whether the SoC/package is the 3516 variant * @flash_pin: whether the flash pin (extended pins for parallel * flash) is set + * @confs: pin config information + * @nconfs: number of pin config information items */ struct gemini_pmx { struct device *dev; @@ -39,6 +54,8 @@ struct gemini_pmx { bool is_3512; bool is_3516; bool flash_pin; + const struct gemini_pin_conf *confs; + unsigned int nconfs; }; /** @@ -59,6 +76,13 @@ struct gemini_pin_group { u32 value; }; +/* Some straight-forward control registers */ +#define GLOBAL_WORD_ID 0x00 +#define GLOBAL_STATUS 0x04 +#define GLOBAL_STATUS_FLPIN BIT(20) +#define GLOBAL_GMAC_CTRL_SKEW 0x1c +#define GLOBAL_GMAC0_DATA_SKEW 0x20 +#define GLOBAL_GMAC1_DATA_SKEW 0x24 /* * Global Miscellaneous Control Register * This register controls all Gemini pad/pin multiplexing @@ -71,9 +95,6 @@ struct gemini_pin_group { * DISABLED again. So you select a flash configuration once, and then * you are stuck with it. */ -#define GLOBAL_WORD_ID 0x00 -#define GLOBAL_STATUS 0x04 -#define GLOBAL_STATUS_FLPIN BIT(20) #define GLOBAL_MISC_CTRL 0x30 #define TVC_CLK_PAD_ENABLE BIT(20) #define PCI_CLK_PAD_ENABLE BIT(17) @@ -1925,7 +1946,7 @@ static const struct pinctrl_ops gemini_pctrl_ops = { .get_group_name = gemini_get_group_name, .get_group_pins = gemini_get_group_pins, .pin_dbg_show = gemini_pin_dbg_show, - .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = pinconf_generic_dt_free_map, }; @@ -2203,10 +2224,155 @@ static const struct pinmux_ops gemini_pmx_ops = { .set_mux = gemini_pmx_set_mux, }; +#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \ + .pin = _n, \ + .reg = _r, \ + .mask = GENMASK(_hb, _lb) \ +} + +static const struct gemini_pin_conf gemini_confs_3512[] = { + GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ + GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ + GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ + GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ + GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ + GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ + GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ + GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ + GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ + GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ + GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ + GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ + GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ + GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ + GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ + GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ + GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ + GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ + GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ + GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ + GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ + GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ + GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ + GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ +}; + +static const struct gemini_pin_conf gemini_confs_3516[] = { + GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ + GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ + GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ + GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ + GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ + GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ + GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ + GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ + GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ + GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ + GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ + GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ + GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ + GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ + GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ + GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ + GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ + GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ + GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ + GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ + GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ + GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ + GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ + GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ +}; + +static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, + unsigned int pin) +{ + const struct gemini_pin_conf *retconf; + int i; + + for (i = 0; i < pmx->nconfs; i++) { + retconf = &gemini_confs_3516[i]; + if (retconf->pin == pin) + return retconf; + } + return NULL; +} + +static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + const struct gemini_pin_conf *conf; + u32 val; + + switch (param) { + case PIN_CONFIG_SKEW_DELAY: + conf = gemini_get_pin_conf(pmx, pin); + if (!conf) + return -ENOTSUPP; + regmap_read(pmx->map, conf->reg, &val); + val &= conf->mask; + val >>= (ffs(conf->mask) - 1); + *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct gemini_pin_conf *conf; + enum pin_config_param param; + u32 arg; + int ret = 0; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_SKEW_DELAY: + if (arg > 0xf) + return -EINVAL; + conf = gemini_get_pin_conf(pmx, pin); + if (!conf) { + dev_err(pmx->dev, + "invalid pin for skew delay %d\n", pin); + return -ENOTSUPP; + } + arg <<= (ffs(conf->mask) - 1); + dev_dbg(pmx->dev, + "set pin %d to skew delay mask %08x, val %08x\n", + pin, conf->mask, arg); + regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); + break; + default: + dev_err(pmx->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + } + + return ret; +} + +static const struct pinconf_ops gemini_pinconf_ops = { + .pin_config_get = gemini_pinconf_get, + .pin_config_set = gemini_pinconf_set, + .is_generic = true, +}; + static struct pinctrl_desc gemini_pmx_desc = { .name = DRIVER_NAME, .pctlops = &gemini_pctrl_ops, .pmxops = &gemini_pmx_ops, + .confops = &gemini_pinconf_ops, .owner = THIS_MODULE, }; @@ -2249,11 +2415,15 @@ static int gemini_pmx_probe(struct platform_device *pdev) val &= 0xffff; if (val == 0x3512) { pmx->is_3512 = true; + pmx->confs = gemini_confs_3512; + pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); gemini_pmx_desc.pins = gemini_3512_pins; gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); dev_info(dev, "detected 3512 chip variant\n"); } else if (val == 0x3516) { pmx->is_3516 = true; + pmx->confs = gemini_confs_3516; + pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); gemini_pmx_desc.pins = gemini_3516_pins; gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); dev_info(dev, "detected 3516 chip variant\n");