From patchwork Sun Oct 29 21:20:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117418 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853628qgn; Sun, 29 Oct 2017 14:24:25 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SwnQN+TnJJcuKzOs/bObHBOOL431fWE1nJVMfkbNlPhdMtWGk7N2tzXwHRTaolPKgLqzWl X-Received: by 10.84.245.15 with SMTP id i15mr5689624pll.437.1509312265829; Sun, 29 Oct 2017 14:24:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312265; cv=none; d=google.com; s=arc-20160816; b=nR7ar7uCDo0JzASnlLNQjE7KvAUK7YVz88LyWaOIdw2y8MhueQtXyy0eYosOO/ouXV J/6dTfhAGGpHcpcPe9FFiAxM/XEij8JmswJJ+DINgJvzMJ+BWYrGdD0rYUuz/39BQhL3 jcvi+hpQGgxAs/hmpRksNjpaSQCRaVzr9WnJhZZSKh05L36dg7P5KKZukMF3R9a1sCv+ SUmRJTUYWlMIDQYEdLMqdY0ZgGG5D0y/0lrB6TzBMlIzX3R2D6yJdQWRx0m/dAazqo0g AePWsqeofUOy5v/1JPPh3XN0XTR1kD7NgUABn6brgd5tQL4E5UYV6qSlF3M/FcLHvv5Z lObw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=iN2W1MQ8GOWR66r3H5whXaHXqpoa/xr32b5KjJefvSI=; b=Oel+zNidZA9L5W9gqcE9KBlWA0EosnUX2TcLqFvDh/TuUJczrmE05ipWB2vHg/Zks0 AnVsBB8Sijlo5kc4lRgyP8VwjbEg83rRMnGJn3N/AerwVLUBA1wFD/mdb/O2/bYRK0lT nzRG7OgRqtrh4RrkgyaaxWwSe6P1r7A3OXgQvrUX4dLCHtN+RTLUBVfCOFxhYYrMLQ9K Ff1BXbGSPMgI6FP5NUPzrIsYJLAQt5aTX6VGO0QWG8T8sl/b2wRYpUwcFLR3pndxlFqb ErzIPzTU3cWD+HXcRhT3tl9fsttFa+9bvP0dtmAbROQ9XccRu5EF74321CNDyOJKU2J8 v9aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=amxZ5hW3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k76si9366466pfb.433.2017.10.29.14.24.25; Sun, 29 Oct 2017 14:24:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=amxZ5hW3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932151AbdJ2VYY (ORCPT + 27 others); Sun, 29 Oct 2017 17:24:24 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:46505 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751319AbdJ2VYW (ORCPT ); Sun, 29 Oct 2017 17:24:22 -0400 Received: by mail-wm0-f65.google.com with SMTP id m72so12185669wmc.1 for ; Sun, 29 Oct 2017 14:24:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iN2W1MQ8GOWR66r3H5whXaHXqpoa/xr32b5KjJefvSI=; b=amxZ5hW3TtJAjQPHVJaL4CWJRlj5FGCoXsPEJPEnUZ3luuOqFnOP27+w/y6lHtHxD2 pOrKOlenSbxRQMTIJgdoW7ZZ4y7iWw3Mkomj6GqiE7tlg+EJ0pZNRfzzN8UPKi+4sl4d B2/iudN4+2ykYdG1BbcUggTvsIze5pkUAjOPc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iN2W1MQ8GOWR66r3H5whXaHXqpoa/xr32b5KjJefvSI=; b=SPVGsSjS26FccvtEOA3H4tEDSETQxPBwmKfjtpQ127JS53jySlJWomK7VzW9SPg9pX KoX0otHWZ8mEAfqlwjhj/G/jiEHzEVCrWyFAUrfLHcrh0VehImAOLQ1C5dpbUD8NAwtp hDsA2fcmXyGlXcMYOO1As4Q9n2VFiPNNs7T9N+zxkb0hQLt+jTG2rwBJHM4ojWmd95YV 2kpuFsCvReIoCfCMlDU7qLfrb9vhKJIoiMrpBLswqShl3Rz68CSSWCBnzdjhfu4qiDLQ GFUv5XXLw9f/VJ1sTGq4WC3h5VenXSp4n7xjoYalivWOHaA2mNXt7/tJFLOVOYulL9O9 8KLw== X-Gm-Message-State: AMCzsaXfoONf9+F+LKj+i3OEMN19S3aWMkSg5lVjefSxFUrDMLZMoIAx yq5mGqaXb+xYG+K0OLrCnf1Sgg== X-Received: by 10.28.67.68 with SMTP id q65mr2042807wma.96.1509312260353; Sun, 29 Oct 2017 14:24:20 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:19 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Geert Uytterhoeven , Rob Herring , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 01/17] dt-bindings: timer: renesas, cmt: Fix SoC-specific compatible values Date: Sun, 29 Oct 2017 22:20:18 +0100 Message-Id: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Geert Uytterhoeven While the new family-specific compatible values introduced by commit 6f54cc1adcc8957f ("devicetree: bindings: R-Car Gen2 CMT0 and CMT1 bindings") use the recommended order ",-", the new SoC-specific compatible values still use the old and deprecated order ",-". Switch the SoC-specific compatible values to the recommended order while there are no upstream users of these compatible values yet. Fixes: 7f03a0ecfdc786c1 ("devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings") Fixes: 63d9e8ca0dd4bfa4 ("devicetree: bindings: Deprecate property, update example") Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,cmt.txt | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 6ca6b9e..d740989 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -20,16 +20,16 @@ Required Properties: (CMT1 on sh73a0 and r8a7740) This is a fallback for the above renesas,cmt-48-* entries. - - "renesas,cmt0-r8a73a4" for the 32-bit CMT0 device included in r8a73a4. - - "renesas,cmt1-r8a73a4" for the 48-bit CMT1 device included in r8a73a4. - - "renesas,cmt0-r8a7790" for the 32-bit CMT0 device included in r8a7790. - - "renesas,cmt1-r8a7790" for the 48-bit CMT1 device included in r8a7790. - - "renesas,cmt0-r8a7791" for the 32-bit CMT0 device included in r8a7791. - - "renesas,cmt1-r8a7791" for the 48-bit CMT1 device included in r8a7791. - - "renesas,cmt0-r8a7793" for the 32-bit CMT0 device included in r8a7793. - - "renesas,cmt1-r8a7793" for the 48-bit CMT1 device included in r8a7793. - - "renesas,cmt0-r8a7794" for the 32-bit CMT0 device included in r8a7794. - - "renesas,cmt1-r8a7794" for the 48-bit CMT1 device included in r8a7794. + - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4. + - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4. + - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. + - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. + - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. + - "renesas,r8a7791-cmt1" for the 48-bit CMT1 device included in r8a7791. + - "renesas,r8a7793-cmt0" for the 32-bit CMT0 device included in r8a7793. + - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793. + - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. + - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2. - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2. @@ -46,7 +46,7 @@ Required Properties: Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes cmt0: timer@ffca0000 { - compatible = "renesas,cmt0-r8a7790", "renesas,rcar-gen2-cmt0"; + compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, <0 142 IRQ_TYPE_LEVEL_HIGH>; @@ -55,7 +55,7 @@ Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes }; cmt1: timer@e6130000 { - compatible = "renesas,cmt1-r8a7790", "renesas,rcar-gen2-cmt1"; + compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, <0 121 IRQ_TYPE_LEVEL_HIGH>, From patchwork Sun Oct 29 21:20:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117434 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1855538qgn; Sun, 29 Oct 2017 14:27:52 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SY36c3PMbJjnavNHA7YJwkLxMjHXBy7/8trFiz0yKGWwYCFaWk4hqu8TQJHAmPBcWvono0 X-Received: by 10.98.163.196 with SMTP id q65mr6636529pfl.7.1509312472609; Sun, 29 Oct 2017 14:27:52 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id k76si8583155pgc.537.2017.10.29.14.27.52; Sun, 29 Oct 2017 14:27:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AQrM7sBk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751273AbdJ2V1u (ORCPT + 27 others); Sun, 29 Oct 2017 17:27:50 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:51117 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751875AbdJ2VYX (ORCPT ); Sun, 29 Oct 2017 17:24:23 -0400 Received: by mail-wr0-f196.google.com with SMTP id p96so10679657wrb.7 for ; Sun, 29 Oct 2017 14:24:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=byssf5KV/rW+pY6zRYLULSOrhaD+/7yyQbZWHqg2eU4=; b=AQrM7sBkPi9F+X7Y1B6opoD0pfx9irELhm3fWIx+DiqsDV5W40w6HEmSAMx1gCTHy1 Yc8J+m9pj8hfRLByXDs511i1XiAURmz3gXYZHKwqri74sOgRZ+tmyWJGY4fBgO0lDdZe 8ili9gaSx4h0vQ/8qF0hDwo6j8al1QfBqhGQU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=byssf5KV/rW+pY6zRYLULSOrhaD+/7yyQbZWHqg2eU4=; b=BRT1PZA8c/YC1j6GRkExjYnxSeVhIHyGy8N2QqNGD4Rb9WnQXf+9SrA+XRsd/U5KRb N6fIPOGte4u3W6hvm0vm7SoSN1BXZl6uXr1ygiCzPB2T0ZI1aJGGuoc0zJhjWbGmGd0Q GvwyV3dALOTyxk7BtrjurZWzHenrd8zR2GmX4+Pv6F8f71UM9W5wOWwbtehiHwYXTRR5 cPJvuTYVn3w0qmec2Q6sHN4cYjT7xBDdA9RUuUiTG1K7ttwVdJ9CwZ+uhVY99ddvb438 hKFP0rTVsVJqe445+Clg/rlxebDDYKogHv/dK0gOT564sdFN3lhwzb8d0xT5LK8SwUA/ +nrw== X-Gm-Message-State: AMCzsaULJD81CTUslWKxoWg3E5oXRRcmlNVZeOpnO3fC9vegpOAKBMT4 dNYhjLYZo7zyKfMQJcv5PfTJ+A== X-Received: by 10.223.184.125 with SMTP id u58mr5552072wrf.8.1509312261860; Sun, 29 Oct 2017 14:24:21 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:21 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Magnus Damm , Geert Uytterhoeven , Laurent Pinchart Subject: [PATCH 02/17] clocksource/drivers/sh_cmt: Use 0x3f mask for SH_CMT_48BIT case Date: Sun, 29 Oct 2017 22:20:19 +0100 Message-Id: <1509312035-17368-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Always use 0x3f as channel mask for the SH_CMT_48BIT type of devices. Once this patch is applied the "renesas,channels-mask" property will be ignored by the driver for older devices matching SH_CMT_48BIT. In the future when all CMT types store channel mask in the driver then we will be able to deprecate and remove "renesas,channels-mask" from DTS. Signed-off-by: Magnus Damm Acked-by: Laurent Pinchart Reviewed-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index e09e8bf..c104c80 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -74,6 +74,8 @@ enum sh_cmt_model { struct sh_cmt_info { enum sh_cmt_model model; + unsigned int channels_mask; + unsigned long width; /* 16 or 32 bit version of hardware block */ unsigned long overflow_bit; unsigned long clear_bits; @@ -212,6 +214,7 @@ static const struct sh_cmt_info sh_cmt_info[] = { }, [SH_CMT_48BIT] = { .model = SH_CMT_48BIT, + .channels_mask = 0x3f, .width = 32, .overflow_bit = SH_CMT32_CMCSR_CMF, .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), @@ -966,9 +969,14 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); cmt->info = id->data; - ret = sh_cmt_parse_dt(cmt); - if (ret < 0) - return ret; + /* prefer in-driver channel configuration over DT */ + if (cmt->info->channels_mask) { + cmt->hw_channels = cmt->info->channels_mask; + } else { + ret = sh_cmt_parse_dt(cmt); + if (ret < 0) + return ret; + } } else if (pdev->dev.platform_data) { struct sh_timer_config *cfg = pdev->dev.platform_data; const struct platform_device_id *id = pdev->id_entry; From patchwork Sun Oct 29 21:20:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117420 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853679qgn; Sun, 29 Oct 2017 14:24:32 -0700 (PDT) X-Google-Smtp-Source: ABhQp+T0ny021Him1d6c1VSVkQZHnUoUZgOSm7jEiEjVbJCokCH95ft3Gs7TvOjLcAy1zx4dsRn6 X-Received: by 10.99.143.88 with SMTP id r24mr5861482pgn.224.1509312272171; Sun, 29 Oct 2017 14:24:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312272; cv=none; d=google.com; s=arc-20160816; b=puA0y0dg58ZoUTcFv65GvpWoby/ZuzaatPgliXec+rGDfGj3/f0/lF/CVL7OJ4xGAk dsN/l4oB56y0eXDu4D1a5CFE1KQxazmmokI0OxtHI3AUFXbabytPep35rTRHkO1BgL/7 k055l8dFiNyVc+Q0EWAWaG20ZZuj/Hlybn9s5LQQJyhA2aVMOsXgVdeDeCDvkgQFnCzf cwe+05m7sTZv6NyFk/TXMCTKgKdViN3fcU7r91IY5pVFfdeFn85HbydJ1dwTLcMv8Fu3 o5QhgEG8CbMY2pWKLJUU9OxfPxDhVKIafvhYxZYcS0yODpjdXKZkp+u0aBR6D5Cu1Fpk 66Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rGGy12+eB2vgUva0ymGaErXj6Fo64KNrjLgJnIZtJ7k=; b=K+aqav7taDDFxLMdM67zTZFBVE3zqmvB69hQVtpjUFeF0LF5IE2+2tK9QUE41W4Yes POAT3rVxVGVdABBxVCKESNWVR+Hu1gbeS4mgB34/+mogMpL9IEfok4A7IiB2qUkNhnIt /U9kEsLljp5i9EW/qKIR6k+TMZclwEzQTZ0qSpuj4kHaq7JYDBb6ngA4TeUu1JutvYlC Vp9sjtkkOiLvHypYUx1Y/EQ74Gv9q0d5vdlL8fUZxYUpsV1IBQHQrwS57Y8BJs4gJKpX eKauyF0rpDgDSVpkEqQHTS3Gyf5ksluzmPKpx5hEALDYsaZgq8KIYdpqNVO5odZ36x+I dxDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BBWZt40q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 62si8504826pgh.81.2017.10.29.14.24.31; Sun, 29 Oct 2017 14:24:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BBWZt40q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932280AbdJ2VYa (ORCPT + 27 others); Sun, 29 Oct 2017 17:24:30 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:51382 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751319AbdJ2VYY (ORCPT ); Sun, 29 Oct 2017 17:24:24 -0400 Received: by mail-wr0-f194.google.com with SMTP id j15so10707275wre.8 for ; Sun, 29 Oct 2017 14:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rGGy12+eB2vgUva0ymGaErXj6Fo64KNrjLgJnIZtJ7k=; b=BBWZt40qAzrsCfsKj49T145rHzasNe3CubTC5Gmu1KRlEE6+6TclY4LLIr95jERwy6 LrNDhYWj84KdRS9GEPsXoxvfRmeBgo/5jfwVG4sTvERZeiIPGCKG+1ciTvsutLi/uf29 KFKy32Vr1HXR4BUXxgQMqVIOsCpyNn9ks4ons= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rGGy12+eB2vgUva0ymGaErXj6Fo64KNrjLgJnIZtJ7k=; b=KkeO7t8668C05wBLWMa1tAfVkjRnyhd5vzQzJg70DNacK9lqQrC0yrK7m0FWCDE1Dc +w5gm6epndeKWjdaPrLATgflTdjk+7SSqKqvwjq2/AHJd9VqiVgegzNpSRb3lULTXlZs feIrtaB9YMSVZNDb6vksCbPHG4PfanWh52m83vI4u6vl9taDhmWa0AkF+a+/zdSohks1 h9L/iKQQt2+niA1q4zn+qrlaxseaaeXKS5H7912crdSKdII7ybL4xPzXzjkAukHskxRG aK6vRPRiSFDNduYHJXzAo8bWyql/olRsRpyQWgggvitQ13lCZ3CkpxVhBTXtQdKWOC1k XSQA== X-Gm-Message-State: AMCzsaXPPvt33HixWH4v/KXc7hNK39y06YW1kt4ypr9JXi8cMh0b+d6W Vam6aeqiGVitk5hA7lIqhY58qg== X-Received: by 10.223.147.166 with SMTP id 35mr6435600wrp.90.1509312263413; Sun, 29 Oct 2017 14:24:23 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:22 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Magnus Damm , Geert Uytterhoeven , Laurent Pinchart Subject: [PATCH 03/17] clocksource/drivers/sh_cmt: Support separate R-Car Gen2 CMT0/1 Date: Sun, 29 Oct 2017 22:20:20 +0100 Message-Id: <1509312035-17368-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Add support for the new R-Car Gen2 CMT0 and CMT1 bindings. Support for the old DT binding is still kept around, however devices using such binding will be treated as a low-feature CMT0 device. If users want to make use of CMT1-specific features then they need to update their DTBs. No special CMT1-specific features are however implemented by his patch, only DT bindings are redone as groundwork for future feature patches. Signed-off-by: Magnus Damm Acked-by: Laurent Pinchart Reviewed-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index c104c80..45af436 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -39,16 +39,16 @@ struct sh_cmt_device; * SoC but also on the particular instance. The following table lists the main * characteristics of those flavours. * - * 16B 32B 32B-F 48B 48B-2 + * 16B 32B 32B-F 48B R-Car Gen2 * ----------------------------------------------------------------------------- * Channels 2 1/4 1 6 2/8 * Control Width 16 16 16 16 32 * Counter Width 16 32 32 32/48 32/48 * Shared Start/Stop Y Y Y Y N * - * The 48-bit gen2 version has a per-channel start/stop register located in the - * channel registers block. All other versions have a shared start/stop register - * located in the global space. + * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register + * located in the channel registers block. All other versions have a shared + * start/stop register located in the global space. * * Channels are indexed from 0 to N-1 in the documentation. The channel index * infers the start/stop bit position in the control register and the channel @@ -68,7 +68,8 @@ enum sh_cmt_model { SH_CMT_32BIT, SH_CMT_32BIT_FAST, SH_CMT_48BIT, - SH_CMT_48BIT_GEN2, + SH_CMT0_RCAR_GEN2, + SH_CMT1_RCAR_GEN2, }; struct sh_cmt_info { @@ -223,8 +224,20 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, - [SH_CMT_48BIT_GEN2] = { - .model = SH_CMT_48BIT_GEN2, + [SH_CMT0_RCAR_GEN2] = { + .model = SH_CMT0_RCAR_GEN2, + .channels_mask = 0x60, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, + [SH_CMT1_RCAR_GEN2] = { + .model = SH_CMT1_RCAR_GEN2, + .channels_mask = 0xff, .width = 32, .overflow_bit = SH_CMT32_CMCSR_CMF, .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), @@ -862,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx; /* * Compute the address of the channel control register block. For the @@ -883,9 +897,11 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, */ ch->ioctrl = cmt->mapbase + 0x40; break; - case SH_CMT_48BIT_GEN2: + case SH_CMT0_RCAR_GEN2: + case SH_CMT1_RCAR_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; break; } @@ -897,8 +913,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value; raw_spin_lock_init(&ch->lock); - ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; - ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), clockevent, clocksource); if (ret) { @@ -941,7 +955,9 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] }, { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, - { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, + { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, + { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] }, { } }; MODULE_DEVICE_TABLE(of, sh_cmt_of_table); From patchwork Sun Oct 29 21:20:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117419 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853673qgn; Sun, 29 Oct 2017 14:24:31 -0700 (PDT) X-Google-Smtp-Source: ABhQp+R5I75bwwtMXMnQk/JeYGV+9R8gitP3bUZ5u+SJ+mN6rHAnsK4nUWrUS5mYGUUWoGT4lg0F X-Received: by 10.98.204.157 with SMTP id j29mr6805784pfk.236.1509312271064; Sun, 29 Oct 2017 14:24:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312271; cv=none; d=google.com; s=arc-20160816; b=SpJB963vt+qtokAu4vx2H4KnqFSeeIM1ax6K5zxUDIxjIF/ZVkPepJrsPn3nQGF9IT 129SZdmyekK1bl9tSwgmaWVJxvmn0uRMGR42+f0BvHYt5ZHcntJBzqZR02i6fBJm9/Ga 5b/+UapO4Atn1I8611zEvRaoRCJOPddj4fQrGyh1sUiZLKy2WV5gkoqBLDIIkgIgtf1H 0aTqdkkDMVVOh5IuODjLrgqFVIxifC5WwKsQuMppSqkIyCbIAwY0tIb8S7RwXQ5e18xP dfi16FjvaGkLgZVGpeaT8fIjmglugjgmDUP7eQf/TY2itwr0wyJkqWppFmUjwzg/Vxct OHKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=zvQvEzF4U1EyertfYmCwOgpa2MT7RxXPj5d2gBeT/ig=; b=hNFLIdHs+wfb8zKYmInQ6j7KNN6B7BEjCOSoye2b/Al2p1jOZskzN11AjQOEGtohV4 VY7tnmpsKRtsI19xu8LXiLWN2w2pt+OaTNqEiCNKK02dlknRJW+blB75SXsAn3XsWufu TRUpo8FKo+PVGdknvzbEdTPuF9KT5tLgN8Fujro7+adThmM5Sy2SlkYkTLOsd0VC4Swi 1a8z9wBNd1bPwCYOjTpss8toX1XbWFNIx7XWdW/klTKxfpBLwyLWyNAQtcmI94N1ZiE8 6EMFqd5tlSaeiKWU+NrQOAjG4ITirUxzaFnfFDpYd4tfUj4wMf/M5U6jdiEu5hUVlhaK zAsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fCYwW5r/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 62si8504826pgh.81.2017.10.29.14.24.30; Sun, 29 Oct 2017 14:24:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fCYwW5r/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932208AbdJ2VY2 (ORCPT + 27 others); Sun, 29 Oct 2017 17:24:28 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:47757 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752100AbdJ2VY0 (ORCPT ); Sun, 29 Oct 2017 17:24:26 -0400 Received: by mail-wm0-f65.google.com with SMTP id r196so12189150wmf.2 for ; Sun, 29 Oct 2017 14:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zvQvEzF4U1EyertfYmCwOgpa2MT7RxXPj5d2gBeT/ig=; b=fCYwW5r/UZ9Rp9TJ8AX2o3GCFfT3hWYF9URIjwRaocDUNxU1igQsQNHeZ+nfjNZ6zq 1f4NJSYf5lsmfAFdOWLK2gX9ciOYBsI1LRX2hmNJBR9aZ9Ci9u1CmYLgsFWF73ZZ/FUf pTvmCrp57i14dRzLPNCMhz0zlBosh07uJuAsQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zvQvEzF4U1EyertfYmCwOgpa2MT7RxXPj5d2gBeT/ig=; b=jWO15Qq73vqPAd0rOh8sfiXfVEkHlGxWx88NcRS8YC8dbt7PPjDZ4nW4CEXkioQhMY fNANh6FOJ0bBEBGXxrqTJxRZou1WAnnHHUlWPGCwQsNQVpx97MeV3ld7u2FNRFJ0eIwe Tmk7S2tYjmDBM+fzKupU96ifU4dV3UoYgSC3X9l6FfSjWc/T6eP89OSv5Vr6s44ljY5A Ksqf7/Lhr1pDOHZ8wb/uHqJpDkrYp9PjRR16IDhlWiqW7+BjQ1o50wp+94jyWBejiuHi elEyQJ22/GOvJKAepW5sZ5FmNpUXi2sIs1SenhV527O/A9rNu8uZBuTlCxXR38DLnBQt kGOA== X-Gm-Message-State: AMCzsaXVjIiCjOrnIFEegCtT1xFy979mt/7uUupHlp5Q8uuAxjl9I7nI DIjOrSiHhp3C/RwLtAPrSetQLw== X-Received: by 10.28.229.149 with SMTP id c143mr1841864wmh.156.1509312264872; Sun, 29 Oct 2017 14:24:24 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:24 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 04/17] clocksource/drivers/sh_cmt: Remove support for "renesas, cmt-32*" Date: Sun, 29 Oct 2017 22:20:21 +0100 Message-Id: <1509312035-17368-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Geert Uytterhoeven Remove driver matching support for the unused "renesas,cmt-32" and "renesas,cmt-32-fast" compatible values, cfr. commit 203bb3479958c48a ("devicetree: bindings: Remove unused 32-bit CMT bindings"). As this removes the last user of SH_CMT_32BIT_FAST, all support for this variant is removed from the driver. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 20 -------------------- 1 file changed, 20 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 45af436..8546736 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -66,7 +66,6 @@ struct sh_cmt_device; enum sh_cmt_model { SH_CMT_16BIT, SH_CMT_32BIT, - SH_CMT_32BIT_FAST, SH_CMT_48BIT, SH_CMT0_RCAR_GEN2, SH_CMT1_RCAR_GEN2, @@ -203,16 +202,6 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, - [SH_CMT_32BIT_FAST] = { - .model = SH_CMT_32BIT_FAST, - .width = 32, - .overflow_bit = SH_CMT32_CMCSR_CMF, - .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), - .read_control = sh_cmt_read16, - .write_control = sh_cmt_write16, - .read_count = sh_cmt_read32, - .write_count = sh_cmt_write32, - }, [SH_CMT_48BIT] = { .model = SH_CMT_48BIT, .channels_mask = 0x3f, @@ -890,13 +879,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT: ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; break; - case SH_CMT_32BIT_FAST: - /* - * The 32-bit "fast" timer has a single channel at hwidx 5 but - * is located at offset 0x40 instead of 0x60 for some reason. - */ - ch->ioctrl = cmt->mapbase + 0x40; - break; case SH_CMT0_RCAR_GEN2: case SH_CMT1_RCAR_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; @@ -952,8 +934,6 @@ static const struct platform_device_id sh_cmt_id_table[] = { MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { - { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] }, - { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, From patchwork Sun Oct 29 21:20:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117433 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1855339qgn; Sun, 29 Oct 2017 14:27:32 -0700 (PDT) X-Google-Smtp-Source: ABhQp+T8YbBNUbEZGd/OIXbuObMmT+jaI20KWIiMbgMJSHXx9HBw78aniZFSC+8BSWRfHwAULLGY X-Received: by 10.98.102.74 with SMTP id a71mr6570673pfc.23.1509312452500; Sun, 29 Oct 2017 14:27:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312452; cv=none; d=google.com; s=arc-20160816; b=uBdBCRRraJcmV6ap2zrahZoIS9fM41helu+5xd+8AP5O7JhWSkZcUGqXchHhQ7fDxM ZCDlwswJHNKsaPlDV5PeMt39JNualDg+OnGQeMPGpM+V96xnDvnIdzvn8zVmRn0Pln3Q 6ODL/cOj87v6SML2pqEHgKWyjP9esF8kpVntP91wtxWSvAwmmoxNeF64iV+YjQBRmRCB Q9zL7LWeRZHVtnEnNGkeD2O9o2myBIqQR5miOfefF1YWNZvhwAnWPxQyUjciDQGJWqO9 FwFHEQVWzdIrHQSE75GjYlFSJE/Of+fEGaQ0LAgMzpnlB1crWXxjAFaVPqNbu8wjrtTG hj7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=LdXW+Rt0UqiRStJMD39C8PoF88+lfU36mO3jEQjGWt8=; b=lpr1R3hIdAFctBmT18VgvIXzr/E28ToQN3DA+cYsDkjKpYqik0orBUZ5lSAKIh3Mx2 NhYX0DP1Mz5CsH4beH7MyBBtncfHqGbnla69mX65Whdu/NdACpomdaHysf75RIEe97lr 5g/lXhLTDFPw7ljU0/DuWRtxuDt/oxFzMmc+8mqr2XSaoXz5yf+r8s88FnvMFDdvoqc5 t0s4xbyVujeXm+2nt6XaXIRUI/+JKwc7J7dBwv5gpciwXYWGSfD6INumg6n/RUKRwTTI HyHgY0yi3H1Oi2HSQBqcOFtwoTtZ6uFAi2GPUPGmCO0yZlZHCJZSSn4q/up5IVmZ9Zr1 9fMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WmxipG3P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u66si9359775pfa.109.2017.10.29.14.27.32; Sun, 29 Oct 2017 14:27:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WmxipG3P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752135AbdJ2V1a (ORCPT + 27 others); Sun, 29 Oct 2017 17:27:30 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:56615 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752101AbdJ2VY1 (ORCPT ); Sun, 29 Oct 2017 17:24:27 -0400 Received: by mail-wr0-f195.google.com with SMTP id r79so10672205wrb.13 for ; Sun, 29 Oct 2017 14:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LdXW+Rt0UqiRStJMD39C8PoF88+lfU36mO3jEQjGWt8=; b=WmxipG3PIjBAyfgYKfp4LAH3eIgGUETwdQ7ku2QfIXugqKTtx044HzpdM6Ppi1XX4K wE/xxW+QPl1oFeOSyu/h9j/74AddacU23AdoKEIGa8tw/fIaJu1w7QdirixTBMHEVybp IFKaIrLKQuZRHrcxDircUaHwnAhymucnQcK8A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LdXW+Rt0UqiRStJMD39C8PoF88+lfU36mO3jEQjGWt8=; b=H8vg5BCdlsnqqMNdFZOIHQoXHrdGplLQSVw6LKVS5kODZ+I90NoF7xc3AwKVD7pZES SngzS+4evFdSB+tob5m6GqXwZCrTmwmdg1N6bCaHhM5/vKxrOS2RjVWKGHzUnRE4E8iN h3QUlf+DmefbcGQR13Vyl8Tw2JarL0uTCMah5u5Q9s6/eFJNWxPCSK72ZDE7ivWxENZE o/UOAR+7+URGdZpAT1RChGgGD9fPKNcbuKPgXWrsCYtBf3ZW35vYV6vVrRcwCXvq9Piw /b+AWFZJiTTpsY08Jo0kRg6tcWKzdrxwYVQwUS5CGWBsg/Ty26qQ2RR7vzXZZw4W3i9o F/Rg== X-Gm-Message-State: AMCzsaUrVGMA2NGXMb1XD0z/jvj5kIg9nyGsdM1bi+Lp/SxAMZYYFc22 yGnF0n84wqaN4IuLvEJNWLMDOWTW300= X-Received: by 10.223.139.85 with SMTP id v21mr6064858wra.70.1509312266242; Sun, 29 Oct 2017 14:24:26 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:25 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 05/17] clocksource/drivers/sh_cmt: Mark "renesas, cmt-48-gen2" deprecated Date: Sun, 29 Oct 2017 22:20:22 +0100 Message-Id: <1509312035-17368-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Geert Uytterhoeven Document in the driver that "renesas,cmt-48-gen2" is deprecated, but still supported for backward compatibility with old DTBs, cfr. commit 4e18111ff38f0664 ("devicetree: bindings: Remove deprecated properties"). Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 8546736..61a9225 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -935,7 +935,11 @@ MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, - { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, + { + /* deprecated, preserved for backward compatibility */ + .compatible = "renesas,cmt-48-gen2", + .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] + }, { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] }, { } From patchwork Sun Oct 29 21:20:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117432 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1855097qgn; Sun, 29 Oct 2017 14:27:08 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SMMEf/WKrAF4xpxaZtPLuw15DswpRH3vd7Gc/La4ZuiVvypK7ifO7rWX+YOLzw88CaItjJ X-Received: by 10.98.33.203 with SMTP id o72mr6639889pfj.41.1509312428895; Sun, 29 Oct 2017 14:27:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312428; cv=none; d=google.com; s=arc-20160816; b=NhIGYbbNYUt/PU57/lAwOocREUAVO45Pys0u0NR5RFRlBpZ65V/FCoJ67PYOuCaS5v YQQLF/UR/82tldJk5+7JCV3MTm6YPmO+jGQJZNHq8p+CqLY3MHqe4DvEW/WVcLn59tqD Tpx18hfzxlzAkEbn8OXDpUFFZ5n4PhJwBhSMp//ZkgXcDWdMan3zYDQfIkWwO87CCuLD xNs2h9Yfb5GNB2ybJDZiOClhXOSd2lU6zCWII4tN4qf06/CdwGGKLGPyZ3SGPuMjgDdg ZYYre1WSxMUZZRv6rpjdY+pAuk6jjAUIfZhTR/2j0jBElhsGNPnL2Yow9sxlFpB1tZUJ 8cmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=jzBGPXNJVnGpnWOKK/oF6N3nprg0r6+WvlvD39//eAA=; b=tAsyMXxhneBSV0YQgAthvK2yEZEnLVser0mQuN1KXgHDyr3a7FM1S/QirD68nbitBM pXBEa+qHilN8yxMTgfQUXcJfq4cCFixbjDU44lpeVVM7Cz59l5DnaZpMjHFf9C1vAEwJ eqEDWvLyMJv5f02XA8kIv3IoQZd/8gHp05BS+0iM8dmHHQ+96o3ooUQmeTMmwQf5zPS0 5+roKmMG0B8tmbQrSsQObw5t2bvnuBTCzNt6xJzXdfaNANE/QlAmN0hZTNJ/LHeJjm1g cQibA4dKHkyrReczKob1WDHEVEoVRpiIlXYBveDr5wL/MjESBQAwSGkkH80nKshnI9p9 phkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIHryOQw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u12si3542739pgq.678.2017.10.29.14.27.08; Sun, 29 Oct 2017 14:27:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIHryOQw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752110AbdJ2V1H (ORCPT + 27 others); Sun, 29 Oct 2017 17:27:07 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:54553 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932193AbdJ2VY2 (ORCPT ); Sun, 29 Oct 2017 17:24:28 -0400 Received: by mail-wr0-f196.google.com with SMTP id o44so10682341wrf.11 for ; Sun, 29 Oct 2017 14:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jzBGPXNJVnGpnWOKK/oF6N3nprg0r6+WvlvD39//eAA=; b=OIHryOQw27v8TOxAPH4Xe8qfqTWKB0kG6DzWmoXNG+UMoPCr0i0KmbeMdQeOBcGrpT SumRbXWUqb8t6GfeThjOrTy44OUrP1HtQMnVJ5Lcl6chKrKYUroGIp7iN/TM7bH9yYzK Pw0rq+et9g0GzYg0CDO9jHFY9wgx+YZ6KCY64= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jzBGPXNJVnGpnWOKK/oF6N3nprg0r6+WvlvD39//eAA=; b=oJVzEppAKxOeaZ1yyEvLstiPL2QUxgEWt6X3JeM9ydq0c+nsXNZUUt/DuGYZ9pANdc 0vr+2KPUH4erpJnlApuoI1Ufl9sVYVhWmRqCNJC9vivlvyOqceLZ8fZgRY5qJg0doKfv 2JOrcIJrSqz/ZeirINAwcxqcLvJ0P9Yv/9ilbi85WSZkFOaqDfMk3b0QRXCf3iG8tGVv wzFmuoHeodcq+ic3zIbB6QadZiMqXHajfAIrwSO7zIUZHuu0GouxDvTnNIXVEHl+5RGJ 6Ch7Dgs9y+NJLmzuVM06W/zd037/04P6nmxulsUKgPYnE9bOKaIz/ber/zC0HWTDml3p 3NLg== X-Gm-Message-State: AMCzsaX6RztC/yCPsYKPiydaija5PqPyG0Ji3aWWEOimH9woYiZaoYmh H27McAPqfne48pwLlzf7ESE//94OGg8= X-Received: by 10.223.196.174 with SMTP id m43mr6407424wrf.7.1509312267593; Sun, 29 Oct 2017 14:24:27 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:27 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 06/17] clocksource/drivers/sh_cmt: Remove unused "renesas, channels-mask" handling Date: Sun, 29 Oct 2017 22:20:23 +0100 Message-Id: <1509312035-17368-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Geert Uytterhoeven The in-driver channel configuration in sh_cmt_info.channels_mask is now always set for all CMT devices instantiated from DT. Hence the "renesas,channels-mask" property is no longer checked, and its handling can be removed, cfr. commit 4e18111ff38f0664 ("devicetree: bindings: Remove deprecated properties"). Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 61a9225..89c514c 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -946,14 +946,6 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { }; MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -static int sh_cmt_parse_dt(struct sh_cmt_device *cmt) -{ - struct device_node *np = cmt->pdev->dev.of_node; - - return of_property_read_u32(np, "renesas,channels-mask", - &cmt->hw_channels); -} - static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) { unsigned int mask; @@ -968,15 +960,7 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); cmt->info = id->data; - - /* prefer in-driver channel configuration over DT */ - if (cmt->info->channels_mask) { - cmt->hw_channels = cmt->info->channels_mask; - } else { - ret = sh_cmt_parse_dt(cmt); - if (ret < 0) - return ret; - } + cmt->hw_channels = cmt->info->channels_mask; } else if (pdev->dev.platform_data) { struct sh_timer_config *cfg = pdev->dev.platform_data; const struct platform_device_id *id = pdev->id_entry; From patchwork Sun Oct 29 21:20:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117421 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853735qgn; Sun, 29 Oct 2017 14:24:38 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RCDaAeccUUs68kTFV3PBxvRg/mwgx7fKa471pAGaNhJs6Z26J3QqIVD4C46HzQaMw16Qcx X-Received: by 10.101.98.72 with SMTP id q8mr1540190pgv.71.1509312278379; Sun, 29 Oct 2017 14:24:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312278; cv=none; d=google.com; s=arc-20160816; b=uNMUK84Zj2C/3qcACkV1A6xgesdi+n7ISQp0x6rZEUh25PIPet9FDz0Ic623DgZxlk y0w2sxcMqec8oQB21RBQNQs8jRgQ+2PabmJm4YJxkxTlbpGvQH4iaUOp4fXEgKDkBkrs 77lacvAffNO4Pvv+l4ZEvKVwmwsM08DmO9ZPjD/14mJSIQVCBwPIRdc+DnnUp2JTKqHn pcED6Ea2Gz4DxDxDuXn/UfEgNc3bLl5aO4zrF2PgQhcLHZI58kKvIX7wpPK3maWjr76E JS0+i1v+1FndpohqOaU6Fo0yw4cDOjDvN5sOV7wIaOctuQccVS1x7QrX1H5Lp0oOPJew Qb5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=L9Hu0654CMjT1ngDV9FWDQUosHOEZKS1YmNueySOUOg=; b=dkNZlrqTGDqjOcXcEVBCLoW5AYeszRwg7qHfUreY1ssrMx0aE0NoOZqeirUTrOJ7kM Wl69vEqJfbuNQR0QhGGTG46vaRQXt8vwoCHMZJx0RC2VQX57fAGxaZUCJnbPY7Q0TZ+L a+JEo9FACjE5EnfGZ5sDq5xGsWNGzwb4z75YYZeGdHWC+qlTK/CCUIGFDOUGf0DCty5a Tyo4CnIhEYtd5aIsfMYPfFnkhvlji11Mm3SIFdGumIfTRQbDQZy2SLcRs8dCjOyDA6yJ 3/SmSN+vj0xMDiKTB1QJtccvqF8E25ksEnV9619iM626RBIYEqR1RvMf32zMTCusXjRf xxEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DPuJCt2a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j124si8618242pgc.216.2017.10.29.14.24.38; Sun, 29 Oct 2017 14:24:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DPuJCt2a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932308AbdJ2VYf (ORCPT + 27 others); Sun, 29 Oct 2017 17:24:35 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:50350 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932242AbdJ2VYa (ORCPT ); Sun, 29 Oct 2017 17:24:30 -0400 Received: by mail-wm0-f65.google.com with SMTP id s66so12091514wmf.5 for ; Sun, 29 Oct 2017 14:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L9Hu0654CMjT1ngDV9FWDQUosHOEZKS1YmNueySOUOg=; b=DPuJCt2aEeC9Og61HG8R3K1MtwEf0Yxj5KKmDXtIcc0NmTrHlVxZ/7hicF4L6L9AKo JRMtrqiVqEjyKxr/Eguex3dUbYTOBNEB6JYo0RS071N/6EPXZ3lcLPtD3mrTooB5LyGR vKYeVRNqQ6/aQf68xZrf7z5pWeQ5V8wSTNLLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L9Hu0654CMjT1ngDV9FWDQUosHOEZKS1YmNueySOUOg=; b=cuaQnKGeRrQMgtfQXjodh2szqBCqQD4GT3ujvFIH870sAfEN9ZFCFKTtU2Nlo49rGG lue1mhNKjlig5cfP2sIVScXethNbNQ8rGszoQOv7255WPTO1nztdPr6N1v4B7LkfVDgZ Yng6IfBF6bzUU5q+OxyBeO9SuaRb2m55jcKVZBAYWpbUmAVZKkPNKZboeigQ7nYs80/p q4hvgPgOjaBe3iyAbMtfZXnsQ5uiS8qxnT7DHgyq1V5Eo/oO4bdygxkDBeI8SPor5He1 1FXnoA0pBtn7myQmqZtZchQDlV4Tt/gdPZedJqvLqZS4lSAb43E4fPUaLNpw7OUERaSg yawA== X-Gm-Message-State: AMCzsaWcxipy1fu35pEgcsUwiil2690seKd5O4JMNwFnZpHqvL0YD2QW wxV/s4voygwSsvsjXPtVkeV1/g== X-Received: by 10.28.199.4 with SMTP id x4mr1850814wmf.124.1509312268888; Sun, 29 Oct 2017 14:24:28 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:28 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 07/17] clocksource/drivers/sh_cmt: Use of_device_get_match_data() helper Date: Sun, 29 Oct 2017 22:20:24 +0100 Message-Id: <1509312035-17368-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Geert Uytterhoeven Use the existing of_device_get_match_data() helper instead of open-coding its functionality. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 89c514c..70b3cf8 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -956,10 +957,7 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) raw_spin_lock_init(&cmt->lock); if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { - const struct of_device_id *id; - - id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); - cmt->info = id->data; + cmt->info = of_device_get_match_data(&pdev->dev); cmt->hw_channels = cmt->info->channels_mask; } else if (pdev->dev.platform_data) { struct sh_timer_config *cfg = pdev->dev.platform_data; From patchwork Sun Oct 29 21:20:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117431 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1854869qgn; Sun, 29 Oct 2017 14:26:47 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SEA+izdnyenJnxdhv3e6fhjeIxTxJt4rjagtaTzpZ4kHDP0Lj4sN47VEnEx5Bfq79iXK5a X-Received: by 10.98.95.197 with SMTP id t188mr6620424pfb.230.1509312407533; Sun, 29 Oct 2017 14:26:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312407; cv=none; d=google.com; s=arc-20160816; b=koG3iyNfyM/TzjX9Zjduz+5vtgktsXR+TfeG4PyJe+5iLmtnPlMEfBgkexwD6U3k6r LCCHjGKxVYt8slL25jpqZCJW2NHGQJoA4HYh85NonabHfKOcYbjRtsAVsk9xkKkN4yG+ RWH5TqKg6ADHiGm6Ivh9XCpd2RCxoukv/brWOquTqmUKBBGMaWFZ5TKGYBHOwc5oSs7K NR6NsOsBl9iJYEVxUMWSgKQQWYOH/7CareDLBaDeO/+Yj25zHco3daIlGaJMFCRncxAS GJmCBZw0eQATnvku9CP+dhtaGVXK56ALkAQWa92bfzM3RfadejTfswwR93hFLULe9Lmi JyJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=w461siXZ+lfTmUgZ8Lj8fpye7eP5CZuGIfHk6Z6K92c=; b=MVIwG0qVxxM0WfoV2qHo4l4c6ltnHhrCnqO8GM9Em+8G/1BIyxzE4dKjk/MftjUqik WB5G1vZc9rhL9L+bJv5cNaYntPb7pOIh6XZOqIE9vh8lt5WHUS6rX3rw6eylR50y0nLP Dm2ST9rmG4S4u5KpgswBeMwAP/1NkTLTcMUS/v8Zf0PqSIJqZmhVIzLTRkknSv9Ve9vN sPwaVYQpHDRXnq5F3kp4NURhoKjsQAEdMPzOmxioodJ0HiJc6YHc661G7189Ziq4QUB+ vlYwMAmPtG7BUQOmgN8NUMfC/rw+2MzFSgFmBPo8COG/vyY8NvY0gpEEJveVE4WwoFQQ 1LAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PWHnNfn/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Arvind Yadav Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 66dd909..32214eb 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -263,14 +263,14 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) fttmr010->base = of_iomap(np, 0); if (!fttmr010->base) { - pr_err("Can't remap registers"); + pr_err("Can't remap registers\n"); ret = -ENXIO; goto out_free; } /* IRQ for timer 1 */ irq = irq_of_parse_and_map(np, 0); if (irq <= 0) { - pr_err("Can't parse IRQ"); + pr_err("Can't parse IRQ\n"); ret = -EINVAL; goto out_unmap; } From patchwork Sun Oct 29 21:20:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117430 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1854739qgn; Sun, 29 Oct 2017 14:26:32 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RucoTFtcqZtl45gyzbPCNlaz+865q3/PfRe3S8huIIScHVLUSMGAquV4ilBP6dCI9OXoj4 X-Received: by 10.99.100.67 with SMTP id y64mr6048098pgb.349.1509312392359; Sun, 29 Oct 2017 14:26:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312392; cv=none; d=google.com; s=arc-20160816; b=zjpZjlYdmFHC7v9AS4gOOBQfCHibfteeMT2MVKrv3Dltn+ZGaRRjypympNFQqVa7jE +tD2gDsfutFboQE+y2aKDMp7dBUXSmV3yy8wVBmdQTMawiXVkQe+KsnJnmhRSSEPaSyR UHZnmMIi2f/6nVrMwoDmmtTwBgiz8pB5zBfxYaqHH2SsczkqSyWpLCSfp5x6dTDnMns2 912R7zTqSqEq7MCHJ+PSV/xqT60aoqKBBrQIFBic7NI3beaLyKTTFjOM0KzxcSr9AVb0 54Im2DWn4puvTZoWoCh5anTee6GjXcjauTOCfo0kuL+psFugEkfrn7+fmM4NJWxR4Oh1 twGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=WYNwWuKgetN4SeLy1hlWiZ8HOlr7ZbjU1FvLMGLKKpw=; b=egrwyOo2O0L53PYSKBFDJcx5I2m3XVMaAOSYNkPNl0w7M7lFHbJJmFlqhbntCzpHqY MysVM6PZUjyqfcrw7CA+gz3B73Kxvm2i32iNC+K0Gg1G/szQecQa53FBtPJwjWlG1G9n +gBkvgv22K+yIEMRz7DreBQVC/Nn71IxFWuxXDSxbj5IzvQuCe87EQ35/srsQ0Y9PH3i u7ovS/QFD2XIGqW6e0dHaZ5cL2/Oa71l9RdclgFRnY4dFjtJIQVYSFzHyCcyzbRmN2/H Dz1U2Bv2QhOAqhO5vr+kNIZt0jCCze7QfoSD64NtJ6KMBgmomkiiMhFSJbjwdxgg/WYx N5SQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WvWzxllL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Arvind Yadav Reviewed-by: Andreas Färber Signed-off-by: Daniel Lezcano --- drivers/clocksource/owl-timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c index d19c53c..c686305 100644 --- a/drivers/clocksource/owl-timer.c +++ b/drivers/clocksource/owl-timer.c @@ -125,7 +125,7 @@ static int __init owl_timer_init(struct device_node *node) owl_timer_base = of_io_request_and_map(node, 0, "owl-timer"); if (IS_ERR(owl_timer_base)) { - pr_err("Can't map timer registers"); + pr_err("Can't map timer registers\n"); return PTR_ERR(owl_timer_base); } @@ -134,7 +134,7 @@ static int __init owl_timer_init(struct device_node *node) timer1_irq = of_irq_get_byname(node, "timer1"); if (timer1_irq <= 0) { - pr_err("Can't parse timer1 IRQ"); + pr_err("Can't parse timer1 IRQ\n"); return -EINVAL; } From patchwork Sun Oct 29 21:20:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117423 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853896qgn; Sun, 29 Oct 2017 14:24:57 -0700 (PDT) X-Google-Smtp-Source: ABhQp+R7hnpzqW3NHqiEMuTgw4c97TWln9nUgABM++LdAAhbhXMyO4h3Ly3+C8A1USvAmT8NolSY X-Received: by 10.84.241.15 with SMTP id a15mr5616464pll.199.1509312297135; Sun, 29 Oct 2017 14:24:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312297; cv=none; d=google.com; s=arc-20160816; b=atE+TwijvQsa0thJy/bg97RP00DefoO9krdZ5NenzwnoEeJlXAcnHR8sI0nEeylcGq 6Y5QUad/X0t47GfJpc1FhuNwYJtQAKjcMBSpX4w1352bKZnmbQw55Aj5mZ9y5WHdLNlY Qe97kaO2Ssa8zu21taH9HQMR8cgbAJaK6AGNIVyidJtJLz1cTk0gUZJi/QykLzDWISpe 1tg8mQHZsWKysIHaDLNs/7VrdevDSVg9JYuqBMF2PzY2m2qMcJ+30+Hsat0Fpk5LcOaX U4alH/ajkMbv/CGXx1PtY85qTrKWOCX9TbRjIj528ZqfxZhBw4EWf48h+y0sAgTRSum6 fsIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=XbhScuhUbmiM+sqLEQLduzmK6YJ1zgkHNdOiIdMlJfU=; b=cv48d5JrugNBJV65ALsa0+bRfqJUCIWo4WYfHj3KxLc98sTyxlEQ1/IG7V2n0k7jDk SEN8p9CXNFDVtUOkd6uT76o+SF1oak/AptARRDrvpKtOuYwWzl5IicRkbZIa+HDAU4Xh ae+HcAAsmj7T9cHrWv4cngo8bTJJ+3uhwHlNA6ZNkaPj5fWKfzz/yu7IEsx/nxgiFTuR r3FOqxaiFo+dZjluRMn4s5ArR91hIFqBIMJ1zK7dz/6AYT92KlOYyUbL36CXb6NrTmyX pq+vE3wjEAatibFE5Oa4G137tXYxAv+el1Hle9oMrb13AM2+8Ab2anfAnpBsxjvTzsTR VkQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QA0D1vsg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Arvind Yadav Signed-off-by: Daniel Lezcano --- drivers/clocksource/rockchip_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c index c27f4c8..33f370d 100644 --- a/drivers/clocksource/rockchip_timer.c +++ b/drivers/clocksource/rockchip_timer.c @@ -274,7 +274,7 @@ static int __init rk_clksrc_init(struct device_node *np) TIMER_NAME, rk_clksrc->freq, 250, 32, clocksource_mmio_readl_down); if (ret) { - pr_err("Failed to register clocksource"); + pr_err("Failed to register clocksource\n"); goto out_clocksource; } From patchwork Sun Oct 29 21:20:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117422 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853760qgn; Sun, 29 Oct 2017 14:24:40 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RfAs7TboY5YreY3GOC12P7BslEO08MfE8ZeyrvKWMYiuNIuPr/UfIhe+z+kL9xjdJVGQZx X-Received: by 10.98.157.18 with SMTP id i18mr6910600pfd.120.1509312280896; Sun, 29 Oct 2017 14:24:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312280; cv=none; d=google.com; s=arc-20160816; b=nFJ0Rl8fLW0yzXgzuh9NtSYvs9uFFM8ZEW9Ro/fsrLafGNFFj0k43x9ILTeL/CZjXe qSUN5wLKohD22m5D/g0eqohD0Tt/fB2Mymsa8Fxw3FefGP7jn/rb+Z+5cAXl/bl/KI8s db9u2LvgAuWC7x9ZXwGmczB78rShD77hhy3pxRjdAjdvsFIf2gG+/LaqgCxy3AaqZ6VZ N24pn9PvGeX+5ekKnj241b8CpeBV5hf9A0licWWo6Huh+Q5e5K0u2/uP/BgMjDdUxTCl 2d1nF2kFZKS+xNkjkV4VxCL8OLL853AWKEBpcOVskmXKlE4+y5L6pvWaK25I/YgePYGU DPmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=va8gCS72P5Nwir9CJFid2r9frXAbyrd/KcIdjIh1nZI=; b=fJP2+rGJkSmpQbEHu4Sugg+1ur33qUelTaf00kvV2l7mFhUDn/GZQZeP/Q9JnJFVMj F8DrwAZqS3eZzlD24A6pPLWNPtBUwHC8s4Veu5iD41+SrZDywfGd/Td+nXNyM+KgjIgD fLItWWcXhyWbRsraG4W7CMnj/LGMZ/WWdkHDtubiOGIugSyZFZ+wWtJ/Bj1HftWrNGxR AdkTIEXgSDHchOT2I8XPJ2FLio3E64+0BFa1jySEhF+nb2JMy9pDBHrmUIK4pNuVeQs3 awHDh3LjCeqA9yKtMvaSZ0hRm+VzlRcLffJ2RtEqfwRt7dTCIOImcLdvDHQHzKx+388g 9XwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gi40tnLf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We could add further dependencies as we did many times, but I have looked a little bit more at what architectures are left that don't use GENERIC_CLOCKEVENTS, and this shows that there is a better solution. On arch/frv and arch/ia64, we never select CONFIG_GENERIC_CLOCKEVENTS and we also don't use ARCH_USES_GETTIMEOFFSET, which would block the clocksource Kconfig menu. On m68k, some platforms use CONFIG_GENERIC_CLOCKEVENTS, some use ARCH_USES_GETTIMEOFFSET, and some use neither of them. The good news is that there is no configuration that does not set CONFIG_GENERIC_CLOCKEVENTS but that wants to enable any of the Kconfig symbols in the menu, so we can simply replace the dependency with the stricter one. While in theory one could have a clocksource driver without the clockevent infrastructure, this seems unlikely to be relevant in the future any more. We can probably drop some of the other dependencies as well now, e.g. there should generally be no reason to depend on CONFIG_ARM unless the driver uses architecture specific assembly. Reported-by: Randy Dunlap Signed-off-by: Arnd Bergmann Reviewed-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 50 ++++++++------------------------------------- 1 file changed, 9 insertions(+), 41 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cc60620..c729a88 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -1,9 +1,8 @@ menu "Clock Source drivers" - depends on !ARCH_USES_GETTIMEOFFSET + depends on GENERIC_CLOCKEVENTS config TIMER_OF bool - depends on GENERIC_CLOCKEVENTS select TIMER_PROBE config TIMER_ACPI @@ -30,21 +29,18 @@ config CLKSRC_MMIO config BCM2835_TIMER bool "BCM2835 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables the support for the BCM2835 timer driver. config BCM_KONA_TIMER bool "BCM mobile timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables the support for the BCM Kona mobile timer driver. config DIGICOLOR_TIMER bool "Digicolor timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO depends on HAS_IOMEM help @@ -52,7 +48,6 @@ config DIGICOLOR_TIMER config DW_APB_TIMER bool "DW APB timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS help Enables the support for the dw_apb timer. @@ -63,7 +58,6 @@ config DW_APB_TIMER_OF config FTTMR010_TIMER bool "Faraday Technology timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM select CLKSRC_MMIO select TIMER_OF @@ -90,7 +84,6 @@ config ARMADA_370_XP_TIMER config MESON6_TIMER bool "Meson6 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables the support for the Meson6 timer driver. @@ -105,14 +98,12 @@ config ORION_TIMER config OWL_TIMER bool "Owl timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables the support for the Actions Semi Owl timer driver. config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM select CLKSRC_MMIO select TIMER_OF @@ -135,7 +126,6 @@ config TEGRA_TIMER config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM help Enables support for the VT8500 driver. @@ -148,7 +138,6 @@ config CADENCE_TTC_TIMER config ASM9260_TIMER bool "ASM9260 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO select TIMER_OF help @@ -171,28 +160,24 @@ config CLKSRC_NOMADIK_MTU_SCHED_CLOCK config CLKSRC_DBX500_PRCMU bool "Clocksource PRCMU Timer" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM help Use the always on PRCMU Timer as clocksource config CLPS711X_TIMER bool "Cirrus logic timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables support for the Cirrus Logic PS711 timer. config ATLAS7_TIMER bool "Atlas7 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables support for the Atlas7 timer. config MXS_TIMER bool "Mxs timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO select STMP_DEVICE help @@ -200,14 +185,12 @@ config MXS_TIMER config PRIMA2_TIMER bool "Prima2 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables support for the Prima2 timer. config U300_TIMER bool "U300 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on ARM select CLKSRC_MMIO help @@ -215,14 +198,12 @@ config U300_TIMER config NSPIRE_TIMER bool "NSpire timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables support for the Nspire timer. config KEYSTONE_TIMER bool "Keystone timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on ARM || ARM64 select CLKSRC_MMIO help @@ -230,7 +211,6 @@ config KEYSTONE_TIMER config INTEGRATOR_AP_TIMER bool "Integrator-ap timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables support for the Integrator-ap timer. @@ -253,7 +233,7 @@ config CLKSRC_EFM32 config CLKSRC_LPC32XX bool "Clocksource for LPC32XX" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + depends on HAS_IOMEM depends on ARM select CLKSRC_MMIO select TIMER_OF @@ -262,7 +242,7 @@ config CLKSRC_LPC32XX config CLKSRC_PISTACHIO bool "Clocksource for Pistachio SoC" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + depends on HAS_IOMEM select TIMER_OF help Enables the clocksource for the Pistachio SoC. @@ -298,7 +278,6 @@ config CLKSRC_MPS2 config ARC_TIMERS bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select TIMER_OF help These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores @@ -307,7 +286,6 @@ config ARC_TIMERS config ARC_TIMERS_64BIT bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on ARC_TIMERS select TIMER_OF help @@ -407,7 +385,6 @@ config ATMEL_PIT config ATMEL_ST bool "Atmel ST timer support" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select TIMER_OF select MFD_SYSCON help @@ -426,7 +403,6 @@ config CLKSRC_EXYNOS_MCT config CLKSRC_SAMSUNG_PWM bool "PWM timer driver for Samsung S3C, S5P" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM help This is a new clocksource driver for the PWM timer found in @@ -436,7 +412,6 @@ config CLKSRC_SAMSUNG_PWM config FSL_FTM_TIMER bool "Freescale FlexTimer Module driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM select CLKSRC_MMIO help @@ -450,7 +425,6 @@ config VF_PIT_TIMER config OXNAS_RPS_TIMER bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select TIMER_OF select CLKSRC_MMIO help @@ -461,7 +435,7 @@ config SYS_SUPPORTS_SH_CMT config MTK_TIMER bool "Mediatek timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + depends on HAS_IOMEM select TIMER_OF select CLKSRC_MMIO help @@ -479,7 +453,6 @@ config SYS_SUPPORTS_EM_STI config CLKSRC_JCORE_PIT bool "J-Core PIT timer driver" if COMPILE_TEST depends on OF - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM select CLKSRC_MMIO help @@ -488,7 +461,6 @@ config CLKSRC_JCORE_PIT config SH_TIMER_CMT bool "Renesas CMT timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT help @@ -498,7 +470,6 @@ config SH_TIMER_CMT config SH_TIMER_MTU2 bool "Renesas MTU2 timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_MTU2 help @@ -508,14 +479,12 @@ config SH_TIMER_MTU2 config RENESAS_OSTM bool "Renesas OSTM timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO help Enables the support for the Renesas OSTM. config SH_TIMER_TMU bool "Renesas TMU timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_TMU help @@ -525,7 +494,7 @@ config SH_TIMER_TMU config EM_TIMER_STI bool "Renesas STI timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + depends on HAS_IOMEM default SYS_SUPPORTS_EM_STI help This enables build of a clocksource and clockevent driver for @@ -566,7 +535,6 @@ config CLKSRC_TANGO_XTAL config CLKSRC_PXA bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM select CLKSRC_MMIO help @@ -575,20 +543,20 @@ config CLKSRC_PXA config H8300_TMR8 bool "Clockevent timer for the H8300 platform" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + depends on HAS_IOMEM help This enables the 8 bits timer for the H8300 platform. config H8300_TMR16 bool "Clockevent timer for the H83069 platform" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + depends on HAS_IOMEM help This enables the 16 bits timer for the H8300 platform with the H83069 cpu. config H8300_TPU bool "Clocksource for the H8300 platform" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + depends on HAS_IOMEM help This enables the clocksource for the H8300 platform with the H8S2678 cpu. @@ -600,7 +568,7 @@ config CLKSRC_IMX_GPT config CLKSRC_IMX_TPM bool "Clocksource using i.MX TPM" if COMPILE_TEST - depends on ARM && CLKDEV_LOOKUP && GENERIC_CLOCKEVENTS + depends on ARM && CLKDEV_LOOKUP select CLKSRC_MMIO help Enable this option to use IMX Timer/PWM Module (TPM) timer as From patchwork Sun Oct 29 21:20:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117429 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1854626qgn; Sun, 29 Oct 2017 14:26:17 -0700 (PDT) X-Google-Smtp-Source: ABhQp+ReDg5ZnVsprHw+b8CvnO7LsM0s77kTtF3FaV/NoTwxCkYHkoyAo3LXdBImRi86OV46ctKe X-Received: by 10.101.64.140 with SMTP id t12mr6104305pgp.305.1509312376954; Sun, 29 Oct 2017 14:26:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312376; cv=none; d=google.com; s=arc-20160816; b=O+GmfLzvaZKQYzlhpjtAglvtZUqn5tg/0vQp9T8IitQbCbXfCUcFu5C645cOVVlmw9 QA3YmhkvDZs8H7utiB+7hP4IoSoj2OH/0aBdRe3FJv8fa6SwFaqzQV+N0mEerKK3+WPq qhk3v/abCoGA6+PMtGtW9aUwH/GW5Q/G2IM3u0g8TsNr+nL6X0+pJrs7KhPY4+13dKWG 2GY3/KYoqOkg9DZXoMl6rapZ9ASGzGQj2qs1hLI4dqqc5rkav9IHOo748V8wfHocHZt6 53TFZ6hOjeL8Fi3LMchvW59shL5kkOI/vy6xMBdNQDkwZ8BqeJsIZQcLbRh2u9WsJJs1 zDiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=2dEA5nuf+q/ACAdvD7iTNU1cwISf0v+LjVWfYELwA28=; b=e9ETOKXJjg375iaT5ZflP22LDR0FqTSdJgcGDt4YOX3R7kVXZGkeYWxKHRaLkwbwz6 Oevuectc0EfwE+aS7pi2OguTOu5Vl0fcJUCMtTo+tVG0WdUjRHa1xFO3m05npSbjXmMd IbTJElaYIAE+V7TK6kybyeAjqNZ+SWu89EBSwDlnvOxk3IUsgQ93Sq/WDoeFDnZ9dsA5 p1GzLN1pOC7oyqOymG895h4okzOlNyyIAV3AeuitxBJJoCRmDe8m0y5ysrplQf+vRCXc 1LjFs4uJdVE3X31gE1kphq8mwRr7qBHe9VKpjciS5kBp/AGR4xNBPA0lyLs7X8ZxptqG 1Ysw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a6VDe3Pt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Greg Kroah-Hartman , Mauro Carvalho Chehab , Randy Dunlap Subject: [PATCH 12/17] MAINTAINERS: Fix path and add bindings to timers Date: Sun, 29 Oct 2017 22:20:29 +0100 Message-Id: <1509312035-17368-12-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As spotted by Andreas Färber, the clocksource directory path does not follow the rule where a maintained directory must end with a '/' character. Also, the timers devicetree bindings documentation is not mentioned in the entry, so every submission touching the devicetree documentation misses to Cc the maintainers of the timers. Reported-by: Andreas Färber Reviewed-by: Andreas Färber Signed-off-by: Daniel Lezcano --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/MAINTAINERS b/MAINTAINERS index 65b0c88..67be8f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3444,7 +3444,8 @@ M: Thomas Gleixner L: linux-kernel@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core S: Supported -F: drivers/clocksource +F: drivers/clocksource/ +F: Documentation/devicetree/bindings/timer/ CMPC ACPI DRIVER M: Thadeu Lima de Souza Cascardo From patchwork Sun Oct 29 21:20:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117424 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853929qgn; Sun, 29 Oct 2017 14:25:02 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RJYzKzJidhLUaAxajW+86Z8p1sTgXBLB/vMT5CS+ttoRYenKZa5CaL/zATkUMYI9LrUwVn X-Received: by 10.159.204.139 with SMTP id t11mr5686921plo.121.1509312302235; Sun, 29 Oct 2017 14:25:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312302; cv=none; d=google.com; s=arc-20160816; b=T9Qd3BnPgizieEOBevZYr1KbBZ8RLevMfIeSh94Q4TJAh3O7Zxxyh4cIpAdYE7Uhj9 CfbYy+9oGX6gWW5AF43NvQGoyFupnlf30RjHTUKHMDVSfWg2yyxDXZ/Hdk+qobwQDnay VNKCuFDCzzn8RxpMe3xIH6xUw5VKDxrT+AdsTkiNqpRlEYlLGM73JuEwlP2ag2iSIBUE DTlm5fY8quw5FeLp7lN7wGZlJxgGo4mGM5c5wWyNt9bnmKnOHHXil5yjSxlKd1pQJXD2 1V4DSF6+ksGbHhVxtXJRRjjpViaM0OnIlCB/pvXrI/SYb5RsBa1Nwzd8YFMxE6uhkxR7 QzZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=KzLa/zs4q6J9kwvUFKbHHqCCydwxjQBFc5Bc7Px30MQ=; b=sAnm6oksnzqwU9SuPUW7B9/tqTE5kOJjg2xArlmbSk5Rwervhmg4dHK8LNWAguDrH2 ZcZs4vqxpyxAHZ0u9PC2sNm3BSm6Kn1IKNPsWWEKdkBy0m2ooqvXO6P47uxB405d9QS2 tvWSAyiaD0F3kSNKWx0ZkV5IOGaMGzSJ2kHtrsMN1Ksb5XLGWYHkMN1UBCeEknzZITDO XwcAQotRqhX9XLPNUyumhm7ae7JB3uP7Ol8GZMzX+5tByxmuMW9Mvg8coOsNe8gJIaAh MMbHpS8Ek8gRilhT0wNn1ona8PQbB4q2Ghese43l7nP7VKk2dC7A6rDUmKZI+EcxpNLm tWsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d3VckFBN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s83si9336457pfg.506.2017.10.29.14.25.01; Sun, 29 Oct 2017 14:25:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d3VckFBN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932380AbdJ2VY7 (ORCPT + 27 others); Sun, 29 Oct 2017 17:24:59 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:45233 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932342AbdJ2VY4 (ORCPT ); Sun, 29 Oct 2017 17:24:56 -0400 Received: by mail-wm0-f65.google.com with SMTP id y80so5351361wmd.0 for ; Sun, 29 Oct 2017 14:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KzLa/zs4q6J9kwvUFKbHHqCCydwxjQBFc5Bc7Px30MQ=; b=d3VckFBNxB1im1+vFRCq+ddLhgcAXGsqQJi5PL0RLy+phfspm7AlmdLERas1KckJrP 2tkwkNilhv4u8tsFgSpzf+peuzTLZBdtes7u7pHQ3+vhc3e7pEhTAuo+70DfyJRYyt70 LyzDlFOQ43+vPALWGqAY9fUoEYxbSfCo+QIx0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KzLa/zs4q6J9kwvUFKbHHqCCydwxjQBFc5Bc7Px30MQ=; b=Uw2xIZUNR0n4FzEDHY+oY5NItWNHK4Vsh6uhIbzj1Vm6kX7ZxeCQOzJ2ZfdHRbiFIp /7BmD6ZGyW/6dEkAqXUyZmhudmy1pb0iYo9sbHQvKABR9lhSn2j1GPNSHBb4pX7GFQX6 +NECptI49L9aP70r/3xo9utHV50ik4SR/uCfUyzMvO5G9Cv8yESk8V/hGc98hdK+kAzH ngvV7vCWFg8ncMH4oY7IggGHRBkWwUHj8iiYi7HY4Y6adQ1cTzXRWWHpCJXWTKz0uTm4 fJR9lUglQMYX2hCPKkJel0p6gdX0qYBl6hBPf+d9DNKV29qLIOgGC9k3twSPA9/Lbv3b ZD3g== X-Gm-Message-State: AMCzsaUvP0wKqaYwzT8RsbFz2qIfLNveOQrjJ7moOYChJNGoXmSCvkwF Owbe/F3D8cvQYTVqjfPcjK+hSb3KtBA= X-Received: by 10.28.35.67 with SMTP id j64mr1853457wmj.55.1509312294669; Sun, 29 Oct 2017 14:24:54 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:54 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Ard Biesheuvel , Mark Rutland , Marc Zyngier , linux-arm-kernel@lists.infradead.org (moderated list:ARM ARCHITECTED TIMER DRIVER) Subject: [PATCH 13/17] clocksource/drivers/arm_arch_timer: Validate CNTFRQ after enabling frame Date: Sun, 29 Oct 2017 22:20:30 +0100 Message-Id: <1509312035-17368-13-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ard Biesheuvel The ACPI GTDT code validates the CNTFRQ field of each MMIO timer frame against the CNTFRQ system register of the current CPU, to ensure that they are equal, which is mandated by the architecture. However, reading the CNTFRQ field of a frame is not possible until the RFRQ bit in the frame's CNTACRn register is set, and doing so before that willl produce the following error: arch_timer: [Firmware Bug]: CNTFRQ mismatch: frame @ 0x00000000e0be0000: (0x00000000), CPU: (0x0ee6b280) arch_timer: Disabling MMIO timers due to CNTFRQ mismatch arch_timer: Failed to initialize memory-mapped timer. The reason is that the CNTFRQ field is RES0 if access is not enabled. So move the validation of CNTFRQ into the loop that iterates over the timers to find the best frame, but defer it until after we have selected the best frame, which should also have enabled the RFRQ bit. Signed-off-by: Ard Biesheuvel Signed-off-by: Mark Rutland Signed-off-by: Daniel Lezcano --- drivers/clocksource/arm_arch_timer.c | 38 ++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 17 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index fd4b7f6..14e2419 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -1268,10 +1268,6 @@ arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem) iounmap(cntctlbase); - if (!best_frame) - pr_err("Unable to find a suitable frame in timer @ %pa\n", - &timer_mem->cntctlbase); - return best_frame; } @@ -1372,6 +1368,8 @@ static int __init arch_timer_mem_of_init(struct device_node *np) frame = arch_timer_mem_find_best_frame(timer_mem); if (!frame) { + pr_err("Unable to find a suitable frame in timer @ %pa\n", + &timer_mem->cntctlbase); ret = -EINVAL; goto out; } @@ -1420,7 +1418,7 @@ arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem) static int __init arch_timer_mem_acpi_init(int platform_timer_count) { struct arch_timer_mem *timers, *timer; - struct arch_timer_mem_frame *frame; + struct arch_timer_mem_frame *frame, *best_frame = NULL; int timer_count, i, ret = 0; timers = kcalloc(platform_timer_count, sizeof(*timers), @@ -1432,14 +1430,6 @@ static int __init arch_timer_mem_acpi_init(int platform_timer_count) if (ret || !timer_count) goto out; - for (i = 0; i < timer_count; i++) { - ret = arch_timer_mem_verify_cntfrq(&timers[i]); - if (ret) { - pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n"); - goto out; - } - } - /* * While unlikely, it's theoretically possible that none of the frames * in a timer expose the combination of feature we want. @@ -1448,12 +1438,26 @@ static int __init arch_timer_mem_acpi_init(int platform_timer_count) timer = &timers[i]; frame = arch_timer_mem_find_best_frame(timer); - if (frame) - break; + if (!best_frame) + best_frame = frame; + + ret = arch_timer_mem_verify_cntfrq(timer); + if (ret) { + pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n"); + goto out; + } + + if (!best_frame) /* implies !frame */ + /* + * Only complain about missing suitable frames if we + * haven't already found one in a previous iteration. + */ + pr_err("Unable to find a suitable frame in timer @ %pa\n", + &timer->cntctlbase); } - if (frame) - ret = arch_timer_mem_frame_register(frame); + if (best_frame) + ret = arch_timer_mem_frame_register(best_frame); out: kfree(timers); return ret; From patchwork Sun Oct 29 21:20:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117428 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1854400qgn; Sun, 29 Oct 2017 14:25:53 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RwSBpnos6kNF07VYZj44WlI9zMjCCQdxUeWfG0/Vvsj0InUOzRrOl/pL6OxU8RJA1MSf+D X-Received: by 10.99.96.208 with SMTP id u199mr6036796pgb.323.1509312353511; Sun, 29 Oct 2017 14:25:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312353; cv=none; d=google.com; s=arc-20160816; b=gOev/Gv/4wnA45NrJCWkTTWQTD9rvRDW5jQ7ENhntdwpEDiCJDHw3ekH973/8jnkG8 vt6dz++3bRVirQX9xw+vl+tIAHDk4sdCxzeS9tIak/PXOqJdpMPWayW5ToDTXU4C+qpP KR6ADd2fB2K0tR/O7ffKBuK7vy/MK3E9llUsdBJQAzaxBcvcPsf6g5aJRustDRuxn/R3 gcL8J8ZmHxYzApVW1tK1KNS4NINLmVT8B1mrzsiwrScfx2bJdK7p3oZ9zq4dcosYmTZl Efg8qnVjcRHhLQVj8o050hxhEHCQOVfuHsEq5r0TwSkmHaIyeZRMrQzdeI/7upQxQkAC zPkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=mXHU6QdygEC6rPDGVoJR8Ci8ANhm/572gpi2eliipsM=; b=MGSvG06H5Qr4gMDoC+Xmwl3mGb4g0eB0GqnS8+2iaOVN2RyNGiYM0bzcJsQ6Vsu29b umn/SXixq/Ewb4DrOuIebNmJS/6kNvApccdP8zCOyyB++EX2SiSZbYOEAoyXHzIe3f2a 51FUafT1qszKqhdfSv1ZOlL6pkHyuiG91XmEpbujokSFcaR3mA1CCEl0HtZboeIcHE0K lnu7RXOY6eLRGKYoombsMzrd2zLXHan7w5SkdpVCYFIglYlxkB0eWq+kOwEBapNFTWOa 2iL2EuLe3g0pLU2/IxFRQnVt0x4oT9QzC7UDQU/wh+R3yHGlS1i1AiiH7Htt7lqSJOkD yVZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L6vG4diK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v126si8527394pgb.554.2017.10.29.14.25.53; Sun, 29 Oct 2017 14:25:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L6vG4diK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932447AbdJ2VZv (ORCPT + 27 others); Sun, 29 Oct 2017 17:25:51 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:54611 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932293AbdJ2VY5 (ORCPT ); Sun, 29 Oct 2017 17:24:57 -0400 Received: by mail-wr0-f193.google.com with SMTP id o44so10683085wrf.11 for ; Sun, 29 Oct 2017 14:24:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mXHU6QdygEC6rPDGVoJR8Ci8ANhm/572gpi2eliipsM=; b=L6vG4diKZNFx7+NWhSKlkL/jNwfAAvjaQXiDfGIAJt+wY3syuqVd9TypKKRcIjDHNX T013LDXCKsMdFMay+RYkPfWyb4l0mooExuE6Imm9EXWcmnJGAb5WMJVRkV8YI11tVVn0 Iko31m8UV+M7+jnDBt4cMsk292x0tAyspkPlo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mXHU6QdygEC6rPDGVoJR8Ci8ANhm/572gpi2eliipsM=; b=XWjmTgVBhQbsHRIvYXZShghdqUULMqecigQtn6uM9Ylagb1GHJWss3mEGokwGDZdlU OU9F18pcCA2EjhqBknyTTjozUcQZqwpLt5/KzG7x5lWIj4yfNtutIix6qLqsApAQ2hfV pLYQ3PwmoeYu4twy3Zwroj2E5VOPU92E3g2O+vIGmhEpWGgy9R1j7h7m4VoIPOW8pe6i V7XzlSgXCl41xDvHIeBP4QuTSCBDH7AGdpX43gpCZj7S/orRqpG1kbtD6SCPjV9Xi4OG zvwg2f/+9BvWcryEZrIzayJcX74vCISpVj9f/MaFE2ofrva1WgeFu547Ca/VvvDwO9b2 xwTQ== X-Gm-Message-State: AMCzsaV7vXD/liw/e95n3/u/Bn+lVN6GT95Xc2PySPWSB+MdVgZxUiaN xBTIAMDsjuW95JUlM6jB7rNo+w== X-Received: by 10.223.176.82 with SMTP id g18mr5484621wra.234.1509312296175; Sun, 29 Oct 2017 14:24:56 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:55 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Mark Rutland , linux-arm-kernel@lists.infradead.org, Marc Zyngier Subject: [PATCH 14/17] clocksource/drivers/arm_arch_timer: Fix DEFINE_PER_CPU expansion Date: Sun, 29 Oct 2017 22:20:31 +0100 Message-Id: <1509312035-17368-14-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Rutland Our ctags mangling script can't handle newlines inside of a DEFINE_PER_CPU(), leading to an annoying message whenever tags are built: ctags: Warning: drivers/clocksource/arm_arch_timer.c:302: null expansion of name pattern "\1" This was dealt with elsewhere in commit: 25528213fe9f75f4 ("tags: Fix DEFINE_PER_CPU expansions") ... by ensuring each DEFINE_PER_CPU() was contained on a single line, even where this would violate the usual code style (checkpatch warnings and all). Let's do the same for the arch timer driver, and get rid of the distraction. Signed-off-by: Mark Rutland Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Daniel Lezcano --- drivers/clocksource/arm_arch_timer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 14e2419..0ecf5be 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -299,8 +299,7 @@ static u64 notrace arm64_858921_read_cntvct_el0(void) #endif #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND -DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, - timer_unstable_counter_workaround); +DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); From patchwork Sun Oct 29 21:20:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117427 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1854230qgn; Sun, 29 Oct 2017 14:25:36 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SYF+wYFGutC5VQ5cHpJJzXG0s9VSOwymLLgXx8vZojgovZTBao7taojywf60wKEx6sF7Wc X-Received: by 10.101.78.207 with SMTP id w15mr6041506pgq.347.1509312336150; Sun, 29 Oct 2017 14:25:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312336; cv=none; d=google.com; s=arc-20160816; b=z4HdxDWqkJCueYqB2oASm0rMU/aufQ4IKWVkVB7ekmBgWjz/anHPCfntQJm2RVbBlt pgAAEq9a5wcgPuMSDUFfGUOTy4Kxt759Qs5p2Kt9T6+BO/AfM9GGggc3YkgBb+IpZP8N mKVf1gJ2fGlozH2O13QfGEuu5DP+3VTjQbHimPI8eKeRoS5AZ6F9AsQ4Vjj0EvbDHkcE xIqEF55HmxECyjZknxQkISJgdkCsPbQX8aKhE5X/tzsdhvshwODpgLqlvzC7pkBtWmv6 LTAKXCLNyLCFmS14nXsAiYcUjpwYtSPTpQqfbFHFQ2b0JtUyZ8gBWqXW1v5BHtpb6l+k 4BlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=MGxxK9z7gZnvqPy6mQ7Yj0gd0XPRMc5sGdILtK3O0/M=; b=S1ukQ9aI+B6f3o1VbN51ntgTVkpe6Feqs6BL8/jTgxW7FJIMojV60agS0xAeRgRo9A 25YeIlZ3Dyc6G9sZcgyT6hN2ekEIbBsUphwgpCkhl61bdahVifV1FjFXmBWoWyzgsJUL Av2iQINlrFKl9yGgMauz09FlFo4DBy024ORIv8UsVD1yqwhObE95gtj2C8qQkGfr4Xhz XWjc3rwhYJl2DH9PF9nergYPv6ZjK9bYR8l7EARGKY3tV6jyJGcm6A3tNCaQtn2G+t4c LiNcdnHaC8tALSjjMg3q9La5Of0yEcaswSVMxB/+hngV/vovbDFEXhQq0IB2135nHoz9 gAbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FiFKoip5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m9si7784711pln.771.2017.10.29.14.25.35; Sun, 29 Oct 2017 14:25:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FiFKoip5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932432AbdJ2VZd (ORCPT + 27 others); Sun, 29 Oct 2017 17:25:33 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44342 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932365AbdJ2VY6 (ORCPT ); Sun, 29 Oct 2017 17:24:58 -0400 Received: by mail-wr0-f193.google.com with SMTP id z55so10727627wrz.1 for ; Sun, 29 Oct 2017 14:24:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MGxxK9z7gZnvqPy6mQ7Yj0gd0XPRMc5sGdILtK3O0/M=; b=FiFKoip54v2RWk6qJPs65XffOvrlwwI6UB7EkZAFOnpbonZFRyHqZjtggQu8M9NpMa LXuYL8StOOSIY12yg2fr/zcVeUR3puxA86+1rZkZZjSVM0McxJermCes/eSwG+XwemYg 9BPkra5cQFfvuPapIolLpZ3VB1HogvSlTQwZE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MGxxK9z7gZnvqPy6mQ7Yj0gd0XPRMc5sGdILtK3O0/M=; b=if2PrxaKWRNQCtP5CDElYAXwUDS/UahqrqsvVjgAFvsO7tFOUZ3aefcsyn0zcijreD 8bsV+6SthmBtw/0YUknETgXcqC/cQF4z3M8gFZCNW67eDcz7Vjshqougw+7ER4N35IHx NdziGd6kxedUdA/arW/ovC2vmMtFXU2+dHTtW03gPRKe6JH/jylHofTC6xRWoQsIzgN4 V/mGov6nLSKJl/itjzpDpGpVXtQCDQaqbhdxKdS6lBHeXNLI5wS0pi3wJujzzs7+9lfO Ci2POwe/Ny5cdWcClK0h0HpcHAzmSQlWzgYrMUVUlYOGPHdS0wyKbc3LLiN2zIEylpZb aQAQ== X-Gm-Message-State: AMCzsaXUbVznalg/vLRDBM8brhaKz5g6Z2y636x6N2OjgE6Q+mKlGRdN C28U1IEl8eNM6hMgUYz2gSkJVg== X-Received: by 10.223.161.79 with SMTP id r15mr5071814wrr.247.1509312297543; Sun, 29 Oct 2017 14:24:57 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:57 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Matt Redfearn Subject: [PATCH 15/17] clocksource/drivers/mips-gic-timer: Remove pointless irq_save, restore Date: Sun, 29 Oct 2017 22:20:32 +0100 Message-Id: <1509312035-17368-15-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matt Redfearn The function gic_next_event is always called with interrupts disabled, so the local_irq_save / local_irq_restore are pointless - remove them. [Daniel Lezcano: Fixed warning by removing unused variable 'flags'] Signed-off-by: Matt Redfearn Suggested-by: Daniel Lezcano Reported-by: Thomas Gleixner Signed-off-by: Daniel Lezcano --- drivers/clocksource/mips-gic-timer.c | 3 --- 1 file changed, 3 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index ae3167c..775dea0 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -39,16 +39,13 @@ static u64 notrace gic_read_count(void) static int gic_next_event(unsigned long delta, struct clock_event_device *evt) { - unsigned long flags; u64 cnt; int res; cnt = gic_read_count(); cnt += (u64)delta; - local_irq_save(flags); write_gic_vl_other(mips_cm_vp_id(cpumask_first(evt->cpumask))); write_gic_vo_compare(cnt); - local_irq_restore(flags); res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; return res; } From patchwork Sun Oct 29 21:20:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117425 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853957qgn; Sun, 29 Oct 2017 14:25:06 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Rc3hYewN5n0/aJvbIZDdkH0b4vbkDAQS+U80nF792qbcnLxDRjnQ6bmbbD4dRsf5+FGFza X-Received: by 10.159.207.147 with SMTP id z19mr5490620plo.441.1509312305913; Sun, 29 Oct 2017 14:25:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312305; cv=none; d=google.com; s=arc-20160816; b=AS2viLe/m/cRX1pTkfqTo4pKBuvVYoT+prNrqVAAzCO1nUwr5ScMVxNDLBVCM+KXJE 120pSSZpsIoUU0tPjQgPUoGs75ee38juGYXX64KBwmWthjyPlsRcizUdGAsQjZm/7E+4 XccTdApD/bCzdI2e5+UARuoLQW2N5zq0SCM8qn1lAGuLGY49oIGf3JtGtVXhHtogG62q zvBiWCufMAUyCjHD9vTkymVjpsfgtp8A0YeXbhqR830J0EtNYzw5JCCda64vZp+TINk+ 5d9yW0am+7SpChxdmr0yQFq6wEOGFu+Xec5kGERo9I+/uLa84qXF2879b1TIr7xBqTld aa8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5S1uUXHbe+0/SB0Ecjm3ZzYvS+YgR0TJPCoWrlOIANQ=; b=Dh0ci65XN6b0SvdodS81sw2wsP7XPGn80/nVXk+k0vmA9f6rN0Ze8hB6nNO31mX8k5 Q1d+CvBYQmPUrkYfyf1sla5p/zM9RVnnGrYgudcfEumIgur31eCk5WEM4DfpWsX3UarX zJ6Lx3UkpkjRv9UxW+qNde31zNEsAhksDJcB/6srTkchBUxvgL0BqZKsL+acCkOl2+HW cbUx4LIFDFnaeBZLgSKXjmP8Xd9WllXATOX5K6o2Rcp2AVFVL0NtSZfMdJiybedDw83N Nvu2mcNrR2iGfH1lOBqPoNJtTATBQG/PiU9li83x0JdxRxOC63gbCiJ4V7aSu08UwGIz kffw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JYfcZYWo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s83si9336457pfg.506.2017.10.29.14.25.05; Sun, 29 Oct 2017 14:25:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JYfcZYWo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932400AbdJ2VZC (ORCPT + 27 others); Sun, 29 Oct 2017 17:25:02 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:54614 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932342AbdJ2VZA (ORCPT ); Sun, 29 Oct 2017 17:25:00 -0400 Received: by mail-wr0-f196.google.com with SMTP id o44so10683132wrf.11 for ; Sun, 29 Oct 2017 14:24:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5S1uUXHbe+0/SB0Ecjm3ZzYvS+YgR0TJPCoWrlOIANQ=; b=JYfcZYWoWsH8vb6rHbJ9eBJLjfB6KdfmhDkNrvCSAqz24HnVAg/qZTSXKhTIqCBEgA 9NtKbWcFxIKLXM17XxnKZjcXfbhsjNpWztfLLCsGmgnCPjAwMQoSv3uZYsCE+SYy3vpJ eeWnNkXfgkh8I3vIHee0hZp84TRwderk9Mn3w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5S1uUXHbe+0/SB0Ecjm3ZzYvS+YgR0TJPCoWrlOIANQ=; b=Y6KAdPLPHTDUcd5kf4TUVklWIACUbBnexfyby+SuCvk72vAC2HLPpA+FdXR+7Oqzln OJL4JX/TpU3IoESnSCdQDexAJalL+HGwI3FusjAhIZQpE7QHrxo8B9wz5pQDW3MVXHZx g4okoP5KKgO3oo7iITLLmf1nMj9REOqCUfOGWT0B/hgQQk4nXOA6aXHJAQWZyZZ/RbHf 7m9jdXe64NElqgfcNsnojy/Q+nv+aA75NuvTVt4VsdZPpxFCRiP9HDbJQbivPrkWmiIJ RRX7boa6CHToIsYHtWsdpzviGIGb4PXnpmIJDZ2dIAGGxUe6mGtUWbQqsrjqbq2YwhjM BpNw== X-Gm-Message-State: AMCzsaUSzAByIbNY44JXWDy9xYKU8Yy7QEzV4daUVEqKnOUk+/EBKNrq jJ6/ORu7w7QXUqgRypNhlN67dg== X-Received: by 10.223.184.230 with SMTP id c35mr5597965wrg.18.1509312298904; Sun, 29 Oct 2017 14:24:58 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:58 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Matt Redfearn Subject: [PATCH 16/17] clocksource/drivers/mips-gic-timer: Add fastpath for local timer updates Date: Sun, 29 Oct 2017 22:20:33 +0100 Message-Id: <1509312035-17368-16-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matt Redfearn Always accessing the compare register via the CM redirect region is (relatively) slow. If the timer being updated is the current CPUs then this can be shortcutted by writing to the CM VP local region. Signed-off-by: Matt Redfearn Signed-off-by: Daniel Lezcano --- drivers/clocksource/mips-gic-timer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 775dea0..a04808a 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -39,13 +39,18 @@ static u64 notrace gic_read_count(void) static int gic_next_event(unsigned long delta, struct clock_event_device *evt) { + int cpu = cpumask_first(evt->cpumask); u64 cnt; int res; cnt = gic_read_count(); cnt += (u64)delta; - write_gic_vl_other(mips_cm_vp_id(cpumask_first(evt->cpumask))); - write_gic_vo_compare(cnt); + if (cpu == raw_smp_processor_id()) { + write_gic_vl_compare(cnt); + } else { + write_gic_vl_other(mips_cm_vp_id(cpu)); + write_gic_vo_compare(cnt); + } res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; return res; } From patchwork Sun Oct 29 21:20:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117426 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1854116qgn; Sun, 29 Oct 2017 14:25:20 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QrDlUuMufWpMWqEj7Kr2Zho2Gc99rKKe2ymCtaAkK/+FEdsFGZyfYJjdw9slcppHUAz3qu X-Received: by 10.98.217.2 with SMTP id s2mr6741426pfg.298.1509312320792; Sun, 29 Oct 2017 14:25:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312320; cv=none; d=google.com; s=arc-20160816; b=EmYOgRtzyCpgconylGzVcMdzHorDwlrGDCPpR0HOq9cmi26TmBOgKLGaNDX8bgo6vJ FWeHGVxWQ0d8gb4pnVm4s0Ez0Yiigt06rmVbO2I/lLenK3vH18ZEUL0cCsKseOMzWO3B Oc/qfjsoPNBC+Gd2UCEgO9UlMZtI4rd7m70PLiAHziyWlWdPVXx9NtSYHH2eYwMTd4qR Db8v6DkA6hJNvS/BWS8IJGhlEwGb9pldEkbiIdgpXPlpztLxUlWLycZn+Kg26g6waueN jQWQ6sgO0MM9pd4jIfgiLRlb7LDo+dJMwAYjYRFaX7iAilWKMR+v/NiWN7wzlAjA8ddT dQSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=hYdPsu97qH6V+e4dz9c/3xKmmJE4+9WCmAKlWKNZGvI=; b=b+nckezNz1Crdni8JjVgsX/p3Hndp+IimUxUsFghvCFQfXZXMMUY3y+qUNpGiqsxv8 uQyBSmdJElTJ4EQr4l4ZsO+lv9zOHyLg6KyNtIZOeA6o0BsMYzNAJQPKi7CtZxM1a8lR Tgw0Tq78BhUWCPe/uu7z6bs/MRaUDiUGqGzyagCDL/oed5dzVfYAUm6AifdouP7VBPAY KUs2rULfZhV2MCKzfqVJvjGAjaItRb6JDbcS56SvJIJNw72SZp+RWdC/VocAnUVxnTrz Tv7pjuFPotl2qPRtVRX0FEf8fwo9/db4vUuC+a7rBI+7SUOSbG44D/ZDLKdJMxfmoIA5 TBEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RFBYrCl0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x136si8512975pgx.750.2017.10.29.14.25.20; Sun, 29 Oct 2017 14:25:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RFBYrCl0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932415AbdJ2VZT (ORCPT + 27 others); Sun, 29 Oct 2017 17:25:19 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:47074 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932381AbdJ2VZB (ORCPT ); Sun, 29 Oct 2017 17:25:01 -0400 Received: by mail-wr0-f194.google.com with SMTP id l1so10718226wrc.3 for ; Sun, 29 Oct 2017 14:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hYdPsu97qH6V+e4dz9c/3xKmmJE4+9WCmAKlWKNZGvI=; b=RFBYrCl00Y/XYZCFgrnUijp7BTRu0ooYHkrOoRR3j4AQ57xD4D0LBzeP0vqd+KXgiT gR8abilanQDlu4+JddrTaMlcaWs0cIstWEc2rPc+FIKACT8hqfsQQuwSdFSXOBtbXG9S uxKY99y86d4nNe9CBtSxicdTTH55L7zclSb2g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hYdPsu97qH6V+e4dz9c/3xKmmJE4+9WCmAKlWKNZGvI=; b=KK4t2QTqQc+OdzVT0I4Vcad4TuH/FR7gCQj2gOmVNlEP0iO0SuAjWTBnzdfnUAiwlC 1dwJIld2s0Ac/FnJt8gfzM9i1o1L5R+z44zaKvn+nyznfgmfWq8c9airpVgiNKER3nh1 KIyRnfswmJn5eHaTHrDjfTOZODJbR7C9HmFi0s/gd9U7w6TLELxrfjP8btBbmZErxr+G MyTvuv0TKYOPfLcXjrkm4WxeCaCSpSz73XFvHaJM1Q1iOd44+pGWEh31fcNGkhbBvbSC qVnW8GAZkW7c0BCfb3p1U7kupgyRHhwc9mMlCuRNNAUhc/sriqaBAg+K693IgmxxXd0c ggiA== X-Gm-Message-State: AMCzsaVQSyA/ILSE7Gic1dgLtwpWV5emVtgtjWHFpZJ6Hm2UqMmTOOv9 mz4GgHf5iw3aqFvZyGcLN3zm3mT5ZOk= X-Received: by 10.223.197.141 with SMTP id m13mr6111920wrg.203.1509312300335; Sun, 29 Oct 2017 14:25:00 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:59 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH 17/17] clocksource/drivers/timer-of: Add timer_of_exit function Date: Sun, 29 Oct 2017 22:20:34 +0100 Message-Id: <1509312035-17368-17-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The timer-of API does not provide a function to undo what has been done by the timer_of_init() function. Add a timer_of_exit() function. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-of.c | 12 ++++++++++++ drivers/clocksource/timer-of.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index c79122d..7c64a5c1 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -176,3 +176,15 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) timer_base_exit(&to->of_base); return ret; } + +void timer_of_exit(struct timer_of *to) +{ + if (to->flags & TIMER_OF_IRQ) + timer_irq_exit(&to->of_irq); + + if (to->flags & TIMER_OF_CLOCK) + timer_clk_exit(&to->of_clk); + + if (to->flags & TIMER_OF_BASE) + timer_base_exit(&to->of_base); +} diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h index e0d7272..44f57e0 100644 --- a/drivers/clocksource/timer-of.h +++ b/drivers/clocksource/timer-of.h @@ -66,4 +66,7 @@ static inline unsigned long timer_of_period(struct timer_of *to) extern int __init timer_of_init(struct device_node *np, struct timer_of *to); + +extern void timer_of_exit(struct timer_of *to); + #endif