From patchwork Thu Feb 23 01:57:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 94366 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp17920qgi; Wed, 22 Feb 2017 18:00:12 -0800 (PST) X-Received: by 10.98.209.16 with SMTP id z16mr43186333pfg.139.1487815212284; Wed, 22 Feb 2017 18:00:12 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si2796229pgc.350.2017.02.22.18.00.12; Wed, 22 Feb 2017 18:00:12 -0800 (PST) Received-SPF: temperror (google.com: error in processing during lookup of devicetree-owner@vger.kernel.org: DNS error) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=temperror (google.com: error in processing during lookup of devicetree-owner@vger.kernel.org: DNS error) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932465AbdBWB7v (ORCPT + 7 others); Wed, 22 Feb 2017 20:59:51 -0500 Received: from mail-pf0-f174.google.com ([209.85.192.174]:34042 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934208AbdBWB7q (ORCPT ); Wed, 22 Feb 2017 20:59:46 -0500 Received: by mail-pf0-f174.google.com with SMTP id p185so1311031pfb.1 for ; Wed, 22 Feb 2017 17:59:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=sCrDMeK0074weCwVbySmoKPIGbbHDITWig/YIfboOOI=; b=HVC2CPZmhT5WFwP3XIiQQRAMQu/8kXTiWdRemr8MjhMVks23YXlWNzPudBGlPBoOJc YmLg6gk04p3K0UtvnUkqhePoturLjVc6IRF1beAV2gD6H3oj0+D4c/HqTYW6zQpU2MB1 +AWhM4KukYsBfiF053wEDFxQIJvWn6TRYLeuI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=sCrDMeK0074weCwVbySmoKPIGbbHDITWig/YIfboOOI=; b=TFqJ6Khd3f3fXTE+Mszz2bdJjoq9XIwgZAm4uIDAR6QwqvmaI7hX+lSzFP/ii2F+qW 9Bc6jnFSFh+hMW0XiFb2m8wE+Zjn3a+iLrqMp0gav0Eznlr5FFdBTcETmZ0cEY+Q9MWE MBIH2cdGpkpZMlngLaIQRB5K0UwTcbFMhHWCmKwfM2iD8riA6/3Uj8yi7Ev8TYPD9FvC Uhfz/xRR7iliVdGmsjjRrAKvIOerF+/pLstrGQNLfqQyFBmfuwMODXHkFr2opwDsjERP DBJvfCbw1yQS74OwmkeYOYAusiBDym61mIj5/aRRt35jRD6f917RYTbir/CRSpvdczA8 umQQ== X-Gm-Message-State: AMke39lhbp2qpDMfovWv7wBgUFWJ696KzHi8r8wI3h0/WvGS7NU9FPn8VB2g0edyScO7FwlG X-Received: by 10.99.215.5 with SMTP id d5mr46122276pgg.51.1487815185641; Wed, 22 Feb 2017 17:59:45 -0800 (PST) Received: from localhost.localdomain ([103.192.224.50]) by smtp.gmail.com with ESMTPSA id y67sm5830689pfa.96.2017.02.22.17.59.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Feb 2017 17:59:44 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Mathieu Poirier , Leo Yan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Subject: [PATCH v1 1/2] coresight: bindings for debug module Date: Thu, 23 Feb 2017 09:57:46 +0800 Message-Id: <1487815067-27511-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> References: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to two clocks, one is apb clock for bus and another is debug clock for debug module self; and also need specify the CPU node which the debug module is dedicated to specific CPU. Signed-off-by: Leo Yan --- .../devicetree/bindings/arm/coresight-debug.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/coresight-debug.txt b/Documentation/devicetree/bindings/arm/coresight-debug.txt new file mode 100644 index 0000000..6e03e9b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-debug.txt @@ -0,0 +1,39 @@ +* CoreSight Debug Component: + +CoreSight debug component are compliant with the ARMv8 architecture reference +manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The external debug +module is mainly used for two modes: self-hosted debug and external debug, and +it can be accessed from mmio region from Coresight and eventually the debug +module connects with CPU for debugging. And the debug module provides +sample-based profiling extension, which can be used to sample CPU program +counter, secure state and exception level, etc; usually every CPU has one +dedicated debug module to be connected. + +Required properties: + +- compatible : should be + * "arm,coresight-debug", "arm,primecell"; supplemented with + "arm,primecell" as driver is using the AMBA bus interface. + +- reg : physical base address and length of the register set. + +- clocks : the clocks associated to this component. + +- clock-names : the name of the clocks referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk", and the debug module + has an additional clock "dbg_clk", which is used to provide + clock for debug module itself. Both clocks are mandatory. + +- cpu : the cpu phandle the debug module is affined to. When omitted + the source is considered to belong to CPU0. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_CS_ATB>, <&acpu_ctrl HI6220_ACPU_DBG_CLK0>; + clock-names = "apb_pclk", "dbg_clk"; + cpu = <&cpu0>; + }; From patchwork Thu Feb 23 01:57:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 94367 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp17926qgi; Wed, 22 Feb 2017 18:00:13 -0800 (PST) X-Received: by 10.84.232.67 with SMTP id f3mr51134887pln.55.1487815213079; Wed, 22 Feb 2017 18:00:13 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si2796229pgc.350.2017.02.22.18.00.12; Wed, 22 Feb 2017 18:00:13 -0800 (PST) Received-SPF: temperror (google.com: error in processing during lookup of devicetree-owner@vger.kernel.org: DNS error) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=temperror (google.com: error in processing during lookup of devicetree-owner@vger.kernel.org: DNS error) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934580AbdBWCAD (ORCPT + 7 others); Wed, 22 Feb 2017 21:00:03 -0500 Received: from mail-pg0-f46.google.com ([74.125.83.46]:36626 "EHLO mail-pg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934551AbdBWB76 (ORCPT ); Wed, 22 Feb 2017 20:59:58 -0500 Received: by mail-pg0-f46.google.com with SMTP id s67so8304692pgb.3 for ; Wed, 22 Feb 2017 17:59:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=ffufPPb9jFW35XMbC2TMPu7yepuq4mawmHwKVdnpPSs=; b=HjibvaGJHw0VKWlbsTLMa/aSUE0LYeF8FgdVFeiWjmxdqHBOicFRm1PXEySjBYlDoq F1jeXSVCRLBbRyoqOtpV7MKz478WwsUrL0ggeSWvYMI9lxmMsVrgYAuY4JvZnNHQgVbM g+E0MjX0vb2o9jaZvWGgKif0pLQyXgnYb2WMM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=ffufPPb9jFW35XMbC2TMPu7yepuq4mawmHwKVdnpPSs=; b=eseH9SKM6REvI+OzH4yitrj1inbljF9C5OHPio0J4VZMxDy4u01KRu+DuwkVeFWqm1 4HgH1q0+w4JTFM9yQLeqX6YgqyflZVCZ3bBhtfMn8i3ikrCvVx1aQbsRasjmxMSfKKUH 6HZuzGGj64MILFI/eu9ABV2vb8++NGIqO9YuPWTfjgvzOLjcSfzHOxpREkmInJecMG8a QqaxR5uW/eFkia6gzIxhc8BrAIoE+gRUkEb14gU3rqDeens7PQ7tLB6juYu/K9OOOo1O DrySJzjwJ9gQHLiDYqBd8tTweGbLQ+T7BYKnUJKpJ/Rg7HkQbQ4zvi5P6deT/mYXdCv7 z2MQ== X-Gm-Message-State: AMke39mferCudYfIPblQneLaNt6hEII6mal6zmDdqB7MRP8VEBPYvKDwBHE4isrrjJSz1G9R X-Received: by 10.98.84.193 with SMTP id i184mr43271986pfb.27.1487815191787; Wed, 22 Feb 2017 17:59:51 -0800 (PST) Received: from localhost.localdomain ([103.192.224.50]) by smtp.gmail.com with ESMTPSA id y67sm5830689pfa.96.2017.02.22.17.59.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Feb 2017 17:59:50 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Mathieu Poirier , Leo Yan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Subject: [PATCH v1 2/2] coresight: add support for debug module Date: Thu, 23 Feb 2017 09:57:47 +0800 Message-Id: <1487815067-27511-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> References: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Coresight includes debug module and usually the module connects with CPU debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has description for related info in "Part H: External Debug". Chapter H7 "The Sample-based Profiling Extension" introduces several sampling registers, e.g. we can check program counter value with combined CPU exception level, secure state, etc. So this is helpful for analysis CPU lockup scenarios, e.g. if one CPU has run into infinite loop with IRQ disabled. In this case the CPU cannot switch context and handle any interrupt (including IPIs), as the result it cannot handle SMP call for stack dump. This patch is to enable coresight debug module, so firstly this driver is to enable clocks for debug module and this is to ensure the debug module can be accessed from program or external debugger. And the driver uses sample-based registers for debug purpose, e.g. when system detects the CPU lockup and trigger panic, the driver will dump program counter and combined context registers (EDCIDSR, EDVIDSR); by parsing context registers so can quickly get to know CPU secure state, exception level, etc. Some of the debug module registers are located in CPU power domain, so in the driver it has checked the power state for CPU before accessing registers within CPU power domain. For most safe way to use this driver, it's suggested to disable CPU low power states, this can simply set "nohlt" in kernel command line. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/Kconfig | 10 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-debug.c | 396 ++++++++++++++++++++++++++ 3 files changed, 407 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-debug.c -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 130cb21..2c8883b 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -89,4 +89,14 @@ config CORESIGHT_STM logging useful software events or data coming from various entities in the system, possibly running different OSs +config CORESIGHT_DEBUG + bool "CoreSight debug driver" + depends on ARM || ARM64 + help + This driver provides support for coresight debugging module. This + is primarily used to dump sample-based profiling registers for + panic. By disable CPU low power states (like "nohlt" in kernel + command line), this is more safe and avoid lockup issue when + access debug module registers. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index af480d9..d540d45 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ coresight-etm4x-sysfs.o obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o +obj-$(CONFIG_CORESIGHT_DEBUG) += coresight-debug.o diff --git a/drivers/hwtracing/coresight/coresight-debug.c b/drivers/hwtracing/coresight/coresight-debug.c new file mode 100644 index 0000000..a109fef --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-debug.c @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2017 Linaro Limited. All rights reserved. + * + * Author: Leo Yan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" + +#define EDPCSR 0x0A0 +#define EDCIDSR 0x0A4 +#define EDVIDSR 0x0A8 +#define EDPCSR_HI 0x0AC +#define EDOSLAR 0x300 +#define EDPRSR 0x314 +#define EDDEVID1 0xFC4 +#define EDDEVID 0xFC8 + +#define EDPCSR_PROHIBITED 0xFFFFFFFF + +/* bits definition for EDPCSR */ +#ifndef CONFIG_64BIT +#define EDPCSR_THUMB BIT(0) +#define EDPCSR_ARM_INST_MASK GENMASK(31, 2) +#define EDPCSR_THUMB_INST_MASK GENMASK(31, 1) +#endif + +/* bits definition for EDPRSR */ +#define EDPRSR_DLK BIT(6) +#define EDPRSR_PU BIT(0) + +/* bits definition for EDVIDSR */ +#define EDVIDSR_NS BIT(31) +#define EDVIDSR_E2 BIT(30) +#define EDVIDSR_E3 BIT(29) +#define EDVIDSR_HV BIT(28) +#define EDVIDSR_VMID GENMASK(7, 0) + +/* bits definition for EDDEVID1 */ +#define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0) +#define EDDEVID1_PCSR_OFFSET_INS_SET (0x0) +#define EDDEVID1_PCSR_NO_OFFSET (0x1) + +/* bits definition for EDDEVID */ +#define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0) +#define EDDEVID_IMPL_NONE (0x0) +#define EDDEVID_IMPL_EDPCSR_EDCIDSR (0x2) +#define EDDEVID_IMPL_FULL (0x3) + +struct debug_drvdata { + void __iomem *base; + struct device *dev; + int cpu; + struct clk *dbg_clk; + + bool edpcsr_present; + bool edvidsr_present; + bool pc_has_offset; + + u32 eddevid; + u32 eddevid1; + + u32 edpcsr; + u32 edpcsr_hi; + u32 edprsr; + u32 edvidsr; + u32 edcidsr; +}; + +static int debug_count; +static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata); + +static void debug_os_unlock(struct debug_drvdata *drvdata) +{ + /* Unlocks the debug registers */ + writel_relaxed(0x0, drvdata->base + EDOSLAR); + wmb(); +} + +/* + * According to ARM DDI 0487A.k, before access external debug + * registers should firstly check the access permission; if any + * below condition has been met then cannot access debug + * registers to avoid lockup issue: + * + * - CPU power domain is powered off; + * - The OS Double Lock is locked; + * + * By checking EDPRSR can get to know if meet these conditions. + */ +static bool debug_access_permit(struct debug_drvdata *drvdata) +{ + /* CPU is powered off */ + if (!(drvdata->edprsr & EDPRSR_PU)) + return false; + + /* The OS Double Lock is locked */ + if (drvdata->edprsr & EDPRSR_DLK) + return false; + + return true; +} + +static void debug_read_regs(struct debug_drvdata *drvdata) +{ + drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR); + + if (!debug_access_permit(drvdata)) + return; + + if (!drvdata->edpcsr_present) + return; + + CS_UNLOCK(drvdata->base); + + debug_os_unlock(drvdata); + + drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR); + + /* + * As described in ARM DDI 0487A.k, if the processing + * element (PE) is in debug state, or sample-based + * profiling is prohibited, EDPCSR reads as 0xFFFFFFFF; + * EDCIDSR, EDVIDSR and EDPCSR_HI registers also become + * UNKNOWN state. So directly bail out for this case. + */ + if (drvdata->edpcsr == EDPCSR_PROHIBITED) { + CS_LOCK(drvdata->base); + return; + } + + /* + * A read of the EDPCSR normally has the side-effect of + * indirectly writing to EDCIDSR, EDVIDSR and EDPCSR_HI; + * at this point it's safe to read value from them. + */ + drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR); +#ifdef CONFIG_64BIT + drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI); +#endif + + if (drvdata->edvidsr_present) + drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR); + + CS_LOCK(drvdata->base); +} + +#ifndef CONFIG_64BIT +static bool debug_pc_has_offset(struct debug_drvdata *drvdata) +{ + u32 pcsr_offset; + + pcsr_offset = drvdata->eddevid1 & EDDEVID1_PCSR_OFFSET_MASK; + + return (pcsr_offset == EDDEVID1_PCSR_OFFSET_INS_SET); +} + +static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata, + unsigned long pc) +{ + unsigned long arm_inst_offset = 0, thumb_inst_offset = 0; + + if (debug_pc_has_offset(drvdata)) { + arm_inst_offset = 8; + thumb_inst_offset = 4; + } + + /* Handle thumb instruction */ + if (pc & EDPCSR_THUMB) { + pc = (pc & EDPCSR_THUMB_INST_MASK) - thumb_inst_offset; + return pc; + } + + /* + * Handle arm instruction offset, if the arm instruction + * is not 4 byte alignment then it's possible the case + * for implementation defined; keep original value for this + * case and print info for notice. + */ + if (pc & BIT(1)) + pr_emerg("Instruction offset is implementation defined\n"); + else + pc = (pc & EDPCSR_ARM_INST_MASK) - arm_inst_offset; + + return pc; +} +#endif + +static void debug_dump_regs(struct debug_drvdata *drvdata) +{ + unsigned long pc; + + pr_emerg("\tEDPRSR: %08x (Power:%s DLK:%s)\n", drvdata->edprsr, + drvdata->edprsr & EDPRSR_PU ? "On" : "Off", + drvdata->edprsr & EDPRSR_DLK ? "Lock" : "Unlock"); + + if (!debug_access_permit(drvdata) || !drvdata->edpcsr_present) { + pr_emerg("No permission to access debug registers!\n"); + return; + } + + if (drvdata->edpcsr == EDPCSR_PROHIBITED) { + pr_emerg("CPU is in Debug state or profiling is prohibited!\n"); + return; + } + +#ifdef CONFIG_64BIT + pc = (unsigned long)drvdata->edpcsr_hi << 32 | + (unsigned long)drvdata->edpcsr; +#else + pc = debug_adjust_pc(drvdata, (unsigned long)drvdata->edpcsr); +#endif + + pr_emerg("\tEDPCSR: [<%p>] %pS\n", (void *)pc, (void *)pc); + pr_emerg("\tEDCIDSR: %08x\n", drvdata->edcidsr); + + if (!drvdata->edvidsr_present) + return; + + pr_emerg("\tEDVIDSR: %08x (State:%s Mode:%s Width:%s VMID:%x)\n", + drvdata->edvidsr, + drvdata->edvidsr & EDVIDSR_NS ? "Non-secure" : "Secure", + drvdata->edvidsr & EDVIDSR_E3 ? "EL3" : + (drvdata->edvidsr & EDVIDSR_E2 ? "EL2" : "EL1/0"), + drvdata->edvidsr & EDVIDSR_HV ? "64bits" : "32bits", + drvdata->edvidsr & (u32)EDVIDSR_VMID); +} + +/* + * Dump out information on panic. + */ +static int debug_notifier_call(struct notifier_block *self, + unsigned long v, void *p) +{ + int cpu; + + pr_emerg("ARM external debug module:\n"); + + for_each_possible_cpu(cpu) { + + if (!per_cpu(debug_drvdata, cpu)) + continue; + + pr_emerg("CPU[%d]:\n", per_cpu(debug_drvdata, cpu)->cpu); + + debug_read_regs(per_cpu(debug_drvdata, cpu)); + debug_dump_regs(per_cpu(debug_drvdata, cpu)); + } + + return 0; +} + +static struct notifier_block debug_notifier = { + .notifier_call = debug_notifier_call, +}; + +static void debug_init_arch_data(void *info) +{ + struct debug_drvdata *drvdata = info; + u32 mode; + + CS_UNLOCK(drvdata->base); + + debug_os_unlock(drvdata); + + /* Read device info */ + drvdata->eddevid = readl_relaxed(drvdata->base + EDDEVID); + drvdata->eddevid1 = readl_relaxed(drvdata->base + EDDEVID1); + + /* Parse implementation feature */ + mode = drvdata->eddevid & EDDEVID_PCSAMPLE_MODE; + if (mode == EDDEVID_IMPL_FULL) { + drvdata->edpcsr_present = true; + drvdata->edvidsr_present = true; + } else if (mode == EDDEVID_IMPL_EDPCSR_EDCIDSR) { + drvdata->edpcsr_present = true; + drvdata->edvidsr_present = false; + } else { + drvdata->edpcsr_present = false; + drvdata->edvidsr_present = false; + } + + CS_LOCK(drvdata->base); +} + +static int debug_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + void __iomem *base; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata = NULL; + struct debug_drvdata *drvdata; + struct resource *res = &adev->res; + struct device_node *np = adev->dev.of_node; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + if (np) { + pdata = of_get_coresight_platform_data(dev, np); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + } + + drvdata->dev = &adev->dev; + drvdata->dbg_clk = devm_clk_get(&adev->dev, "dbg_clk"); + if (IS_ERR(drvdata->dbg_clk)) { + dev_err(dev, "debug clock initialization failed.\n"); + return PTR_ERR(drvdata->dbg_clk); + } + + ret = clk_prepare_enable(drvdata->dbg_clk); + if (ret) + return ret; + + dev_set_drvdata(dev, drvdata); + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + drvdata->cpu = pdata ? pdata->cpu : 0; + + get_online_cpus(); + per_cpu(debug_drvdata, drvdata->cpu) = drvdata; + + if (smp_call_function_single(drvdata->cpu, + debug_init_arch_data, drvdata, 1)) + dev_err(dev, "Debug arch init failed\n"); + + if (!debug_count++) + atomic_notifier_chain_register(&panic_notifier_list, + &debug_notifier); + put_online_cpus(); + + dev_info(dev, "%s initialized\n", (char *)id->data); + return 0; +} + +static struct amba_id debug_ids[] = { + { /* Debug for Cortex-A53 */ + .id = 0x000bbd03, + .mask = 0x000fffff, + .data = "debug", + }, + { /* Debug for Cortex-A57 */ + .id = 0x000bbd07, + .mask = 0x000fffff, + .data = "debug", + }, + { /* Debug for Cortex-A72 */ + .id = 0x000bbd08, + .mask = 0x000fffff, + .data = "debug", + }, + { 0, 0}, +}; + +static struct amba_driver debug_driver = { + .drv = { + .name = "coresight-debug", + .suppress_bind_attrs = true, + }, + .probe = debug_probe, + .id_table = debug_ids, +}; +builtin_amba_driver(debug_driver);