From patchwork Wed Sep 30 14:55:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40728C4727C for ; Wed, 30 Sep 2020 15:01:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4F532076B for ; Wed, 30 Sep 2020 15:01:32 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Wed, 30 Sep 2020 14:55:33 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id BD1C35C1C4; Wed, 30 Sep 2020 14:55:30 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 01/20] softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag) Date: Wed, 30 Sep 2020 16:55:04 +0200 Message-Id: <20200930145523.71087-2-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , David Hildenbrand , Cornelia Huck , Richard Henderson , qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Implementation inspired by minmax_floats(). Unfortuantely, we don't have any tests we can simply adjust/unlock. Cc: Aurelien Jarno Cc: Peter Maydell Cc: "Alex Bennée" Signed-off-by: David Hildenbrand Signed-off-by: David Hildenbrand --- fpu/softfloat.c | 100 ++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 6 +++ 2 files changed, 106 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9af75b9146..9463c5ea56 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -621,6 +621,8 @@ static inline FloatParts float64_unpack_raw(float64 f) return unpack_raw(float64_params, f); } +static void float128_unpack(FloatParts128 *p, float128 a, float_status *status); + /* Pack a float from parts, but do not canonicalize. */ static inline uint64_t pack_raw(FloatFmt fmt, FloatParts p) { @@ -3180,6 +3182,89 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, } } +static float128 float128_minmax(float128 a, float128 b, bool ismin, bool ieee, + bool ismag, float_status *s) +{ + FloatParts128 pa, pb; + int a_exp, b_exp; + bool a_less; + + float128_unpack(&pa, a, s); + float128_unpack(&pb, b, s); + + if (unlikely(is_nan(pa.cls) || is_nan(pb.cls))) { + /* See comment in minmax_floats() */ + if (ieee && !is_snan(pa.cls) && !is_snan(pb.cls)) { + if (is_nan(pa.cls) && !is_nan(pb.cls)) { + return b; + } else if (is_nan(pb.cls) && !is_nan(pa.cls)) { + return a; + } + } + + /* Similar logic to pick_nan(), avoiding re-packing. */ + if (is_snan(pa.cls) || is_snan(pb.cls)) { + s->float_exception_flags |= float_flag_invalid; + } + if (s->default_nan_mode) { + return float128_default_nan(s); + } + if (pickNaN(pa.cls, pb.cls, + pa.frac0 > pb.frac0 || + (pa.frac0 == pb.frac0 && pa.frac1 > pb.frac1) || + (pa.frac0 == pb.frac0 && pa.frac1 == pb.frac1 && + pa.sign < pb.sign), s)) { + return is_snan(pb.cls) ? float128_silence_nan(b, s) : b; + } + return is_snan(pa.cls) ? float128_silence_nan(a, s) : a; + } + + switch (pa.cls) { + case float_class_normal: + a_exp = pa.exp; + break; + case float_class_inf: + a_exp = INT_MAX; + break; + case float_class_zero: + a_exp = INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + switch (pb.cls) { + case float_class_normal: + b_exp = pb.exp; + break; + case float_class_inf: + b_exp = INT_MAX; + break; + case float_class_zero: + b_exp = INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + + a_less = a_exp < b_exp; + if (a_exp == b_exp) { + a_less = pa.frac0 < pb.frac0; + if (pa.frac0 == pb.frac0) { + a_less = pa.frac1 < pb.frac1; + } + } + + if (ismag && + (a_exp != b_exp || pa.frac0 != pb.frac0 || pa.frac1 != pb.frac1)) { + return a_less ^ ismin ? b : a; + } else if (pa.sign == pb.sign) { + return pa.sign ^ a_less ^ ismin ? b : a; + } + return pa.sign ^ ismin ? b : a; +} + #define MINMAX(sz, name, ismin, isiee, ismag) \ float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ @@ -3214,6 +3299,21 @@ MINMAX(64, maxnummag, false, true, true) #undef MINMAX +#define F128_MINMAX(name, ismin, isiee, ismag) \ +float128 float128_ ## name(float128 a, float128 b, float_status *s) \ +{ \ + return float128_minmax(a, b, ismin, isiee, ismag, s); \ +} + +F128_MINMAX(min, true, false, false) +F128_MINMAX(minnum, true, true, false) +F128_MINMAX(minnummag, true, true, true) +F128_MINMAX(max, false, false, false) +F128_MINMAX(maxnum, false, true, false) +F128_MINMAX(maxnummag, false, true, true) + +#undef F128_MINMAX + #define BF16_MINMAX(name, ismin, isiee, ismag) \ bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ { \ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a38433deb4..4fab2ef6f4 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1201,6 +1201,12 @@ float128 float128_muladd(float128, float128, float128, int, float128 float128_sqrt(float128, float_status *status); FloatRelation float128_compare(float128, float128, float_status *status); FloatRelation float128_compare_quiet(float128, float128, float_status *status); +float128 float128_min(float128, float128, float_status *status); +float128 float128_max(float128, float128, float_status *status); +float128 float128_minnum(float128, float128, float_status *status); +float128 float128_maxnum(float128, float128, float_status *status); +float128 float128_minnummag(float128, float128, float_status *status); +float128 float128_maxnummag(float128, float128, float_status *status); bool float128_is_quiet_nan(float128, float_status *status); bool float128_is_signaling_nan(float128, float_status *status); float128 float128_silence_nan(float128, float_status *status); From patchwork Wed Sep 30 14:55:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96F0EC4727E for ; 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Wed, 30 Sep 2020 10:55:36 -0400 X-MC-Unique: cvUnMh92MDO_8970faxAWw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 316CB10BBEC3; Wed, 30 Sep 2020 14:55:35 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6B6485C1D0; Wed, 30 Sep 2020 14:55:33 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 02/20] s390x/tcg: Implement VECTOR BIT PERMUTE Date: Wed, 30 Sep 2020 16:55:05 +0200 Message-Id: <20200930145523.71087-3-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:31:59 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 ++ target/s390x/translate_vx.c.inc | 8 ++++++++ target/s390x/vec_helper.c | 22 ++++++++++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 55bd1551e6..f579fd38a7 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -126,6 +126,7 @@ DEF_HELPER_FLAGS_1(stck, TCG_CALL_NO_RWG_SE, i64, env) DEF_HELPER_FLAGS_3(probe_write_access, TCG_CALL_NO_WG, void, env, i64, i64) /* === Vector Support Instructions === */ +DEF_HELPER_FLAGS_4(gvec_vbperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(vll, TCG_CALL_NO_WG, void, env, ptr, i64, i64) DEF_HELPER_FLAGS_4(gvec_vpk16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vpk32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index d3bcdfd67b..b55cb44f60 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -989,6 +989,8 @@ /* === Vector Support Instructions === */ +/* VECTOR BIT PERMUTE */ + E(0xe785, VBPERM, VRR_c, VE, 0, 0, 0, 0, vbperm, 0, 0, IF_VEC) /* VECTOR GATHER ELEMENT */ E(0xe713, VGEF, VRV, V, la2, 0, 0, 0, vge, 0, ES_32, IF_VEC) E(0xe712, VGEG, VRV, V, la2, 0, 0, 0, vge, 0, ES_64, IF_VEC) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index eb767f5288..44f54a79f4 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -327,6 +327,14 @@ static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_temp_free_i64(bh); } +static DisasJumpType op_vbperm(DisasContext *s, DisasOps *o) +{ + gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), get_field(s, v3), 0, + gen_helper_gvec_vbperm); + + return DISAS_NEXT; +} + static DisasJumpType op_vge(DisasContext *s, DisasOps *o) { const uint8_t es = s->insn->data; diff --git a/target/s390x/vec_helper.c b/target/s390x/vec_helper.c index 986e7cc825..7d9843f37f 100644 --- a/target/s390x/vec_helper.c +++ b/target/s390x/vec_helper.c @@ -19,6 +19,28 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3, + uint32_t desc) +{ + S390Vector tmp = {}; + uint16_t result = 0; + int i; + + for (i = 0; i < 16; i++) { + const uint8_t bit_nr = s390_vec_read_element8(v3, i); + uint16_t bit; + + if (bit_nr >= 128) { + continue; + } + bit = !!(s390_vec_read_element8(v2, bit_nr / 8) & + (0x80 >> (bit_nr % 8))); + result |= (bit << (15 - i)); + } + s390_vec_write_element16(&tmp, 3, result); + *(S390Vector *)v1 = tmp; +} + void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes) { if (likely(bytes >= 16)) { From patchwork Wed Sep 30 14:55:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 548D8C4727E for ; Wed, 30 Sep 2020 14:57:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8D3C206FC for ; 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Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- target/s390x/insn-data.def | 2 ++ target/s390x/translate_vx.c.inc | 52 +++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index b55cb44f60..da7fe6f21c 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1151,6 +1151,8 @@ F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC) /* VECTOR MULTIPLY LOGICAL ODD */ F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC) +/* VECTOR MULTIPLY SUM LOGICAL */ + F(0xe7b8, VMSL, VRR_d, VE, 0, 0, 0, 0, vmsl, 0, IF_VEC) /* VECTOR NAND */ F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC) /* VECTOR NOR */ diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 44f54a79f4..4c1b430013 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -1779,6 +1779,58 @@ static DisasJumpType op_vm(DisasContext *s, DisasOps *o) return DISAS_NEXT; } +static DisasJumpType op_vmsl(DisasContext *s, DisasOps *o) +{ + TCGv_i64 l1, h1, l2, h2; + + if (get_field(s, m4) != ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + l1 = tcg_temp_new_i64(); + h1 = tcg_temp_new_i64(); + l2 = tcg_temp_new_i64(); + h2 = tcg_temp_new_i64(); + + /* Multipy both even elements from v2 and v3 */ + read_vec_element_i64(l1, get_field(s, v2), 0, ES_64); + read_vec_element_i64(h1, get_field(s, v3), 0, ES_64); + tcg_gen_mulu2_i64(l1, h1, l1, h1); + /* Shift result left by one bit if requested */ + if (extract32(get_field(s, m6), 3, 1)) { + tcg_gen_extract2_i64(h1, l1, h1, 63); + tcg_gen_shli_i64(l1, l1, 1); + } + + /* Multipy both odd elements from v2 and v3 */ + read_vec_element_i64(l2, get_field(s, v2), 1, ES_64); + read_vec_element_i64(h2, get_field(s, v3), 1, ES_64); + tcg_gen_mulu2_i64(l2, h2, l2, h2); + /* Shift result left by one bit if requested */ + if (extract32(get_field(s, m6), 2, 1)) { + tcg_gen_extract2_i64(h2, l2, h2, 63); + tcg_gen_shli_i64(l2, l2, 1); + } + + /* Add both intermediate results */ + tcg_gen_add2_i64(l1, h1, l1, h1, l2, h2); + /* Add whole v4 */ + read_vec_element_i64(h2, get_field(s, v4), 0, ES_64); + read_vec_element_i64(l2, get_field(s, v4), 1, ES_64); + tcg_gen_add2_i64(l1, h1, l1, h1, l2, h2); + + /* Store final result into v1. */ + write_vec_element_i64(h1, get_field(s, v1), 0, ES_64); + write_vec_element_i64(l1, get_field(s, v1), 1, ES_64); + + tcg_temp_free_i64(l1); + tcg_temp_free_i64(h1); + tcg_temp_free_i64(l2); + tcg_temp_free_i64(h2); + return DISAS_NEXT; +} + static DisasJumpType op_vnn(DisasContext *s, DisasOps *o) { gen_gvec_fn_3(nand, ES_8, get_field(s, v1), From patchwork Wed Sep 30 14:55:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56787C4727C for ; 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Wed, 30 Sep 2020 10:55:40 -0400 X-MC-Unique: P9_HiuyWNkuMPzWBtxM2Qg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 62D80805EE3; Wed, 30 Sep 2020 14:55:39 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id CDA655C1C4; Wed, 30 Sep 2020 14:55:37 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 04/20] s390x/tcg: Implement 32/128 bit for VECTOR FP ADD Date: Wed, 30 Sep 2020 16:55:07 +0200 Message-Id: <20200930145523.71087-5-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In case of 128bit, we always have a single element. Add some helpers that allow to generically read/write 32/64/128 bit floats. Convert the existing implementation of vop64_3 into a macro that deals with float* instead of uint* instead - the other users keep working as typedef uint32_t float32; typedef uint64_t float64; Most of them will get converted next. Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 + target/s390x/translate_vx.c.inc | 31 +++++++-- target/s390x/vec_fpu_helper.c | 119 +++++++++++++++++++++----------- 3 files changed, 107 insertions(+), 46 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index f579fd38a7..3d59f143e0 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -247,8 +247,11 @@ DEF_HELPER_6(gvec_vstrc_cc_rt16, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_6(gvec_vstrc_cc_rt32, void, ptr, cptr, cptr, cptr, env, i32) /* === Vector Floating-Point Instructions */ +DEF_HELPER_FLAGS_5(gvec_vfa32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfa32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfa128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32) DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 4c1b430013..2ba2170b16 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2504,16 +2504,27 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) const uint8_t fpf = get_field(s, m4); const uint8_t m5 = get_field(s, m5); const bool se = extract32(m5, 3, 1); - gen_helper_gvec_3_ptr *fn; - - if (fpf != FPF_LONG || extract32(m5, 0, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } + gen_helper_gvec_3_ptr *fn = NULL; switch (s->fields.op2) { case 0xe3: - fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64; + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfa32s : gen_helper_gvec_vfa32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfa128; + } + break; + default: + break; + } break; case 0xe5: fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64; @@ -2527,6 +2538,12 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) default: g_assert_not_reached(); } + + if (!fn || extract32(m5, 0, 3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), cpu_env, 0, fn); return DISAS_NEXT; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index c1564e819b..ae803ba602 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -78,6 +78,40 @@ static void handle_ieee_exc(CPUS390XState *env, uint8_t vxc, uint8_t vec_exc, } } +static float32 s390_vec_read_float32(const S390Vector *v, uint8_t enr) +{ + return make_float32(s390_vec_read_element32(v, enr)); +} + +static float64 s390_vec_read_float64(const S390Vector *v, uint8_t enr) +{ + return make_float64(s390_vec_read_element64(v, enr)); +} + +static float128 s390_vec_read_float128(const S390Vector *v, uint8_t enr) +{ + g_assert(enr == 0); + return make_float128(s390_vec_read_element64(v, 0), + s390_vec_read_element64(v, 1)); +} + +static void s390_vec_write_float32(S390Vector *v, uint8_t enr, float32 data) +{ + return s390_vec_write_element32(v, enr, data); +} + +static void s390_vec_write_float64(S390Vector *v, uint8_t enr, float64 data) +{ + return s390_vec_write_element64(v, enr, data); +} + +static void s390_vec_write_float128(S390Vector *v, uint8_t enr, float128 data) +{ + g_assert(enr == 0); + s390_vec_write_element64(v, 0, data.high); + s390_vec_write_element64(v, 1, data.low); +} + typedef uint64_t (*vop64_2_fn)(uint64_t a, float_status *s); static void vop64_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, bool s, bool XxC, uint8_t erm, vop64_2_fn fn, @@ -102,45 +136,52 @@ static void vop64_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, *v1 = tmp; } -typedef uint64_t (*vop64_3_fn)(uint64_t a, uint64_t b, float_status *s); -static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, - CPUS390XState *env, bool s, vop64_3_fn fn, - uintptr_t retaddr) -{ - uint8_t vxc, vec_exc = 0; - S390Vector tmp = {}; - int i; - - for (i = 0; i < 2; i++) { - const uint64_t a = s390_vec_read_element64(v2, i); - const uint64_t b = s390_vec_read_element64(v3, i); - - s390_vec_write_element64(&tmp, i, fn(a, b, &env->fpu_status)); - vxc = check_ieee_exc(env, i, false, &vec_exc); - if (s || vxc) { - break; - } - } - handle_ieee_exc(env, vxc, vec_exc, retaddr); - *v1 = tmp; -} - -static uint64_t vfa64(uint64_t a, uint64_t b, float_status *s) -{ - return float64_add(a, b, s); -} - -void HELPER(gvec_vfa64)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, false, vfa64, GETPC()); -} - -void HELPER(gvec_vfa64s)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, true, vfa64, GETPC()); -} +#define DEF_VOP_3(BITS) \ +typedef float##BITS (*vop##BITS##_3_fn)(float##BITS a, float##BITS b, \ + float_status *s); \ +static void vop##BITS##_3(S390Vector *v1, const S390Vector *v2, \ + const S390Vector *v3, CPUS390XState *env, bool s, \ + vop##BITS##_3_fn fn, uintptr_t retaddr) \ +{ \ + uint8_t vxc, vec_exc = 0; \ + S390Vector tmp = {}; \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const float##BITS a = s390_vec_read_float##BITS(v2, i); \ + const float##BITS b = s390_vec_read_float##BITS(v3, i); \ + \ + s390_vec_write_float##BITS(&tmp, i, fn(a, b, &env->fpu_status)); \ + vxc = check_ieee_exc(env, i, false, &vec_exc); \ + if (s || vxc) { \ + break; \ + } \ + } \ + handle_ieee_exc(env, vxc, vec_exc, retaddr); \ + *v1 = tmp; \ +} +DEF_VOP_3(32) +DEF_VOP_3(64) +DEF_VOP_3(128) + +#define DEF_GVEC_FVA(BITS) \ +void HELPER(gvec_vfa##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, false, float##BITS##_add, GETPC()); \ +} +DEF_GVEC_FVA(32) +DEF_GVEC_FVA(64) +DEF_GVEC_FVA(128) + +#define DEF_GVEC_FVA_S(BITS) \ +void HELPER(gvec_vfa##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, true, float##BITS##_add, GETPC()); \ +} +DEF_GVEC_FVA_S(32) +DEF_GVEC_FVA_S(64) static int wfc64(const S390Vector *v1, const S390Vector *v2, CPUS390XState *env, bool signal, uintptr_t retaddr) From patchwork Wed Sep 30 14:55:08 2020 Content-Type: text/plain; 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bh=sjgP+CMA4hlBuLDbl3DpB1L9Fm8TD3g65IOy2pCdwpI=; b=BRmJarKtfZYbM+wNWVjjVcKCLuXCBshZP3RjS10iwV1sfQ37qhSniBMfW85E1VKR6qmy+I RM9wVy03cfJn8Sy4BWvFvQs8YnzhExEd6XdFWnubJpAsYn13G3qkodnKnXyTObJfwCgCOU hfzIernlH7rWQxI36mpUaglmj7pSuPo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-594-kkKlO7fdO4GP_3lZ3ur5GA-1; Wed, 30 Sep 2020 10:55:42 -0400 X-MC-Unique: kkKlO7fdO4GP_3lZ3ur5GA-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5EEFE807352; Wed, 30 Sep 2020 14:55:41 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id C0C075C1C4; Wed, 30 Sep 2020 14:55:39 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 05/20] s390x/tcg: Implement 32/128 bit for VECTOR FP DIVIDE Date: Wed, 30 Sep 2020 16:55:08 +0200 Message-Id: <20200930145523.71087-6-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; 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Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 +++ target/s390x/translate_vx.c.inc | 18 +++++++++++++++++- target/s390x/vec_fpu_helper.c | 28 +++++++++++++++------------- 3 files changed, 35 insertions(+), 14 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 3d59f143e0..3dfd480fc1 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -274,8 +274,11 @@ DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vcgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vclgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vclgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfd32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfd32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfd64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfd128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfi64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 2ba2170b16..ea1b2732bc 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2527,7 +2527,23 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) } break; case 0xe5: - fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64; + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfd32s : gen_helper_gvec_vfd32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfd128; + } + break; + default: + break; + } break; case 0xe7: fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index ae803ba602..cfa143b62a 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -411,22 +411,24 @@ void HELPER(gvec_vclgd64s)(void *v1, const void *v2, CPUS390XState *env, vop64_2(v1, v2, env, true, XxC, erm, vclgd64, GETPC()); } -static uint64_t vfd64(uint64_t a, uint64_t b, float_status *s) -{ - return float64_div(a, b, s); -} - -void HELPER(gvec_vfd64)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, false, vfd64, GETPC()); +#define DEF_GVEC_FVD(BITS) \ +void HELPER(gvec_vfd##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, false, float##BITS##_div, GETPC()); \ } +DEF_GVEC_FVD(32) +DEF_GVEC_FVD(64) +DEF_GVEC_FVD(128) -void HELPER(gvec_vfd64s)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, true, vfd64, GETPC()); +#define DEF_GVEC_FVD_S(BITS) \ +void HELPER(gvec_vfd##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, true, float##BITS##_div, GETPC()); \ } +DEF_GVEC_FVD_S(32) +DEF_GVEC_FVD_S(64) static uint64_t vfi64(uint64_t a, float_status *s) { From patchwork Wed Sep 30 14:55:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40CD5C4727C for ; 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Wed, 30 Sep 2020 10:55:44 -0400 X-MC-Unique: _hPARnlWOSSJbCn7Nb1pWQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 61BB5807340; Wed, 30 Sep 2020 14:55:43 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id B28635C1C4; Wed, 30 Sep 2020 14:55:41 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 06/20] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY Date: Wed, 30 Sep 2020 16:55:09 +0200 Message-Id: <20200930145523.71087-7-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Just like VECTOR FP ADD. Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 +++ target/s390x/translate_vx.c.inc | 18 +++++++++++++++++- target/s390x/vec_fpu_helper.c | 28 +++++++++++++++------------- 3 files changed, 35 insertions(+), 14 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 3dfd480fc1..a7a902ed9c 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -285,8 +285,11 @@ DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfm32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfm32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfm128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index ea1b2732bc..65385ce5ee 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2546,7 +2546,23 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) } break; case 0xe7: - fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64; + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfm32s : gen_helper_gvec_vfm32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfm128; + } + break; + default: + break; + } break; case 0xe2: fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index cfa143b62a..335d540622 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -531,22 +531,24 @@ void HELPER(gvec_vflr64s)(void *v1, const void *v2, CPUS390XState *env, vflr64(v1, v2, env, true, XxC, erm, GETPC()); } -static uint64_t vfm64(uint64_t a, uint64_t b, float_status *s) -{ - return float64_mul(a, b, s); -} - -void HELPER(gvec_vfm64)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, false, vfm64, GETPC()); +#define DEF_GVEC_FVM(BITS) \ +void HELPER(gvec_vfm##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, false, float##BITS##_mul, GETPC()); \ } +DEF_GVEC_FVM(32) +DEF_GVEC_FVM(64) +DEF_GVEC_FVM(128) -void HELPER(gvec_vfm64s)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, true, vfm64, GETPC()); +#define DEF_GVEC_FVM_S(BITS) \ +void HELPER(gvec_vfm##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, true, float##BITS##_mul, GETPC()); \ } +DEF_GVEC_FVM_S(32) +DEF_GVEC_FVM_S(64) static void vfma64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, const S390Vector *v4, CPUS390XState *env, bool s, int flags, From patchwork Wed Sep 30 14:55:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC0D3C4727E for ; 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Wed, 30 Sep 2020 10:55:49 -0400 X-MC-Unique: _dvghxFJPpecY14UfjFWtQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E12251021203; Wed, 30 Sep 2020 14:55:47 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id B94D35C1C4; Wed, 30 Sep 2020 14:55:43 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 07/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SUBTRACT Date: Wed, 30 Sep 2020 16:55:10 +0200 Message-Id: <20200930145523.71087-8-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; 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Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 +++ target/s390x/translate_vx.c.inc | 18 +++++++++++++++++- target/s390x/vec_fpu_helper.c | 28 +++++++++++++++------------- 3 files changed, 35 insertions(+), 14 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index a7a902ed9c..ab41555764 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -296,8 +296,11 @@ DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfs32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfs32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfs128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_4(gvec_vftci64, void, ptr, cptr, env, i32) DEF_HELPER_4(gvec_vftci64s, void, ptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 65385ce5ee..91d4e74a68 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2565,7 +2565,23 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) } break; case 0xe2: - fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64; + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfs32s : gen_helper_gvec_vfs32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfs128; + } + break; + default: + break; + } break; default: g_assert_not_reached(); diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 335d540622..799e7f793e 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -615,22 +615,24 @@ void HELPER(gvec_vfsq64s)(void *v1, const void *v2, CPUS390XState *env, vop64_2(v1, v2, env, true, false, 0, vfsq64, GETPC()); } -static uint64_t vfs64(uint64_t a, uint64_t b, float_status *s) -{ - return float64_sub(a, b, s); -} - -void HELPER(gvec_vfs64)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, false, vfs64, GETPC()); +#define DEF_GVEC_FVS(BITS) \ +void HELPER(gvec_vfs##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, false, float##BITS##_sub, GETPC()); \ } +DEF_GVEC_FVS(32) +DEF_GVEC_FVS(64) +DEF_GVEC_FVS(128) -void HELPER(gvec_vfs64s)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vop64_3(v1, v2, v3, env, true, vfs64, GETPC()); +#define DEF_GVEC_FVS_S(BITS) \ +void HELPER(gvec_vfs##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3(v1, v2, v3, env, true, float##BITS##_sub, GETPC()); \ } +DEF_GVEC_FVS_S(32) +DEF_GVEC_FVS_S(64) static int vftci64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, bool s, uint16_t i3) From patchwork Wed Sep 30 14:55:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68DA6C47420 for ; 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Wed, 30 Sep 2020 10:55:51 -0400 X-MC-Unique: BRDRSrUXNLiWIES5DIwMGg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EF94E1021208; Wed, 30 Sep 2020 14:55:49 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4AEED5C1C4; Wed, 30 Sep 2020 14:55:48 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 08/20] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR Date: Wed, 30 Sep 2020 16:55:11 +0200 Message-Id: <20200930145523.71087-9-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:31:59 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 4 +++ target/s390x/translate_vx.c.inc | 38 +++++++++++++++----- target/s390x/vec_fpu_helper.c | 64 +++++++++++++++++++-------------- 3 files changed, 72 insertions(+), 34 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index ab41555764..6bf4d3e7d0 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -252,8 +252,12 @@ DEF_HELPER_FLAGS_5(gvec_vfa32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfa128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_4(gvec_wfc32, void, cptr, cptr, env, i32) +DEF_HELPER_4(gvec_wfk32, void, cptr, cptr, env, i32) DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32) DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32) +DEF_HELPER_4(gvec_wfc128, void, cptr, cptr, env, i32) +DEF_HELPER_4(gvec_wfk128, void, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfce64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfce64_cc, void, ptr, cptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 91d4e74a68..cc745784e5 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2601,19 +2601,41 @@ static DisasJumpType op_wfc(DisasContext *s, DisasOps *o) { const uint8_t fpf = get_field(s, m3); const uint8_t m4 = get_field(s, m4); + gen_helper_gvec_2_ptr *fn = NULL; - if (fpf != FPF_LONG || m4) { + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_wfk32; + if (s->fields.op2 == 0xcb) { + fn = gen_helper_gvec_wfc32; + } + } + break; + case FPF_LONG: + fn = gen_helper_gvec_wfk64; + if (s->fields.op2 == 0xcb) { + fn = gen_helper_gvec_wfc64; + } + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_wfk128; + if (s->fields.op2 == 0xcb) { + fn = gen_helper_gvec_wfc128; + } + } + break; + default: + break; + }; + + if (!fn || m4) { gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (s->fields.op2 == 0xcb) { - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, gen_helper_gvec_wfc64); - } else { - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, gen_helper_gvec_wfk64); - } + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, 0, fn); set_cc_static(s); return DISAS_NEXT; } diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 799e7f793e..1b78b6c088 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -183,37 +183,49 @@ void HELPER(gvec_vfa##BITS##s)(void *v1, const void *v2, const void *v3, \ DEF_GVEC_FVA_S(32) DEF_GVEC_FVA_S(64) -static int wfc64(const S390Vector *v1, const S390Vector *v2, - CPUS390XState *env, bool signal, uintptr_t retaddr) -{ - /* only the zero-indexed elements are compared */ - const float64 a = s390_vec_read_element64(v1, 0); - const float64 b = s390_vec_read_element64(v2, 0); - uint8_t vxc, vec_exc = 0; - int cmp; - - if (signal) { - cmp = float64_compare(a, b, &env->fpu_status); - } else { - cmp = float64_compare_quiet(a, b, &env->fpu_status); - } - vxc = check_ieee_exc(env, 0, false, &vec_exc); - handle_ieee_exc(env, vxc, vec_exc, retaddr); - - return float_comp_to_cc(env, cmp); +#define DEF_WFC(BITS) \ +static int wfc##BITS(const S390Vector *v1, const S390Vector *v2, \ + CPUS390XState *env, bool signal, uintptr_t retaddr) \ +{ \ + /* only the zero-indexed elements are compared */ \ + const float##BITS a = s390_vec_read_float##BITS(v1, 0); \ + const float##BITS b = s390_vec_read_float##BITS(v2, 0); \ + uint8_t vxc, vec_exc = 0; \ + int cmp; \ + \ + if (signal) { \ + cmp = float##BITS##_compare(a, b, &env->fpu_status); \ + } else { \ + cmp = float##BITS##_compare_quiet(a, b, &env->fpu_status); \ + } \ + vxc = check_ieee_exc(env, 0, false, &vec_exc); \ + handle_ieee_exc(env, vxc, vec_exc, retaddr); \ + \ + return float_comp_to_cc(env, cmp); \ } +DEF_WFC(32) +DEF_WFC(64) +DEF_WFC(128) -void HELPER(gvec_wfc64)(const void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - env->cc_op = wfc64(v1, v2, env, false, GETPC()); +#define DEF_GVEC_WFC(BITS) \ +void HELPER(gvec_wfc##BITS)(const void *v1, const void *v2, CPUS390XState *env,\ + uint32_t desc) \ +{ \ + env->cc_op = wfc##BITS(v1, v2, env, false, GETPC()); \ } +DEF_GVEC_WFC(32) +DEF_GVEC_WFC(64) +DEF_GVEC_WFC(128) -void HELPER(gvec_wfk64)(const void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - env->cc_op = wfc64(v1, v2, env, true, GETPC()); +#define DEF_GVEC_WFK(BITS) \ +void HELPER(gvec_wfk##BITS)(const void *v1, const void *v2, CPUS390XState *env,\ + uint32_t desc) \ +{ \ + env->cc_op = wfc##BITS(v1, v2, env, true, GETPC()); \ } +DEF_GVEC_WFK(32) +DEF_GVEC_WFK(64) +DEF_GVEC_WFK(128) typedef bool (*vfc64_fn)(float64 a, float64 b, float_status *status); static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, From patchwork Wed Sep 30 14:55:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98A05C4727C for ; Wed, 30 Sep 2020 15:17:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 965802071E for ; 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Wed, 30 Sep 2020 14:55:52 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 572285C1C4; Wed, 30 Sep 2020 14:55:50 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 09/20] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE * Date: Wed, 30 Sep 2020 16:55:12 +0200 Message-Id: <20200930145523.71087-10-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In addition to 32/128bit variants, we also have to support the "Signal-on-QNaN (SQ)" bit ... let's pass it as a simple flag, I don't feel like duplicating all helpers and coming up with names like "...s_cc_sq". Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 18 +++ target/s390x/translate_vx.c.inc | 91 +++++++++--- target/s390x/vec_fpu_helper.c | 250 ++++++++++++++++++++++---------- 3 files changed, 258 insertions(+), 101 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 6bf4d3e7d0..538d55420b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -258,18 +258,36 @@ DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32) DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32) DEF_HELPER_4(gvec_wfc128, void, cptr, cptr, env, i32) DEF_HELPER_4(gvec_wfk128, void, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfce32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfce32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfce64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfce128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfce32_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfce32s_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfce64_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfce64s_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfce128_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfch32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfch32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfch64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfch64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfch128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfch32_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfch32s_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfch64_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfch64s_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfch128_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfche32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfche32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfche64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfche128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfche32_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfche32s_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_5(gvec_vfche128_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vcdg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index cc745784e5..fd1cd6f6d5 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2646,45 +2646,90 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o) const uint8_t m5 = get_field(s, m5); const uint8_t m6 = get_field(s, m6); const bool se = extract32(m5, 3, 1); + const bool sq = extract32(m5, 2, 1); const bool cs = extract32(m6, 0, 1); - gen_helper_gvec_3_ptr *fn; - - if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } + gen_helper_gvec_3_ptr *fn = NULL; - if (cs) { - switch (s->fields.op2) { - case 0xe8: - fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc; + switch (s->fields.op2) { + case 0xe8: + switch (fpf) { + case FPF_SHORT: + fn = se ? gen_helper_gvec_vfce32s : gen_helper_gvec_vfce32; + if (cs) { + fn = se ? gen_helper_gvec_vfce32s_cc : + gen_helper_gvec_vfce32_cc; + } break; - case 0xeb: - fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64; + if (cs) { + fn = se ? gen_helper_gvec_vfce64s_cc : + gen_helper_gvec_vfce64_cc; + } break; - case 0xea: - fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc; + case FPF_EXT: + fn = cs ? gen_helper_gvec_vfce128_cc : gen_helper_gvec_vfce128; break; default: - g_assert_not_reached(); + break; } - } else { - switch (s->fields.op2) { - case 0xe8: - fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64; + break; + case 0xeb: + switch (fpf) { + case FPF_SHORT: + fn = se ? gen_helper_gvec_vfch32s : gen_helper_gvec_vfch32; + if (cs) { + fn = se ? gen_helper_gvec_vfch32s_cc : gen_helper_gvec_vfch32_cc; + } break; - case 0xeb: + case FPF_LONG: fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64; + if (cs) { + fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc; + } + break; + case FPF_EXT: + fn = cs ? gen_helper_gvec_vfch128_cc : gen_helper_gvec_vfch128; break; - case 0xea: + default: + break; + } + break; + case 0xea: + switch (fpf) { + case FPF_SHORT: + fn = se ? gen_helper_gvec_vfche32s : gen_helper_gvec_vfche32; + if (cs) { + fn = se ? gen_helper_gvec_vfche32s_cc : + gen_helper_gvec_vfche32_cc; + } + break; + case FPF_LONG: fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64; + if (cs) { + fn = se ? gen_helper_gvec_vfche64s_cc : + gen_helper_gvec_vfche64_cc; + } + break; + case FPF_EXT: + fn = cs ? gen_helper_gvec_vfche128_cc : gen_helper_gvec_vfche128; break; default: - g_assert_not_reached(); + break; } + default: + break; } + + if (!fn || extract32(m5, 0, 2) || extract32(m6, 1, 3) || + (!s390_has_feat(S390_FEAT_VECTOR_ENH) && (fpf != FPF_LONG || sq))) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* Pass the "sq" flag as data. */ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, 0, fn); + get_field(s, v3), cpu_env, sq, fn); if (cs) { set_cc_static(s); } diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 1b78b6c088..e8ae608da6 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -20,6 +20,10 @@ #include "exec/helper-proto.h" #include "fpu/softfloat.h" +const float32 float32_ones = make_float32(-1u); +const float64 float64_ones = make_float64(-1ull); +const float128 float128_ones = make_float128(-1ull, -1ull); + #define VIC_INVALID 0x1 #define VIC_DIVBYZERO 0x2 #define VIC_OVERFLOW 0x3 @@ -227,109 +231,199 @@ DEF_GVEC_WFK(32) DEF_GVEC_WFK(64) DEF_GVEC_WFK(128) -typedef bool (*vfc64_fn)(float64 a, float64 b, float_status *status); -static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, - CPUS390XState *env, bool s, vfc64_fn fn, uintptr_t retaddr) -{ - uint8_t vxc, vec_exc = 0; - S390Vector tmp = {}; - int match = 0; - int i; - - for (i = 0; i < 2; i++) { - const float64 a = s390_vec_read_element64(v2, i); - const float64 b = s390_vec_read_element64(v3, i); - - /* swap the order of the parameters, so we can use existing functions */ - if (fn(b, a, &env->fpu_status)) { - match++; - s390_vec_write_element64(&tmp, i, -1ull); - } - vxc = check_ieee_exc(env, i, false, &vec_exc); - if (s || vxc) { - break; - } - } - - handle_ieee_exc(env, vxc, vec_exc, retaddr); - *v1 = tmp; - if (match) { - return s || match == 2 ? 0 : 1; - } - return 3; +#define DEF_VFC(BITS) \ +typedef bool (*vfc##BITS##_fn)(float##BITS a, float##BITS b, \ + float_status *status); \ +static int vfc##BITS(S390Vector *v1, const S390Vector *v2, \ + const S390Vector *v3, CPUS390XState *env, bool s, \ + vfc##BITS##_fn fn, uintptr_t retaddr) \ +{ \ + uint8_t vxc, vec_exc = 0; \ + S390Vector tmp = {}; \ + int match = 0; \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const float##BITS a = s390_vec_read_float##BITS(v2, i); \ + const float##BITS b = s390_vec_read_float##BITS(v3, i); \ + \ + /* swap the parameters, so we can use existing functions */ \ + if (fn(b, a, &env->fpu_status)) { \ + match++; \ + s390_vec_write_float##BITS(&tmp, i, float##BITS##_ones); \ + } \ + vxc = check_ieee_exc(env, i, false, &vec_exc); \ + if (s || vxc) { \ + break; \ + } \ + } \ + \ + handle_ieee_exc(env, vxc, vec_exc, retaddr); \ + *v1 = tmp; \ + if (match) { \ + return s || match == (128 / BITS) ? 0 : 1; \ + } \ + return 3; \ } +DEF_VFC(32) +DEF_VFC(64) +DEF_VFC(128) -void HELPER(gvec_vfce64)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC()); +#define DEF_GVEC_VFCE(BITS) \ +void HELPER(gvec_vfce##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + vfc##BITS(v1, v2, v3, env, false, \ + sq ? float##BITS##_eq : float##BITS##_eq_quiet, GETPC()); \ } +DEF_GVEC_VFCE(32) +DEF_GVEC_VFCE(64) +DEF_GVEC_VFCE(128) -void HELPER(gvec_vfce64s)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC()); +#define DEF_GVEC_VFCE_S(BITS) \ +void HELPER(gvec_vfce##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + vfc##BITS(v1, v2, v3, env, true, \ + sq ? float##BITS##_eq : float##BITS##_eq_quiet, GETPC()); \ } +DEF_GVEC_VFCE_S(32) +DEF_GVEC_VFCE_S(64) -void HELPER(gvec_vfce64_cc)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - env->cc_op = vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC()); +#define DEF_GVEC_VFCE_CC(BITS) \ +void HELPER(gvec_vfce##BITS##_cc)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + env->cc_op = vfc##BITS(v1, v2, v3, env, false, \ + sq ? float##BITS##_eq : float##BITS##_eq_quiet, \ + GETPC()); \ } +DEF_GVEC_VFCE_CC(32) +DEF_GVEC_VFCE_CC(64) +DEF_GVEC_VFCE_CC(128) -void HELPER(gvec_vfce64s_cc)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - env->cc_op = vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC()); +#define DEF_GVEC_VFCE_S_CC(BITS) \ +void HELPER(gvec_vfce##BITS##s_cc)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + env->cc_op = vfc##BITS(v1, v2, v3, env, true, \ + sq ? float##BITS##_eq : float##BITS##_eq_quiet, \ + GETPC()); \ } +DEF_GVEC_VFCE_S_CC(32) +DEF_GVEC_VFCE_S_CC(64) -void HELPER(gvec_vfch64)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC()); +#define DEF_GVEC_VFCH(BITS) \ +void HELPER(gvec_vfch##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + vfc##BITS(v1, v2, v3, env, false, \ + sq ? float##BITS##_lt : float##BITS##_lt_quiet, GETPC()); \ } +DEF_GVEC_VFCH(32) +DEF_GVEC_VFCH(64) +DEF_GVEC_VFCH(128) -void HELPER(gvec_vfch64s)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC()); +#define DEF_GVEC_VFCH_S(BITS) \ +void HELPER(gvec_vfch##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + vfc##BITS(v1, v2, v3, env, true, \ + sq ? float##BITS##_lt : float##BITS##_lt_quiet, GETPC()); \ } +DEF_GVEC_VFCH_S(32) +DEF_GVEC_VFCH_S(64) -void HELPER(gvec_vfch64_cc)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - env->cc_op = vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC()); +#define DEF_GVEC_VFCH_CC(BITS) \ +void HELPER(gvec_vfch##BITS##_cc)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + env->cc_op = vfc##BITS(v1, v2, v3, env, false, \ + sq ? float##BITS##_lt : float##BITS##_lt_quiet, \ + GETPC()); \ } +DEF_GVEC_VFCH_CC(32) +DEF_GVEC_VFCH_CC(64) +DEF_GVEC_VFCH_CC(128) -void HELPER(gvec_vfch64s_cc)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - env->cc_op = vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC()); +#define DEF_GVEC_VFCH_S_CC(BITS) \ +void HELPER(gvec_vfch##BITS##s_cc)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + env->cc_op = vfc##BITS(v1, v2, v3, env, true, \ + sq ? float##BITS##_lt : float##BITS##_lt_quiet, \ + GETPC()); \ } +DEF_GVEC_VFCH_S_CC(32) +DEF_GVEC_VFCH_S_CC(64) -void HELPER(gvec_vfche64)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC()); +#define DEF_GVEC_VFCHE(BITS) \ +void HELPER(gvec_vfche##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + vfc##BITS(v1, v2, v3, env, false, \ + sq ? float##BITS##_le : float##BITS##_le_quiet, GETPC()); \ } +DEF_GVEC_VFCHE(32) +DEF_GVEC_VFCHE(64) +DEF_GVEC_VFCHE(128) -void HELPER(gvec_vfche64s)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC()); +#define DEF_GVEC_VFCHE_S(BITS) \ +void HELPER(gvec_vfche##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + vfc##BITS(v1, v2, v3, env, true, \ + sq ? float##BITS##_le : float##BITS##_le_quiet, GETPC()); \ } +DEF_GVEC_VFCHE_S(32) +DEF_GVEC_VFCHE_S(64) -void HELPER(gvec_vfche64_cc)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - env->cc_op = vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC()); +#define DEF_GVEC_VFCHE_CC(BITS) \ +void HELPER(gvec_vfche##BITS##_cc)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + env->cc_op = vfc##BITS(v1, v2, v3, env, false, \ + sq ? float##BITS##_le : float##BITS##_le_quiet, \ + GETPC()); \ } +DEF_GVEC_VFCHE_CC(32) +DEF_GVEC_VFCHE_CC(64) +DEF_GVEC_VFCHE_CC(128) -void HELPER(gvec_vfche64s_cc)(void *v1, const void *v2, const void *v3, - CPUS390XState *env, uint32_t desc) -{ - env->cc_op = vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC()); +#define DEF_GVEC_VFCHE_S_CC(BITS) \ +void HELPER(gvec_vfche##BITS##s_cc)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + const bool sq = simd_data(desc); \ + \ + env->cc_op = vfc##BITS(v1, v2, v3, env, true, \ + sq ? float##BITS##_le : float##BITS##_le_quiet, \ + GETPC()); \ } +DEF_GVEC_VFCHE_S_CC(32) +DEF_GVEC_VFCHE_S_CC(64) static uint64_t vcdg64(uint64_t a, float_status *s) { From patchwork Wed Sep 30 14:55:13 2020 Content-Type: text/plain; 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bh=4nbEBF+4BBHaosGjopfBxFq9VoWAhW6zrFzy9lLwsLA=; b=VLK9npUJBvVDhbHQCPWBr3VbYjDBAZVImPqVEh+L3NUNjgdrWdS/+MGdAf4IIuSwlL+WY2 ibxb6tea7fblwmJjFPUEEXe+8Z9t1LyDyWKX14Q+RSNj33KgLwfjohhwSDhj9VhbrXkn7g 82QL0SIp2wAm1BdhJbKasxFP2Rzn2gw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-493-XS-Sxq8hNZ6F5Jf-DkYV4Q-1; Wed, 30 Sep 2020 10:55:55 -0400 X-MC-Unique: XS-Sxq8hNZ6F5Jf-DkYV4Q-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2575A1021200; Wed, 30 Sep 2020 14:55:54 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8EE765C1C4; Wed, 30 Sep 2020 14:55:52 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 10/20] s390x/tcg: Implement 32/128 bit for VECTOR LOAD FP INTEGER Date: Wed, 30 Sep 2020 16:55:13 +0200 Message-Id: <20200930145523.71087-11-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Convert vop64_2 into a macro, similar to already done with vop64_3. Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 ++ target/s390x/translate_vx.c.inc | 51 ++++++++++++++----- target/s390x/vec_fpu_helper.c | 90 ++++++++++++++++++--------------- 3 files changed, 91 insertions(+), 53 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 538d55420b..ae9f855b05 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -301,8 +301,11 @@ DEF_HELPER_FLAGS_5(gvec_vfd32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfd64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfd128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vfi32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vfi32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfi64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vfi128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index fd1cd6f6d5..f6aed65ff5 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2742,35 +2742,62 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o) const uint8_t m4 = get_field(s, m4); const uint8_t erm = get_field(s, m5); const bool se = extract32(m4, 3, 1); - gen_helper_gvec_2_ptr *fn; - - if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } + gen_helper_gvec_2_ptr *fn = NULL; switch (s->fields.op2) { case 0xc3: - fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64; + if (fpf == FPF_LONG) { + fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64; + } break; case 0xc1: - fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64; + if (fpf == FPF_LONG) { + fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64; + } break; case 0xc2: - fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64; + if (fpf == FPF_LONG) { + fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64; + } break; case 0xc0: - fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64; + if (fpf == FPF_LONG) { + fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64; + } break; case 0xc7: - fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64; + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfi32s : gen_helper_gvec_vfi32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfi128; + } + break; + default: + break; + } break; case 0xc5: - fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64; + if (fpf == FPF_LONG) { + fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64; + } break; default: g_assert_not_reached(); } + + if (!fn || extract32(m4, 0, 2) || erm > 7 || erm == 2) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, deposit32(m4, 4, 4, erm), fn); return DISAS_NEXT; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index e8ae608da6..9bc7f5c8d7 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -116,29 +116,33 @@ static void s390_vec_write_float128(S390Vector *v, uint8_t enr, float128 data) s390_vec_write_element64(v, 1, data.low); } -typedef uint64_t (*vop64_2_fn)(uint64_t a, float_status *s); -static void vop64_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, - bool s, bool XxC, uint8_t erm, vop64_2_fn fn, - uintptr_t retaddr) -{ - uint8_t vxc, vec_exc = 0; - S390Vector tmp = {}; - int i, old_mode; - - old_mode = s390_swap_bfp_rounding_mode(env, erm); - for (i = 0; i < 2; i++) { - const uint64_t a = s390_vec_read_element64(v2, i); - - s390_vec_write_element64(&tmp, i, fn(a, &env->fpu_status)); - vxc = check_ieee_exc(env, i, XxC, &vec_exc); - if (s || vxc) { - break; - } - } - s390_restore_bfp_rounding_mode(env, old_mode); - handle_ieee_exc(env, vxc, vec_exc, retaddr); - *v1 = tmp; +#define DEF_VOP_2(BITS) \ +typedef float##BITS (*vop##BITS##_2_fn)(float##BITS a, float_status *s); \ +static void vop##BITS##_2(S390Vector *v1, const S390Vector *v2, \ + CPUS390XState *env, bool s, bool XxC, uint8_t erm, \ + vop##BITS##_2_fn fn, uintptr_t retaddr) \ +{ \ + uint8_t vxc, vec_exc = 0; \ + S390Vector tmp = {}; \ + int i, old_mode; \ + \ + old_mode = s390_swap_bfp_rounding_mode(env, erm); \ + for (i = 0; i < (128 / BITS); i++) { \ + const float##BITS a = s390_vec_read_float##BITS(v2, i); \ + \ + s390_vec_write_float##BITS(&tmp, i, fn(a, &env->fpu_status)); \ + vxc = check_ieee_exc(env, i, XxC, &vec_exc); \ + if (s || vxc) { \ + break; \ + } \ + } \ + s390_restore_bfp_rounding_mode(env, old_mode); \ + handle_ieee_exc(env, vxc, vec_exc, retaddr); \ + *v1 = tmp; \ } +DEF_VOP_2(32) +DEF_VOP_2(64) +DEF_VOP_2(128) #define DEF_VOP_3(BITS) \ typedef float##BITS (*vop##BITS##_3_fn)(float##BITS a, float##BITS b, \ @@ -536,28 +540,32 @@ void HELPER(gvec_vfd##BITS##s)(void *v1, const void *v2, const void *v3, \ DEF_GVEC_FVD_S(32) DEF_GVEC_FVD_S(64) -static uint64_t vfi64(uint64_t a, float_status *s) -{ - return float64_round_to_int(a, s); -} - -void HELPER(gvec_vfi64)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - const uint8_t erm = extract32(simd_data(desc), 4, 4); - const bool XxC = extract32(simd_data(desc), 2, 1); - - vop64_2(v1, v2, env, false, XxC, erm, vfi64, GETPC()); +#define DEF_GVEC_VFI(BITS) \ +void HELPER(gvec_vfi##BITS)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + const uint8_t erm = extract32(simd_data(desc), 4, 4); \ + const bool XxC = extract32(simd_data(desc), 2, 1); \ + \ + vop##BITS##_2(v1, v2, env, false, XxC, erm, float##BITS##_round_to_int, \ + GETPC()); \ } +DEF_GVEC_VFI(32) +DEF_GVEC_VFI(64) +DEF_GVEC_VFI(128) -void HELPER(gvec_vfi64s)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - const uint8_t erm = extract32(simd_data(desc), 4, 4); - const bool XxC = extract32(simd_data(desc), 2, 1); - - vop64_2(v1, v2, env, true, XxC, erm, vfi64, GETPC()); +#define DEF_GVEC_VFI_S(BITS) \ +void HELPER(gvec_vfi##BITS##s)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + const uint8_t erm = extract32(simd_data(desc), 4, 4); \ + const bool XxC = extract32(simd_data(desc), 2, 1); \ + \ + vop##BITS##_2(v1, v2, env, true, XxC, erm, float##BITS##_round_to_int, \ + GETPC()); \ } +DEF_GVEC_VFI_S(32) +DEF_GVEC_VFI_S(64) static void vfll32(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, bool s, uintptr_t retaddr) From patchwork Wed Sep 30 14:55:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BB83C4727C for ; Wed, 30 Sep 2020 15:06:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C47F72076B for ; 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Wed, 30 Sep 2020 14:55:56 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 817BC5C1C4; Wed, 30 Sep 2020 14:55:54 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 11/20] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED Date: Wed, 30 Sep 2020 16:55:14 +0200 Message-Id: <20200930145523.71087-12-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" 64 bit -> 128 bit, there is only a single final element. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/translate_vx.c.inc | 21 ++++++++++++++++----- target/s390x/vec_fpu_helper.c | 13 +++++++++++++ 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index ae9f855b05..e643672ec4 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -308,6 +308,7 @@ DEF_HELPER_FLAGS_4(gvec_vfi64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfi128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vfll64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index f6aed65ff5..ff697f3470 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2807,16 +2807,27 @@ static DisasJumpType op_vfll(DisasContext *s, DisasOps *o) { const uint8_t fpf = get_field(s, m3); const uint8_t m4 = get_field(s, m4); - gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfll32; + const bool se = extract32(m4, 3, 1); + gen_helper_gvec_2_ptr *fn = NULL; - if (fpf != FPF_SHORT || extract32(m4, 0, 3)) { + switch (fpf) { + case FPF_SHORT: + fn = se ? gen_helper_gvec_vfll32s : gen_helper_gvec_vfll32; + break; + case FPF_LONG: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfll64; + } + break; + default: + break; + } + + if (!fn || extract32(m4, 0, 3)) { gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (extract32(m4, 3, 1)) { - fn = gen_helper_gvec_vfll32s; - } gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, 0, fn); return DISAS_NEXT; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 9bc7f5c8d7..5ded2ccbcd 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -602,6 +602,19 @@ void HELPER(gvec_vfll32s)(void *v1, const void *v2, CPUS390XState *env, vfll32(v1, v2, env, true, GETPC()); } +void HELPER(gvec_vfll64)(void *v1, const void *v2, CPUS390XState *env, + uint32_t desc) +{ + /* load from even element */ + float128 ret = float64_to_float128(s390_vec_read_float64(v2, 0), + &env->fpu_status); + uint8_t vxc, vec_exc = 0; + + vxc = check_ieee_exc(env, 0, false, &vec_exc); + handle_ieee_exc(env, vxc, vec_exc, GETPC()); + s390_vec_write_float128(v1, 0, ret); +} + static void vflr64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, bool s, bool XxC, uint8_t erm, uintptr_t retaddr) { From patchwork Wed Sep 30 14:55:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1621FC4727C for ; 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Wed, 30 Sep 2020 10:55:59 -0400 X-MC-Unique: bwiy60oaMdyYXB7sIymUWg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3B9FA807345; Wed, 30 Sep 2020 14:55:58 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8890A5C1C4; Wed, 30 Sep 2020 14:55:56 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 12/20] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED Date: Wed, 30 Sep 2020 16:55:15 +0200 Message-Id: <20200930145523.71087-13-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" 128 bit -> 64 bit, there is only a single element to process. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/translate_vx.c.inc | 11 ++++++++++- target/s390x/vec_fpu_helper.c | 19 +++++++++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index e643672ec4..79e3fa14f8 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -311,6 +311,7 @@ DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfll64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vflr128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index ff697f3470..0b21e8789f 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2785,8 +2785,17 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o) } break; case 0xc5: - if (fpf == FPF_LONG) { + switch (fpf) { + case FPF_LONG: fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vflr128; + } + break; + default: + break; } break; default: diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 5ded2ccbcd..f8ebd04516 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -658,6 +658,25 @@ void HELPER(gvec_vflr64s)(void *v1, const void *v2, CPUS390XState *env, vflr64(v1, v2, env, true, XxC, erm, GETPC()); } +void HELPER(gvec_vflr128)(void *v1, const void *v2, CPUS390XState *env, + uint32_t desc) +{ + const uint8_t erm = extract32(simd_data(desc), 4, 4); + const bool XxC = extract32(simd_data(desc), 2, 1); + uint8_t vxc, vec_exc = 0; + int old_mode; + float64 ret; + + old_mode = s390_swap_bfp_rounding_mode(env, erm); + ret = float128_to_float64(s390_vec_read_float128(v2, 0), &env->fpu_status); + vxc = check_ieee_exc(env, 0, XxC, &vec_exc); + s390_restore_bfp_rounding_mode(env, old_mode); + handle_ieee_exc(env, vxc, vec_exc, GETPC()); + + /* place at even element, odd element is unpredictable */ + s390_vec_write_float64(v1, 0, ret); +} + #define DEF_GVEC_FVM(BITS) \ void HELPER(gvec_vfm##BITS)(void *v1, const void *v2, const void *v3, \ CPUS390XState *env, uint32_t desc) \ From patchwork Wed Sep 30 14:55:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5D14C4727E for ; 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Wed, 30 Sep 2020 10:56:01 -0400 X-MC-Unique: OggmO_OqNASDF32vGJzT4A-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 325801891E87; Wed, 30 Sep 2020 14:56:00 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 998775C1C4; Wed, 30 Sep 2020 14:55:58 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 13/20] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION Date: Wed, 30 Sep 2020 16:55:16 +0200 Message-Id: <20200930145523.71087-14-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- target/s390x/translate_vx.c.inc | 100 +++++++++++++++++++++----------- 1 file changed, 67 insertions(+), 33 deletions(-) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 0b21e8789f..ee79d97e19 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2872,48 +2872,82 @@ static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o) const uint8_t fpf = get_field(s, m3); const uint8_t m4 = get_field(s, m4); const uint8_t m5 = get_field(s, m5); + const bool se = extract32(m4, 3, 1); TCGv_i64 tmp; - if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) { + if ((fpf != FPF_LONG && !s390_has_feat(S390_FEAT_VECTOR_ENH)) || + extract32(m4, 0, 3) || m5 > 2) { gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (extract32(m4, 3, 1)) { - tmp = tcg_temp_new_i64(); - read_vec_element_i64(tmp, v2, 0, ES_64); - switch (m5) { - case 0: - /* sign bit is inverted (complement) */ - tcg_gen_xori_i64(tmp, tmp, 1ull << 63); - break; - case 1: - /* sign bit is set to one (negative) */ - tcg_gen_ori_i64(tmp, tmp, 1ull << 63); - break; - case 2: - /* sign bit is set to zero (positive) */ - tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1); - break; + switch (fpf) { + case FPF_SHORT: + if (!se) { + switch (m5) { + case 0: + /* sign bit is inverted (complement) */ + gen_gvec_fn_2i(xori, ES_32, v1, v2, 1ull << 31); + break; + case 1: + /* sign bit is set to one (negative) */ + gen_gvec_fn_2i(ori, ES_32, v1, v2, 1ull << 31); + break; + case 2: + /* sign bit is set to zero (positive) */ + gen_gvec_fn_2i(andi, ES_32, v1, v2, (1ull << 31) - 1); + break; + } + return DISAS_NEXT; } - write_vec_element_i64(tmp, v1, 0, ES_64); - tcg_temp_free_i64(tmp); - } else { - switch (m5) { - case 0: - /* sign bit is inverted (complement) */ - gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63); - break; - case 1: - /* sign bit is set to one (negative) */ - gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63); - break; - case 2: - /* sign bit is set to zero (positive) */ - gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1); - break; + break; + case FPF_LONG: + if (!se) { + switch (m5) { + case 0: + /* sign bit is inverted (complement) */ + gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63); + break; + case 1: + /* sign bit is set to one (negative) */ + gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63); + break; + case 2: + /* sign bit is set to zero (positive) */ + gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1); + break; + } + return DISAS_NEXT; } + break; + case FPF_EXT: + /* Only a single element. */ + break; + default: + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* With a single element, we are only interested in bit 0. */ + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, v2, 0, ES_64); + switch (m5) { + case 0: + /* sign bit is inverted (complement) */ + tcg_gen_xori_i64(tmp, tmp, 1ull << 63); + break; + case 1: + /* sign bit is set to one (negative) */ + tcg_gen_ori_i64(tmp, tmp, 1ull << 63); + break; + case 2: + /* sign bit is set to zero (positive) */ + tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1); + break; } + write_vec_element_i64(tmp, v1, 0, ES_64); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; } From patchwork Wed Sep 30 14:55:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8694DC4727E for ; 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Wed, 30 Sep 2020 10:56:03 -0400 X-MC-Unique: WmDvmeDmO-ag7J_0bgllSw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B844580B73A; Wed, 30 Sep 2020 14:56:02 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8243A5C1C4; Wed, 30 Sep 2020 14:56:00 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 14/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SQUARE ROOT Date: Wed, 30 Sep 2020 16:55:17 +0200 Message-Id: <20200930145523.71087-15-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 +++ target/s390x/translate_vx.c.inc | 26 +++++++++++++++++++++----- target/s390x/vec_fpu_helper.c | 28 +++++++++++++++------------- 3 files changed, 39 insertions(+), 18 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 79e3fa14f8..bee283e3d4 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -321,8 +321,11 @@ DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vfsq32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vfsq32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) +DEF_HELPER_FLAGS_4(gvec_vfsq128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index ee79d97e19..7d4811ccf7 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2955,16 +2955,32 @@ static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o) { const uint8_t fpf = get_field(s, m3); const uint8_t m4 = get_field(s, m4); - gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64; + const bool se = extract32(m4, 3, 1); + gen_helper_gvec_2_ptr *fn = NULL; - if (fpf != FPF_LONG || extract32(m4, 0, 3)) { + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfsq32s : gen_helper_gvec_vfsq32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfsq64s : gen_helper_gvec_vfsq64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfsq128; + } + break; + default: + break; + } + + if (!fn || extract32(m4, 0, 3)) { gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (extract32(m4, 3, 1)) { - fn = gen_helper_gvec_vfsq64s; - } gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, 0, fn); return DISAS_NEXT; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index f8ebd04516..b7045e85d6 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -744,22 +744,24 @@ void HELPER(gvec_vfms64s)(void *v1, const void *v2, const void *v3, vfma64(v1, v2, v3, v4, env, true, float_muladd_negate_c, GETPC()); } -static uint64_t vfsq64(uint64_t a, float_status *s) -{ - return float64_sqrt(a, s); -} - -void HELPER(gvec_vfsq64)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - vop64_2(v1, v2, env, false, false, 0, vfsq64, GETPC()); +#define DEF_GVEC_VFSQ(BITS) \ +void HELPER(gvec_vfsq##BITS)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vop##BITS##_2(v1, v2, env, false, false, 0, float##BITS##_sqrt, GETPC()); \ } +DEF_GVEC_VFSQ(32) +DEF_GVEC_VFSQ(64) +DEF_GVEC_VFSQ(128) -void HELPER(gvec_vfsq64s)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - vop64_2(v1, v2, env, true, false, 0, vfsq64, GETPC()); +#define DEF_GVEC_VFSQ_S(BITS) \ +void HELPER(gvec_vfsq##BITS##s)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vop##BITS##_2(v1, v2, env, true, false, 0, float##BITS##_sqrt, GETPC()); \ } +DEF_GVEC_VFSQ_S(32) +DEF_GVEC_VFSQ_S(64) #define DEF_GVEC_FVS(BITS) \ void HELPER(gvec_vfs##BITS)(void *v1, const void *v2, const void *v3, \ From patchwork Wed Sep 30 14:55:18 2020 Content-Type: text/plain; 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auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:31:59 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 ++ target/s390x/translate_vx.c.inc | 26 ++++++++--- target/s390x/vec_fpu_helper.c | 76 +++++++++++++++++++-------------- 3 files changed, 69 insertions(+), 36 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bee283e3d4..c2ded83669 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -331,8 +331,11 @@ DEF_HELPER_FLAGS_5(gvec_vfs32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_4(gvec_vftci32, void, ptr, cptr, env, i32) +DEF_HELPER_4(gvec_vftci32s, void, ptr, cptr, env, i32) DEF_HELPER_4(gvec_vftci64, void, ptr, cptr, env, i32) DEF_HELPER_4(gvec_vftci64s, void, ptr, cptr, env, i32) +DEF_HELPER_4(gvec_vftci128, void, ptr, cptr, env, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 7d4811ccf7..6bd599b319 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2991,16 +2991,32 @@ static DisasJumpType op_vftci(DisasContext *s, DisasOps *o) const uint16_t i3 = get_field(s, i3); const uint8_t fpf = get_field(s, m4); const uint8_t m5 = get_field(s, m5); - gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64; + const bool se = extract32(m5, 3, 1); + gen_helper_gvec_2_ptr *fn = NULL; - if (fpf != FPF_LONG || extract32(m5, 0, 3)) { + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vftci32s : gen_helper_gvec_vftci32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vftci64s : gen_helper_gvec_vftci64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vftci128; + } + break; + default: + break; + } + + if (!fn || extract32(m5, 0, 3)) { gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (extract32(m5, 3, 1)) { - fn = gen_helper_gvec_vftci64s; - } gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, i3, fn); set_cc_static(s); return DISAS_NEXT; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index b7045e85d6..f18f0ae8e2 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -23,6 +23,9 @@ const float32 float32_ones = make_float32(-1u); const float64 float64_ones = make_float64(-1ull); const float128 float128_ones = make_float128(-1ull, -1ull); +const float32 float32_zeroes = make_float32(0); +const float64 float64_zeroes = make_float64(0); +const float128 float128_zeroes = make_float128(0, 0); #define VIC_INVALID 0x1 #define VIC_DIVBYZERO 0x2 @@ -782,39 +785,50 @@ void HELPER(gvec_vfs##BITS##s)(void *v1, const void *v2, const void *v3, \ DEF_GVEC_FVS_S(32) DEF_GVEC_FVS_S(64) -static int vftci64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, - bool s, uint16_t i3) -{ - int i, match = 0; - - for (i = 0; i < 2; i++) { - float64 a = s390_vec_read_element64(v2, i); - - if (float64_dcmask(env, a) & i3) { - match++; - s390_vec_write_element64(v1, i, -1ull); - } else { - s390_vec_write_element64(v1, i, 0); - } - if (s) { - break; - } - } - - if (match) { - return s || match == 2 ? 0 : 1; - } - return 3; +#define DEF_VFTCI(BITS) \ +static int vftci##BITS(S390Vector *v1, const S390Vector *v2, \ + CPUS390XState *env, bool s, uint16_t i3) \ +{ \ + int i, match = 0; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + float##BITS a = s390_vec_read_float##BITS(v2, i); \ + \ + if (float##BITS##_dcmask(env, a) & i3) { \ + match++; \ + s390_vec_write_float##BITS(v1, i, float##BITS##_ones); \ + } else { \ + s390_vec_write_float##BITS(v1, i, float##BITS##_zeroes); \ + } \ + if (s) { \ + break; \ + } \ + } \ + \ + if (match) { \ + return s || match == (128 / BITS) ? 0 : 1; \ + } \ + return 3; \ } +DEF_VFTCI(32) +DEF_VFTCI(64) +DEF_VFTCI(128) -void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - env->cc_op = vftci64(v1, v2, env, false, simd_data(desc)); +#define DEF_GVEC_VFTCI(BITS) \ +void HELPER(gvec_vftci##BITS)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + env->cc_op = vftci##BITS(v1, v2, env, false, simd_data(desc)); \ } +DEF_GVEC_VFTCI(32) +DEF_GVEC_VFTCI(64) +DEF_GVEC_VFTCI(128) -void HELPER(gvec_vftci64s)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - env->cc_op = vftci64(v1, v2, env, true, simd_data(desc)); +#define DEF_GVEC_VFTCI_S(BITS) \ +void HELPER(gvec_vftci##BITS##s)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + env->cc_op = vftci##BITS(v1, v2, env, true, simd_data(desc)); \ } +DEF_GVEC_VFTCI_S(32) +DEF_GVEC_VFTCI_S(64) From patchwork Wed Sep 30 14:55:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB242C4727C for ; Wed, 30 Sep 2020 15:08:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 54ABB206FC for ; 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Wed, 30 Sep 2020 14:56:09 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id E1F445C1C4; Wed, 30 Sep 2020 14:56:07 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 16/20] s390x/tcg: Implement 32/128bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT) Date: Wed, 30 Sep 2020 16:55:19 +0200 Message-Id: <20200930145523.71087-17-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:31:59 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 6 ++ target/s390x/translate_vx.c.inc | 48 +++++++++++++--- target/s390x/vec_fpu_helper.c | 98 ++++++++++++++++++++------------- 3 files changed, 107 insertions(+), 45 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index c2ded83669..e4d60299dc 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -317,10 +317,16 @@ DEF_HELPER_FLAGS_5(gvec_vfm32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfma32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfma32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfma128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfms32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfms32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfms128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 6bd599b319..5d31498cc1 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2847,18 +2847,52 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps *o) const uint8_t m5 = get_field(s, m5); const uint8_t fpf = get_field(s, m6); const bool se = extract32(m5, 3, 1); - gen_helper_gvec_4_ptr *fn; + gen_helper_gvec_4_ptr *fn = NULL; - if (fpf != FPF_LONG || extract32(m5, 0, 3)) { + switch (s->fields.op2) { + case 0x8f: + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfma32s : gen_helper_gvec_vfma32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64; + break; + default: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfma128; + } + break; + } + break; + case 0x8e: + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vfms32s : gen_helper_gvec_vfms32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64; + break; + default: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vfms128; + } + break; + } + break; + default: + g_assert_not_reached(); + } + + if (!fn || extract32(m5, 0, 3)) { gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (s->fields.op2 == 0x8f) { - fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64; - } else { - fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64; - } gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), get_field(s, v4), cpu_env, 0, fn); diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index f18f0ae8e2..0b25718365 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -699,53 +699,75 @@ void HELPER(gvec_vfm##BITS##s)(void *v1, const void *v2, const void *v3, \ DEF_GVEC_FVM_S(32) DEF_GVEC_FVM_S(64) -static void vfma64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, - const S390Vector *v4, CPUS390XState *env, bool s, int flags, - uintptr_t retaddr) -{ - uint8_t vxc, vec_exc = 0; - S390Vector tmp = {}; - int i; - - for (i = 0; i < 2; i++) { - const uint64_t a = s390_vec_read_element64(v2, i); - const uint64_t b = s390_vec_read_element64(v3, i); - const uint64_t c = s390_vec_read_element64(v4, i); - uint64_t ret = float64_muladd(a, b, c, flags, &env->fpu_status); - - s390_vec_write_element64(&tmp, i, ret); - vxc = check_ieee_exc(env, i, false, &vec_exc); - if (s || vxc) { - break; - } - } - handle_ieee_exc(env, vxc, vec_exc, retaddr); - *v1 = tmp; +#define DEF_VFMA(BITS) \ +static void vfma##BITS(S390Vector *v1, const S390Vector *v2, \ + const S390Vector *v3, const S390Vector *v4, \ + CPUS390XState *env, bool s, int flags, \ + uintptr_t retaddr) \ +{ \ + uint8_t vxc, vec_exc = 0; \ + S390Vector tmp = {}; \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const float##BITS a = s390_vec_read_float##BITS(v2, i); \ + const float##BITS b = s390_vec_read_float##BITS(v3, i); \ + const float##BITS c = s390_vec_read_float##BITS(v4, i); \ + float##BITS ret = float##BITS##_muladd(a, b, c, flags, \ + &env->fpu_status); \ + \ + s390_vec_write_float##BITS(&tmp, i, ret); \ + vxc = check_ieee_exc(env, i, false, &vec_exc); \ + if (s || vxc) { \ + break; \ + } \ + } \ + handle_ieee_exc(env, vxc, vec_exc, retaddr); \ + *v1 = tmp; \ } +DEF_VFMA(32) +DEF_VFMA(64) +DEF_VFMA(128) -void HELPER(gvec_vfma64)(void *v1, const void *v2, const void *v3, - const void *v4, CPUS390XState *env, uint32_t desc) -{ - vfma64(v1, v2, v3, v4, env, false, 0, GETPC()); +#define DEF_GVEC_VFMA(BITS) \ +void HELPER(gvec_vfma##BITS)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, uint32_t desc)\ +{ \ + vfma##BITS(v1, v2, v3, v4, env, false, 0, GETPC()); \ } +DEF_GVEC_VFMA(32) +DEF_GVEC_VFMA(64) +DEF_GVEC_VFMA(128) -void HELPER(gvec_vfma64s)(void *v1, const void *v2, const void *v3, - const void *v4, CPUS390XState *env, uint32_t desc) -{ - vfma64(v1, v2, v3, v4, env, true, 0, GETPC()); +#define DEF_GVEC_VFMA_S(BITS) \ +void HELPER(gvec_vfma##BITS##s)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vfma##BITS(v1, v2, v3, v4, env, true, 0, GETPC()); \ } +DEF_GVEC_VFMA_S(32) +DEF_GVEC_VFMA_S(64) -void HELPER(gvec_vfms64)(void *v1, const void *v2, const void *v3, - const void *v4, CPUS390XState *env, uint32_t desc) -{ - vfma64(v1, v2, v3, v4, env, false, float_muladd_negate_c, GETPC()); +#define DEF_GVEC_VFMS(BITS) \ +void HELPER(gvec_vfms##BITS)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, uint32_t desc)\ +{ \ + vfma##BITS(v1, v2, v3, v4, env, false, float_muladd_negate_c, GETPC()); \ } +DEF_GVEC_VFMS(32) +DEF_GVEC_VFMS(64) +DEF_GVEC_VFMS(128) -void HELPER(gvec_vfms64s)(void *v1, const void *v2, const void *v3, - const void *v4, CPUS390XState *env, uint32_t desc) -{ - vfma64(v1, v2, v3, v4, env, true, float_muladd_negate_c, GETPC()); +#define DEF_GVEC_VFMS_S(BITS) \ +void HELPER(gvec_vfms##BITS##s)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vfma##BITS(v1, v2, v3, v4, env, true, float_muladd_negate_c, GETPC()); \ } +DEF_GVEC_VFMS_S(32) +DEF_GVEC_VFMS_S(64) #define DEF_GVEC_VFSQ(BITS) \ void HELPER(gvec_vfsq##BITS)(void *v1, const void *v2, CPUS390XState *env, \ From patchwork Wed Sep 30 14:55:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 141F5C4727C for ; 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Wed, 30 Sep 2020 10:56:12 -0400 X-MC-Unique: 9Fkh9By1NniV_VrtJZwwHA-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 87294802B68; Wed, 30 Sep 2020 14:56:11 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id D91AF5C1C4; Wed, 30 Sep 2020 14:56:09 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 17/20] s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT) Date: Wed, 30 Sep 2020 16:55:20 +0200 Message-Id: <20200930145523.71087-18-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:26:33 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 10 ++++++++ target/s390x/insn-data.def | 4 +++ target/s390x/translate_vx.c.inc | 26 +++++++++++++++++++ target/s390x/vec_fpu_helper.c | 45 +++++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index e4d60299dc..6b4a6c5185 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -327,6 +327,16 @@ DEF_HELPER_FLAGS_6(gvec_vfms32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, en DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfms128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnma32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnma32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnma128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnms32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnms32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_vfnms128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index da7fe6f21c..082de27298 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1259,6 +1259,10 @@ F(0xe78f, VFMA, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC) /* VECTOR FP MULTIPLY AND SUBTRACT */ F(0xe78e, VFMS, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC) +/* VECTOR FP NEGATIVE MULTIPLY AND ADD */ + F(0xe79f, VFNMA, VRR_e, VE, 0, 0, 0, 0, vfma, 0, IF_VEC) +/* VECTOR FP NEGATIVE MULTIPLY AND SUBTRACT */ + F(0xe79e, VFNMS, VRR_e, VE, 0, 0, 0, 0, vfma, 0, IF_VEC) /* VECTOR FP PERFORM SIGN OPERATION */ F(0xe7cc, VFPSO, VRR_a, V, 0, 0, 0, 0, vfpso, 0, IF_VEC) /* VECTOR FP SQUARE ROOT */ diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 5d31498cc1..40e452f552 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2884,6 +2884,32 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps *o) break; } break; + case 0x9f: + switch (fpf) { + case FPF_SHORT: + fn = se ? gen_helper_gvec_vfnma32s : gen_helper_gvec_vfnma32; + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfnma64s : gen_helper_gvec_vfnma64; + break; + default: + fn = gen_helper_gvec_vfnma128; + break; + } + break; + case 0x9e: + switch (fpf) { + case FPF_SHORT: + fn = se ? gen_helper_gvec_vfnms32s : gen_helper_gvec_vfnms32; + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vfnms64s : gen_helper_gvec_vfnms64; + break; + default: + fn = gen_helper_gvec_vfnms128; + break; + } + break; default: g_assert_not_reached(); } diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 0b25718365..92858c8c59 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -769,6 +769,51 @@ void HELPER(gvec_vfms##BITS##s)(void *v1, const void *v2, const void *v3, \ DEF_GVEC_VFMS_S(32) DEF_GVEC_VFMS_S(64) +#define DEF_GVEC_VFNMA(BITS) \ +void HELPER(gvec_vfnma##BITS)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vfma##BITS(v1, v2, v3, v4, env, false, float_muladd_negate_result, \ + GETPC()); \ +} +DEF_GVEC_VFNMA(32) +DEF_GVEC_VFNMA(64) +DEF_GVEC_VFNMA(128) + +#define DEF_GVEC_VFNMA_S(BITS) \ +void HELPER(gvec_vfnma##BITS##s)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vfma##BITS(v1, v2, v3, v4, env, true, float_muladd_negate_result, GETPC());\ +} +DEF_GVEC_VFNMA_S(32) +DEF_GVEC_VFNMA_S(64) + +#define DEF_GVEC_VFNMS(BITS) \ +void HELPER(gvec_vfnms##BITS)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vfma##BITS(v1, v2, v3, v4, env, false, \ + float_muladd_negate_c | float_muladd_negate_result, GETPC()); \ +} +DEF_GVEC_VFNMS(32) +DEF_GVEC_VFNMS(64) +DEF_GVEC_VFNMS(128) + +#define DEF_GVEC_VFNMS_S(BITS) \ +void HELPER(gvec_vfnms##BITS##s)(void *v1, const void *v2, const void *v3, \ + const void *v4, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + vfma##BITS(v1, v2, v3, v4, env, true, \ + float_muladd_negate_c | float_muladd_negate_result, GETPC()); \ +} +DEF_GVEC_VFNMS_S(32) +DEF_GVEC_VFNMS_S(64) + #define DEF_GVEC_VFSQ(BITS) \ void HELPER(gvec_vfsq##BITS)(void *v1, const void *v2, CPUS390XState *env, \ uint32_t desc) \ From patchwork Wed Sep 30 14:55:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 770B1C4727E for ; Wed, 30 Sep 2020 15:24:28 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AFBEE20759 for ; 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Wed, 30 Sep 2020 14:56:13 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id E58D85C1CF; Wed, 30 Sep 2020 14:56:11 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 18/20] s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM) Date: Wed, 30 Sep 2020 16:55:21 +0200 Message-Id: <20200930145523.71087-19-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:31:59 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For IEEE functions, we can reuse the softfloat implementations. For the other functions, implement it generically for 32bit/64bit/128bit - carefully taking care of all weird special cases according to the tables defined in the PoP. While we could add plenty of helpers to do the function selection at translation time, I don't feel like adding 20*(3+2) helpers for that. Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 10 ++ target/s390x/insn-data.def | 4 + target/s390x/translate_vx.c.inc | 44 +++++ target/s390x/vec_fpu_helper.c | 300 ++++++++++++++++++++++++++++++++ 4 files changed, 358 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 6b4a6c5185..b2f8ccc60d 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -317,6 +317,16 @@ DEF_HELPER_FLAGS_5(gvec_vfm32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfm128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmax32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmax32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmax64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmax64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmax128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmin32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmin32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmin64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmin64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_vfmin128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfma32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfma32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 082de27298..e9a3fdbc5a 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1253,6 +1253,10 @@ F(0xe7c4, VFLL, VRR_a, V, 0, 0, 0, 0, vfll, 0, IF_VEC) /* VECTOR LOAD ROUNDED */ F(0xe7c5, VFLR, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC) +/* VECTOR FP MAXIMUM */ + F(0xe7ef, VFMAX, VRR_c, VE, 0, 0, 0, 0, vfmax, 0, IF_VEC) +/* VECTOR FP MINIMUM */ + F(0xe7ee, VFMIN, VRR_c, VE, 0, 0, 0, 0, vfmax, 0, IF_VEC) /* VECTOR FP MULTIPLY */ F(0xe7e7, VFM, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC) /* VECTOR FP MULTIPLY AND ADD */ diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 40e452f552..e2bde426e0 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2842,6 +2842,50 @@ static DisasJumpType op_vfll(DisasContext *s, DisasOps *o) return DISAS_NEXT; } +static DisasJumpType op_vfmax(DisasContext *s, DisasOps *o) +{ + const bool se = extract32(get_field(s, m5), 3, 1); + const uint8_t fpf = get_field(s, m4); + const uint8_t m6 = get_field(s, m6); + gen_helper_gvec_3_ptr *fn; + + if (m6 == 5 || m6 == 6 || m6 == 7 || m6 > 13) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (fpf) { + case FPF_SHORT: + if (s->fields.op2 == 0xef) { + fn = se ? gen_helper_gvec_vfmax32s : gen_helper_gvec_vfmax32; + } else { + fn = se ? gen_helper_gvec_vfmin32s : gen_helper_gvec_vfmin32; + } + break; + case FPF_LONG: + if (s->fields.op2 == 0xef) { + fn = se ? gen_helper_gvec_vfmax64s : gen_helper_gvec_vfmax64; + } else { + fn = se ? gen_helper_gvec_vfmin64s : gen_helper_gvec_vfmin64; + } + break; + case FPF_EXT: + if (s->fields.op2 == 0xef) { + fn = gen_helper_gvec_vfmax128; + } else { + fn = gen_helper_gvec_vfmin128; + } + break; + default: + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), + cpu_env, m6, fn); + return DISAS_NEXT; +} + static DisasJumpType op_vfma(DisasContext *s, DisasOps *o) { const uint8_t m5 = get_field(s, m5); diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 92858c8c59..80c6b644bf 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -899,3 +899,303 @@ void HELPER(gvec_vftci##BITS##s)(void *v1, const void *v2, CPUS390XState *env, \ } DEF_GVEC_VFTCI_S(32) DEF_GVEC_VFTCI_S(64) + +typedef enum S390MinMaxType { + s390_minmax_java_math_min, + s390_minmax_java_math_max, + s390_minmax_c_macro_min, + s390_minmax_c_macro_max, + s390_minmax_fmin, + s390_minmax_fmax, + s390_minmax_cpp_alg_min, + s390_minmax_cpp_alg_max, +} S390MinMaxType; + +#define S390_MINMAX(BITS, TYPE) \ +static float##BITS TYPE##BITS(float##BITS a, float##BITS b, float_status *s) \ +{ \ + const bool zero_a = float##BITS##_is_infinity(a); \ + const bool zero_b = float##BITS##_is_infinity(b); \ + const bool inf_a = float##BITS##_is_infinity(a); \ + const bool inf_b = float##BITS##_is_infinity(b); \ + const bool nan_a = float##BITS##_is_infinity(a); \ + const bool nan_b = float##BITS##_is_infinity(b); \ + const bool neg_a = float##BITS##_is_neg(a); \ + const bool neg_b = float##BITS##_is_neg(b); \ + \ + if (unlikely(nan_a || nan_b)) { \ + const bool sig_a = float##BITS##_is_signaling_nan(a, s); \ + const bool sig_b = float##BITS##_is_signaling_nan(b, s); \ + \ + if (sig_a || sig_b) { \ + s->float_exception_flags |= float_flag_invalid; \ + } \ + switch (TYPE) { \ + case s390_minmax_java_math_min: \ + case s390_minmax_java_math_max: \ + if (sig_a) { \ + return float##BITS##_silence_nan(a, s); \ + } else if (sig_b) { \ + return float##BITS##_silence_nan(b, s); \ + } \ + /* fall through */ \ + case s390_minmax_fmin: \ + case s390_minmax_fmax: \ + return nan_a ? a : b; \ + case s390_minmax_c_macro_min: \ + case s390_minmax_c_macro_max: \ + s->float_exception_flags |= float_flag_invalid; \ + return b; \ + case s390_minmax_cpp_alg_min: \ + case s390_minmax_cpp_alg_max: \ + s->float_exception_flags |= float_flag_invalid; \ + return a; \ + default: \ + g_assert_not_reached(); \ + } \ + } else if (unlikely(inf_a && inf_b)) { \ + switch (TYPE) { \ + case s390_minmax_java_math_min: \ + return neg_a && !neg_b ? a : b; \ + case s390_minmax_java_math_max: \ + case s390_minmax_fmax: \ + case s390_minmax_cpp_alg_max: \ + return neg_a && !neg_b ? b : a; \ + case s390_minmax_c_macro_min: \ + case s390_minmax_cpp_alg_min: \ + return neg_b ? b : a; \ + case s390_minmax_c_macro_max: \ + return !neg_a && neg_b ? a : b; \ + case s390_minmax_fmin: \ + return !neg_a && neg_b ? b : a; \ + default: \ + g_assert_not_reached(); \ + } \ + } else if (unlikely(zero_a && zero_b)) { \ + switch (TYPE) { \ + case s390_minmax_java_math_min: \ + return neg_a && !neg_b ? a : b; \ + case s390_minmax_java_math_max: \ + case s390_minmax_fmax: \ + return neg_a && !neg_b ? b : a; \ + case s390_minmax_c_macro_min: \ + case s390_minmax_c_macro_max: \ + return b; \ + case s390_minmax_fmin: \ + return !neg_a && neg_b ? b : a; \ + case s390_minmax_cpp_alg_min: \ + case s390_minmax_cpp_alg_max: \ + return a; \ + default: \ + g_assert_not_reached(); \ + } \ + } \ + \ + /* We can process all remaining cases using simple comparison. */ \ + switch (TYPE) { \ + case s390_minmax_java_math_min: \ + case s390_minmax_c_macro_min: \ + case s390_minmax_fmin: \ + case s390_minmax_cpp_alg_min: \ + if (float##BITS##_le_quiet(a, b, s)) { \ + return a; \ + } \ + return b; \ + case s390_minmax_java_math_max: \ + case s390_minmax_c_macro_max: \ + case s390_minmax_fmax: \ + case s390_minmax_cpp_alg_max: \ + if (float##BITS##_le_quiet(a, b, s)) { \ + return b; \ + } \ + return a; \ + default: \ + g_assert_not_reached(); \ + } \ +} + +#define S390_MINMAX_ABS(BITS, TYPE) \ +static float##BITS TYPE##_abs##BITS(float##BITS a, float##BITS b, \ + float_status *s) \ +{ \ + return TYPE##BITS(float##BITS##_abs(a), float##BITS##_abs(b), s); \ +} + +S390_MINMAX(32, s390_minmax_java_math_min) +S390_MINMAX(32, s390_minmax_java_math_max) +S390_MINMAX(32, s390_minmax_c_macro_min) +S390_MINMAX(32, s390_minmax_c_macro_max) +S390_MINMAX(32, s390_minmax_fmin) +S390_MINMAX(32, s390_minmax_fmax) +S390_MINMAX(32, s390_minmax_cpp_alg_min) +S390_MINMAX(32, s390_minmax_cpp_alg_max) +S390_MINMAX_ABS(32, s390_minmax_java_math_min) +S390_MINMAX_ABS(32, s390_minmax_java_math_max) +S390_MINMAX_ABS(32, s390_minmax_c_macro_min) +S390_MINMAX_ABS(32, s390_minmax_c_macro_max) +S390_MINMAX_ABS(32, s390_minmax_fmin) +S390_MINMAX_ABS(32, s390_minmax_fmax) +S390_MINMAX_ABS(32, s390_minmax_cpp_alg_min) +S390_MINMAX_ABS(32, s390_minmax_cpp_alg_max) + +S390_MINMAX(64, s390_minmax_java_math_min) +S390_MINMAX(64, s390_minmax_java_math_max) +S390_MINMAX(64, s390_minmax_c_macro_min) +S390_MINMAX(64, s390_minmax_c_macro_max) +S390_MINMAX(64, s390_minmax_fmin) +S390_MINMAX(64, s390_minmax_fmax) +S390_MINMAX(64, s390_minmax_cpp_alg_min) +S390_MINMAX(64, s390_minmax_cpp_alg_max) +S390_MINMAX_ABS(64, s390_minmax_java_math_min) +S390_MINMAX_ABS(64, s390_minmax_java_math_max) +S390_MINMAX_ABS(64, s390_minmax_c_macro_min) +S390_MINMAX_ABS(64, s390_minmax_c_macro_max) +S390_MINMAX_ABS(64, s390_minmax_fmin) +S390_MINMAX_ABS(64, s390_minmax_fmax) +S390_MINMAX_ABS(64, s390_minmax_cpp_alg_min) +S390_MINMAX_ABS(64, s390_minmax_cpp_alg_max) + +S390_MINMAX(128, s390_minmax_java_math_min) +S390_MINMAX(128, s390_minmax_java_math_max) +S390_MINMAX(128, s390_minmax_c_macro_min) +S390_MINMAX(128, s390_minmax_c_macro_max) +S390_MINMAX(128, s390_minmax_fmin) +S390_MINMAX(128, s390_minmax_fmax) +S390_MINMAX(128, s390_minmax_cpp_alg_min) +S390_MINMAX(128, s390_minmax_cpp_alg_max) +S390_MINMAX_ABS(128, s390_minmax_java_math_min) +S390_MINMAX_ABS(128, s390_minmax_java_math_max) +S390_MINMAX_ABS(128, s390_minmax_c_macro_min) +S390_MINMAX_ABS(128, s390_minmax_c_macro_max) +S390_MINMAX_ABS(128, s390_minmax_fmin) +S390_MINMAX_ABS(128, s390_minmax_fmax) +S390_MINMAX_ABS(128, s390_minmax_cpp_alg_min) +S390_MINMAX_ABS(128, s390_minmax_cpp_alg_max) + +static vop32_3_fn const vfmax_fns32[16] = { + [0] = float32_maxnum, + [1] = s390_minmax_java_math_max32, + [2] = s390_minmax_c_macro_max32, + [3] = s390_minmax_cpp_alg_max32, + [4] = s390_minmax_fmax32, + [8] = float32_maxnummag, + [9] = s390_minmax_java_math_max_abs32, + [10] = s390_minmax_c_macro_max_abs32, + [11] = s390_minmax_cpp_alg_max_abs32, + [12] = s390_minmax_fmax_abs32, +}; + +static vop64_3_fn const vfmax_fns64[16] = { + [0] = float64_maxnum, + [1] = s390_minmax_java_math_max64, + [2] = s390_minmax_c_macro_max64, + [3] = s390_minmax_cpp_alg_max64, + [4] = s390_minmax_fmax64, + [8] = float64_maxnummag, + [9] = s390_minmax_java_math_max_abs64, + [10] = s390_minmax_c_macro_max_abs64, + [11] = s390_minmax_cpp_alg_max_abs64, + [12] = s390_minmax_fmax_abs64, +}; + +static vop128_3_fn const vfmax_fns128[16] = { + [0] = float128_maxnum, + [1] = s390_minmax_java_math_max128, + [2] = s390_minmax_c_macro_max128, + [3] = s390_minmax_cpp_alg_max128, + [4] = s390_minmax_fmax128, + [8] = float128_maxnummag, + [9] = s390_minmax_java_math_max_abs128, + [10] = s390_minmax_c_macro_max_abs128, + [11] = s390_minmax_cpp_alg_max_abs128, + [12] = s390_minmax_fmax_abs128, +}; + +#define DEF_GVEC_VFMAX(BITS) \ +void HELPER(gvec_vfmax##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3_fn fn = vfmax_fns##BITS[simd_data(desc)]; \ + \ + g_assert(fn); \ + vop##BITS##_3(v1, v2, v3, env, false, fn, GETPC()); \ +} +DEF_GVEC_VFMAX(32) +DEF_GVEC_VFMAX(64) +DEF_GVEC_VFMAX(128) + +#define DEF_GVEC_VFMAX_S(BITS) \ +void HELPER(gvec_vfmax##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3_fn fn = vfmax_fns##BITS[simd_data(desc)]; \ + \ + g_assert(fn); \ + vop##BITS##_3(v1, v2, v3, env, true, fn, GETPC()); \ +} +DEF_GVEC_VFMAX_S(32) +DEF_GVEC_VFMAX_S(64) + +static vop32_3_fn const vfmin_fns32[16] = { + [0] = float32_minnum, + [1] = s390_minmax_java_math_min32, + [2] = s390_minmax_c_macro_min32, + [3] = s390_minmax_cpp_alg_min32, + [4] = s390_minmax_fmin32, + [8] = float32_minnummag, + [9] = s390_minmax_java_math_min_abs32, + [10] = s390_minmax_c_macro_min_abs32, + [11] = s390_minmax_cpp_alg_min_abs32, + [12] = s390_minmax_fmin_abs32, +}; + +static vop64_3_fn const vfmin_fns64[16] = { + [0] = float64_minnum, + [1] = s390_minmax_java_math_min64, + [2] = s390_minmax_c_macro_min64, + [3] = s390_minmax_cpp_alg_min64, + [4] = s390_minmax_fmin64, + [8] = float64_minnummag, + [9] = s390_minmax_java_math_min_abs64, + [10] = s390_minmax_c_macro_min_abs64, + [11] = s390_minmax_cpp_alg_min_abs64, + [12] = s390_minmax_fmin_abs64, +}; + +static vop128_3_fn const vfmin_fns128[16] = { + [0] = float128_minnum, + [1] = s390_minmax_java_math_min128, + [2] = s390_minmax_c_macro_min128, + [3] = s390_minmax_cpp_alg_min128, + [4] = s390_minmax_fmin128, + [8] = float128_minnummag, + [9] = s390_minmax_java_math_min_abs128, + [10] = s390_minmax_c_macro_min_abs128, + [11] = s390_minmax_cpp_alg_min_abs128, + [12] = s390_minmax_fmin_abs128, +}; + +#define DEF_GVEC_VFMIN(BITS) \ +void HELPER(gvec_vfmin##BITS)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3_fn fn = vfmin_fns##BITS[simd_data(desc)]; \ + \ + g_assert(fn); \ + vop##BITS##_3(v1, v2, v3, env, false, fn, GETPC()); \ +} +DEF_GVEC_VFMIN(32) +DEF_GVEC_VFMIN(64) +DEF_GVEC_VFMIN(128) + +#define DEF_GVEC_VFMIN_S(BITS) \ +void HELPER(gvec_vfmin##BITS##s)(void *v1, const void *v2, const void *v3, \ + CPUS390XState *env, uint32_t desc) \ +{ \ + vop##BITS##_3_fn fn = vfmin_fns##BITS[simd_data(desc)]; \ + \ + g_assert(fn); \ + vop##BITS##_3(v1, v2, v3, env, true, fn, GETPC()); \ +} +DEF_GVEC_VFMIN_S(32) +DEF_GVEC_VFMIN_S(64) From patchwork Wed Sep 30 14:55:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 272343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10AD7C4727E for ; Wed, 30 Sep 2020 15:07:28 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 899F3206FC for ; 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/****** END FEATURE DEFS ******/ From patchwork Wed Sep 30 14:55:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 304009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5B74C4727E for ; Wed, 30 Sep 2020 15:26:28 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D0EB2071E for ; Wed, 30 Sep 2020 15:26:28 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Cc: Christian Borntraeger Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- hw/s390x/s390-virtio-ccw.c | 2 ++ target/s390x/cpu_models.c | 4 ++-- target/s390x/gen-features.c | 15 +++++++++------ 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 3106bbea33..5f9931d509 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -812,7 +812,9 @@ DEFINE_CCW_MACHINE(5_2, "5.2", true); static void ccw_machine_5_1_instance_options(MachineState *machine) { + static const S390FeatInit qemu_cpu_feat = { S390_FEAT_LIST_QEMU_V5_1 }; ccw_machine_5_2_instance_options(machine); + s390_set_qemu_cpu_model(0x2964, 13, 2, qemu_cpu_feat); } static void ccw_machine_5_1_class_options(MachineClass *mc) diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index b97e9596ab..c613ea87e8 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -88,8 +88,8 @@ static S390CPUDef s390_cpu_defs[] = { CPUDEF_INIT(0x8562, 15, 1, 47, 0x08000000U, "gen15b", "IBM 8562 GA1"), }; -#define QEMU_MAX_CPU_TYPE 0x2964 -#define QEMU_MAX_CPU_GEN 13 +#define QEMU_MAX_CPU_TYPE 0x3906 +#define QEMU_MAX_CPU_GEN 14 #define QEMU_MAX_CPU_EC_GA 2 static const S390FeatInit qemu_max_cpu_feat_init = { S390_FEAT_LIST_QEMU_MAX }; static S390FeatBitmap qemu_max_cpu_feat; diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c index a7bad36f35..017b8ac95e 100644 --- a/target/s390x/gen-features.c +++ b/target/s390x/gen-features.c @@ -704,23 +704,25 @@ static uint16_t qemu_V4_1[] = { S390_FEAT_VECTOR, }; -static uint16_t qemu_LATEST[] = { +static uint16_t qemu_V5_1[] = { S390_FEAT_ACCESS_EXCEPTION_FS_INDICATION, S390_FEAT_SIDE_EFFECT_ACCESS_ESOP2, S390_FEAT_ESOP, }; -/* add all new definitions before this point */ -static uint16_t qemu_MAX[] = { - /* generates a dependency warning, leave it out for now */ - S390_FEAT_MSA_EXT_5, - /* features introduced after the z13 */ +static uint16_t qemu_LATEST[] = { S390_FEAT_INSTRUCTION_EXEC_PROT, S390_FEAT_MISC_INSTRUCTION_EXT2, S390_FEAT_MSA_EXT_8, S390_FEAT_VECTOR_ENH, }; +/* add all new definitions before this point */ +static uint16_t qemu_MAX[] = { + /* generates a dependency warning, leave it out for now */ + S390_FEAT_MSA_EXT_5, +}; + /****** END FEATURE DEFS ******/ #define _YEARS "2016" @@ -837,6 +839,7 @@ static FeatGroupDefSpec QemuFeatDef[] = { QEMU_FEAT_INITIALIZER(V3_1), QEMU_FEAT_INITIALIZER(V4_0), QEMU_FEAT_INITIALIZER(V4_1), + QEMU_FEAT_INITIALIZER(V5_1), QEMU_FEAT_INITIALIZER(LATEST), QEMU_FEAT_INITIALIZER(MAX), };