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[209.51.188.17]) by mx.google.com with ESMTPS id l206si12404246ybb.76.2020.09.14.20.12.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 Sep 2020 20:12:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WCB9iQFe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kI1Os-0000Fx-95 for patch@linaro.org; Mon, 14 Sep 2020 23:12:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kI1O6-0000Dq-CK for qemu-devel@nongnu.org; Mon, 14 Sep 2020 23:12:10 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:32933) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kI1O2-0001fV-65 for qemu-devel@nongnu.org; Mon, 14 Sep 2020 23:12:10 -0400 Received: by mail-pl1-x636.google.com with SMTP id d19so594194pld.0 for ; Mon, 14 Sep 2020 20:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SVvavflqwBHyVfPeo3WkPtz2sD2s7cZLSNZLl+ZfUO0=; b=WCB9iQFeDkSIxhrOaxldsUCpTkakmnF3WXhKhUR08k7N3Cz8gNPyiQAK+sdNGusu4x M81u8VLniD7W7iDXb6O19pQlWstd2YyJcebF+nNjdl4XFMVj5/w63fzeXYFSxpbwFbNQ OJJj0wIIuBTTwoUUAW7zfFgdiEplas1GBENkhCwnD+5dFFlr2Kr11zfuMedEI9Gs4rFw 3B2LhcsPm/K+6nZncZ4oATmTNPsQJN9n42CuEvIkoaTBtYE3pbs5vYJ53SxwJFH6nJ77 GEwmkacaZDZf830deyyIFxZOxDrNMXnjCQVM/TWmIps8GxYqbr17dMQqSnVC+LnyOgAQ Xyhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SVvavflqwBHyVfPeo3WkPtz2sD2s7cZLSNZLl+ZfUO0=; b=U6qw56JyydhkHrcUb4RAE7WojIYYb5U7KSHoJUyWBFBO12hDinzLvcik+EV0SRZC3u vwpHIem+dnbEAAv8e2N+O8Wuu+Ksq8NoIjnq5spqTAUER4CBkxRFrRz52tUk+fZIe4so o7OVPgr29mJbk3H+Mcs6kYPcXjgAa+Y+dQaIUbiLtRrASXZ7QIUM+PeWi/P7T3lpRcd+ LKtKqcHtKquduyGsy/6xKh0h0JQhlVYkjelNW5Edn7e3P74uN1s+SAc7ClLdfdveXkNa KpBVdewYC4v3EmtGMlxjcosHM5TxRU24KkMGytFyNCqa8QRBf7EiUAxaSPxVGkn3Z9En h3zA== X-Gm-Message-State: AOAM531fBR+JiP5gK465tOSarmmJVuQVf7ozsh5ZcD1uUuJ0mxH06bki dlZGIBhI6PcRnJKBcUCKstzq X-Received: by 2002:a17:902:e901:b029:d1:920c:bf93 with SMTP id k1-20020a170902e901b02900d1920cbf93mr16620603pld.21.1600139524697; Mon, 14 Sep 2020 20:12:04 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id g23sm11551776pfh.133.2020.09.14.20.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 20:12:04 -0700 (PDT) From: Haibo Xu To: drjones@redhat.com, richard.henderson@linaro.org Subject: [PATCH v3 01/12] update Linux headers with new vSPE macros Date: Tue, 15 Sep 2020 03:11:37 +0000 Message-Id: <35e621987cca029c207c9ef68032364d2b765cf7.1600135462.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=haibo.xu@linaro.org; helo=mail-pl1-x636.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Haibo Xu --- linux-headers/asm-arm64/kvm.h | 4 ++++ linux-headers/linux/kvm.h | 2 ++ 2 files changed, 6 insertions(+) -- 2.17.1 diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index 9e34f0f875..802319ee02 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -106,6 +106,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ +#define KVM_ARM_VCPU_SPE_V1 7 /* Support guest SPEv1 */ struct kvm_vcpu_init { __u32 target; @@ -334,6 +335,9 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 +#define KVM_ARM_VCPU_SPE_V1_CTRL 3 +#define KVM_ARM_VCPU_SPE_V1_IRQ 0 +#define KVM_ARM_VCPU_SPE_V1_INIT 1 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_VCPU2_SHIFT 28 diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index a28c366737..35ef0ae842 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1031,6 +1031,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_SECURE_GUEST 181 #define KVM_CAP_HALT_POLL 182 #define KVM_CAP_ASYNC_PF_INT 183 +#define KVM_CAP_ARM_SPE_V1 184 #ifdef KVM_CAP_IRQ_ROUTING @@ -1671,6 +1672,7 @@ struct kvm_assigned_msix_entry { #define KVM_ARM_DEV_EL1_VTIMER (1 << 0) #define KVM_ARM_DEV_EL1_PTIMER (1 << 1) #define KVM_ARM_DEV_PMU (1 << 2) +#define KVM_ARM_DEV_SPE (1 << 3) struct kvm_hyperv_eventfd { __u32 conn_id; From patchwork Tue Sep 15 03:11:38 2020 Content-Type: text/plain; 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Mon, 14 Sep 2020 20:12:06 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id g23sm11551776pfh.133.2020.09.14.20.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 20:12:05 -0700 (PDT) From: Haibo Xu To: drjones@redhat.com, richard.henderson@linaro.org Subject: [PATCH v3 02/12] target/arm/kvm: spe: Add helper to detect SPE when using KVM Date: Tue, 15 Sep 2020 03:11:38 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=haibo.xu@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Andrew Jones Reviewed-by: Richard Henderson Signed-off-by: Haibo Xu --- target/arm/kvm.c | 5 +++++ target/arm/kvm_arm.h | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8bb7318378..58f991e890 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -214,6 +214,11 @@ bool kvm_arm_pmu_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); } +bool kvm_arm_spe_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_SPE_V1); +} + int kvm_arm_get_max_vm_ipa_size(MachineState *ms) { KVMState *s = KVM_STATE(ms->accelerator); diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index adb38514bf..f79655674e 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -283,6 +283,14 @@ bool kvm_arm_aarch32_supported(void); */ bool kvm_arm_pmu_supported(void); +/** + * kvm_arm_spe_supported: + * + * Returns: true if the KVM VCPU can enable its SPE + * and false otherwise. + */ +bool kvm_arm_spe_supported(void); + /** * kvm_arm_sve_supported: * @@ -366,6 +374,11 @@ static inline bool kvm_arm_pmu_supported(void) return false; } +static inline bool kvm_arm_spe_supported(void) +{ + return false; +} + static inline bool kvm_arm_sve_supported(void) { return false; From patchwork Tue Sep 15 03:11:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 273759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72836C43461 for ; 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Mon, 14 Sep 2020 20:12:07 -0700 (PDT) From: Haibo Xu To: drjones@redhat.com, richard.henderson@linaro.org Subject: [PATCH v3 03/12] target/arm/cpu: spe: Add an option to turn on/off vSPE support Date: Tue, 15 Sep 2020 03:11:39 +0000 Message-Id: <90fec9ff0da7595f52caccf052c019d9359c8724.1600135462.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=haibo.xu@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Adds a spe=[on/off] option to enable/disable vSPE support in guest vCPU. Reviewed-by: Andrew Jones Signed-off-by: Haibo Xu --- target/arm/cpu.c | 6 ++++++ target/arm/cpu.h | 13 ++++++++++++ target/arm/cpu64.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c179e0752d..f211958eaa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1310,6 +1310,12 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) error_propagate(errp, local_err); return; } + + arm_cpu_spe_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } } } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a1c7d8ebae..baf2bbcee8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "qapi/qapi-types-common.h" /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -196,9 +197,11 @@ typedef struct { #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_spe_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } +static inline void arm_cpu_spe_finalize(ARMCPU *cpu, Error **errp) { } #endif typedef struct ARMVectorReg { @@ -829,6 +832,8 @@ struct ARMCPU { bool has_el3; /* CPU has PMU (Performance Monitor Unit) */ bool has_pmu; + /* CPU has SPE (Statistical Profiling Extension) */ + OnOffAuto has_spe; /* CPU has VFP */ bool has_vfp; /* CPU has Neon */ @@ -3869,6 +3874,14 @@ static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } +/* + * Currently we don't differentiate between the ARMv8.2-SPE and ARMv8.3-SPE. + */ +static inline bool isar_feature_aa64_spe(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMSVER) != 0; +} + static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3c2b3d9599..4997c4a3c0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -572,6 +572,55 @@ void aarch64_add_sve_properties(Object *obj) } } +void arm_cpu_spe_finalize(ARMCPU *cpu, Error **errp) +{ + uint64_t t; + uint32_t value = 0; + + if (cpu->has_spe == ON_OFF_AUTO_AUTO) { + if (kvm_enabled() && kvm_arm_spe_supported()) { + cpu->has_spe = ON_OFF_AUTO_ON; + } else { + cpu->has_spe = ON_OFF_AUTO_OFF; + } + } else if (cpu->has_spe == ON_OFF_AUTO_ON) { + if (!kvm_enabled() || !kvm_arm_spe_supported()) { + error_setg(errp, "'spe' cannot be enabled on this host"); + return; + } + } + + /* + * According to the ARM ARM, the ID_AA64DFR0[PMSVER] currently + * support 3 values: + * + * 0b0000: SPE not implemented + * 0b0001: ARMv8.2-SPE implemented + * 0b0010: ARMv8.3-SPE implemented + * + * But the kernel KVM API didn't expose all these 3 values, and + * we can only get whether the SPE feature is supported or not. + * So here we just set the PMSVER to 1 if this feature was supported. + */ + if (cpu->has_spe == ON_OFF_AUTO_ON) { + value = 1; + } + + t = cpu->isar.id_aa64dfr0; + t = FIELD_DP64(t, ID_AA64DFR0, PMSVER, value); + cpu->isar.id_aa64dfr0 = t; +} + +static bool arm_spe_get(Object *obj, Error **errp) +{ + return ARM_CPU(obj)->has_spe != ON_OFF_AUTO_OFF; +} + +static void arm_spe_set(Object *obj, bool value, Error **errp) +{ + ARM_CPU(obj)->has_spe = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -721,6 +770,9 @@ static void aarch64_max_initfn(Object *obj) aarch64_add_sve_properties(obj); object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, NULL, NULL); + + cpu->has_spe = ON_OFF_AUTO_AUTO; + object_property_add_bool(obj, "spe", arm_spe_get, arm_spe_set); } static const ARMCPUInfo aarch64_cpus[] = { From patchwork Tue Sep 15 03:11:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 273756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28E9DC43461 for ; Tue, 15 Sep 2020 03:17:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 90DB820672 for ; Tue, 15 Sep 2020 03:17:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lReM+xXe" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 90DB820672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:37056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kI1TK-0000Hk-Di for qemu-devel@archiver.kernel.org; Mon, 14 Sep 2020 23:17:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kI1O8-0000H8-MJ for qemu-devel@nongnu.org; Mon, 14 Sep 2020 23:12:12 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:44472) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kI1O6-0001h4-5U for qemu-devel@nongnu.org; Mon, 14 Sep 2020 23:12:12 -0400 Received: by mail-pf1-x42f.google.com with SMTP id o20so1089544pfp.11 for ; Mon, 14 Sep 2020 20:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9QKIG2CP5FsAJO1K1yLLKcM8WhKJpvUJh/YJzIciQaE=; b=lReM+xXelGsNPF4vWL0t5TX+kwVrfj1L95xQ0vopMAc4L0dPqxD7n6zkpBUwiV/Dz3 22euqP3i6uymqRzuL3XM1y/J5AfJDdY15Bx7nmzor2pTp1fd/bOFSm3Ei8hZs1SN+pbB iVcRL/FbS7DT+dhaFvy6SfnWXrp+s2UZRlA+rZnGvd+GJ3IXM2pTPCJbZltuRHDouEBm M8hL1vF4+al0ND+0T0vP/yjpM9Blpwkp9wXUnYYbCJD2JqxUHE0h3Xt1m/95xyCWuz+f Ifiit+RPZYHGPrL6MnXkCODG1XsNnoti8rMfNa3GpTrQhn275mxR+7o7DNGJ2//FEBeo 6kwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9QKIG2CP5FsAJO1K1yLLKcM8WhKJpvUJh/YJzIciQaE=; b=Hs2rhEem0hMv9+2okDJxtd9r26xbklnUIiHGgdXdEzBO12rbErt1EY4sbMXdoa7pge s58J7CnQ6DfDqwr+5jfsqx2LV8dVjLzqE4hdZ/vsZhcfOgwqBFQ5NWE9VojTZW4BK5zm 7IXBG/JAWACgtTjb9lcqgtOZBTy4/HTR61QSo9r93FQTk6fq1Ag5Q4EhwuN35usfjbxp FQvYifwm4d7qDohkEFqw4+ziwlu+Dthaqy21YJiS66r1O3qgABpShqrN8PVwIeCgLQOv ywSlPrTygZzcOuZRngz1rfWU5JX8G/bzpU+fvWELcP8S8x7maYV8f3YEF18yjHsrivW+ Bnjg== X-Gm-Message-State: AOAM531bnf+L/ocngyynoxgYSKsvZVFe/FhwgICJmNmiLsgfr6aZsqZh Dn6XYg6eqUhPAFM2ge3Sehktk0BIBzqA5BU= X-Google-Smtp-Source: ABdhPJwzcELHdUBZj0OKiWALwi4hE/VYrFhdNnfmm1roO/9PdowVnggBaW3eqXLDeuZO+qm9o/A9YA== X-Received: by 2002:a63:5043:: with SMTP id q3mr12880104pgl.293.1600139528926; Mon, 14 Sep 2020 20:12:08 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id g23sm11551776pfh.133.2020.09.14.20.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 20:12:08 -0700 (PDT) From: Haibo Xu To: drjones@redhat.com, richard.henderson@linaro.org Subject: [PATCH v3 04/12] target/arm: spe: Only enable SPE from 5.2 compat machines. Date: Tue, 15 Sep 2020 03:11:40 +0000 Message-Id: <6d88497a83105b3317bb39ce26d763b729a426eb.1600135462.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=haibo.xu@linaro.org; helo=mail-pf1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Andrew Jones Signed-off-by: Haibo Xu --- hw/arm/virt.c | 7 +++++++ include/hw/arm/virt.h | 1 + 2 files changed, 8 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index acf9bfbece..3f6d26c531 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1830,6 +1830,10 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "pmu", false, NULL); } + if (vmc->no_spe && object_property_find(cpuobj, "spe", NULL)) { + object_property_set_bool(cpuobj, "spe", false, NULL); + } + if (object_property_find(cpuobj, "reset-cbar", NULL)) { object_property_set_int(cpuobj, "reset-cbar", vms->memmap[VIRT_CPUPERIPHS].base, @@ -2553,8 +2557,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2) static void virt_machine_5_1_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_5_2_options(mc); compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); + vmc->no_spe = true; } DEFINE_VIRT_MACHINE(5, 1) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index dff67e1bef..72c269aaa5 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -126,6 +126,7 @@ typedef struct { bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ bool kvm_no_adjvtime; bool acpi_expose_flash; + bool no_spe; } VirtMachineClass; typedef struct { From patchwork Tue Sep 15 03:11:41 2020 Content-Type: text/plain; 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Mon, 14 Sep 2020 20:12:10 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id g23sm11551776pfh.133.2020.09.14.20.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 20:12:09 -0700 (PDT) From: Haibo Xu To: drjones@redhat.com, richard.henderson@linaro.org Subject: [PATCH v3 05/12] target/arm/kvm: spe: Unify device attr operation helper Date: Tue, 15 Sep 2020 03:11:41 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=haibo.xu@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Rename kvm_arm_pmu_set_attr() to kvm_arm_set_device_attr(), So both the vPMU and vSPE device can share the same API. Signed-off-by: Andrew Jones Signed-off-by: Haibo Xu --- target/arm/kvm64.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ef1e960285..8ffd31ffdf 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -397,19 +397,20 @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr) return NULL; } -static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr) +static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, + const char *name) { int err; err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); if (err != 0) { - error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err)); + error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); return false; } err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); if (err != 0) { - error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err)); + error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); return false; } @@ -426,7 +427,7 @@ void kvm_arm_pmu_init(CPUState *cs) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_pmu_set_attr(cs, &attr)) { + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { error_report("failed to init PMU"); abort(); } @@ -443,7 +444,7 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_pmu_set_attr(cs, &attr)) { + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { error_report("failed to set irq for PMU"); abort(); } From patchwork Tue Sep 15 03:11:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 303965 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2156792ilg; Mon, 14 Sep 2020 20:14:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYWWUUmEEnAl0N9e/msat5QPiwP+Vpvtgk/RfD0mUDp6S/OBBpqQDWih+V6QLjCFRBZNp0 X-Received: by 2002:a5b:bd0:: with SMTP id c16mr5259272ybr.290.1600139688585; Mon, 14 Sep 2020 20:14:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600139688; cv=none; d=google.com; s=arc-20160816; b=H2d9HNYINMDk991gdeSh7bEUdZj8yGBhFclZEo3nijo1BhZR6RQy9ofBGJG7ZslrLZ /naiUaARwSHe570SRTKnaagk3sDq/fmXp680mJCm2I895rsVcGkH6msE3oDYzJtmsnSl pNzDKJ1OnJ5zEfTh9MBarKwH+Th4vSYcfqJOZ6C69Ddxy7wGRMtrJcMLqGgxCONrjoJb iUDV1Zu2Pv2RQH7OgXOYM1Qc818UN7dyWFS8qmd16nm1rGMrpSENGpc10qkigvT7hMTV cfw7bxMUjPQnFRkc53W5P09VvfToenPE86uOc1w+3EJhXsHlJSF6VDTRWGqmUB/R3Qd0 gf4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=W+V3obnXTS2moUn5807WDrMB34yhPyYZkE7Y60hl+S0=; b=Wcb8IKyMbXI+pIVme8dHCJ1Bfd6FhfRfVK+0i04A/VUkqxJ9F5ipnCOnGzdvYjh5Rc bvHaym+4MfuwjaWOHqpNgpGUKIK2PW/vpjLFPzjF4+uufXcFxv62ezIITJnuVTVtVeDg 3smY3azGDJin+CYhZfN3JxFiyo2YsVVQBno6Ur1jJ/sgEaXy5M/hTbVrmstWmEzfMfDM Y1w6RiHhTgP/RvPlMh6+cmaRn8yDYqmyW9qaRuWUZAGTkTOjylYmjBqnEPPy2f2zqB9b a3zy6uY+8OBS82q+GC0cviB6XMg1dn5WIlR31h/q1IPKwSa9wCDCWm/N1kWarD/7A9tb NxQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ifSRseTT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Andrew Jones Signed-off-by: Haibo Xu --- target/arm/kvm64.c | 33 +++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 5 +++++ 2 files changed, 38 insertions(+) -- 2.17.1 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 8ffd31ffdf..5a2032fc9e 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -450,6 +450,39 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) } } +void kvm_arm_spe_init(CPUState *cs) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_SPE_V1_CTRL, + .attr = KVM_ARM_VCPU_SPE_V1_INIT, + }; + + if (!ARM_CPU(cs)->has_spe) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "SPE")) { + error_report("failed to init SPE"); + abort(); + } +} + +void kvm_arm_spe_set_irq(CPUState *cs, int irq) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_SPE_V1_CTRL, + .addr = (intptr_t)&irq, + .attr = KVM_ARM_VCPU_SPE_V1_IRQ, + }; + + if (!ARM_CPU(cs)->has_spe) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "SPE")) { + error_report("failed to set irq for SPE"); + abort(); + } +} + static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) { uint64_t ret; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index f79655674e..bb155322eb 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -348,6 +348,8 @@ int kvm_arm_vgic_probe(void); void kvm_arm_pmu_set_irq(CPUState *cs, int irq); void kvm_arm_pmu_init(CPUState *cs); +void kvm_arm_spe_set_irq(CPUState *cs, int irq); +void kvm_arm_spe_init(CPUState *cs); int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); #else @@ -397,6 +399,9 @@ static inline int kvm_arm_vgic_probe(void) static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} static inline void kvm_arm_pmu_init(CPUState *cs) {} +static inline void kvm_arm_spe_set_irq(CPUState *cs, int irq) {} +static inline void kvm_arm_spe_init(CPUState *cs) {} + static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {} static inline void kvm_arm_get_virtual_time(CPUState *cs) {} From patchwork Tue Sep 15 03:11:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 303969 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2158118ilg; Mon, 14 Sep 2020 20:17:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwx/4+tepmGSBkYKwWGGbVP2X32m4WxvrZLJ4trwS//Oef51WbWesCwWaQtzK1NlRx0U4cw X-Received: by 2002:ad4:5a44:: with SMTP id ej4mr15907797qvb.42.1600139832359; Mon, 14 Sep 2020 20:17:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600139832; cv=none; d=google.com; s=arc-20160816; b=sqMNJCSLDpcxrGjchMErM+zFe4Xus9mNeLheZrctuC62KqhcKfHkr1HsdagyoYklpn NtkeklhHnUmXoySvERKtlFQP+LsYKoz+icaxFt33lVJ5KGBOq0wvEcD3JEo4hduyI2UX h+1wrLXfAacCllXL0bn3Zq+E68GTpWzaR0m5REKPfhq1I/hMdbjHB3wQKixhCVp32Z3u CPT9k+W7pbIFTULFLGbXB98vniYeHTvQp0Rkxr7lmeYZYxLSFDHYwIB6bV3lz/W1xpSy l9TdcbzitY8f8Qo5ohen9UE8mg3+iMGtCqaXbRi8xXWwsxUwzmldsMjllR6QnyVLEMTQ ikVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qMrkJnwKfU2uQTjfoYTo9jsqV6eugUKH6001G6BMUT0=; b=z3AYGLNbY0qxC3G4t7T3dqr4+YiM8sej0hYhiSX/svIKQsw0KkAg2YIQ7hmn3h7SMX 08Mh0qz2aH/mpMvcRcw0L9RiZqJyclu3NVhynYpM7NKbpGa7dDyWQqdxV1bmGJSpUUAz 0t9cDZUe9/IHFZEj2W782C8Ci4DlN1ZRXL3NXqleZo9ES86T0Q/BcU4817u5TOV32Frn cBtbJnAfWdSiTAVwAS8IszaA8zG3NcZyr27x7LYbHe7I6qIf11BP37J43Yla8cXyzI8s iD6FLGOU4XPj9+paXZu+Zl+0Egvctp6WnHOuy3j+KecFamJqPzmhi1fW+YO19DNpGUkH GVOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z86x1mBE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones We'll add more to this new function in coming patches so we also state the gic must be created and call it below create_gic(). No functional change intended. Signed-off-by: Andrew Jones Reviewed-by: Peter Maydell --- hw/arm/virt.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3f6d26c531..2ffcb073af 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1672,6 +1672,26 @@ static void finalize_gic_version(VirtMachineState *vms) } } +static void virt_cpu_post_init(VirtMachineState *vms) +{ + bool aarch64; + + aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); + + if (!kvm_enabled()) { + if (aarch64 && vms->highmem) { + int requested_pa_size = 64 - clz64(vms->highest_gpa); + int pamax = arm_pamax(ARM_CPU(first_cpu)); + + if (pamax < requested_pa_size) { + error_report("VCPU supports less PA bits (%d) than requested " + "by the memory map (%d)", pamax, requested_pa_size); + exit(1); + } + } + } +} + static void machvirt_init(MachineState *machine) { VirtMachineState *vms = VIRT_MACHINE(machine); @@ -1890,22 +1910,6 @@ static void machvirt_init(MachineState *machine) fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); - if (!kvm_enabled()) { - ARMCPU *cpu = ARM_CPU(first_cpu); - bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); - - if (aarch64 && vms->highmem) { - int requested_pa_size, pamax = arm_pamax(cpu); - - requested_pa_size = 64 - clz64(vms->highest_gpa); - if (pamax < requested_pa_size) { - error_report("VCPU supports less PA bits (%d) than requested " - "by the memory map (%d)", pamax, requested_pa_size); - exit(1); - } - } - } - memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, machine->ram); if (machine->device_memory) { @@ -1917,6 +1921,8 @@ static void machvirt_init(MachineState *machine) create_gic(vms); + virt_cpu_post_init(vms); + fdt_add_pmu_nodes(vms); create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); From patchwork Tue Sep 15 03:11:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 303972 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2159129ilg; Mon, 14 Sep 2020 20:18:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxlSpFKs5Tefs4qNR4MlYdq7dAip5n7JN01aNW4eTlxUePZUEhUH6WU/lBOgdjurV3u33DF X-Received: by 2002:a37:78b:: with SMTP id 133mr15579003qkh.107.1600139938319; Mon, 14 Sep 2020 20:18:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600139938; cv=none; d=google.com; s=arc-20160816; b=G2EdBuqL2YHRfcdv5vYqwmqM2VmWYm07h4alu8yR68ZdtOf3VdGwpkznOeXqeFSPsQ vTPbtnaAGwFj/ljiZFoUH1CJ6FS1jR4U+iNt+L4WNQJn53XEnk6tWFojaX2WMoDZ3hhH wRdlURr85Yv5CTkMHe2VbhiVEBd6KF4XHdNk8GItbdZWHLRuxsz2e5bjnFWN88a+W0ps +7yKKoo17InkWB87dD9jqbM4ZDF8IT9hIV2kfSXKxAV1ByKtsGZkvUMP/BnCsy3X0b6/ XPMIlsgAWw/99srd5f93wGpPya1Mnm9fKclkk688jPLbN8OpMWoyg0y3xcMuRORkhb7C BdVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aCZKhsO2QByw5JkTztWmspLBY6hhifDHq83bnO4MirI=; b=b4YOz4+txVggg75XxF1HVbkmr5pCvr7msvV5r5PRWb3PizyQ+URn8HfP7qiY9CZu8j ksj+p9qwvyOEwUxB/jloUqbTzYeR8tKjhp+arVTuDJ1gPNf574H2c4RVJBX3RvOsDvtk WuLBt0GCB6CvsJuvGW1qRK+TU3VB+ZdTQZ6A/HKMf1PV0PrrVooYDuLyZVtuANAhKjxM LPEL2x6XqprIY7ZbeQdM3CTkFhGtZiqQsHM1NB4nanl6GJri2YwznIWZyCc1rTI7Dw/J jh11unD+d27WCPcwy5Y+A5lknP3spPbWv6RF/Hgs+aVWq12i+/lXSAZnHCl04xcf4KCZ N1GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UbhBHfdH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Move the KVM PMU setup part of fdt_add_pmu_nodes() to virt_cpu_post_init(), which is a more appropriate location. Now fdt_add_pmu_nodes() is also named more appropriately, because it no longer does anything but fdt node creation. No functional change intended. Signed-off-by: Andrew Jones Reviewed-by: Peter Maydell --- hw/arm/virt.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2ffcb073af..6bacfb668d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -521,21 +521,12 @@ static void fdt_add_gic_node(VirtMachineState *vms) static void fdt_add_pmu_nodes(const VirtMachineState *vms) { - CPUState *cpu; - ARMCPU *armcpu; + ARMCPU *armcpu = ARM_CPU(first_cpu); uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; - CPU_FOREACH(cpu) { - armcpu = ARM_CPU(cpu); - if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { - return; - } - if (kvm_enabled()) { - if (kvm_irqchip_in_kernel()) { - kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); - } - kvm_arm_pmu_init(cpu); - } + if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { + assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); + return; } if (vms->gic_version == VIRT_GIC_VERSION_2) { @@ -544,7 +535,6 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) (1 << vms->smp_cpus) - 1); } - armcpu = ARM_CPU(qemu_get_cpu(0)); qemu_fdt_add_subnode(vms->fdt, "/pmu"); if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { const char compat[] = "arm,armv8-pmuv3"; @@ -1674,11 +1664,23 @@ static void finalize_gic_version(VirtMachineState *vms) static void virt_cpu_post_init(VirtMachineState *vms) { - bool aarch64; + bool aarch64, pmu; + CPUState *cpu; aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); + pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); - if (!kvm_enabled()) { + if (kvm_enabled()) { + CPU_FOREACH(cpu) { + if (pmu) { + assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); + if (kvm_irqchip_in_kernel()) { + kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); + } + kvm_arm_pmu_init(cpu); + } + } + } else { if (aarch64 && vms->highmem) { int requested_pa_size = 64 - clz64(vms->highest_gpa); int pamax = arm_pamax(ARM_CPU(first_cpu)); From patchwork Tue Sep 15 03:11:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 273755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31CCCC43461 for ; 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Mon, 14 Sep 2020 20:12:14 -0700 (PDT) From: Haibo Xu To: drjones@redhat.com, richard.henderson@linaro.org Subject: [PATCH v3 09/12] hw/arm/virt: spe: Add vSPE device and corresponding interrupt support Date: Tue, 15 Sep 2020 03:11:45 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=haibo.xu@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a virtual SPE device for virt machine while using PPI 5 for SPE overflow interrupt number which has already selected in kvmtool for the in-kernel irqchip support. Reviewed-by: Andrew Jones Signed-off-by: Haibo Xu --- hw/arm/virt-acpi-build.c | 3 +++ hw/arm/virt.c | 43 ++++++++++++++++++++++++++++++++++++- include/hw/acpi/acpi-defs.h | 3 +++ include/hw/arm/virt.h | 1 + target/arm/cpu.c | 2 ++ target/arm/cpu.h | 2 ++ 6 files changed, 53 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9efd7a3881..3fd80fda53 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -665,6 +665,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); } + if (cpu_isar_feature(aa64_spe, armcpu)) { + gicc->spe_interrupt = cpu_to_le32(PPI(VIRTUAL_SPE_IRQ)); + } if (vms->virt) { gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6bacfb668d..ee0831922b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -545,6 +545,32 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) } } +static void fdt_add_spe_nodes(const VirtMachineState *vms) +{ + ARMCPU *armcpu = ARM_CPU(first_cpu); + uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; + + if (!cpu_isar_feature(aa64_spe, armcpu)) { + assert(!object_property_get_bool(OBJECT(armcpu), "spe", NULL)); + return; + } + + if (vms->gic_version == VIRT_GIC_VERSION_2) { + irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, + GIC_FDT_IRQ_PPI_CPU_WIDTH, + (1 << vms->smp_cpus) - 1); + } + + qemu_fdt_add_subnode(vms->fdt, "/spe"); + if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { + const char compat[] = "arm,statistical-profiling-extension-v1"; + qemu_fdt_setprop(vms->fdt, "/spe", "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_cells(vms->fdt, "/spe", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_SPE_IRQ, irqflags); + } +} + static inline DeviceState *create_acpi_ged(VirtMachineState *vms) { DeviceState *dev; @@ -717,6 +743,10 @@ static void create_gic(VirtMachineState *vms) qdev_get_gpio_in(vms->gic, ppibase + VIRTUAL_PMU_IRQ)); + qdev_connect_gpio_out_named(cpudev, "spe-interrupt", 0, + qdev_get_gpio_in(vms->gic, ppibase + + VIRTUAL_SPE_IRQ)); + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); @@ -1664,11 +1694,12 @@ static void finalize_gic_version(VirtMachineState *vms) static void virt_cpu_post_init(VirtMachineState *vms) { - bool aarch64, pmu; + bool aarch64, pmu, spe; CPUState *cpu; aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); + spe = object_property_get_bool(OBJECT(first_cpu), "spe", NULL); if (kvm_enabled()) { CPU_FOREACH(cpu) { @@ -1679,6 +1710,14 @@ static void virt_cpu_post_init(VirtMachineState *vms) } kvm_arm_pmu_init(cpu); } + + if (spe) { + assert(ARM_CPU(cpu)->has_spe == ON_OFF_AUTO_ON); + if (kvm_irqchip_in_kernel()) { + kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ)); + kvm_arm_spe_init(cpu); + } + } } } else { if (aarch64 && vms->highmem) { @@ -1927,6 +1966,8 @@ static void machvirt_init(MachineState *machine) fdt_add_pmu_nodes(vms); + fdt_add_spe_nodes(vms); + create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); if (vms->secure) { diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 38a42f409a..21e58f27c5 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -302,6 +302,9 @@ struct AcpiMadtGenericCpuInterface { uint32_t vgic_interrupt; uint64_t gicr_base_address; uint64_t arm_mpidr; + uint8_t efficiency_class; + uint8_t reserved2[1]; + uint16_t spe_interrupt; /* ACPI 6.3 */ } QEMU_PACKED; typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 72c269aaa5..6013b6d535 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -49,6 +49,7 @@ #define ARCH_TIMER_NS_EL1_IRQ 14 #define ARCH_TIMER_NS_EL2_IRQ 10 +#define VIRTUAL_SPE_IRQ 5 #define VIRTUAL_PMU_IRQ 7 #define PPI(irq) ((irq) + 16) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f211958eaa..786cc6134c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1041,6 +1041,8 @@ static void arm_cpu_initfn(Object *obj) "gicv3-maintenance-interrupt", 1); qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, "pmu-interrupt", 1); + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->spe_interrupt, + "spe-interrupt", 1); #endif /* DTB consumers generally don't in fact care what the 'compatible' diff --git a/target/arm/cpu.h b/target/arm/cpu.h index baf2bbcee8..395a1e5df8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -800,6 +800,8 @@ struct ARMCPU { qemu_irq gicv3_maintenance_interrupt; /* GPIO output for the PMU interrupt */ qemu_irq pmu_interrupt; + /* GPIO output for the SPE interrupt */ + qemu_irq spe_interrupt; /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; From patchwork Tue Sep 15 03:11:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 273754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5532EC433E2 for ; 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Mon, 14 Sep 2020 20:12:16 -0700 (PDT) From: Haibo Xu To: drjones@redhat.com, richard.henderson@linaro.org Subject: [PATCH v3 10/12] target/arm/cpu: spe: Enable spe to work with host cpu Date: Tue, 15 Sep 2020 03:11:46 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=haibo.xu@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Turn on the spe cpu property by default if host cpu support it, i.e. we can now do '-cpu max|host' to add the vSPE, and '-cpu max|host,spe=off' to remove it. Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones --- target/arm/cpu.c | 1 + target/arm/cpu.h | 2 ++ target/arm/cpu64.c | 10 +++++++--- target/arm/kvm64.c | 12 ++++++++++++ 4 files changed, 22 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 786cc6134c..05a4b7d208 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2271,6 +2271,7 @@ static void arm_host_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); + aarch64_add_spe_properties(obj); } arm_cpu_post_init(obj); } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 395a1e5df8..5a3ea876c8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1040,6 +1040,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); void aarch64_add_sve_properties(Object *obj); +void aarch64_add_spe_properties(Object *obj); /* * SVE registers are encoded in KVM's memory in an endianness-invariant format. @@ -1071,6 +1072,7 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n, bool a) { } static inline void aarch64_add_sve_properties(Object *obj) { } +static inline void aarch64_add_spe_properties(Object *obj) { } #endif #if !defined(CONFIG_TCG) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4997c4a3c0..04daeb901d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -621,6 +621,12 @@ static void arm_spe_set(Object *obj, bool value, Error **errp) ARM_CPU(obj)->has_spe = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; } +void aarch64_add_spe_properties(Object *obj) +{ + ARM_CPU(obj)->has_spe = ON_OFF_AUTO_AUTO; + object_property_add_bool(obj, "spe", arm_spe_get, arm_spe_set); +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -632,6 +638,7 @@ static void aarch64_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + aarch64_add_spe_properties(obj); } else { uint64_t t; uint32_t u; @@ -770,9 +777,6 @@ static void aarch64_max_initfn(Object *obj) aarch64_add_sve_properties(obj); object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, NULL, NULL); - - cpu->has_spe = ON_OFF_AUTO_AUTO; - object_property_add_bool(obj, "spe", arm_spe_get, arm_spe_set); } static const ARMCPUInfo aarch64_cpus[] = { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5a2032fc9e..20269efeff 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -515,6 +515,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) */ int fdarray[3]; bool sve_supported; + bool spe_supported; uint64_t features = 0; uint64_t t; int err; @@ -655,6 +656,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; + spe_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, + KVM_CAP_ARM_SPE_V1) > 0; kvm_arm_destroy_scratch_host_vcpu(fdarray); @@ -668,6 +671,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); ahcf->isar.id_aa64pfr0 = t; } + if (spe_supported) { + t = ahcf->isar.id_aa64dfr0; + t = FIELD_DP64(t, ID_AA64DFR0, PMSVER, 1); + ahcf->isar.id_aa64dfr0 = t; + } /* * We can assume any KVM supporting CPU is at least a v8 @@ -830,6 +838,10 @@ int kvm_arch_init_vcpu(CPUState *cs) assert(kvm_arm_sve_supported()); cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; } + if (cpu_isar_feature(aa64_spe, cpu)) { + assert(kvm_arm_spe_supported()); + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SPE_V1; + } /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); From patchwork Tue Sep 15 03:11:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 303964 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2156362ilg; Mon, 14 Sep 2020 20:14:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8nPkKiXZ8o+inDrxiCUUHMXGP8WDzp1eFOYC6ijIrq0YJOEGxPnTMqU2+JErOpj8HeJ9y X-Received: by 2002:ac8:142:: with SMTP id f2mr3808615qtg.191.1600139642893; Mon, 14 Sep 2020 20:14:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600139642; cv=none; d=google.com; s=arc-20160816; b=zMzvzq0hk/h1TWcqakw89dB6Ez3a1pJbZ60eX5CBXRO5vq18/rAdXtoLgaiHyp5y5R dasSbELL8TehJIBVweAP+N+dsZojgNJfdhoCgDTQbbg3zwJm0uwuyvzr/Y4gySpC8Bxa tIutNW6VC83jSKy+FHI98Fyr0PDwx2voAKbhh7R9qFHZhrzlnNUnjGGnYKzIxnVYcSak Io8kiPm1ULsiS3p0Hkw0spKP6I9PqVBTE2hzdBAH6/GZmK4ntmyFBLmEHi7S3shH6Rtt YwSzivD9pBrzGznVarryn5CFLhYeC0S/a/+coGdIYggBknUw5IdpEx9Y02puwJLL1grp mx7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ttZlTeQRiqAfohcWiL5/T40b1TJUWiG1lTmcd0fZw3M=; b=eM9rCguxABveEo9Nh7CGtooayShu4W6Ex1LaLnQp5aKRRYDvJc5z7gLnQIk/AChNDr NC7L0zR+gjVxuGVXS4FdigJuI1PU8XvkAGNkHzAhX46hJWZU+EYwqNg6WIERACms9jaQ AboT9Rve2n9VhsLXO+sTSz01D+G0FdO6RWL2ghNFtDtzShWEu4fYx2R3KAumANfQAn/s +m3TOgldJ9c0v/1p5c9ol5SqWIR7eT1x2FwOpLy+kOAuggpQx1lrCwfm0rvKZiIsAi10 WQfwlTcDrTlW0SJWhNDjSetst/mevJr1a2h9LT+XropS+0JuE+VN/GCOZlMz4XEL6uUI zt2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IS2O6XuE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Date: Tue, 15 Sep 2020 03:11:47 +0000 Message-Id: <6e6ef8d1ea15180514a6f1540933aca4d59939a8.1600135462.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=haibo.xu@linaro.org; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since the current kernel patches haven't enabled the userspace irqchip support, this patch is not verified yet! Reviewed-by: Andrew Jones Signed-off-by: Haibo Xu --- hw/arm/virt.c | 2 +- target/arm/kvm.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ee0831922b..bdb1ce925c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1715,8 +1715,8 @@ static void virt_cpu_post_init(VirtMachineState *vms) assert(ARM_CPU(cpu)->has_spe == ON_OFF_AUTO_ON); if (kvm_irqchip_in_kernel()) { kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ)); - kvm_arm_spe_init(cpu); } + kvm_arm_spe_init(cpu); } } } else { diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 58f991e890..7950ff1d83 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -820,6 +820,11 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) switched_level &= ~KVM_ARM_DEV_PMU; } + if (switched_level & KVM_ARM_DEV_SPE) { + qemu_set_irq(cpu->spe_interrupt, + !!(run->s.regs.device_irq_level & KVM_ARM_DEV_SPE)); + switched_level &= ~KVM_ARM_DEV_SPE; + } if (switched_level) { qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n", __func__, switched_level); From patchwork Tue Sep 15 03:11:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 303968 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2157579ilg; Mon, 14 Sep 2020 20:16:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZQGuSTMT9eJ8s/CkrA+Onf6aG95XWfoXkSshay1UiZH41Ak4B5Lfh5LmU4SejcoxcpFgv X-Received: by 2002:ac8:24cb:: with SMTP id t11mr4111323qtt.264.1600139778862; Mon, 14 Sep 2020 20:16:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600139778; cv=none; d=google.com; s=arc-20160816; b=Mvd67vkEccheJcEw5reYG3Ph+g7ae436VFh/fnFDaf7/eiB52bC1JTi97Ni3F2FLdF lJSBp/HpSQDQI8XK2O/3UDbpB6iuXoDAp00ztr7rSxBqyE25aJ00r6NZaos7JZWXuSed u5NeiOuscIQKkgyN5752a9Rd7+B31XZDlz0aCibg+XCqD4vnROaSxtxKvt40hzVVkZ// 8P04c+2Ps3xo24fgj9sCFDbMVAFjnhjZQDhBw9ZqLxlWg9M/RHaCrN7G0D/v/Rg1I3Wm sZee2O3YF2GnFLJ7pGOfKlYxtmKY4D90DmrHSFuL4wf1N5jAqBhJ8Da9ylcpln3sHLfh PWsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lp4BszfnJ+gdPupxEQ8UJGzcoaSEVDtxDHyalqIp0D8=; b=H2cYhxsF2wAFgIAGbUkmpGLZ6XR5jh2Q6kD4RxiFZpGU71KvKURMGQ6+PB/NPb9GbP jcqQbVjvVB28d1pBC2d7MhSpTAn7aPBj7rQE40Jh3PmWS1Ql2aJg7bAz6Nm/4+llwyt4 GXTixMNktLsp/Hs2CWQU75c+D4213v677ui6kaqCgo0V/9t3dhIPqeCUcA04u4DJKNHE tIRayjGeiwiTVmm3eE4BSIWPQ23xOrPFJ7wVWbsnEY/p3umjKxubwAwhYqXFP3aZ9lnR vlUz/at7PUGvW5lbIlVDLijI/w+9vWAvhbQJ3amsHMOrhbiuxwWfCKnSHNVO8h2bmXQ1 VZ8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RHf8GeW8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Date: Tue, 15 Sep 2020 03:11:48 +0000 Message-Id: <53adf9e25750962eca7dd09f924c97bb17c1214a.1600135462.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=haibo.xu@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Andrew Jones Signed-off-by: Haibo Xu --- target/arm/monitor.c | 2 +- tests/qtest/arm-cpu-features.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/monitor.c b/target/arm/monitor.c index ba6e01abd0..1b8f08988a 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -99,7 +99,7 @@ QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); * then the order that considers those dependencies must be used. */ static const char *cpu_model_advertised_features[] = { - "aarch64", "pmu", "sve", + "aarch64", "pmu", "spe", "sve", "sve128", "sve256", "sve384", "sve512", "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 77b5e30a9c..4d393fb2e2 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -494,6 +494,7 @@ static void test_query_cpu_model_expansion_kvm(const void *data) if (g_str_equal(qtest_get_arch(), "aarch64")) { bool kvm_supports_sve; + bool kvm_supports_spe; char max_name[8], name[8]; uint32_t max_vq, vq; uint64_t vls; @@ -512,8 +513,10 @@ static void test_query_cpu_model_expansion_kvm(const void *data) "with KVM on this host", NULL); assert_has_feature(qts, "host", "sve"); + assert_has_feature(qts, "host", "spe"); resp = do_query_no_props(qts, "host"); kvm_supports_sve = resp_get_feature(resp, "sve"); + kvm_supports_spe = resp_get_feature(resp, "spe"); vls = resp_get_sve_vls(resp); qobject_unref(resp); @@ -573,10 +576,16 @@ static void test_query_cpu_model_expansion_kvm(const void *data) } else { g_assert(vls == 0); } + + if (kvm_supports_spe) { + assert_set_feature(qts, "host", "spe", false); + assert_set_feature(qts, "host", "spe", true); + } } else { assert_has_not_feature(qts, "host", "aarch64"); assert_has_not_feature(qts, "host", "pmu"); assert_has_not_feature(qts, "host", "sve"); + assert_has_not_feature(qts, "host", "spe"); } qtest_quit(qts);