From patchwork Fri Nov 3 17:49:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 117955 Delivered-To: patch@linaro.org Received: by 10.80.245.45 with SMTP id t42csp3584104edm; Fri, 3 Nov 2017 10:50:24 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SbvsXrUI2DMp4f90AwxPoEWtpqZ2ay4FRKgigWKcVsGT0oqNU3ffmv0N0Z5bpSxUJNzxZZ X-Received: by 10.98.74.206 with SMTP id c75mr8608211pfj.100.1509731424120; Fri, 03 Nov 2017 10:50:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509731424; cv=none; d=google.com; s=arc-20160816; b=aKpR8nf19ZbQoLrTRycOtyQwJA38r7S5W/ZP5a8IFMZL9VqfVNMgBHME16uLzHYKiD eU2ixOpMeZE26dCBlpHoHxtfUdClvryjXT2kJeZ6WYgggcbHqsiq7y8i5Ot3TB4StuYP 6OExLIi/lfxcCIraIe57Lh0FyGcNqTMBkAxZ520CoYme0G2DFSsR+xd879c0cE92rGvv QuPFgHFYaqKPHlqzni2Ifi1oButlgq2/lhYh5SrQm5JkbS2iaLnv7i2YoRWbrYX4gU/w Vi7NHaZJeaGsg3vwxwHpZz+PuanWMvcADbPEscYzWaZv4QfFCTZUgRjnAqnQrOXmlyCf AUmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:cc:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=fWZciGsbwKRvI3GqFcEpkSPAntDpCrxYuRunBISmzaQ=; b=gdDiPAYXMPbI7ZcZP3Kk2yfYKBo1IPzxL5y7JQ5Bss7vbiuPrQxx1B3cx5zNsl3SWW /zXWlnx6MLUyg/m+ZEQj5Vk8MhVi/5m5xRsZREmYaK0bLLb9OO1uF/UN81xo96ygRiVz A8Pua5uJPWl0N7vSJ7+QZquszh9/8L+2v57pGOWEnA8Z5KbJD5VfBGgKSI4HdCC55vMs jnVPBTctUb6481as5MnOnfIQMxjHZykuT7+SW0IVJYX6mOdTAIdCfHhCiCR4qVgRSuXv sDaUMbAC/vuTtcO56UuWZtdN92Dm85th+H/bY3FE2E7fRUJRFcJsfDAui5yv/17ry1Xo FfdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Egp9Zzwu; spf=pass (google.com: domain of gcc-patches-return-465906-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465906-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id az4si5178516plb.548.2017.11.03.10.50.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 10:50:24 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-465906-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Egp9Zzwu; spf=pass (google.com: domain of gcc-patches-return-465906-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465906-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; q=dns; s=default; b=lKFMN9J6m+Ov7evh LBkEsCfA3nKzGMat1tpp7TVQDFG7YA2mZLdUg8l+f94ndsKvcklDx8qh+/2Pr/ae 4T36xeV6ybJ2rBTo0JS1rWoAblhMt84aJzlgev/SdRxIjkeKne1KlKvmH47+VmBO Qypq3QeVYOTZKy2NfyqhNUIAAkI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; s=default; bh=KnFw4HOmEONoBgKtBwetKo 2yIYo=; b=Egp9Zzwux7tEui8vT78eYZCklX/xQFcg7oRKunPI1jN/edkRPUeZ8j piTdQEtpJTDTknCvCB/IsuyPxIiGnqsDsnIsTUl4U3krT6m5IHZe4cPbmeArtrqJ l/u5mhRdeMGHDg1E4oNfMF5Sv4lzKGb6/AQTPAWSfNH6zxxIU8T5I= Received: (qmail 83855 invoked by alias); 3 Nov 2017 17:50:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 83555 invoked by uid 89); 3 Nov 2017 17:50:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=UD:no-vfa-vect-depend-3.c, UD:no-vfa-vect-depend-2.c X-HELO: mail-wr0-f196.google.com Received: from mail-wr0-f196.google.com (HELO mail-wr0-f196.google.com) (209.85.128.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 Nov 2017 17:50:02 +0000 Received: by mail-wr0-f196.google.com with SMTP id j15so3181971wre.8 for ; Fri, 03 Nov 2017 10:50:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:cc:subject:references :date:in-reply-to:message-id:user-agent:mime-version; bh=fWZciGsbwKRvI3GqFcEpkSPAntDpCrxYuRunBISmzaQ=; b=DbNy/yPWyZtnn+NCbQaClVmSvyJsZesumWqvNbvWrH0Cf2cgrfKNCctKzwMxZlEH2x gmMZRXm8GBHr/bSne9Y+xhrOKGRH1fmKxsugPjAoh32QxxFRez/HVkKTj3/7+nKzovnD +9X9EWpvLMXy3sh3bK1oP0ZChobnd6C1qjfhGTHI2kDbLE1mgg2StYqiDTyesBnwf/p5 inJM9YSZFPUYqNJxRoT+aRClBUpvOuSaY1REodfnoiq5MdkLwOAGeLVDUp/jcruhyndK 3LJe4hTDTk48XqdroCsS9IsCD2z8oDpb3uUNkmZDkedsmSuyhFatLR5RX7aurwYmaGez dVLQ== X-Gm-Message-State: AMCzsaUKOJZU0lhR0HgIa0k39yHhZm5Ty27mmYK0keMj5xquiakDZ9Wm R9etkl4Jg8elKWYFEeZqzyG9xw== X-Received: by 10.223.134.250 with SMTP id 55mr6879690wry.249.1509731399362; Fri, 03 Nov 2017 10:49:59 -0700 (PDT) Received: from localhost (188.29.164.162.threembb.co.uk. [188.29.164.162]) by smtp.gmail.com with ESMTPSA id n14sm6042488wrg.38.2017.11.03.10.49.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Nov 2017 10:49:58 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@linaro.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [2/4] [AArch64] Testsuite markup for SVE References: <87a803ntmg.fsf@linaro.org> Date: Fri, 03 Nov 2017 17:49:56 +0000 In-Reply-To: <87a803ntmg.fsf@linaro.org> (Richard Sandiford's message of "Fri, 03 Nov 2017 17:45:43 +0000") Message-ID: <871slfntff.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 This patch adds new target selectors for SVE and updates existing selectors accordingly. It also XFAILs some tests that don't yet work for some SVE modes; most of these go away with follow-on vectorisation enhancements. 2017-11-03 Richard Sandiford Alan Hayward David Sherwood gcc/testsuite/ * lib/target-supports.exp (check_effective_target_aarch64_sve) (aarch64_sve_bits, check_effective_target_aarch64_sve_hw) (aarch64_sve_hw_bits, check_effective_target_aarch64_sve256_hw): New procedures. (check_effective_target_vect_perm): Handle SVE. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. (check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. (check_effective_target_vect_widen_mult_hi_to_si): Likewise. (check_effective_target_vect_element_align_preferred): Likewise. (check_effective_target_vect_align_stack_vars): Likewise. (check_effective_target_vect_load_lanes): Likewise. (check_effective_target_vect_masked_store): Likewise. (available_vector_sizes): Use aarch64_sve_bits for SVE. * gcc.dg/vect/tree-vect.h (VECTOR_BITS): Define appropriately for SVE. * gcc.dg/tree-ssa/ssa-dom-cse-2.c: Add SVE XFAIL. * gcc.dg/vect/bb-slp-pr69907.c: Likewise. * gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise. * gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise. * gcc.dg/vect/slp-23.c: Likewise. * gcc.dg/vect/slp-25.c: Likewise. * gcc.dg/vect/slp-perm-5.c: Likewise. * gcc.dg/vect/slp-perm-6.c: Likewise. * gcc.dg/vect/slp-perm-9.c: Likewise. * gcc.dg/vect/slp-reduc-3.c: Likewise. * gcc.dg/vect/vect-114.c: Likewise. * gcc.dg/vect/vect-119.c: Likewise. * gcc.dg/vect/vect-cselim-1.c: Likewise. * gcc.dg/vect/vect-live-slp-1.c: Likewise. * gcc.dg/vect/vect-live-slp-2.c: Likewise. * gcc.dg/vect/vect-live-slp-3.c: Likewise. * gcc.dg/vect/vect-mult-const-pattern-1.c: Likewise. * gcc.dg/vect/vect-mult-const-pattern-2.c: Likewise. * gcc.dg/vect/vect-over-widen-1-big-array.c: Likewise. * gcc.dg/vect/vect-over-widen-1.c: Likewise. * gcc.dg/vect/vect-over-widen-3-big-array.c: Likewise. * gcc.dg/vect/vect-over-widen-4-big-array.c: Likewise. * gcc.dg/vect/vect-over-widen-4.c: Likewise. Index: gcc/testsuite/lib/target-supports.exp =================================================================== --- gcc/testsuite/lib/target-supports.exp 2017-11-03 17:22:13.533564036 +0000 +++ gcc/testsuite/lib/target-supports.exp 2017-11-03 17:24:09.475993817 +0000 @@ -3350,6 +3350,35 @@ proc check_effective_target_aarch64_litt }] } +# Return 1 if this is an AArch64 target supporting SVE. +proc check_effective_target_aarch64_sve { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_no_compiler_messages aarch64_sve assembly { + #if !defined (__ARM_FEATURE_SVE) + #error FOO + #endif + }] +} + +# Return the size in bits of an SVE vector, or 0 if the size is variable. +proc aarch64_sve_bits { } { + return [check_cached_effective_target aarch64_sve_bits { + global tool + + set src dummy[pid].c + set f [open $src "w"] + puts $f "int bits = __ARM_FEATURE_SVE_BITS;" + close $f + set output [${tool}_target_compile $src "" preprocess ""] + file delete $src + + regsub {.*bits = ([^;]*);.*} $output {\1} bits + expr { $bits } + }] +} + # Return 1 if this is a compiler supporting ARC atomic operations proc check_effective_target_arc_atomic { } { return [check_no_compiler_messages arc_atomic assembly { @@ -4275,6 +4304,49 @@ proc check_effective_target_arm_neon_hw } [add_options_for_arm_neon ""]] } +# Return true if this is an AArch64 target that can run SVE code. + +proc check_effective_target_aarch64_sve_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_sve_hw_available { + int + main (void) + { + asm volatile ("ptrue p0.b"); + return 0; + } + }] +} + +# Return true if this is an AArch64 target that can run SVE code and +# if its SVE vectors have exactly BITS bits. + +proc aarch64_sve_hw_bits { bits } { + if { ![check_effective_target_aarch64_sve_hw] } { + return 0 + } + return [check_runtime aarch64_sve${bits}_hw [subst { + int + main (void) + { + int res; + asm volatile ("cntd %0" : "=r" (res)); + if (res * 64 != $bits) + __builtin_abort (); + return 0; + } + }]] +} + +# Return true if this is an AArch64 target that can run SVE code and +# if its SVE vectors have exactly 256 bits. + +proc check_effective_target_aarch64_sve256_hw { } { + return [aarch64_sve_hw_bits 256] +} + proc check_effective_target_arm_neonv2_hw { } { return [check_runtime arm_neon_hwv2_available { #include "arm_neon.h" @@ -5531,7 +5603,8 @@ proc check_effective_target_vect_perm { } else { set et_vect_perm_saved($et_index) 0 if { [is-effective-target arm_neon] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_vect_variable_length]) || [istarget powerpc*-*-*] || [istarget spu-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] @@ -5636,7 +5709,8 @@ proc check_effective_target_vect_perm_by if { ([is-effective-target arm_neon] && [is-effective-target arm_little_endian]) || ([istarget aarch64*-*-*] - && [is-effective-target aarch64_little_endian]) + && [is-effective-target aarch64_little_endian] + && ![check_effective_target_vect_variable_length]) || [istarget powerpc*-*-*] || [istarget spu-*-*] || ([istarget mips-*.*] @@ -5675,7 +5749,8 @@ proc check_effective_target_vect_perm_sh if { ([is-effective-target arm_neon] && [is-effective-target arm_little_endian]) || ([istarget aarch64*-*-*] - && [is-effective-target aarch64_little_endian]) + && [is-effective-target aarch64_little_endian] + && ![check_effective_target_vect_variable_length]) || [istarget powerpc*-*-*] || [istarget spu-*-*] || ([istarget mips*-*-*] @@ -5735,7 +5810,8 @@ proc check_effective_target_vect_widen_s } else { set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 0 if { [istarget powerpc*-*-*] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) || [is-effective-target arm_neon] || [istarget ia64-*-*] } { set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 1 @@ -5847,7 +5923,8 @@ proc check_effective_target_vect_widen_m set et_vect_widen_mult_qi_to_hi_saved($et_index) 0 } if { [istarget powerpc*-*-*] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) || [is-effective-target arm_neon] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) } { @@ -5885,7 +5962,8 @@ proc check_effective_target_vect_widen_m if { [istarget powerpc*-*-*] || [istarget spu-*-*] || [istarget ia64-*-*] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) || [istarget i?86-*-*] || [istarget x86_64-*-*] || [is-effective-target arm_neon] || ([istarget s390*-*-*] @@ -6347,12 +6425,16 @@ proc check_effective_target_vect_natural # alignment during vectorization. proc check_effective_target_vect_element_align_preferred { } { - return [check_effective_target_vect_variable_length] + return [expr { [check_effective_target_aarch64_sve] + && [check_effective_target_vect_variable_length] }] } # Return 1 if we can align stack data to the preferred vector alignment. proc check_effective_target_vect_align_stack_vars { } { + if { [check_effective_target_aarch64_sve] } { + return [check_effective_target_vect_variable_length] + } return 1 } @@ -6424,7 +6506,8 @@ proc check_effective_target_vect_load_la } else { set et_vect_load_lanes 0 if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) - || [istarget aarch64*-*-*] } { + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) } { set et_vect_load_lanes 1 } } @@ -6436,7 +6519,7 @@ proc check_effective_target_vect_load_la # Return 1 if the target supports vector masked stores. proc check_effective_target_vect_masked_store { } { - return 0 + return [check_effective_target_aarch64_sve] } # Return 1 if the target supports vector conditional operations, 0 otherwise. @@ -6704,6 +6787,9 @@ foreach N {2 3 4 8} { proc available_vector_sizes { } { set result {} if { [istarget aarch64*-*-*] } { + if { [check_effective_target_aarch64_sve] } { + lappend result [aarch64_sve_bits] + } lappend result 128 64 } elseif { [istarget arm*-*-*] && [check_effective_target_arm_neon_ok] } { Index: gcc/testsuite/gcc.dg/vect/tree-vect.h =================================================================== --- gcc/testsuite/gcc.dg/vect/tree-vect.h 2017-11-03 17:21:09.761094925 +0000 +++ gcc/testsuite/gcc.dg/vect/tree-vect.h 2017-11-03 17:24:09.472993942 +0000 @@ -76,4 +76,12 @@ check_vect (void) signal (SIGILL, SIG_DFL); } -#define VECTOR_BITS 128 +#if defined (__ARM_FEATURE_SVE) +# if __ARM_FEATURE_SVE_BITS == 0 +# define VECTOR_BITS 1024 +# else +# define VECTOR_BITS __ARM_FEATURE_SVE_BITS +# endif +#else +# define VECTOR_BITS 128 +#endif Index: gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c =================================================================== --- gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c 2017-02-23 19:54:09.000000000 +0000 +++ gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c 2017-11-03 17:24:09.471993983 +0000 @@ -25,4 +25,4 @@ foo () but the loop reads only one element at a time, and DOM cannot resolve these. The same happens on powerpc depending on the SIMD support available. */ -/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* } || { lp64 && { powerpc*-*-* sparc*-*-* riscv*-*-* } } } } } } */ +/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* } || { { lp64 && { powerpc*-*-* sparc*-*-* riscv*-*-* } } || aarch64_sve } } } } } */ Index: gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c =================================================================== --- gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c 2017-11-03 17:21:09.758095046 +0000 +++ gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c 2017-11-03 17:24:09.471993983 +0000 @@ -17,4 +17,6 @@ void foo(unsigned *p1, unsigned short *p p1[n] = p2[n * 2]; } -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" } } */ +/* Disable for SVE because for long or variable-length vectors we don't + get an unrolled epilogue loop. */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { ! aarch64_sve } } } } */ Index: gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c =================================================================== --- gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c 2015-06-02 23:53:38.000000000 +0100 +++ gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c 2017-11-03 17:24:09.471993983 +0000 @@ -51,4 +51,7 @@ int main (void) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {xfail { vect_no_align && { ! vect_hw_misalign } } } } } */ -/* { dg-final { scan-tree-dump-times "dependence distance negative" 1 "vect" } } */ +/* Requires reverse for variable-length SVE, which is implemented for + by a later patch. Until then we report it twice, once for SVE and + once for 128-bit Advanced SIMD. */ +/* { dg-final { scan-tree-dump-times "dependence distance negative" 1 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ Index: gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c =================================================================== --- gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c 2015-06-02 23:53:38.000000000 +0100 +++ gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c 2017-11-03 17:24:09.472993942 +0000 @@ -183,4 +183,7 @@ int main () } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" {xfail { vect_no_align && { ! vect_hw_misalign } } } } } */ -/* { dg-final { scan-tree-dump-times "dependence distance negative" 4 "vect" } } */ +/* f4 requires reverse for SVE, which is implemented by a later patch. + Until then we report it twice, once for SVE and once for 128-bit + Advanced SIMD. */ +/* { dg-final { scan-tree-dump-times "dependence distance negative" 4 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ Index: gcc/testsuite/gcc.dg/vect/slp-23.c =================================================================== --- gcc/testsuite/gcc.dg/vect/slp-23.c 2017-11-03 17:21:09.742095692 +0000 +++ gcc/testsuite/gcc.dg/vect/slp-23.c 2017-11-03 17:24:09.472993942 +0000 @@ -107,6 +107,8 @@ int main (void) /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided8 && { ! { vect_no_align} } } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided8 || vect_no_align } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_perm } } } } */ +/* We fail to vectorize the second loop with variable-length SVE but + fall back to 128-bit vectors, which does use SLP. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_perm } xfail aarch64_sve } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_perm } } } */ Index: gcc/testsuite/gcc.dg/vect/slp-25.c =================================================================== --- gcc/testsuite/gcc.dg/vect/slp-25.c 2017-11-03 17:21:09.814092784 +0000 +++ gcc/testsuite/gcc.dg/vect/slp-25.c 2017-11-03 17:24:09.472993942 +0000 @@ -57,4 +57,6 @@ int main (void) /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail { { ! vect_unaligned_possible } || { ! vect_natural_alignment } } } } } */ +/* Needs store_lanes for SVE, otherwise falls back to Advanced SIMD. + Will be fixed when SVE LOAD_LANES support is added. */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail { { { ! vect_unaligned_possible } || { ! vect_natural_alignment } } && { ! { aarch64_sve && vect_variable_length } } } } } } */ Index: gcc/testsuite/gcc.dg/vect/slp-perm-5.c =================================================================== --- gcc/testsuite/gcc.dg/vect/slp-perm-5.c 2017-11-03 17:21:09.792093672 +0000 +++ gcc/testsuite/gcc.dg/vect/slp-perm-5.c 2017-11-03 17:24:09.472993942 +0000 @@ -104,7 +104,9 @@ int main (int argc, const char* argv[]) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } } } } */ +/* Fails for variable-length SVE because we fall back to Advanced SIMD + and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target vect_load_lanes } } } */ /* { dg-final { scan-tree-dump "note: Built SLP cancelled: can use load/store-lanes" "vect" { target { vect_perm3_int && vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump "LOAD_LANES" "vect" { target vect_load_lanes } } } */ Index: gcc/testsuite/gcc.dg/vect/slp-perm-6.c =================================================================== --- gcc/testsuite/gcc.dg/vect/slp-perm-6.c 2017-11-03 17:21:09.792093672 +0000 +++ gcc/testsuite/gcc.dg/vect/slp-perm-6.c 2017-11-03 17:24:09.472993942 +0000 @@ -103,7 +103,9 @@ int main (int argc, const char* argv[]) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } } } } */ +/* Fails for variable-length SVE because we fall back to Advanced SIMD + and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_load_lanes } } } */ /* { dg-final { scan-tree-dump "note: Built SLP cancelled: can use load/store-lanes" "vect" { target { vect_perm3_int && vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump "LOAD_LANES" "vect" { target vect_load_lanes } } } */ Index: gcc/testsuite/gcc.dg/vect/slp-perm-9.c =================================================================== --- gcc/testsuite/gcc.dg/vect/slp-perm-9.c 2017-11-03 17:21:09.792093672 +0000 +++ gcc/testsuite/gcc.dg/vect/slp-perm-9.c 2017-11-03 17:24:09.472993942 +0000 @@ -57,10 +57,11 @@ int main (int argc, const char* argv[]) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 2 "vect" { target { ! { vect_perm_short || vect_load_lanes } } } } } */ +/* Fails for variable-length SVE because we fall back to Advanced SIMD + and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */ +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 2 "vect" { target { ! { vect_perm_short || vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_perm_short || vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump-times "permutation requires at least three vectors" 1 "vect" { target { vect_perm_short && { ! vect_perm3_short } } } } } */ /* { dg-final { scan-tree-dump-not "permutation requires at least three vectors" "vect" { target vect_perm3_short } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { { ! vect_perm3_short } || vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_perm3_short && { ! vect_load_lanes } } } } } */ - Index: gcc/testsuite/gcc.dg/vect/slp-reduc-3.c =================================================================== --- gcc/testsuite/gcc.dg/vect/slp-reduc-3.c 2015-06-02 23:53:38.000000000 +0100 +++ gcc/testsuite/gcc.dg/vect/slp-reduc-3.c 2017-11-03 17:24:09.472993942 +0000 @@ -58,4 +58,7 @@ int main (void) /* The initialization loop in main also gets vectorized. */ /* { dg-final { scan-tree-dump-times "vect_recog_dot_prod_pattern: detected" 1 "vect" { xfail *-*-* } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_short_mult && { vect_widen_sum_hi_to_si && vect_unpack } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { ! vect_unpack } } } } } */ +/* We can't yet create the necessary SLP constant vector for variable-length + SVE and so fall back to Advanced SIMD. This means that we repeat each + analysis note. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { { ! vect_unpack } || { aarch64_sve && vect_variable_length } } } } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-114.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-114.c 2015-06-02 23:53:35.000000000 +0100 +++ gcc/testsuite/gcc.dg/vect/vect-114.c 2017-11-03 17:24:09.473993900 +0000 @@ -34,6 +34,9 @@ int main (void) return main1 (); } -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_perm } } } } } */ +/* Requires reverse for SVE, which is implemented by a later patch. + Until then we fall back to Advanced SIMD and successfully vectorize + the loop. */ +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_perm } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-119.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-119.c 2015-08-05 22:28:34.000000000 +0100 +++ gcc/testsuite/gcc.dg/vect/vect-119.c 2017-11-03 17:24:09.473993900 +0000 @@ -25,4 +25,7 @@ unsigned int foo (const unsigned int x[O return sum; } -/* { dg-final { scan-tree-dump-times "Detected interleaving load of size 2" 1 "vect" } } */ +/* Requires load-lanes for SVE, which is implemented by a later patch. + Until then we report it twice, once for SVE and once for 128-bit + Advanced SIMD. */ +/* { dg-final { scan-tree-dump-times "Detected interleaving load of size 2" 1 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-cselim-1.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2017-11-03 17:21:09.849091370 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2017-11-03 17:24:09.473993900 +0000 @@ -83,4 +83,6 @@ main (void) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! vect_masked_store } xfail { { vect_no_align && { ! vect_hw_misalign } } || { ! vect_strided2 } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_masked_store } } } } */ +/* Fails for variable-length SVE because we can't yet handle the + interleaved load. This is fixed by a later patch. */ +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_masked_store xfail { aarch64_sve && vect_variable_length } } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-live-slp-1.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-live-slp-1.c 2016-11-22 21:16:10.000000000 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-live-slp-1.c 2017-11-03 17:24:09.473993900 +0000 @@ -69,4 +69,7 @@ main (void) /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" } } */ -/* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not relevant" 4 "vect" } } */ +/* We can't yet create the necessary SLP constant vector for variable-length + SVE and so fall back to Advanced SIMD. This means that we repeat each + analysis note. */ +/* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not relevant" 4 "vect" { xfail { aarch64_sve && vect_variable_length } } } }*/ Index: gcc/testsuite/gcc.dg/vect/vect-live-slp-2.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-live-slp-2.c 2016-11-22 21:16:10.000000000 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-live-slp-2.c 2017-11-03 17:24:09.473993900 +0000 @@ -63,4 +63,7 @@ main (void) /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" } } */ -/* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not relevant" 2 "vect" } } */ +/* We can't yet create the necessary SLP constant vector for variable-length + SVE and so fall back to Advanced SIMD. This means that we repeat each + analysis note. */ +/* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not relevant" 2 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c 2016-11-22 21:16:10.000000000 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c 2017-11-03 17:24:09.473993900 +0000 @@ -70,4 +70,7 @@ main (void) /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" } } */ -/* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not relevant" 4 "vect" } } */ +/* We can't yet create the necessary SLP constant vector for variable-length + SVE and so fall back to Advanced SIMD. This means that we repeat each + analysis note. */ +/* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not relevant" 4 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c 2016-11-22 21:16:10.000000000 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c 2017-11-03 17:24:09.473993900 +0000 @@ -37,5 +37,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* xfail aarch64_sve } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target aarch64*-*-* } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c 2016-11-22 21:16:10.000000000 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c 2017-11-03 17:24:09.473993900 +0000 @@ -36,5 +36,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* xfail aarch64_sve } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target aarch64*-*-* } } } */ Index: gcc/testsuite/gcc.dg/vect/vect-over-widen-1-big-array.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-over-widen-1-big-array.c 2016-01-13 13:48:42.000000000 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-over-widen-1-big-array.c 2017-11-03 17:24:09.473993900 +0000 @@ -59,6 +59,8 @@ int main (void) /* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ /* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ -/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { ! vect_widen_shift } } } } */ +/* Requires LD4 for variable-length SVE. Until that's supported we fall + back to Advanced SIMD, which does have widening shifts. */ +/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { ! vect_widen_shift } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ Index: gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c 2017-11-03 17:21:09.762094884 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c 2017-11-03 17:24:09.474993858 +0000 @@ -63,7 +63,9 @@ int main (void) /* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ /* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ -/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { { ! vect_sizes_32B_16B } && { ! vect_widen_shift } } } } } */ +/* Requires LD4 for variable-length SVE. Until that's supported we fall + back to Advanced SIMD, which does have widening shifts. */ +/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { { ! vect_sizes_32B_16B } && { ! vect_widen_shift } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 8 "vect" { target vect_sizes_32B_16B } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ Index: gcc/testsuite/gcc.dg/vect/vect-over-widen-3-big-array.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-over-widen-3-big-array.c 2017-11-03 17:21:09.763094844 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-over-widen-3-big-array.c 2017-11-03 17:24:09.474993858 +0000 @@ -59,7 +59,9 @@ int main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 2 "vect" { target { ! vect_widen_shift } } } } */ +/* Requires LD4 for variable-length SVE. Until that's supported we fall + back to Advanced SIMD, which does have widening shifts. */ +/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 2 "vect" { target { ! vect_widen_shift } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 1 "vect" { target vect_widen_shift } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ Index: gcc/testsuite/gcc.dg/vect/vect-over-widen-4-big-array.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-over-widen-4-big-array.c 2016-01-13 13:48:42.000000000 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-over-widen-4-big-array.c 2017-11-03 17:24:09.474993858 +0000 @@ -63,6 +63,8 @@ int main (void) /* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ /* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ -/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { ! vect_widen_shift } } } } */ +/* Requires LD4 for variable-length SVE. Until that's supported we fall + back to Advanced SIMD, which does have widening shifts. */ +/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { ! vect_widen_shift } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ Index: gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c =================================================================== --- gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c 2017-11-03 17:21:09.763094844 +0000 +++ gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c 2017-11-03 17:24:09.474993858 +0000 @@ -67,7 +67,9 @@ int main (void) /* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ /* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 2 "vect" { target vect_widen_shift } } } */ -/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { { ! vect_sizes_32B_16B } && { ! vect_widen_shift } } } } } */ +/* Requires LD4 for variable-length SVE. Until that's supported we fall + back to Advanced SIMD, which does have widening shifts. */ +/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" { target { { ! vect_sizes_32B_16B } && { ! vect_widen_shift } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 8 "vect" { target vect_sizes_32B_16B } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ From patchwork Fri Nov 3 17:52:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 117956 Delivered-To: patch@linaro.org Received: by 10.80.245.45 with SMTP id t42csp3586065edm; Fri, 3 Nov 2017 10:52:30 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QV6syM5wGZ1iXXlRIQ7VzBfG+56xqCD5NngVwrXZT53pKoaVHiQXC9d4uzTAQDHpZ/0Kxa X-Received: by 10.159.196.151 with SMTP id c23mr7516578plo.276.1509731550729; Fri, 03 Nov 2017 10:52:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509731550; cv=none; d=google.com; s=arc-20160816; b=glffXBtetri2PCCO7PEdaWUXouU6bSrcqjmFBCYqp6JJB8QOKoyc176hEWD4+8bunP BaxPs2O89z8GfiQrqi7/FrT/7HG3xqYvlhAoIsqVSg9YAlFsGDc9xednd1xV41l1Fx7H SY6gK4xY+5ykQQui62C0MYVB4k/nZ8fDajdH2yijqR5bAdwSI07kvINbYEKRAlV1bcY8 MxDDLcBY4QD5k/G0SHbRSMiQVAMii6YDoFqTIoeb5cKk5B5r1uet1hSPJkLbpxJdTgs8 R//r9UwDz2mH6HrB0h5IJxhk8NryNr7pahZJ3+wyZV+i4HY4bep8lSwXpWHMtcFRep/a 01cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:cc:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=hI0XUn6bs9ivwUhFFXiVvQ0vf4b8gLCIjcQywfsfW+w=; b=SbAnMIc8IHOl7FsbKrVWhSmF9U8jhPDHnYeq4uTjMD+wk6Cx3Z3tdQzdvYnkm3rQGd Jty2e1Zo+1MOEJ+iC5KWdvFEjfBxMqYXDTtZnEmOBUCfHvGFUACAhqovUuCYJQLjzUTV 7nAc617dUg7OoChaBdJQn2r0uXDqO25HckQ3TTHwopuBpwjf7xi6T7xuk/7hLnfRmsVJ n3hWz2i92EQ3dzkq/FukT4iXgyutDIUeAE3KCsRUMLKlIYFhp4ygXTzSb8sHSOLyaPYQ u8k5//Rfl9/y43M6M5QyEL3JHAoLExr88cZ76LBMiENn+tI8+gaLi6IS9bgdcdrVdoNm JkRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Oxma3KUp; spf=pass (google.com: domain of gcc-patches-return-465908-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465908-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id r2si6482128pgs.685.2017.11.03.10.52.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 10:52:30 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-465908-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Oxma3KUp; spf=pass (google.com: domain of gcc-patches-return-465908-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465908-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; q=dns; s=default; b=omUFLm7+HAJdtl6t aeNFZs3IH2cfc1jsJmND2B4FBOQAXNEQ7+oJVhbng5GY8fg1nVJXbG2qXTBaiVgo OSohWPx1RaEhC4cwPtw6THR+UWYTHx5D3KMQdr8y0947cs5hxZGnRhLAlPm0TYdB oKtRHVO3FEiut6VfeQ6/nyS5Dzo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; s=default; bh=2zXSwCnoJwN/7kp4v/b2If jiIiM=; b=Oxma3KUphjpkg3U9RnvmuFq/ZYdDmR1uWiONLRfs6bh/evvjZbl9Ol MBAFTFx50Zp/lhbgLhlaH7gE9Qrde8nlQBOeH+W8FSAOcNtVtGa8Z18QrTTozYQ5 3QHaW7IRPqmBP/Nafpfjwd120Y7st5yp75MFmyHZ8BqPelWuIGJGM= Received: (qmail 80048 invoked by alias); 3 Nov 2017 17:52:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 80032 invoked by uid 89); 3 Nov 2017 17:52:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-13.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS, UNSUBSCRIBE_BODY autolearn=ham version=3.3.2 spammy=testi, thrown, *c X-HELO: mail-wr0-f178.google.com Received: from mail-wr0-f178.google.com (HELO mail-wr0-f178.google.com) (209.85.128.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 Nov 2017 17:52:10 +0000 Received: by mail-wr0-f178.google.com with SMTP id y39so3204561wrd.4 for ; Fri, 03 Nov 2017 10:52:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:cc:subject:references :date:in-reply-to:message-id:user-agent:mime-version; bh=hI0XUn6bs9ivwUhFFXiVvQ0vf4b8gLCIjcQywfsfW+w=; b=fIK+2TIPLyxNUJMSHy74AAQtgk9uzgnSPvkO+IFBftnSiFpbpnUmPuB+RIfl6Yc78Y poM4jnHgB9ZJfD/jyrHlChQ7gnVkhKLPnl1CD6RUI8XWUc/iSH0lpGKZF5rr4bWPrBHX XOeD4KFqKIabb5tcxXWnPxiZktp3I5Emc7UVES9gD6ksrSrhFrfMlgg2BTc8v+ImZr6d 4cvqXnjN5snqtZ55IsjvE9Nof/kTtil3/g2chSHqclTbvGyy7aL6YqupXifWEWkOBwge omroHxX4fC2TGA0VAYV2E9Ut33xbsSrbKwUVOjyJWuOloi+Imb0kR8vf0HrwvVpdIUue 9/xA== X-Gm-Message-State: AMCzsaUpukhw4ohG2stf0HYdLiiPiuO/GnRKARe47O5iNzROxylZ9HQb Jc6OINJsuZixVa7oCRRFioOVcnE3UVg= X-Received: by 10.223.133.214 with SMTP id 22mr6478905wru.23.1509731528388; Fri, 03 Nov 2017 10:52:08 -0700 (PDT) Received: from localhost (188.29.164.162.threembb.co.uk. [188.29.164.162]) by smtp.gmail.com with ESMTPSA id f19sm1441479wmf.4.2017.11.03.10.52.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Nov 2017 10:52:07 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@linaro.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [4/4] SVE unwinding References: <87a803ntmg.fsf@linaro.org> Date: Fri, 03 Nov 2017 17:52:05 +0000 In-Reply-To: <87a803ntmg.fsf@linaro.org> (Richard Sandiford's message of "Fri, 03 Nov 2017 17:45:43 +0000") Message-ID: <87shdvmere.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 This patch adds support for unwinding frames that use the SVE pseudo VG register. We want this register to act like a normal register if the CFI explicitly sets it, but want to provide a default value otherwise. Computing the default value requires an SVE target, so we only want to compute it on demand. aarch64_vg uses a hard-coded .inst in order to avoid a build dependency on binutils 2.28 or later. 2017-11-03 Richard Sandiford libgcc/ * config/aarch64/value-unwind.h (aarch64_vg): New function. (DWARF_LAZY_REGISTER_VALUE): Define. * unwind-dw2.c (_Unwind_GetGR): Use DWARF_LAZY_REGISTER_VALUE to provide a fallback register value. gcc/testsuite/ * g++.target/aarch64/aarch64.exp: New harness. * g++.target/aarch64/sve_catch_1.C: New test. * g++.target/aarch64/sve_catch_2.C: Likewise. * g++.target/aarch64/sve_catch_3.C: Likewise. * g++.target/aarch64/sve_catch_4.C: Likewise. * g++.target/aarch64/sve_catch_5.C: Likewise. * g++.target/aarch64/sve_catch_6.C: Likewise. Reviewed-by: James Greenhalgh Index: libgcc/config/aarch64/value-unwind.h =================================================================== --- libgcc/config/aarch64/value-unwind.h 2017-02-23 19:53:58.000000000 +0000 +++ libgcc/config/aarch64/value-unwind.h 2017-11-03 17:24:20.172023500 +0000 @@ -23,3 +23,19 @@ #if defined __aarch64__ && !defined __LP64__ # define REG_VALUE_IN_UNWIND_CONTEXT #endif + +/* Return the value of the pseudo VG register. This should only be + called if we know this is an SVE host. */ +static inline int +aarch64_vg (void) +{ + register int vg asm ("x0"); + /* CNTD X0. */ + asm (".inst 0x04e0e3e0" : "=r" (vg)); + return vg; +} + +/* Lazily provide a value for VG, so that we don't try to execute SVE + instructions unless we know they're needed. */ +#define DWARF_LAZY_REGISTER_VALUE(REGNO, VALUE) \ + ((REGNO) == AARCH64_DWARF_VG && ((*VALUE) = aarch64_vg (), 1)) Index: libgcc/unwind-dw2.c =================================================================== --- libgcc/unwind-dw2.c 2017-02-23 19:54:02.000000000 +0000 +++ libgcc/unwind-dw2.c 2017-11-03 17:24:20.172023500 +0000 @@ -216,12 +216,12 @@ _Unwind_IsExtendedContext (struct _Unwin || (context->flags & EXTENDED_CONTEXT_BIT)); } -/* Get the value of register INDEX as saved in CONTEXT. */ +/* Get the value of register REGNO as saved in CONTEXT. */ inline _Unwind_Word -_Unwind_GetGR (struct _Unwind_Context *context, int index) +_Unwind_GetGR (struct _Unwind_Context *context, int regno) { - int size; + int size, index; _Unwind_Context_Reg_Val val; #ifdef DWARF_ZERO_REG @@ -229,7 +229,7 @@ _Unwind_GetGR (struct _Unwind_Context *c return 0; #endif - index = DWARF_REG_TO_UNWIND_COLUMN (index); + index = DWARF_REG_TO_UNWIND_COLUMN (regno); gcc_assert (index < (int) sizeof(dwarf_reg_size_table)); size = dwarf_reg_size_table[index]; val = context->reg[index]; @@ -237,6 +237,14 @@ _Unwind_GetGR (struct _Unwind_Context *c if (_Unwind_IsExtendedContext (context) && context->by_value[index]) return _Unwind_Get_Unwind_Word (val); +#ifdef DWARF_LAZY_REGISTER_VALUE + { + _Unwind_Word value; + if (DWARF_LAZY_REGISTER_VALUE (regno, &value)) + return value; + } +#endif + /* This will segfault if the register hasn't been saved. */ if (size == sizeof(_Unwind_Ptr)) return * (_Unwind_Ptr *) (_Unwind_Internal_Ptr) val; Index: gcc/testsuite/g++.target/aarch64/aarch64.exp =================================================================== --- /dev/null 2017-11-03 10:40:07.002381728 +0000 +++ gcc/testsuite/g++.target/aarch64/aarch64.exp 2017-11-03 17:24:20.171023116 +0000 @@ -0,0 +1,38 @@ +# Specific regression driver for AArch64. +# Copyright (C) 2009-2017 Free Software Foundation, Inc. +# Contributed by ARM Ltd. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . */ + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if {![istarget aarch64*-*-*] } then { + return +} + +# Load support procs. +load_lib g++-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] "" "" + +# All done. +dg-finish Index: gcc/testsuite/g++.target/aarch64/sve_catch_1.C =================================================================== --- /dev/null 2017-11-03 10:40:07.002381728 +0000 +++ gcc/testsuite/g++.target/aarch64/sve_catch_1.C 2017-11-03 17:24:20.171023116 +0000 @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer" } */ +/* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer -march=armv8-a+sve" { target aarch64_sve_hw } } */ + +/* Invoke X (P##n) for n in [0, 7]. */ +#define REPEAT8(X, P) \ + X (P##0) X (P##1) X (P##2) X (P##3) X (P##4) X (P##5) X (P##6) X (P##7) + +/* Invoke X (n) for all octal n in [0, 39]. */ +#define REPEAT40(X) \ + REPEAT8 (X, 0) REPEAT8 (X, 1) REPEAT8 (X, 2) REPEAT8 (X, 3) REPEAT8 (X, 4) + +volatile int testi; + +/* Throw to f3. */ +void __attribute__ ((weak)) +f1 (int x[40][100], int *y) +{ + /* A wild write to x and y. */ + asm volatile ("" ::: "memory"); + if (y[testi] == x[testi][testi]) + throw 100; +} + +/* Expect vector work to be done, with spilling of vector registers. */ +void __attribute__ ((weak)) +f2 (int x[40][100], int *y) +{ + /* Try to force some spilling. */ +#define DECLARE(N) int y##N = y[N]; + REPEAT40 (DECLARE); + for (int j = 0; j < 20; ++j) + { + f1 (x, y); +#pragma omp simd + for (int i = 0; i < 100; ++i) + { +#define INC(N) x[N][i] += y##N; + REPEAT40 (INC); + } + } +} + +/* Catch an exception thrown from f1, via f2. */ +void __attribute__ ((weak)) +f3 (int x[40][100], int *y, int *z) +{ + volatile int extra = 111; + try + { + f2 (x, y); + } + catch (int val) + { + *z = val + extra; + } +} + +static int x[40][100]; +static int y[40]; +static int z; + +int +main (void) +{ + f3 (x, y, &z); + if (z != 211) + __builtin_abort (); + return 0; +} Index: gcc/testsuite/g++.target/aarch64/sve_catch_2.C =================================================================== --- /dev/null 2017-11-03 10:40:07.002381728 +0000 +++ gcc/testsuite/g++.target/aarch64/sve_catch_2.C 2017-11-03 17:24:20.171023116 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fopenmp-simd -fomit-frame-pointer" } */ +/* { dg-options "-O3 -fopenmp-simd -fomit-frame-pointer -march=armv8-a+sve" { target aarch64_sve_hw } } */ + +#include "sve_catch_1.C" Index: gcc/testsuite/g++.target/aarch64/sve_catch_3.C =================================================================== --- /dev/null 2017-11-03 10:40:07.002381728 +0000 +++ gcc/testsuite/g++.target/aarch64/sve_catch_3.C 2017-11-03 17:24:20.171023116 +0000 @@ -0,0 +1,79 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer" } */ +/* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer -march=armv8-a+sve" { target aarch64_sve_hw } } */ + +/* Invoke X (P##n) for n in [0, 7]. */ +#define REPEAT8(X, P) \ + X (P##0) X (P##1) X (P##2) X (P##3) X (P##4) X (P##5) X (P##6) X (P##7) + +/* Invoke X (n) for all octal n in [0, 39]. */ +#define REPEAT40(X) \ + REPEAT8 (X, 0) REPEAT8 (X, 1) REPEAT8 (X, 2) REPEAT8 (X, 3) REPEAT8 (X, 4) + +volatile int testi, sink; + +/* Take 2 stack arguments and throw to f3. */ +void __attribute__ ((weak)) +f1 (int x[40][100], int *y, int z1, int z2, int z3, int z4, + int z5, int z6, int z7, int z8) +{ + /* A wild write to x and y. */ + sink = z1; + sink = z2; + sink = z3; + sink = z4; + sink = z5; + sink = z6; + sink = z7; + sink = z8; + asm volatile ("" ::: "memory"); + if (y[testi] == x[testi][testi]) + throw 100; +} + +/* Expect vector work to be done, with spilling of vector registers. */ +void __attribute__ ((weak)) +f2 (int x[40][100], int *y) +{ + /* Try to force some spilling. */ +#define DECLARE(N) int y##N = y[N]; + REPEAT40 (DECLARE); + for (int j = 0; j < 20; ++j) + { + f1 (x, y, 1, 2, 3, 4, 5, 6, 7, 8); +#pragma omp simd + for (int i = 0; i < 100; ++i) + { +#define INC(N) x[N][i] += y##N; + REPEAT40 (INC); + } + } +} + +/* Catch an exception thrown from f1, via f2. */ +void __attribute__ ((weak)) +f3 (int x[40][100], int *y, int *z) +{ + volatile int extra = 111; + try + { + f2 (x, y); + } + catch (int val) + { + *z = val + extra; + } +} + +static int x[40][100]; +static int y[40]; +static int z; + +int +main (void) +{ + f3 (x, y, &z); + if (z != 211) + __builtin_abort (); + return 0; +} Index: gcc/testsuite/g++.target/aarch64/sve_catch_4.C =================================================================== --- /dev/null 2017-11-03 10:40:07.002381728 +0000 +++ gcc/testsuite/g++.target/aarch64/sve_catch_4.C 2017-11-03 17:24:20.171023116 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fopenmp-simd -fomit-frame-pointer" } */ +/* { dg-options "-O3 -fopenmp-simd -fomit-frame-pointer -march=armv8-a+sve" { target aarch64_sve_hw } } */ + +#include "sve_catch_3.C" Index: gcc/testsuite/g++.target/aarch64/sve_catch_5.C =================================================================== --- /dev/null 2017-11-03 10:40:07.002381728 +0000 +++ gcc/testsuite/g++.target/aarch64/sve_catch_5.C 2017-11-03 17:24:20.172023500 +0000 @@ -0,0 +1,82 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer" } */ +/* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer -march=armv8-a+sve" { target aarch64_sve_hw } } */ + +/* Invoke X (P##n) for n in [0, 7]. */ +#define REPEAT8(X, P) \ + X (P##0) X (P##1) X (P##2) X (P##3) X (P##4) X (P##5) X (P##6) X (P##7) + +/* Invoke X (n) for all octal n in [0, 39]. */ +#define REPEAT40(X) \ + REPEAT8 (X, 0) REPEAT8 (X, 1) REPEAT8 (X, 2) REPEAT8 (X, 3) REPEAT8 (X, 4) + +volatile int testi, sink; +volatile void *ptr; + +/* Take 2 stack arguments and throw to f3. */ +void __attribute__ ((weak)) +f1 (int x[40][100], int *y, int z1, int z2, int z3, int z4, + int z5, int z6, int z7, int z8) +{ + /* A wild write to x and y. */ + sink = z1; + sink = z2; + sink = z3; + sink = z4; + sink = z5; + sink = z6; + sink = z7; + sink = z8; + asm volatile ("" ::: "memory"); + if (y[testi] == x[testi][testi]) + throw 100; +} + +/* Expect vector work to be done, with spilling of vector registers. */ +void __attribute__ ((weak)) +f2 (int x[40][100], int *y) +{ + /* Create a true variable-sized frame. */ + ptr = __builtin_alloca (testi + 40); + /* Try to force some spilling. */ +#define DECLARE(N) int y##N = y[N]; + REPEAT40 (DECLARE); + for (int j = 0; j < 20; ++j) + { + f1 (x, y, 1, 2, 3, 4, 5, 6, 7, 8); +#pragma omp simd + for (int i = 0; i < 100; ++i) + { +#define INC(N) x[N][i] += y##N; + REPEAT40 (INC); + } + } +} + +/* Catch an exception thrown from f1, via f2. */ +void __attribute__ ((weak)) +f3 (int x[40][100], int *y, int *z) +{ + volatile int extra = 111; + try + { + f2 (x, y); + } + catch (int val) + { + *z = val + extra; + } +} + +static int x[40][100]; +static int y[40]; +static int z; + +int +main (void) +{ + f3 (x, y, &z); + if (z != 211) + __builtin_abort (); + return 0; +} Index: gcc/testsuite/g++.target/aarch64/sve_catch_6.C =================================================================== --- /dev/null 2017-11-03 10:40:07.002381728 +0000 +++ gcc/testsuite/g++.target/aarch64/sve_catch_6.C 2017-11-03 17:24:20.172023500 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fopenmp-simd -fomit-frame-pointer" } */ +/* { dg-options "-O3 -fopenmp-simd -fomit-frame-pointer -march=armv8-a+sve" { target aarch64_sve_hw } } */ + +#include "sve_catch_5.C"