From patchwork Thu Aug 27 12:38:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8809FC433DF for ; Thu, 27 Aug 2020 12:40:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D2772177B for ; Thu, 27 Aug 2020 12:40:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D2772177B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHCE-0001Kt-FU for qemu-devel@archiver.kernel.org; Thu, 27 Aug 2020 08:40:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBHBR-0007xe-IZ for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:13 -0400 Received: from mail02.asahi-net.or.jp ([202.224.55.14]:56301) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHBN-0005u5-SJ for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:13 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail02.asahi-net.or.jp (Postfix) with ESMTPA id 84A9B25525; Thu, 27 Aug 2020 21:39:05 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 0BBA51C0792; Thu, 27 Aug 2020 21:39:05 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 01/20] loader.c: Add support Motrola S-record format. Date: Thu, 27 Aug 2020 21:38:40 +0900 Message-Id: <20200827123859.81793-2-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.14; envelope-from=ysato@users.sourceforge.jp; helo=mail02.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Yoshinori Sato --- include/hw/loader.h | 14 +++ hw/core/loader.c | 208 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 222 insertions(+) diff --git a/include/hw/loader.h b/include/hw/loader.h index a9eeea3952..6f1fb62ded 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -55,6 +55,20 @@ int load_image_targphys_as(const char *filename, */ int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as); +/* + * load_targphys_srec_as: + * @filename: Path to the .hex file + * @entry: Store the entry point given by the .hex file + * @as: The AddressSpace to load the .hex file to. The value of + * address_space_memory is used if nothing is supplied here. + * + * Load a fixed .srec file into memory. + * + * Returns the size of the loaded .hex file on success, -1 otherwise. + */ +int load_targphys_srec_as(const char *filename, + hwaddr *entry, AddressSpace *as); + /** load_image_targphys: * Same as load_image_targphys_as(), but doesn't allow the caller to specify * an AddressSpace. diff --git a/hw/core/loader.c b/hw/core/loader.c index 8bbb1797a4..6964b04ec7 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1618,3 +1618,211 @@ int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as) g_free(hex_blob); return total_size; } + +typedef enum { + SREC_SOH, + SREC_TYPE, + SREC_LEN, + SREC_ADDR, + SREC_DATA, + SREC_SKIP, + SREC_SUM, +} srec_state; + +typedef struct { + srec_state state; + int nibble; + int total_size; + uint32_t address; + uint32_t topaddr; + uint32_t bufremain; + int length; + int addr_len; + int record_type; + uint8_t byte; + uint8_t data[DATA_FIELD_MAX_LEN]; + uint8_t *datap; + uint8_t *bufptr; + uint8_t sum; +} SrecLine; + +static bool parse_srec_line(SrecLine *line, char c) +{ + if (!g_ascii_isxdigit(c)) { + return false; + } + line->byte <<= 4; + line->byte |= g_ascii_xdigit_value(c); + line->nibble++; + if (line->nibble == 2) { + line->nibble = 0; + line->length--; + line->sum += line->byte; + switch (line->state) { + case SREC_SOH: + case SREC_TYPE: + /* first 2chars ignore parse */ + break; + case SREC_LEN: + line->sum = line->length = line->byte; + if (line->addr_len > 0) { + line->state = SREC_ADDR; + line->address = 0; + } else { + line->state = SREC_SKIP; + } + break; + case SREC_ADDR: + line->address <<= 8; + line->address |= line->byte; + if (--line->addr_len == 0) { + if (line->length > 1) { + if (line->record_type != 0) { + line->state = SREC_DATA; + } else { + line->state = SREC_SKIP; + } + line->datap = line->data; + } else { + line->state = SREC_SUM; + } + } + break; + case SREC_DATA: + *line->datap++ = line->byte; + /* fail through */ + case SREC_SKIP: + if (line->length == 1) { + line->state = SREC_SUM; + } + break; + case SREC_SUM: + if ((line->sum & 0xff) != 0xff) { + return false; + } + } + } + return true; +} + +#define SRECBUFSIZE 0x40000 + +/* return size or -1 if error */ +static int parse_srec_blob(const char *filename, hwaddr *addr, + uint8_t *hex_blob, size_t hex_blob_size, + AddressSpace *as) +{ + SrecLine line; + size_t len; + int total_len = 0; + uint8_t *end = hex_blob + hex_blob_size; + rom_transaction_begin(); + line.state = SREC_SOH; + line.bufptr = g_malloc(SRECBUFSIZE); + line.bufremain = SRECBUFSIZE; + line.topaddr = UINT32_MAX; + for (; hex_blob < end; ++hex_blob) { + switch (*hex_blob) { + case '\r': + case '\n': + if (line.state == SREC_SUM) { + switch (line.record_type) { + case 1: + case 2: + case 3: + len = line.datap - line.data; + if (line.topaddr == UINT32_MAX) { + line.topaddr = line.address; + } + if (line.bufremain < len || line.address < line.topaddr) { + rom_add_blob_fixed_as(filename, line.bufptr, + SRECBUFSIZE - line.bufremain, + line.topaddr, as); + line.topaddr = line.address; + line.bufremain = SRECBUFSIZE; + } + memcpy(line.bufptr + (line.address - line.topaddr), + line.data, len); + line.bufremain -= len; + total_len += len; + break; + case 7: + case 8: + case 9: + *addr = line.address; + break; + } + line.state = SREC_SOH; + } + break; + /* start of a new record. */ + case 'S': + if (line.state != SREC_SOH) { + total_len = -1; + goto out; + } + line.state = SREC_TYPE; + break; + /* decoding lines */ + default: + if (line.state == SREC_TYPE) { + if (g_ascii_isdigit(*hex_blob)) { + line.record_type = g_ascii_digit_value(*hex_blob); + switch (line.record_type) { + case 1: + case 2: + case 3: + line.addr_len = 1 + line.record_type; + break; + case 0: + case 5: + line.addr_len = 2; + break; + case 7: + case 8: + case 9: + line.addr_len = 11 - line.record_type; + break; + default: + line.addr_len = 0; + } + } + line.state = SREC_LEN; + line.nibble = 0; + } else { + if (!parse_srec_line(&line, *hex_blob)) { + total_len = -1; + goto out; + } + } + break; + } + } + if (line.bufremain < SRECBUFSIZE) { + rom_add_blob_fixed_as(filename, line.bufptr, + SRECBUFSIZE - line.bufremain, + line.topaddr, as); + } +out: + rom_transaction_end(total_len != -1); + g_free(line.bufptr); + return total_len; +} + +/* return size or -1 if error */ +int load_targphys_srec_as(const char *filename, hwaddr *entry, AddressSpace *as) +{ + gsize hex_blob_size; + gchar *hex_blob; + int total_size = 0; + + if (!g_file_get_contents(filename, &hex_blob, &hex_blob_size, NULL)) { + return -1; + } + + total_size = parse_srec_blob(filename, entry, (uint8_t *)hex_blob, + hex_blob_size, as); + + g_free(hex_blob); + return total_size; +} From patchwork Thu Aug 27 12:38:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F04AC433E4 for ; Thu, 27 Aug 2020 12:40:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6D522177B for ; Thu, 27 Aug 2020 12:39:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D6D522177B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHCA-0001AB-95 for qemu-devel@archiver.kernel.org; Thu, 27 Aug 2020 08:39:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBHBQ-0007xC-6F for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:12 -0400 Received: from mail02.asahi-net.or.jp ([202.224.55.14]:56302) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHBN-0005u8-TJ for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:11 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail02.asahi-net.or.jp (Postfix) with ESMTPA id CC51026329; Thu, 27 Aug 2020 21:39:05 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 7C96C1C07B2; Thu, 27 Aug 2020 21:39:05 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 03/20] hw/rx: Firmware and kernel loader. Date: Thu, 27 Aug 2020 21:38:42 +0900 Message-Id: <20200827123859.81793-4-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.14; envelope-from=ysato@users.sourceforge.jp; helo=mail02.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Suppoerted format. ELF, HEX, SREC and Raw firmware. fit and Raw kernel image. Signed-off-by: Yoshinori Sato --- include/hw/rx/loader.h | 35 ++++++++ hw/rx/loader.c | 182 +++++++++++++++++++++++++++++++++++++++++ hw/rx/Kconfig | 1 + hw/rx/meson.build | 1 + 4 files changed, 219 insertions(+) create mode 100644 include/hw/rx/loader.h create mode 100644 hw/rx/loader.c diff --git a/include/hw/rx/loader.h b/include/hw/rx/loader.h new file mode 100644 index 0000000000..71f3bd2bb3 --- /dev/null +++ b/include/hw/rx/loader.h @@ -0,0 +1,35 @@ +/* + * RX QEMU frimware loader + * + * Copyright (c) 2020 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qapi/error.h" +#include "qemu/error-report.h" + +typedef struct { + hwaddr ram_start; + size_t ram_size; + hwaddr entry; + hwaddr kernel_entry; + hwaddr dtb_address; + const char *filename; + const char *dtbname; + const char *cmdline; +} rx_kernel_info_t; + +bool load_bios(const char *filename, int rom_size, Error **errp); + +bool load_kernel(rx_kernel_info_t *info); diff --git a/hw/rx/loader.c b/hw/rx/loader.c new file mode 100644 index 0000000000..c262f3ef86 --- /dev/null +++ b/hw/rx/loader.c @@ -0,0 +1,182 @@ +/* + * RX QEMU frimware loader + * + * Copyright (c) 2020 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "elf.h" +#include "hw/loader.h" +#include "hw/loader-fit.h" +#include "hw/rx/loader.h" +#include "sysemu/device_tree.h" +#include "exec/cpu-defs.h" +#include + +#define RX_RESET_VEC 0xfffffffc +#define ADDRESS_TOP ((1LL << TARGET_PHYS_ADDR_SPACE_BITS) - 1) + +bool load_bios(const char *filename, int rom_size, Error **errp) +{ + int size; + uint64_t entry64 = UINT64_MAX; + uint32_t entry; + + size = load_elf(filename, NULL, NULL, NULL, &entry64, + NULL, NULL, NULL, 0, EM_RX, 0, 0); + if (size > 0) { + goto load_ok; + } + size = load_targphys_hex_as(filename, &entry64, NULL); + if (size > 0) { + goto load_ok; + } + size = load_targphys_srec_as(filename, &entry64, NULL); + if (size > 0) { + goto load_ok; + } + size = get_image_size(filename); + if (size < 0) { + error_setg(errp, "\"%s\" is open failed.", filename); + return false; + } + if (size > rom_size) { + error_setg(errp, "\"%s\" is too large for ROM area.", filename); + return false; + } + + /* + * The RX CPU reset vector is at the top of the ROM, + * so the raw binary is loaded there. + */ + rom_add_file_fixed(filename, -size, 0); + load_ok: + if (rom_ptr(RX_RESET_VEC, 4) == NULL) { + if (entry64 <= ADDRESS_TOP) { + entry = cpu_to_le32(entry64); + rom_add_blob_fixed("entry", &entry, 4, RX_RESET_VEC); + } else { + error_setg(errp, "Reset vector is not set"); + return false; + } + } + return true; +} + +static hwaddr rx_addr_to_phys(void *opaque, uint64_t addr) +{ + /* No address translation */ + return addr; +} + +static bool setup_commandline(void *dtb, rx_kernel_info_t *info) +{ + if (info->cmdline && + qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", + info->cmdline) < 0) { + return false; + } + return true; +} + + +static const void *rx_fdt_filter(void *opaque, const void *fdt_orig, + const void *match_data, hwaddr *load_addr) +{ + rx_kernel_info_t *info = opaque; + void *fdt; + size_t fdt_sz; + int err; + + fdt_sz = fdt_totalsize(fdt_orig) + 0x1000; + fdt = g_malloc0(fdt_sz); + + err = fdt_open_into(fdt_orig, fdt, fdt_sz); + if (err) { + error_report("couldn't open dtb"); + return NULL; + } + + if (!setup_commandline(fdt, info)) { + error_report("couldn't set /chosen/bootargs"); + return NULL; + } + fdt_sz = fdt_totalsize(fdt); + fdt = g_realloc(fdt, fdt_totalsize(fdt)); + info->dtb_address = info->ram_start + info->ram_size - fdt_sz; + *load_addr = info->dtb_address; + + return fdt; +} + +static const void *rx_kernel_filter(void *opaque, const void *kernel, + hwaddr *load_addr, hwaddr *entry_addr) +{ + rx_kernel_info_t *info = opaque; + + info->kernel_entry = *entry_addr; + + return kernel; +} + +static const struct fit_loader rx_fit_loader = { + .addr_to_phys = rx_addr_to_phys, + .fdt_filter = rx_fdt_filter, + .kernel_filter = rx_kernel_filter, +}; + +bool load_kernel(rx_kernel_info_t *info) +{ + ram_addr_t kernel_offset; + size_t kernel_size; + + if (load_fit(&rx_fit_loader, info->filename, info) == 0) { + return true; + } + + /* + * The kernel image is loaded into + * the latter half of the SDRAM space. + */ + kernel_offset = info->ram_size / 2; + + info->entry = info->ram_start + kernel_offset; + kernel_size = load_image_targphys(info->filename, + info->entry, info->ram_size / 2); + if (kernel_size == -1) { + return false; + } + if (info->dtbname) { + ram_addr_t dtb_offset; + int dtb_size; + void *dtb; + + dtb = load_device_tree(info->dtbname, &dtb_size); + if (dtb == NULL) { + error_report("Couldn't open dtb file %s", info->dtbname); + return false; + } + if (!setup_commandline(dtb, info)) { + error_report("Couldn't set /chosen/bootargs"); + return false; + } + /* DTB is located at the end of SDRAM space. */ + dtb_size = fdt_totalsize(dtb); + dtb_offset = info->ram_size - dtb_size; + info->dtb_address = info->ram_start + dtb_offset; + rom_add_blob_fixed("dtb", dtb, dtb_size, info->dtb_address); + } + return true; +} diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig index 2b297c5a6a..a63e4a5520 100644 --- a/hw/rx/Kconfig +++ b/hw/rx/Kconfig @@ -8,3 +8,4 @@ config RX62N_MCU config RX_GDBSIM bool select RX62N_MCU + select FITLOADER diff --git a/hw/rx/meson.build b/hw/rx/meson.build index d223512a78..e73850f303 100644 --- a/hw/rx/meson.build +++ b/hw/rx/meson.build @@ -1,4 +1,5 @@ rx_ss = ss.source_set() +rx_ss.add(files('loader.c')) rx_ss.add(when: 'CONFIG_RX_GDBSIM', if_true: files('rx-gdbsim.c')) rx_ss.add(when: 'CONFIG_RX62N_MCU', if_true: files('rx62n.c')) From patchwork Thu Aug 27 12:38:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A005C433E1 for ; Thu, 27 Aug 2020 12:41:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D09812177B for ; Thu, 27 Aug 2020 12:41:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D09812177B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:47024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHDU-0004Yd-20 for qemu-devel@archiver.kernel.org; Thu, 27 Aug 2020 08:41:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBHBS-0007yC-83 for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:14 -0400 Received: from mail01.asahi-net.or.jp ([202.224.55.13]:47877) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHBN-0005uA-Tb for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:13 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id 045621080B5; Thu, 27 Aug 2020 21:39:06 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id B23DE1C0696; Thu, 27 Aug 2020 21:39:05 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 04/20] hw/rx: New firmware loader. Date: Thu, 27 Aug 2020 21:38:43 +0900 Message-Id: <20200827123859.81793-5-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.13; envelope-from=ysato@users.sourceforge.jp; helo=mail01.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Separate the loading of the firmware from the target definition as it is an obstacle to adding more targets. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 15 +++++++ hw/rx/rx-gdbsim.c | 98 +++++++++++++++++++++---------------------- hw/rx/rx62n.c | 25 ----------- 3 files changed, 64 insertions(+), 74 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index aa94758c27..32e460bbad 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -45,6 +45,21 @@ #define RX62N_NR_CMT 2 #define RX62N_NR_SCI 6 +typedef struct RX62NClass { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + const char *name; + uint64_t ram_size; + uint64_t rom_flash_size; + uint64_t data_flash_size; +} RX62NClass; + +#define RX62N_MCU_CLASS(klass) \ + OBJECT_CLASS_CHECK(RX62NClass, (klass), TYPE_RX62N_MCU) +#define RX62N_MCU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RX62NClass, (obj), TYPE_RX62N_MCU) + typedef struct RX62NState { /*< private >*/ DeviceState parent_obj; diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 54992ebe57..02e03c797c 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -25,6 +25,7 @@ #include "hw/hw.h" #include "hw/sysbus.h" #include "hw/loader.h" +#include "hw/rx/loader.h" #include "hw/rx/rx62n.h" #include "sysemu/sysemu.h" #include "sysemu/qtest.h" @@ -40,6 +41,7 @@ typedef struct RxGdbSimMachineClass { /*< public >*/ const char *mcu_name; uint32_t xtal_freq_hz; + size_t romsize; } RxGdbSimMachineClass; typedef struct RxGdbSimMachineState { @@ -59,26 +61,39 @@ typedef struct RxGdbSimMachineState { #define RX_GDBSIM_MACHINE_GET_CLASS(obj) \ OBJECT_GET_CLASS(RxGdbSimMachineClass, (obj), TYPE_RX_GDBSIM_MACHINE) -static void rx_load_image(RXCPU *cpu, const char *filename, - uint32_t start, uint32_t size) +#define TINYBOOT_TOP (0xffffff00) + +static void set_bootstrap(hwaddr entry, hwaddr dtb) { - static uint32_t extable[32]; - long kernel_size; + /* Minimal hardware initialize for kernel requirement */ + /* linux kernel only works little-endian mode */ + static uint8_t tinyboot[256] = { + 0xfb, 0x2e, 0x20, 0x00, 0x08, /* mov.l #0x80020, r2 */ + 0xf8, 0x2e, 0x00, 0x01, 0x01, /* mov.l #0x00010100, [r2] */ + 0xfb, 0x2e, 0x10, 0x00, 0x08, /* mov.l #0x80010, r2 */ + 0xf8, 0x22, 0xdf, 0x7d, 0xff, 0xff, /* mov.l #0xffff7ddf, [r2] */ + 0x62, 0x42, /* add #4, r2 */ + 0xf8, 0x22, 0xff, 0x7f, 0xff, 0x7f, /* mov.l #0x7fff7fff, [r2] */ + 0xfb, 0x2e, 0x40, 0x82, 0x08, /* mov.l #0x88240, r2 */ + 0x3c, 0x22, 0x00, /* mov.b #0, 2[r2] */ + 0x3c, 0x21, 0x4e, /* mov.b #78, 1[r2] */ + 0xfb, 0x22, 0x70, 0xff, 0xff, 0xff, /* mov.l #0xffffff70, r2 */ + 0xec, 0x21, /* mov.l [r2], r1 */ + 0xfb, 0x22, 0x74, 0xff, 0xff, 0xff, /* mov.l #0xffffff74, r2 */ + 0xec, 0x22, /* mov.l [r2], r2 */ + 0x7f, 0x02, /* jmp r2 */ + }; int i; - kernel_size = load_image_targphys(filename, start, size); - if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", filename); - exit(1); - } - cpu->env.pc = start; + *((uint32_t *)&tinyboot[0x70]) = cpu_to_le32(dtb); + *((uint32_t *)&tinyboot[0x74]) = cpu_to_le32(entry); /* setup exception trap trampoline */ - /* linux kernel only works little-endian mode */ - for (i = 0; i < ARRAY_SIZE(extable); i++) { - extable[i] = cpu_to_le32(0x10 + i * 4); + for (i = 0; i < 31; i++) { + *((uint32_t *)&tinyboot[0x40 + i * 4]) = cpu_to_le32(0x10 + i * 4); } - rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_BASE); + *((uint32_t *)&tinyboot[0xfc - 0x40]) = cpu_to_le32(TINYBOOT_TOP); + rom_add_blob_fixed("tinyboot", tinyboot, sizeof(tinyboot), TINYBOOT_TOP); } static void rx_gdbsim_init(MachineState *machine) @@ -86,10 +101,11 @@ static void rx_gdbsim_init(MachineState *machine) MachineClass *mc = MACHINE_GET_CLASS(machine); RxGdbSimMachineState *s = RX_GDBSIM_MACHINE(machine); RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_GET_CLASS(machine); + RX62NClass *rx62nc; MemoryRegion *sysmem = get_system_memory(); const char *kernel_filename = machine->kernel_filename; const char *dtb_filename = machine->dtb; - + rx_kernel_info_t kernel_info; if (machine->ram_size < mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); error_report("Invalid RAM size, should be more than %s", sz); @@ -101,49 +117,33 @@ static void rx_gdbsim_init(MachineState *machine) /* Initialize MCU */ object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name); + rx62nc = RX62N_MCU_GET_CLASS(&s->mcu); object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem), &error_abort); object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", rxc->xtal_freq_hz, &error_abort); - object_property_set_bool(OBJECT(&s->mcu), "load-kernel", - kernel_filename != NULL, &error_abort); - qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); - /* Load kernel and dtb */ if (kernel_filename) { - ram_addr_t kernel_offset; - - /* - * The kernel image is loaded into - * the latter half of the SDRAM space. - */ - kernel_offset = machine->ram_size / 2; - rx_load_image(RXCPU(first_cpu), kernel_filename, - SDRAM_BASE + kernel_offset, kernel_offset); - if (dtb_filename) { - ram_addr_t dtb_offset; - int dtb_size; - void *dtb; - - dtb = load_device_tree(dtb_filename, &dtb_size); - if (dtb == NULL) { - error_report("Couldn't open dtb file %s", dtb_filename); - exit(1); - } - if (machine->kernel_cmdline && - qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", - machine->kernel_cmdline) < 0) { - error_report("Couldn't set /chosen/bootargs"); - exit(1); + kernel_info.ram_start = SDRAM_BASE; + kernel_info.ram_size = machine->ram_size; + kernel_info.filename = kernel_filename; + kernel_info.dtbname = dtb_filename; + kernel_info.cmdline = machine->kernel_cmdline; + if (!load_kernel(&kernel_info)) { + exit(1); + } + set_bootstrap(kernel_info.entry, kernel_info.dtb_address); + } else { + if (bios_name) { + if (!load_bios(bios_name, rx62nc->rom_flash_size, &error_abort)) { + exit(0); } - /* DTB is located at the end of SDRAM space. */ - dtb_offset = machine->ram_size - dtb_size; - rom_add_blob_fixed("dtb", dtb, dtb_size, - SDRAM_BASE + dtb_offset); - /* Set dtb address to R1 */ - RXCPU(first_cpu)->env.regs[1] = SDRAM_BASE + dtb_offset; + } else if (!qtest_enabled()) { + error_report("No bios or kernel specified"); + exit(1); } } + qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); } static void rx_gdbsim_class_init(ObjectClass *oc, void *data) diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index b9c217ebfa..4b5c3c1079 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -60,21 +60,6 @@ #define RX62N_XTAL_MAX_HZ (14 * 1000 * 1000) #define RX62N_PCLK_MAX_HZ (50 * 1000 * 1000) -typedef struct RX62NClass { - /*< private >*/ - DeviceClass parent_class; - /*< public >*/ - const char *name; - uint64_t ram_size; - uint64_t rom_flash_size; - uint64_t data_flash_size; -} RX62NClass; - -#define RX62N_MCU_CLASS(klass) \ - OBJECT_CLASS_CHECK(RX62NClass, (klass), TYPE_RX62N_MCU) -#define RX62N_MCU_GET_CLASS(obj) \ - OBJECT_GET_CLASS(RX62NClass, (obj), TYPE_RX62N_MCU) - /* * IRQ -> IPR mapping table * 0x00 - 0x91: IPR no (IPR00 to IPR91) @@ -245,15 +230,6 @@ static void rx62n_realize(DeviceState *dev, Error **errp) rxc->rom_flash_size, &error_abort); memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash); - if (!s->kernel) { - if (bios_name) { - rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); - } else if (!qtest_enabled()) { - error_report("No bios or kernel specified"); - exit(1); - } - } - /* Initialize CPU */ object_initialize_child(OBJECT(s), "cpu", &s->cpu, TYPE_RX62N_CPU); qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); @@ -270,7 +246,6 @@ static void rx62n_realize(DeviceState *dev, Error **errp) static Property rx62n_properties[] = { DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false), DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0), DEFINE_PROP_END_OF_LIST(), }; From patchwork Thu Aug 27 12:38:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 764BEC433E3 for ; Thu, 27 Aug 2020 12:45:29 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 412C922B4B for ; Thu, 27 Aug 2020 12:45:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 412C922B4B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:35244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHHU-0002nR-Cx for qemu-devel@archiver.kernel.org; Thu, 27 Aug 2020 08:45:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBHBT-00082T-Jm for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:15 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:39208) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHBO-0005uR-1U for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:15 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail03.asahi-net.or.jp (Postfix) with ESMTPA id 47DB7268A6; Thu, 27 Aug 2020 21:39:06 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id E2D131C0792; Thu, 27 Aug 2020 21:39:05 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 05/20] hw/rx: Add RX62N Clock generator Date: Thu, 27 Aug 2020 21:38:44 +0900 Message-Id: <20200827123859.81793-6-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.15; envelope-from=ysato@users.sourceforge.jp; helo=mail03.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This module generated core and peripheral clock. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n-cpg.h | 72 ++++++++ include/hw/rx/rx62n.h | 5 +- hw/rx/rx62n-cpg.c | 344 ++++++++++++++++++++++++++++++++++++++ hw/rx/rx62n.c | 52 +++--- hw/rx/meson.build | 2 +- 5 files changed, 447 insertions(+), 28 deletions(-) create mode 100644 include/hw/rx/rx62n-cpg.h create mode 100644 hw/rx/rx62n-cpg.c diff --git a/include/hw/rx/rx62n-cpg.h b/include/hw/rx/rx62n-cpg.h new file mode 100644 index 0000000000..d90a067313 --- /dev/null +++ b/include/hw/rx/rx62n-cpg.h @@ -0,0 +1,72 @@ +/* + * RX62N Clock generator circuit + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2020 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_RX_RX62N_CPG_H +#define HW_RX_RX62N_CPG_H + +#include "hw/sysbus.h" +#include "hw/qdev-clock.h" + +#define TYPE_RX62N_CPG "rx62n-cpg" +#define RX62NCPG(obj) OBJECT_CHECK(RX62NCPGState, (obj), TYPE_RX62N_CPG) + +enum { + CK_TMR8_1, + CK_TMR8_0, + CK_MTU_1, + CK_MTU_0, + CK_CMT_1, + CK_CMT_0, + CK_EDMAC, + CK_SCI6, + CK_SCI5, + CK_SCI3, + CK_SCI2, + CK_SCI1, + CK_SCI0, + NUM_SUBCLOCK, +}; + +typedef struct RX62NCPGState { + SysBusDevice parent_obj; + uint32_t mstpcr[3]; + uint32_t sckcr; + uint8_t bckcr; + uint8_t ostdcr; + + int ick; + Clock *clk_ick; + int bck; + Clock *clk_bck; + int pck; + Clock *clk_pck; + Clock *dev_clocks[NUM_SUBCLOCK]; + uint32_t xtal_freq_hz; + MemoryRegion memory; +} RX62NCPGState; + +typedef struct RX62NCPGClass { + SysBusDeviceClass parent; +} RX62NCPGClass; + +#define OSTDCR_KEY 0xac + +#endif diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 32e460bbad..e0ca1cfc33 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -29,6 +29,7 @@ #include "hw/timer/renesas_tmr.h" #include "hw/timer/renesas_cmt.h" #include "hw/char/renesas_sci.h" +#include "hw/rx/rx62n-cpg.h" #include "qemu/units.h" #define TYPE_RX62N_MCU "rx62n-mcu" @@ -70,9 +71,9 @@ typedef struct RX62NState { RTMRState tmr[RX62N_NR_TMR]; RCMTState cmt[RX62N_NR_CMT]; RSCIState sci[RX62N_NR_SCI]; + RX62NCPGState cpg; MemoryRegion *sysmem; - bool kernel; MemoryRegion iram; MemoryRegion iomem1; @@ -84,8 +85,6 @@ typedef struct RX62NState { /* Input Clock (XTAL) frequency */ uint32_t xtal_freq_hz; - /* Peripheral Module Clock frequency */ - uint32_t pclk_freq_hz; } RX62NState; #endif diff --git a/hw/rx/rx62n-cpg.c b/hw/rx/rx62n-cpg.c new file mode 100644 index 0000000000..9d70004302 --- /dev/null +++ b/hw/rx/rx62n-cpg.c @@ -0,0 +1,344 @@ +/* + * RX62N Clock Generation Circuit + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2020 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/hw.h" +#include "hw/rx/rx62n-cpg.h" +#include "hw/sysbus.h" +#include "hw/qdev-properties.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/clock.h" +#include "migration/vmstate.h" + +#define RX62N_XTAL_MIN_HZ (8 * 1000 * 1000) +#define RX62N_XTAL_MAX_HZ (14 * 1000 * 1000) + +REG32(MSTPCRA, 0) +REG32(MSTPCRB, 4) +REG32(MSTPCRC, 8) +REG32(SCKCR, 16) + FIELD(SCKCR, PCK, 8, 3) + FIELD(SCKCR, BCK, 16, 3) + FIELD(SCKCR, PSTOP, 22, 2) + FIELD(SCKCR, ICK, 24, 3) +REG8(BCKCR, 32) + FIELD(BCKCR, BCLKDIV, 0, 1) +REG16(OSTDCR, 48) + FIELD(OSTDCR, OSTDF, 6, 1) + FIELD(OSTDCR, OSTDE, 7, 1) + +static const int access_size[] = {4, 4, 1, 2}; + +typedef struct { + const char *name; + int devnum; + int reg; + int offset; + int parentck; +} dev_clock_t; + +enum { + parent_ick, parent_bck, parent_pck, +}; + +static const dev_clock_t dev_clock_list[] = { + { .name = "pck_tmr8-1", + .devnum = CK_TMR8_1, .reg = 0, .offset = 4, .parentck = parent_pck, }, + { .name = "pck_tmr8-0", + .devnum = CK_TMR8_0, .reg = 0, .offset = 5, .parentck = parent_pck, }, + { .name = "pck_mtu-1", + .devnum = CK_MTU_1, .reg = 0, .offset = 8, .parentck = parent_pck, }, + { .name = "pck_mtu-0", + .devnum = CK_MTU_0, .reg = 0, .offset = 9, .parentck = parent_pck, }, + { .name = "pck_cmt-1", + .devnum = CK_CMT_1, .reg = 0, .offset = 14, .parentck = parent_pck, }, + { .name = "pck_cmt-0", + .devnum = CK_CMT_0, .reg = 0, .offset = 15, .parentck = parent_pck, }, + { .name = "ick_edmac", + .devnum = CK_EDMAC, .reg = 1, .offset = 15, .parentck = parent_ick, }, + { .name = "pck_sci-6", + .devnum = CK_SCI6, .reg = 1, .offset = 25, .parentck = parent_pck, }, + { .name = "pck_sci-5", + .devnum = CK_SCI5, .reg = 1, .offset = 26, .parentck = parent_pck, }, + { .name = "pck_sci-3", + .devnum = CK_SCI3, .reg = 1, .offset = 28, .parentck = parent_pck, }, + { .name = "pck_sci-2", + .devnum = CK_SCI2, .reg = 1, .offset = 29, .parentck = parent_pck, }, + { .name = "pck_sci-1", + .devnum = CK_SCI1, .reg = 1, .offset = 30, .parentck = parent_pck, }, + { .name = "pck_sci-0", + .devnum = CK_SCI0, .reg = 1, .offset = 31, .parentck = parent_pck, }, + { }, +}; + +static void set_clock_in(RX62NCPGState *cpg, const dev_clock_t *ck) +{ + Clock *out; + uint64_t period; + + out = qdev_get_clock_out(DEVICE(cpg), ck->name); + g_assert(out); + period = 0; + if (extract32(cpg->mstpcr[ck->reg], ck->offset, 1) == 0) { + switch (ck->parentck) { + case parent_ick: + period = clock_get(cpg->clk_ick); + break; + case parent_pck: + period = clock_get(cpg->clk_pck); + break; + } + } + if (clock_get(out) != period) { + clock_update(out, period); + } +} + +#define update_ck(ckname) \ + if (cpg->ckname != ckname) { \ + cpg->ckname = ckname; \ + ckname = 8 / (1 << ckname); \ + clock_update_hz(cpg->clk_ ## ckname, \ + cpg->xtal_freq_hz * ckname); \ + } + +#define validate_setting(ckname) \ + if (ick > ckname) { \ + qemu_log_mask(LOG_GUEST_ERROR, \ + "rx62n-cpg: Invalid " #ckname " setting." \ + " (ick=%d " #ckname "=%d)\n", ick, ckname); \ + cpg->ckname = ckname = ick; \ + } + +static void update_divrate(RX62NCPGState *cpg) +{ + int ick = FIELD_EX32(cpg->sckcr, SCKCR, ICK); + int bck = FIELD_EX32(cpg->sckcr, SCKCR, BCK); + int pck = FIELD_EX32(cpg->sckcr, SCKCR, PCK); + const dev_clock_t *p = dev_clock_list; + validate_setting(pck); + validate_setting(bck); + update_ck(ick); + update_ck(bck); + update_ck(pck); + while (p->name) { + set_clock_in(cpg, p); + p++; + } +} + +static const dev_clock_t *find_clock_list(int crno, int bit) +{ + const dev_clock_t *ret = dev_clock_list; + while (ret->name) { + if (ret->reg == crno && ret->offset == bit) { + return ret; + } + ret++; + } + return NULL; +} + +static void update_mstpcr(RX62NCPGState *cpg, int crno, uint32_t diff) +{ + int bit = 0; + const dev_clock_t *p; + + while (diff) { + if (diff & 1) { + p = find_clock_list(crno, bit); + if (p) { + set_clock_in(cpg, p); + } else { + qemu_log_mask(LOG_UNIMP, "rx62n-cpg: MSTPCR%c " + " bit %d is not implement.\n", 'A' + crno, bit); + } + } + bit++; + diff >>= 1; + } +} + +static uint64_t cpg_read(void *opaque, hwaddr addr, unsigned size) +{ + RX62NCPGState *cpg = RX62NCPG(opaque); + + if (access_size[addr >> 4] != size) { + qemu_log_mask(LOG_GUEST_ERROR, "rx62n-cpg: Register 0x%" + HWADDR_PRIX " Invalid access size.\n", addr); + return UINT64_MAX; + } + switch (addr) { + case A_MSTPCRA: + return cpg->mstpcr[0] | 0x473530cf; + case A_MSTPCRB: + return cpg->mstpcr[1] | 0x09407ffe; + case A_MSTPCRC: + return (cpg->mstpcr[2] | 0xffff0000) & 0xffff0003; + case A_SCKCR: + return cpg->sckcr & 0x0fcf0f00; + case A_BCKCR: + return cpg->bckcr & 0x01; + case A_OSTDCR: + /* Main OSC always good */ + return cpg->ostdcr & 0x0080; + default: + qemu_log_mask(LOG_GUEST_ERROR, "rx62n-cpg: Register 0x%" + HWADDR_PRIX " Invalid address.\n", addr); + return UINT64_MAX; + } +} + +static void cpg_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + RX62NCPGState *cpg = RX62NCPG(opaque); + uint32_t old_mstpcr; + int cr_no; + if (access_size[addr >> 4] != size) { + qemu_log_mask(LOG_GUEST_ERROR, "rx62n-cpg: Register 0x%" + HWADDR_PRIX " Invalid access size.\n", addr); + return; + } + switch (addr) { + case A_MSTPCRA: + case A_MSTPCRB: + case A_MSTPCRC: + cr_no = (addr & 0x0f) >> 2; + old_mstpcr = cpg->mstpcr[cr_no]; + old_mstpcr ^= val; + cpg->mstpcr[cr_no] = val; + update_mstpcr(cpg, cr_no, old_mstpcr); + break; + case A_SCKCR: + cpg->sckcr = val; + update_divrate(cpg); + break; + case A_BCKCR: + cpg->bckcr = val; + break; + case A_OSTDCR: + if (extract16(val, 8, 8) == OSTDCR_KEY) { + cpg->ostdcr = val; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "rx62n-cpg: Register 0x%" + HWADDR_PRIX " Invalid key value.\n", addr); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "rx62n-cpg: Register 0x%" + HWADDR_PRIX " Invalid address.\n", addr); + } +} + +static const MemoryRegionOps cpg_ops = { + .write = cpg_write, + .read = cpg_read, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static const ClockPortInitArray rx62n_cpg_clocks = { + QDEV_CLOCK_OUT(RX62NCPGState, clk_ick), + QDEV_CLOCK_OUT(RX62NCPGState, clk_bck), + QDEV_CLOCK_OUT(RX62NCPGState, clk_pck), + QDEV_CLOCK_END +}; + +static void cpg_realize(DeviceState *dev, Error **errp) +{ + RX62NCPGState *cpg = RX62NCPG(dev); + const dev_clock_t *p = dev_clock_list; + + if (cpg->xtal_freq_hz == 0) { + error_setg(errp, "\"xtal-frequency-hz\" property must be provided."); + return; + } + /* XTAL range: 8-14 MHz */ + if (cpg->xtal_freq_hz < RX62N_XTAL_MIN_HZ || + cpg->xtal_freq_hz > RX62N_XTAL_MAX_HZ) { + error_setg(errp, "\"xtal-frequency-hz\" property in incorrect range."); + return; + } + + cpg->sckcr = FIELD_DP32(cpg->sckcr, SCKCR, ICK, 2); + cpg->sckcr = FIELD_DP32(cpg->sckcr, SCKCR, BCK, 2); + cpg->sckcr = FIELD_DP32(cpg->sckcr, SCKCR, PCK, 2); + cpg->ostdcr = FIELD_DP8(cpg->ostdcr, OSTDCR, OSTDE, 1); + cpg->mstpcr[0] = 0x47ffffff; + cpg->mstpcr[1] = 0xffffffff; + cpg->mstpcr[2] = 0xffff0000; + + /* set initial state */ + while (p->name) { + set_clock_in(cpg, p); + p++; + } + update_divrate(cpg); +} + +static void rx62n_cpg_init(Object *obj) +{ + RX62NCPGState *cpg = RX62NCPG(obj); + const dev_clock_t *p = dev_clock_list; + qdev_init_clocks(DEVICE(obj), rx62n_cpg_clocks); + /* connect parent clock */ + while (p->name) { + cpg->dev_clocks[p->devnum] = qdev_init_clock_out(DEVICE(obj), + p->name); + p++; + } + + memory_region_init_io(&cpg->memory, OBJECT(cpg), &cpg_ops, + cpg, "rx62n-cpg", 0x40); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &cpg->memory); +} + +static Property rx62n_cpg_properties[] = { + DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NCPGState, xtal_freq_hz, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rx62n_cpg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = cpg_realize; + device_class_set_props(dc, rx62n_cpg_properties); +} + +static const TypeInfo rx62n_cpg_info[] = { + { + .name = TYPE_RX62N_CPG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(RX62NCPGState), + .instance_init = rx62n_cpg_init, + .class_init = rx62n_cpg_class_init, + .class_size = sizeof(RX62NCPGClass), + }, +}; + +DEFINE_TYPES(rx62n_cpg_info) diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 4b5c3c1079..ec63fa5db1 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -47,6 +47,7 @@ #define RX62N_TMR_BASE 0x00088200 #define RX62N_CMT_BASE 0x00088000 #define RX62N_SCI_BASE 0x00088240 +#define RX62N_CPG_BASE 0x00080010 /* * RX62N Peripheral IRQ @@ -56,10 +57,6 @@ #define RX62N_CMT_IRQ 28 #define RX62N_SCI_IRQ 214 -#define RX62N_XTAL_MIN_HZ (8 * 1000 * 1000) -#define RX62N_XTAL_MAX_HZ (14 * 1000 * 1000) -#define RX62N_PCLK_MAX_HZ (50 * 1000 * 1000) - /* * IRQ -> IPR mapping table * 0x00 - 0x91: IPR no (IPR00 to IPR91) @@ -149,36 +146,45 @@ static void register_tmr(RX62NState *s, int unit) { SysBusDevice *tmr; int i, irqbase; + char ckname[16]; object_initialize_child(OBJECT(s), "tmr[*]", &s->tmr[unit], TYPE_RENESAS_TMR); tmr = SYS_BUS_DEVICE(&s->tmr[unit]); - qdev_prop_set_uint64(DEVICE(tmr), "input-freq", s->pclk_freq_hz); - sysbus_realize(tmr, &error_abort); irqbase = RX62N_TMR_IRQ + TMR_NR_IRQ * unit; for (i = 0; i < TMR_NR_IRQ; i++) { sysbus_connect_irq(tmr, i, s->irq[irqbase + i]); } sysbus_mmio_map(tmr, 0, RX62N_TMR_BASE + unit * 0x10); + + qdev_prop_set_uint32(DEVICE(tmr), "unit", unit); + sysbus_realize(tmr, &error_abort); + snprintf(ckname, sizeof(ckname), "pck_tmr8-%d", unit); + qdev_connect_clock_in(DEVICE(tmr), "pck", + qdev_get_clock_out(DEVICE(&s->cpg), ckname)); } static void register_cmt(RX62NState *s, int unit) { SysBusDevice *cmt; int i, irqbase; + char ckname[16]; object_initialize_child(OBJECT(s), "cmt[*]", &s->cmt[unit], TYPE_RENESAS_CMT); cmt = SYS_BUS_DEVICE(&s->cmt[unit]); - qdev_prop_set_uint64(DEVICE(cmt), "input-freq", s->pclk_freq_hz); - sysbus_realize(cmt, &error_abort); + qdev_prop_set_uint32(DEVICE(cmt), "unit", unit); irqbase = RX62N_CMT_IRQ + CMT_NR_IRQ * unit; for (i = 0; i < CMT_NR_IRQ; i++) { sysbus_connect_irq(cmt, i, s->irq[irqbase + i]); } sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10); + sysbus_realize(cmt, &error_abort); + snprintf(ckname, sizeof(ckname), "pck_cmt-%d", unit); + qdev_connect_clock_in(DEVICE(cmt), "pck", + qdev_get_clock_out(DEVICE(&s->cpg), ckname)); } static void register_sci(RX62NState *s, int unit) @@ -190,7 +196,6 @@ static void register_sci(RX62NState *s, int unit) &s->sci[unit], TYPE_RENESAS_SCI); sci = SYS_BUS_DEVICE(&s->sci[unit]); qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); - qdev_prop_set_uint64(DEVICE(sci), "input-freq", s->pclk_freq_hz); sysbus_realize(sci, &error_abort); irqbase = RX62N_SCI_IRQ + SCI_NR_IRQ * unit; @@ -200,26 +205,23 @@ static void register_sci(RX62NState *s, int unit) sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08); } +static void register_cpg(RX62NState *s) +{ + SysBusDevice *cpg; + + object_initialize_child(OBJECT(s), "rx62n-cpg", &s->cpg, + TYPE_RX62N_CPG); + cpg = SYS_BUS_DEVICE(&s->cpg); + qdev_prop_set_uint64(DEVICE(cpg), "xtal-frequency-hz", s->xtal_freq_hz); + + sysbus_mmio_map(cpg, 0, RX62N_CPG_BASE); +} + static void rx62n_realize(DeviceState *dev, Error **errp) { RX62NState *s = RX62N_MCU(dev); RX62NClass *rxc = RX62N_MCU_GET_CLASS(dev); - if (s->xtal_freq_hz == 0) { - error_setg(errp, "\"xtal-frequency-hz\" property must be provided."); - return; - } - /* XTAL range: 8-14 MHz */ - if (s->xtal_freq_hz < RX62N_XTAL_MIN_HZ - || s->xtal_freq_hz > RX62N_XTAL_MAX_HZ) { - error_setg(errp, "\"xtal-frequency-hz\" property in incorrect range."); - return; - } - /* Use a 4x fixed multiplier */ - s->pclk_freq_hz = 4 * s->xtal_freq_hz; - /* PCLK range: 8-50 MHz */ - assert(s->pclk_freq_hz <= RX62N_PCLK_MAX_HZ); - memory_region_init_ram(&s->iram, OBJECT(dev), "iram", rxc->ram_size, &error_abort); memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram); @@ -236,11 +238,13 @@ static void rx62n_realize(DeviceState *dev, Error **errp) register_icu(s); s->cpu.env.ack = qdev_get_gpio_in_named(DEVICE(&s->icu), "ack", 0); + register_cpg(s); register_tmr(s, 0); register_tmr(s, 1); register_cmt(s, 0); register_cmt(s, 1); register_sci(s, 0); + sysbus_realize(SYS_BUS_DEVICE(&s->cpg), &error_abort); } static Property rx62n_properties[] = { diff --git a/hw/rx/meson.build b/hw/rx/meson.build index e73850f303..3a81d85a53 100644 --- a/hw/rx/meson.build +++ b/hw/rx/meson.build @@ -1,6 +1,6 @@ rx_ss = ss.source_set() rx_ss.add(files('loader.c')) rx_ss.add(when: 'CONFIG_RX_GDBSIM', if_true: files('rx-gdbsim.c')) -rx_ss.add(when: 'CONFIG_RX62N_MCU', if_true: files('rx62n.c')) +rx_ss.add(when: 'CONFIG_RX62N_MCU', if_true: files('rx62n.c', 'rx62n-cpg.c')) hw_arch += {'rx': rx_ss} From patchwork Thu Aug 27 12:38:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77E18C433E1 for ; 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Thu, 27 Aug 2020 08:39:17 -0400 Received: from mail01.asahi-net.or.jp ([202.224.55.13]:47908) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHBR-0005xg-F8 for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:16 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id F28311086DC; Thu, 27 Aug 2020 21:39:07 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id B20451C0696; Thu, 27 Aug 2020 21:39:07 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 12/20] hw/rx/rx62n: Use New SCI module. Date: Thu, 27 Aug 2020 21:38:51 +0900 Message-Id: <20200827123859.81793-13-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.13; envelope-from=ysato@users.sourceforge.jp; helo=mail01.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 2 +- hw/rx/rx62n.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 1182ca24de..f463148799 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -70,7 +70,7 @@ typedef struct RX62NState { RXICUState icu; RenesasTMR8State tmr[RX62N_NR_TMR]; RenesasCMTState cmt[RX62N_NR_CMT]; - RSCIState sci[RX62N_NR_SCI]; + RSCIAState sci[RX62N_NR_SCI]; RX62NCPGState cpg; MemoryRegion *sysmem; diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 0223396110..f61383a4c2 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -191,11 +191,13 @@ static void register_sci(RX62NState *s, int unit) { SysBusDevice *sci; int i, irqbase; + char ckname[16]; object_initialize_child(OBJECT(s), "sci[*]", - &s->sci[unit], TYPE_RENESAS_SCI); + &s->sci[unit], TYPE_RENESAS_SCIA); sci = SYS_BUS_DEVICE(&s->sci[unit]); qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); + qdev_prop_set_uint32(DEVICE(sci), "unit", unit); sysbus_realize(sci, &error_abort); irqbase = RX62N_SCI_IRQ + SCI_NR_IRQ * unit; @@ -203,6 +205,9 @@ static void register_sci(RX62NState *s, int unit) sysbus_connect_irq(sci, i, s->irq[irqbase + i]); } sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08); + snprintf(ckname, sizeof(ckname), "pck_sci-%d", unit); + qdev_connect_clock_in(DEVICE(sci), "pck", + qdev_get_clock_out(DEVICE(&s->cpg), ckname)); } static void register_cpg(RX62NState *s) From patchwork Thu Aug 27 12:38:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E255C433E1 for ; Thu, 27 Aug 2020 12:48:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3885622CAF for ; Thu, 27 Aug 2020 12:48:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3885622CAF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46760 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHKX-0007Xm-Hg for qemu-devel@archiver.kernel.org; Thu, 27 Aug 2020 08:48:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBHBW-0008Ax-Lh for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:18 -0400 Received: from mail01.asahi-net.or.jp ([202.224.55.13]:47911) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBHBS-0005y5-3g for qemu-devel@nongnu.org; Thu, 27 Aug 2020 08:39:18 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id 95A8910894A; Thu, 27 Aug 2020 21:39:08 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 50D301C0696; Thu, 27 Aug 2020 21:39:08 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 14/20] hw/rx/rx62n: RX62N Add MTU module Date: Thu, 27 Aug 2020 21:38:53 +0900 Message-Id: <20200827123859.81793-15-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.13; envelope-from=ysato@users.sourceforge.jp; helo=mail01.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 3 +++ hw/rx/rx62n.c | 28 ++++++++++++++++++++++++++++ hw/rx/Kconfig | 1 + 3 files changed, 32 insertions(+) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index f463148799..170c8cb6fc 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -28,6 +28,7 @@ #include "hw/intc/rx_icu.h" #include "hw/timer/renesas_tmr8.h" #include "hw/timer/renesas_timer.h" +#include "hw/timer/renesas_mtu.h" #include "hw/char/renesas_sci.h" #include "hw/rx/rx62n-cpg.h" #include "qemu/units.h" @@ -45,6 +46,7 @@ #define RX62N_NR_TMR 2 #define RX62N_NR_CMT 2 #define RX62N_NR_SCI 6 +#define RX62N_NR_MTU 2 typedef struct RX62NClass { /*< private >*/ @@ -70,6 +72,7 @@ typedef struct RX62NState { RXICUState icu; RenesasTMR8State tmr[RX62N_NR_TMR]; RenesasCMTState cmt[RX62N_NR_CMT]; + RenesasMTU2State mtu[RX62N_NR_MTU]; RSCIAState sci[RX62N_NR_SCI]; RX62NCPGState cpg; diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index f61383a4c2..344be846bc 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -46,6 +46,7 @@ #define RX62N_ICU_BASE 0x00087000 #define RX62N_TMR_BASE 0x00088200 #define RX62N_CMT_BASE 0x00088000 +#define RX62N_MTU_BASE 0x00088600 #define RX62N_SCI_BASE 0x00088240 #define RX62N_CPG_BASE 0x00080010 @@ -55,6 +56,7 @@ */ #define RX62N_TMR_IRQ 174 #define RX62N_CMT_IRQ 28 +#define RX62N_MTU_IRQ 114 #define RX62N_SCI_IRQ 214 /* @@ -187,6 +189,30 @@ static void register_cmt(RX62NState *s, int unit) qdev_get_clock_out(DEVICE(&s->cpg), ckname)); } +static void register_mtu(RX62NState *s, int unit) +{ + SysBusDevice *mtu; + int i, irqbase; + char ckname[16]; + + object_initialize_child(OBJECT(s), "mtu[*]", &s->mtu[unit], + TYPE_RENESAS_MTU2); + mtu = SYS_BUS_DEVICE(&s->mtu[unit]); + qdev_prop_set_uint32(DEVICE(mtu), "unit", unit); + + sysbus_mmio_map(mtu, 0, RX62N_MTU_BASE + 0x100 + unit * 0x400); + sysbus_mmio_map(mtu, 1, RX62N_MTU_BASE + unit * 0x400); + sysbus_mmio_map(mtu, 2, RX62N_MTU_BASE + 0x280 + unit * 0x400); + irqbase = RX62N_MTU_IRQ + MTU_NR_IRQ * unit; + for (i = 0; i < MTU_NR_IRQ; i++) { + sysbus_connect_irq(mtu, i, s->irq[irqbase + i]); + } + sysbus_realize(mtu, &error_abort); + snprintf(ckname, sizeof(ckname), "pck_mtu-%d", unit); + qdev_connect_clock_in(DEVICE(mtu), "pck", + qdev_get_clock_out(DEVICE(&s->cpg), ckname)); +} + static void register_sci(RX62NState *s, int unit) { SysBusDevice *sci; @@ -248,6 +274,8 @@ static void rx62n_realize(DeviceState *dev, Error **errp) register_tmr(s, 1); register_cmt(s, 0); register_cmt(s, 1); + register_mtu(s, 0); + register_mtu(s, 1); register_sci(s, 0); sysbus_realize(SYS_BUS_DEVICE(&s->cpg), &error_abort); } diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig index d1812870ea..887a5782bb 100644 --- a/hw/rx/Kconfig +++ b/hw/rx/Kconfig @@ -4,6 +4,7 @@ config RX62N_MCU select RENESAS_TMR8 select RENESAS_TIMER select RENESAS_SCI + select RENESAS_MTU config RX_GDBSIM bool From patchwork Thu Aug 27 12:38:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCC80C433E1 for ; Thu, 27 Aug 2020 12:49:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 82FA822CAE for ; Thu, 27 Aug 2020 12:49:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 82FA822CAE Authentication-Results: mail.kernel.org; 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Thu, 27 Aug 2020 21:39:08 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 813D91C0792; Thu, 27 Aug 2020 21:39:08 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 15/20] hw/net: Add generic Bit-bang MDIO PHY. Date: Thu, 27 Aug 2020 21:38:54 +0900 Message-Id: <20200827123859.81793-16-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.13; envelope-from=ysato@users.sourceforge.jp; helo=mail01.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Only supported link status. Signed-off-by: Yoshinori Sato --- include/hw/net/mdio.h | 126 ++++++++++++++++++++ hw/net/mdio.c | 264 ++++++++++++++++++++++++++++++++++++++++++ hw/net/Kconfig | 3 + hw/net/meson.build | 2 + 4 files changed, 395 insertions(+) create mode 100644 include/hw/net/mdio.h create mode 100644 hw/net/mdio.c diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h new file mode 100644 index 0000000000..55a7170e67 --- /dev/null +++ b/include/hw/net/mdio.h @@ -0,0 +1,126 @@ +/* + * MDIO PHY emulation + * + * Copyright 2020 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; under version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#ifndef MDIO_H +#define MDIO_H + +#include "hw/qdev-core.h" +#include "hw/net/mii.h" + +typedef enum mdio_pin { + mdio_z = -1, + mdio_l = 0, + mdio_h = 1, +} MDIOPin; + +#define TYPE_ETHER_PHY "ether-phy" +#define TYPE_ETHER_PHY_CLASS(obj) \ + OBJECT_GET_CLASS(EtherPHYClass, (obj), TYPE_ETHER_PHY) +#define EtherPHYClass(klass) \ + OBJECT_CHECK_CLASS(EtherPHYClass, (klass), TYPE_ETHER_PHY) +#define EtherPHY(obj) \ + OBJECT_CHECK(PHYState, (obj), TYPE_ETHER_PHY) + +#define TYPE_ETHER_MDIO_BB "ether-mdio-bb" +#define TYPE_ETHER_MDIO_BB_CLASS(obj) \ + OBJECT_GET_CLASS(MDIO_BBClass, (obj), TYPE_ETHER_MDIO_BB) +#define MDIO_BBClass(klass) \ + OBJECT_CHECK_CLASS(MDIO_BBClass, (klass), TYPE_ETHER_MDIO_BB) +#define MDIO_BB(obj) \ + OBJECT_CHECK(MDIOState, (obj), TYPE_ETHER_MDIO_BB) + +typedef enum { + phy_out_p = 0, /* Link up is 'H' */ + phy_out_n = 1, /* Link up is 'L' */ +} phy_output_polarity; + +typedef struct { + DeviceState parent; + + uint16_t regs[32]; + uint32_t identifier; + bool link_ok; + phy_output_polarity link_out_pol; + uint16_t bmsr; + uint16_t anlpar; +} PHYState; + +#define MDIO_ANLPAR_LINK \ + (MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 | \ + MII_ANLPAR_CSMACD) + +typedef enum { + BB_PRE, + BB_ST, + BB_CMD, + BB_TA_R, + BB_TA_W, + BB_DATA_R, + BB_DATA_W, + BB_INH, +} mdio_bb_state; + +typedef struct { + DeviceState parent; + + PHYState *phy; + mdio_bb_state bb_state; + int pclk; + int bits; + int cmd; + int phyad; + int selphy; + int regad; + int data; + int mdi_pin; + int mdo_pin; +} MDIOState; + +#define mdio_get_phy(s) (s->phy) + +typedef struct { + DeviceClass parent; +} EtherPHYClass; + +typedef struct { + DeviceClass parent; +} MDIO_BBClass; + +/* Generic PHY interface */ +void mdio_phy_set_link(PHYState *s, bool ok); +int mdio_phy_linksta(PHYState *s); +uint16_t mdio_phy_read(PHYState *s, int addr); +void mdio_phy_write(PHYState *s, int addr, uint16_t val); + +/* Bit-bang MDIO operation */ +static inline MDIOPin mdio_read_mdi_pin(MDIOState *s) +{ + return s->mdi_pin; +} + +static inline void mdio_set_mdo_pin(MDIOState *s, MDIOPin mdo) +{ + s->mdo_pin = mdo; +} + +void mdio_set_mdc_pin(MDIOState *s, int clk); + +#endif diff --git a/hw/net/mdio.c b/hw/net/mdio.c new file mode 100644 index 0000000000..39670e70c6 --- /dev/null +++ b/hw/net/mdio.c @@ -0,0 +1,264 @@ +/* + * Bit-bang MII emulation + * + * Copyright 2020 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; under version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/net/mdio.h" + +void mdio_phy_set_link(PHYState *s, bool ok) +{ + if (ok) { + s->regs[MII_BMSR] |= MII_BMSR_LINK_ST; + s->regs[MII_ANLPAR] |= MDIO_ANLPAR_LINK; + } else { + s->regs[MII_BMSR] &= ~(MII_BMSR_LINK_ST | MII_BMSR_AUTONEG); + s->regs[MII_ANLPAR] &= MDIO_ANLPAR_LINK; + } + s->link_ok = ok; +} + +static void mdio_phy_reset(PHYState *s) +{ + memset(s->regs, 0, sizeof(s->regs)); + s->regs[MII_BMSR] = s->bmsr; + s->regs[MII_ANLPAR] = s->anlpar; + s->regs[MII_PHYID1] = extract32(s->identifier, 16, 16); + s->regs[MII_PHYID2] = extract32(s->identifier, 0, 16); + mdio_phy_set_link(s, s->link_ok); +} + +uint16_t mdio_phy_read(PHYState *s, int addr) +{ + if (addr >= 0 && addr < 32) { + return s->regs[addr]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "mdio: Register %04x invalid address.\n", addr); + return 0; + } +} + +int mdio_phy_linksta(PHYState *s) +{ + return s->link_ok ^ s->link_out_pol; +} + +void mdio_phy_write(PHYState *s, int addr, uint16_t val) +{ + switch (addr) { + case MII_BMCR: + s->regs[MII_BMCR] = val & 0xfd80; + if (val & MII_BMCR_RESET) { + mdio_phy_reset(s); + } + break; + case MII_BMSR: + case MII_ANLPAR: + /* Read only */ + qemu_log_mask(LOG_GUEST_ERROR, + "mdio: Register %04x is read only register.\n", addr); + break; + case MII_PHYID1: + case MII_PHYID2: + s->regs[addr] = val; + break; + case MII_ANAR: + s->regs[addr] = val & 0x2dff; + break; + default: + qemu_log_mask(LOG_UNIMP, + "mdio: Register %04x not implemented\n", addr); + break; + } +} + +static Property phy_properties[] = { + DEFINE_PROP_UINT32("phy-id", PHYState, identifier, 0), + DEFINE_PROP_UINT32("link-out-pol", PHYState, link_out_pol, 0), + DEFINE_PROP_UINT16("bmsr", PHYState, bmsr, 0), + DEFINE_PROP_UINT16("anlpar", PHYState, anlpar, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void phy_realize(DeviceState *dev, Error **errp) +{ + PHYState *s = EtherPHY(dev); + mdio_phy_reset(s); +} + +static void phy_class_init(ObjectClass *klass, void *class_data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + device_class_set_props(dc, phy_properties); + dc->realize = phy_realize; +} + +/* shift in MDO */ +static void read_mdo(MDIOState *s) +{ + int op; + s->bits++; + switch (s->bb_state) { + case BB_PRE: /* preamble */ + if (s->mdo_pin == 0) { + /* ST 1st bit found */ + s->bb_state = BB_ST; + } + break; + case BB_ST: /* ST 2nd bit */ + if (s->mdo_pin == 0) { + s->bb_state = BB_CMD; + s->cmd = 0; + s->bits = 2; + s->selphy = -1; + s->regad = -1; + } else { + s->bb_state = BB_PRE; + } + break; + case BB_CMD: + s->cmd <<= 1; + s->cmd |= (s->mdo_pin & 1); + if (s->bits == 14) { + op = extract32(s->cmd, 10, 2); + s->selphy = extract32(s->cmd, 5, 5); + s->regad = extract32(s->cmd, 0, 5); + switch (op) { + case 0x02: /* READ */ + s->bb_state = BB_TA_R; + break; + case 0x01: /* WRITE */ + s->bb_state = BB_TA_W; + break; + default: + s->bb_state = BB_INH; + break; + } + } + break; + case BB_TA_R: + s->mdi_pin = 0; + if (s->bits == 16) { + if (s->phyad == s->selphy) { + s->data = mdio_phy_read(s->phy, s->regad); + s->bb_state = BB_DATA_R; + } else { + s->bb_state = BB_INH; + } + } + break; + case BB_TA_W: + if (s->bits == 16) { + s->bb_state = BB_DATA_W; + } + break; + case BB_DATA_W: + s->data <<= 1; + s->data |= (s->mdo_pin & 1); + if (s->bits == 32) { + if (s->phyad == s->selphy) { + mdio_phy_write(s->phy, s->regad, s->data); + } + s->bb_state = BB_PRE; + } + break; + case BB_INH: + case BB_DATA_R: + if (s->bits == 32) { + s->bb_state = BB_PRE; + } + break; + } +} + +/* shift out MDI */ +static void write_mdi(MDIOState *s) +{ + switch (s->bb_state) { + case BB_DATA_R: + s->mdi_pin = (s->data >> 15) & 1; + s->data <<= 1; + break; + case BB_TA_R: + s->mdi_pin = 0; + break; + default: + s->mdi_pin = mdio_z; + break; + } +} + +/* MDIO pin operation */ +void mdio_set_mdc_pin(MDIOState *s, int clk) +{ + if (s->pclk ^ (clk & 1)) { + s->pclk = (clk & 1); + if (s->pclk == 1) { + /* rising edge */ + read_mdo(s); + } else { + /* faling edge */ + write_mdi(s); + } + } +} + +static Property bb_properties[] = { + DEFINE_PROP_INT32("address", MDIOState, phyad, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void bb_init(Object *obj) +{ + MDIOState *s = MDIO_BB(obj); + + object_property_add_link(obj, "phy", + TYPE_ETHER_PHY, + (Object **)&s->phy, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); +} + +static void bb_class_init(ObjectClass *klass, void *class_data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + device_class_set_props(dc, bb_properties); +} + +static const TypeInfo phy_types_info[] = { + { + .name = TYPE_ETHER_PHY, + .parent = TYPE_DEVICE, + .class_init = phy_class_init, + .instance_size = sizeof(PHYState), + }, + { + .name = TYPE_ETHER_MDIO_BB, + .parent = TYPE_DEVICE, + .class_init = bb_class_init, + .instance_size = sizeof(MDIOState), + .instance_init = bb_init, + }, +}; + +DEFINE_TYPES(phy_types_info); diff --git a/hw/net/Kconfig b/hw/net/Kconfig index e43c96dae0..e6a32a2ab0 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -143,3 +143,6 @@ config CAN_SJA1000 default y if PCI_DEVICES depends on PCI select CAN_BUS + +config MDIO_PHY + bool diff --git a/hw/net/meson.build b/hw/net/meson.build index 4a7051b54a..faa4e3d2c0 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -64,4 +64,6 @@ softmmu_ss.add(when: 'CONFIG_ROCKER', if_true: files( ), if_false: files('rocker/qmp-norocker.c')) softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('rocker/qmp-norocker.c')) +softmmu_ss.add(when: 'CONFIG_MDIO_PHY', if_true: files('mdio.c')) + subdir('can') From patchwork Thu Aug 27 12:38:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDC59C433E1 for ; Thu, 27 Aug 2020 12:43:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 980E62177B for ; Thu, 27 Aug 2020 12:43:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 980E62177B Authentication-Results: mail.kernel.org; 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Thu, 27 Aug 2020 21:39:09 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 167771C0792; Thu, 27 Aug 2020 21:39:09 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 17/20] hw/rx/rx62n: Add Ethernet support. Date: Thu, 27 Aug 2020 21:38:56 +0900 Message-Id: <20200827123859.81793-18-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.15; envelope-from=ysato@users.sourceforge.jp; helo=mail03.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 3 +++ hw/rx/rx62n.c | 26 ++++++++++++++++++++++++++ hw/rx/Kconfig | 3 ++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 170c8cb6fc..4f11ca3fd9 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -30,6 +30,7 @@ #include "hw/timer/renesas_timer.h" #include "hw/timer/renesas_mtu.h" #include "hw/char/renesas_sci.h" +#include "hw/net/renesas_eth.h" #include "hw/rx/rx62n-cpg.h" #include "qemu/units.h" @@ -74,6 +75,8 @@ typedef struct RX62NState { RenesasCMTState cmt[RX62N_NR_CMT]; RenesasMTU2State mtu[RX62N_NR_MTU]; RSCIAState sci[RX62N_NR_SCI]; + RenesasEthState ether; + MDIOState *mdio; RX62NCPGState cpg; MemoryRegion *sysmem; diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 344be846bc..8b41cdf90c 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -28,6 +28,7 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" +#include "hw/net/mdio.h" #include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "cpu.h" @@ -48,6 +49,8 @@ #define RX62N_CMT_BASE 0x00088000 #define RX62N_MTU_BASE 0x00088600 #define RX62N_SCI_BASE 0x00088240 +#define RX62N_EDMAC_BASE 0x000c0000 +#define RX62N_ETHER_BASE 0x000c0100 #define RX62N_CPG_BASE 0x00080010 /* @@ -58,6 +61,7 @@ #define RX62N_CMT_IRQ 28 #define RX62N_MTU_IRQ 114 #define RX62N_SCI_IRQ 214 +#define RX62N_EDMAC_IRQ 32 /* * IRQ -> IPR mapping table @@ -236,6 +240,25 @@ static void register_sci(RX62NState *s, int unit) qdev_get_clock_out(DEVICE(&s->cpg), ckname)); } +static void register_eth(RX62NState *s, NICInfo *nd) +{ + SysBusDevice *etherc; + + qemu_check_nic_model(nd, TYPE_RENESAS_ETH); + object_initialize_child(OBJECT(s), "ether", + &s->ether, TYPE_RENESAS_ETH); + etherc = SYS_BUS_DEVICE(&s->ether); + qdev_set_nic_properties(DEVICE(etherc), nd); + object_property_set_link(OBJECT(etherc), "mdio", + OBJECT(s->mdio), &error_abort); + sysbus_realize(etherc, &error_abort); + sysbus_connect_irq(etherc, 0, s->irq[RX62N_EDMAC_IRQ]); + sysbus_mmio_map(etherc, 0, RX62N_ETHER_BASE); + sysbus_mmio_map(etherc, 1, RX62N_EDMAC_BASE); + qdev_connect_clock_in(DEVICE(etherc), "ick", + qdev_get_clock_out(DEVICE(&s->cpg), "ick_edmac")); +} + static void register_cpg(RX62NState *s) { SysBusDevice *cpg; @@ -277,6 +300,7 @@ static void rx62n_realize(DeviceState *dev, Error **errp) register_mtu(s, 0); register_mtu(s, 1); register_sci(s, 0); + register_eth(s, nd_table); sysbus_realize(SYS_BUS_DEVICE(&s->cpg), &error_abort); } @@ -284,6 +308,8 @@ static Property rx62n_properties[] = { DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0), + DEFINE_PROP_LINK("mdiodev", RX62NState, mdio, TYPE_ETHER_MDIO_BB, + MDIOState *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig index 887a5782bb..f20ea63fd9 100644 --- a/hw/rx/Kconfig +++ b/hw/rx/Kconfig @@ -3,8 +3,9 @@ config RX62N_MCU select RX_ICU select RENESAS_TMR8 select RENESAS_TIMER - select RENESAS_SCI select RENESAS_MTU + select RENESAS_SCI + select RENESAS_ETH config RX_GDBSIM bool From patchwork Thu Aug 27 12:38:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 275415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 067E7C433E1 for ; Thu, 27 Aug 2020 12:42:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9E012177B for ; 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Thu, 27 Aug 2020 21:39:09 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 783C81C0792; Thu, 27 Aug 2020 21:39:09 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 19/20] hw/rx: Add CQ-FRK-RX62N target Date: Thu, 27 Aug 2020 21:38:58 +0900 Message-Id: <20200827123859.81793-20-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.14; envelope-from=ysato@users.sourceforge.jp; helo=mail02.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" It most popular RX target board in Japan. Signed-off-by: Yoshinori Sato --- default-configs/rx-softmmu.mak | 1 + hw/rx/cq-frk-rx62n.c | 94 ++++++++++++++++++++++++++++++++++ hw/rx/Kconfig | 3 ++ hw/rx/meson.build | 1 + 4 files changed, 99 insertions(+) create mode 100644 hw/rx/cq-frk-rx62n.c diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak index ea8731d67b..dbbaee8809 100644 --- a/default-configs/rx-softmmu.mak +++ b/default-configs/rx-softmmu.mak @@ -2,3 +2,4 @@ CONFIG_RX_GDBSIM=y CONFIG_TKDN_RX62N=y +CONFIG_FRK_RX62N=y diff --git a/hw/rx/cq-frk-rx62n.c b/hw/rx/cq-frk-rx62n.c new file mode 100644 index 0000000000..a1cd9cb2ad --- /dev/null +++ b/hw/rx/cq-frk-rx62n.c @@ -0,0 +1,94 @@ +/* + * CQ publishing CQ-FRK-RX62N + * + * Copyright (c) 2020 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/loader.h" +#include "hw/rx/loader.h" +#include "hw/qdev-properties.h" +#include "hw/rx/rx62n.h" +#include "sysemu/sysemu.h" +#include "sysemu/qtest.h" +#include "sysemu/device_tree.h" +#include "hw/boards.h" + +typedef struct { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ + RX62NState mcu; +} FRK_RX62NMachineState; + +#define TYPE_FRK_RX62N_MACHINE MACHINE_TYPE_NAME("cq-frk-rx62n") + +#define FRK_RX62N_MACHINE(obj) \ + OBJECT_CHECK(FRK_RX62NMachineState, (obj), TYPE_FRK_RX62N_MACHINE) + +static void frk_rx62n_init(MachineState *machine) +{ + FRK_RX62NMachineState *s = FRK_RX62N_MACHINE(machine); + RX62NClass *rx62nc; + MemoryRegion *sysmem = get_system_memory(); + + /* Initialize MCU */ + object_initialize_child(OBJECT(machine), "mcu", + &s->mcu, TYPE_R5F562N7_MCU); + rx62nc = RX62N_MCU_GET_CLASS(&s->mcu); + object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem), + &error_abort); + object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", + 12 * 1000 * 1000, &error_abort); + if (bios_name) { + if (!load_bios(bios_name, rx62nc->rom_flash_size, &error_abort)) { + exit(0); + } + } else if (!qtest_enabled()) { + error_report("No bios specified"); + exit(1); + } + qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); +} + +static void frk_rx62n_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "CQ publishing CQ-FRK-RX62N"; + mc->init = frk_rx62n_init; + mc->is_default = 0; + mc->default_cpu_type = TYPE_RX62N_CPU; +} + +static const TypeInfo frk_rx62n_type = { + .name = MACHINE_TYPE_NAME("cq-frk-rx62n"), + .parent = TYPE_MACHINE, + .instance_size = sizeof(FRK_RX62NMachineState), + .class_init = frk_rx62n_class_init, +}; + +static void frk_rx62n_machine_init(void) +{ + type_register_static(&frk_rx62n_type); +} + +type_init(frk_rx62n_machine_init) diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig index 0ef20d0c3c..ab2c472510 100644 --- a/hw/rx/Kconfig +++ b/hw/rx/Kconfig @@ -17,3 +17,6 @@ config TKDN_RX62N select RX62N_MCU select FITLOADER +config FRK_RX62N + bool + select RX62N_MCU diff --git a/hw/rx/meson.build b/hw/rx/meson.build index 0a741e091c..0f26f1fcb2 100644 --- a/hw/rx/meson.build +++ b/hw/rx/meson.build @@ -2,6 +2,7 @@ rx_ss = ss.source_set() rx_ss.add(files('loader.c')) rx_ss.add(when: 'CONFIG_RX_GDBSIM', if_true: files('rx-gdbsim.c')) rx_ss.add(when: 'CONFIG_TKDN_RX62N', if_true: files('tkdn-rx62n.c')) +rx_ss.add(when: 'CONFIG_FRK_RX62N', if_true: files('cq-frk-rx62n.c')) rx_ss.add(when: 'CONFIG_RX62N_MCU', if_true: files('rx62n.c', 'rx62n-cpg.c')) hw_arch += {'rx': rx_ss} From patchwork Thu Aug 27 12:38:59 2020 Content-Type: text/plain; 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Thu, 27 Aug 2020 21:39:10 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id A78621C0696; Thu, 27 Aug 2020 21:39:09 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 20/20] MAINTAINERS: Update RX entry Date: Thu, 27 Aug 2020 21:38:59 +0900 Message-Id: <20200827123859.81793-21-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200827123859.81793-1-ysato@users.sourceforge.jp> References: <20200827123859.81793-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.15; envelope-from=ysato@users.sourceforge.jp; helo=mail03.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 08:39:06 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Yoshinori Sato --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5a22c8be42..cee8448a73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2054,9 +2054,11 @@ F: hw/char/renesas_sci.c F: hw/char/sh_serial.c F: hw/timer/renesas_*.c F: hw/timer/sh_timer.c +F: hw/net/renesas_eth.c F: include/hw/char/renesas_sci.h F: include/hw/sh4/sh.h F: include/hw/timer/renesas_*.h +F: include/hw/net/renesas_eth.h Renesas RX peripherals M: Yoshinori Sato