From patchwork Wed Aug 12 19:13:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 276663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD0B0C433DF for ; Wed, 12 Aug 2020 19:24:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8788A20838 for ; Wed, 12 Aug 2020 19:24:23 +0000 (UTC) Authentication-Results: mail.kernel.org; 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13 Aug 2020 03:23:16 +0800 IronPort-SDR: ii49DnrbmH24uTUXU/gZoBrH+yj8k7xbxna2S2BYgQQ72hckUvMHk242+AtP6rLqvae6/T8SDA empCkgI/c01g== Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 12:11:08 -0700 IronPort-SDR: LqX//zM9FQjRt/lD18USpcQ4leE553RuuQP09AdwXpa9sB23KaZEE3csiKOtsMlQj+9pSnY7uF RLKUohES8x6w== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip01.wdc.com with ESMTP; 12 Aug 2020 12:23:17 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 01/13] target/riscv: Allow setting a two-stage lookup in the virt status Date: Wed, 12 Aug 2020 12:13:16 -0700 Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:14 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a804a5d0ba..383808bf88 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -321,6 +321,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(CPURISCVState *env); +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8117e8b5a7..ba0a5b50ff 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -467,6 +467,7 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 +#define HS_TWO_STAGE 4 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..68abccc993 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); } +bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, HS_TWO_STAGE); +} + +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt = set_field(env->virt, HS_TWO_STAGE, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env; From patchwork Wed Aug 12 19:13:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 276660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59CBBC433E0 for ; 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d="scan'208";a="146029191" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 13 Aug 2020 03:23:20 +0800 IronPort-SDR: +MDfb9EEXhyhMpTxaUMMvHjmyHg6ciMnHEPQvwGk+ru2oAHEdrMIILQIdzMDziz5OZsKnAP1TW LzWbsfe7LXsw== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 12:10:28 -0700 IronPort-SDR: BkVFMQklJKKWNcy90JoMdoruCYbn4g4zc6TbDXq+8+fa0pqDmgAvo5PGPHIkWCvrLzwZU0iDDg /txsLiCpN4QA== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip02.wdc.com with ESMTP; 12 Aug 2020 12:23:21 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions Date: Wed, 12 Aug 2020 12:13:19 -0700 Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:20 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32-64.decode | 5 + target/riscv/insn32.decode | 11 + target/riscv/insn_trans/trans_rvh.inc.c | 340 ++++++++++++++++++++++++ target/riscv/op_helper.c | 114 ++++++++ 6 files changed, 474 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ba0a5b50ff..7abae4267f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -443,6 +443,7 @@ #define HSTATUS_SP2V 0x00000200 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HU 0x00000200 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/helper.h b/target/riscv/helper.h index acc298219d..c8029d83f9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -80,6 +80,9 @@ DEF_HELPER_1(tlb_flush, void, env) /* Hypervisor functions */ #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) +DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) +DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) +DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif /* Vector functions */ diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 86153d93fa..8157dee8b7 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -81,3 +81,8 @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 + +# *** RV32H Base Instruction Set *** +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bdd8563067..84080dd18c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -78,6 +78,7 @@ @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd +@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -223,6 +224,16 @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm # *** RV32H Base Instruction Set *** +hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 +hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 +hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 +hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 +hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 +hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 +hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 +hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s +hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s +hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c index 263b652d90..db650ae62a 100644 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -16,6 +16,346 @@ * this program. If not, see . */ +static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_UB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +#ifdef TARGET_RISCV64 +static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} +#endif + +static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv mem_idx = tcg_temp_new(); + TCGv memop = tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7cccd42a1e..3d306c343c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -207,4 +207,118 @@ void helper_hyp_tlb_flush(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } +target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + pte = cpu_ldsb_data_ra(env, address, GETPC()); + break; + case MO_UB: + pte = cpu_ldub_data_ra(env, address, GETPC()); + break; + case MO_TESW: + pte = cpu_ldsw_data_ra(env, address, GETPC()); + break; + case MO_TEUW: + pte = cpu_lduw_data_ra(env, address, GETPC()); + break; + case MO_TESL: + pte = cpu_ldl_data_ra(env, address, GETPC()); + break; + case MO_TEUL: + pte = cpu_ldl_data_ra(env, address, GETPC()); + break; + case MO_TEQ: + pte = cpu_ldq_data_ra(env, address, GETPC()); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + +void helper_hyp_store(CPURISCVState *env, target_ulong address, + target_ulong val, target_ulong attrs, target_ulong memop) +{ + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + case MO_UB: + cpu_stb_data_ra(env, address, val, GETPC()); + break; + case MO_TESW: + case MO_TEUW: + cpu_stw_data_ra(env, address, val, GETPC()); + break; + case MO_TESL: + case MO_TEUL: + cpu_stl_data_ra(env, address, val, GETPC()); + break; + case MO_TEQ: + cpu_stq_data_ra(env, address, val, GETPC()); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); +} + +target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_TEUL: + pte = cpu_ldub_data_ra(env, address, GETPC()); + break; + case MO_TEUW: + pte = cpu_lduw_data_ra(env, address, GETPC()); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + #endif /* !CONFIG_USER_ONLY */ From patchwork Wed Aug 12 19:13:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 276659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24A68C433E0 for ; Wed, 12 Aug 2020 19:28:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5CE020838 for ; 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d="scan'208";a="146029196" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 13 Aug 2020 03:23:23 +0800 IronPort-SDR: ZFlXZx/5V0I7SSOfmELKhpgu5SghfTLyYcpVTEDmpW2esLK9ISLuS2AbGawhsDsHhAhMkXcoKb xRzf/GLofC6Q== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 12:10:30 -0700 IronPort-SDR: lRBo3PVA30BiJAYMpqkkFc1H1Crb7vhCRJj3qEf1q856c7yHy70PhTqNvB7Cq3FJW8HMK9HP8p cclYjraY5j/A== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip02.wdc.com with ESMTP; 12 Aug 2020 12:23:23 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions Date: Wed, 12 Aug 2020 12:13:22 -0700 Message-Id: <024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:20 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 60 ++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 68abccc993..10c9f8b63b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ + if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) { + use_background = true; + } + if (mode == PRV_M && access_type != MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); - - if (riscv_has_ext(env, RVH) && - MSTATUS_MPV_ISSET(env)) { - use_background = true; - } - } - } - - if (mode == PRV_S && access_type != MMU_INST_FETCH && - riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { - if (get_field(env->hstatus, HSTATUS_SPRV)) { - mode = get_field(env->mstatus, SSTATUS_SPP); - use_background = true; } } @@ -607,7 +598,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, } break; case MMU_DATA_LOAD: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) && + !first_stage) { cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { cs->exception_index = page_fault_exceptions ? @@ -615,7 +607,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, } break; case MMU_DATA_STORE: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) && + !first_stage) { cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; } else { cs->exception_index = page_fault_exceptions ? @@ -705,8 +698,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, hwaddr pa = 0; int prot, prot2; bool pmp_violation = false; - bool m_mode_two_stage = false; - bool hs_mode_two_stage = false; bool first_stage_error = true; int ret = TRANSLATE_FAIL; int mode = mmu_idx; @@ -716,30 +707,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); - /* - * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is - * set and we want to access a virtulisation address. - */ - if (riscv_has_ext(env, RVH)) { - m_mode_two_stage = env->priv == PRV_M && - access_type != MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env); - - hs_mode_two_stage = env->priv == PRV_S && - !riscv_cpu_virt_enabled(env) && - access_type != MMU_INST_FETCH && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV); - } - if (mode == PRV_M && access_type != MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); } } - if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { + if (riscv_has_ext(env, RVH) && env->priv == PRV_M && + access_type != MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, true); + } + + if (riscv_cpu_virt_enabled(env) || + (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) { /* Two stage lookup */ ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, true, true); @@ -791,6 +773,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, __func__, address, ret, pa, prot); } + /* We did the two stage lookup based on MPRV, unset the lookup */ + if (riscv_has_ext(env, RVH) && env->priv == PRV_M && + access_type != MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, false); + } + if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { From patchwork Wed Aug 12 19:13:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 276662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AE73C433DF for ; Wed, 12 Aug 2020 19:24:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFBD920838 for ; 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d="scan'208";a="146029205" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 13 Aug 2020 03:23:31 +0800 IronPort-SDR: FBl84v5v7N/qXvzKYKCppL8fhopBzNuv47Q6MzQ0T9s7sqKEFDB3ZYOnN9pNty+ZA0iotI+9TG GTAcvMu6UXvA== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 12:10:39 -0700 IronPort-SDR: q1CVShgbAh1DsTxCETgXK7d4m8LfQfWuv9JA3nnNK09Vwn2+Q1xO6UTng9LqtrrmZ08uROlwOP Z25IpNxfjGBA== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip02.wdc.com with ESMTP; 12 Aug 2020 12:23:32 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 06/13] target/riscv: Fix the interrupt cause code Date: Wed, 12 Aug 2020 12:13:30 -0700 Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:20 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b5f4264525..9ab3ca4675 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -909,14 +909,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt * no if hypervisor has delegated one of hs mode's interrupt */ if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || - cause == IRQ_VS_EXT) + cause == IRQ_VS_EXT) { cause = cause - 1; - /* Trap to VS mode */ + } env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ From patchwork Wed Aug 12 19:13:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 276658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45D06C433DF for ; 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d="scan'208";a="146029207" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 13 Aug 2020 03:23:34 +0800 IronPort-SDR: lp6BIsHYS0PPJq8a229N33K1QzQSsPK370GCCcC8ztLtORYpPJmNtBF1Gb+e6R8BupztYYOlr7 uYg/j0yI9wZg== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 12:10:41 -0700 IronPort-SDR: HxFbRqBpgc3yX0nYobIkwhglqese/yCQBH8mVohhWU+LOBsOFbQbUA5FXliA0JLFPhrVW6Oc8v KWndJ3aClAJQ== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip02.wdc.com with ESMTP; 12 Aug 2020 12:23:34 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry Date: Wed, 12 Aug 2020 12:13:33 -0700 Message-Id: X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:20 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 16 ++++++---------- target/riscv/op_helper.c | 8 ++------ target/riscv/translate.c | 10 ---------- 4 files changed, 9 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 43617e7c1f..fb6a3e9092 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -445,6 +445,7 @@ #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 #define HSTATUS_GVA 0x00000040 +#define HSTATUS_SPVP 0x00000100 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9ab3ca4675..79166875a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -922,9 +922,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); - env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_SPV)); - env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, + env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, get_field(env->mstatus, SSTATUS_SPP)); env->hstatus = set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); @@ -935,13 +933,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_SPV)); - env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, - get_field(env->mstatus, SSTATUS_SPP)); - env->hstatus = set_field(env->hstatus, HSTATUS_SPV, - riscv_cpu_virt_enabled(env)); - + if (!riscv_cpu_two_stage_lookup(env)) { + env->hstatus = set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + } + riscv_cpu_set_two_stage_lookup(env, false); htval = env->guest_phys_fault_addr; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3d306c343c..4b64bfe7d2 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -97,12 +97,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) prev_priv = get_field(mstatus, MSTATUS_SPP); prev_virt = get_field(hstatus, HSTATUS_SPV); - hstatus = set_field(hstatus, HSTATUS_SPV, - get_field(hstatus, HSTATUS_SP2V)); - mstatus = set_field(mstatus, MSTATUS_SPP, - get_field(hstatus, HSTATUS_SP2P)); - hstatus = set_field(hstatus, HSTATUS_SP2V, 0); - hstatus = set_field(hstatus, HSTATUS_SP2P, 0); + hstatus = set_field(hstatus, HSTATUS_SPV, 0); + mstatus = set_field(mstatus, MSTATUS_SPP, 0); mstatus = set_field(mstatus, SSTATUS_SIE, get_field(mstatus, SSTATUS_SPIE)); mstatus = set_field(mstatus, SSTATUS_SPIE, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9632e79cf3..f896412235 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -768,16 +768,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { ctx->virt_enabled = riscv_cpu_virt_enabled(env); - if (env->priv_ver == PRV_M && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { - ctx->virt_enabled = true; - } else if (env->priv == PRV_S && - !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV)) { - ctx->virt_enabled = true; - } } else { ctx->virt_enabled = false; } From patchwork Wed Aug 12 19:13:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 276657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34377C433DF for ; Wed, 12 Aug 2020 19:33:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3E3C206DA for ; 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d="scan'208";a="146029213" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 13 Aug 2020 03:23:44 +0800 IronPort-SDR: 8ey442028y/wFLMoqA/iwugdxDCYSMkshuesCx6M2ma/Hod1ZSNO4KtqLLr5KSCs+wonhB5FPq uQOqcOF8gTaA== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 12:10:52 -0700 IronPort-SDR: kbMWJKpA77Pz6dDH0+poUud5pet7du5OgPB8NXcfRpFAYafLF6HWnJ3D6HEx6PjaNrzmy4/F4f 3sdXkXAkcu9Q== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip02.wdc.com with ESMTP; 12 Aug 2020 12:23:45 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs Date: Wed, 12 Aug 2020 12:13:44 -0700 Message-Id: <644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:20 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 573d85da41..d88e2ea30d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -197,9 +197,12 @@ #define CSR_HIDELEG 0x603 #define CSR_HIE 0x604 #define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 #define CSR_HTVAL 0x643 +#define CSR_HVIP 0x645 #define CSR_HIP 0x644 #define CSR_HTINST 0x64A +#define CSR_HGEIP 0xE12 #define CSR_HGATP 0x680 #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5e50683c58..7dc50e6299 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -883,12 +883,25 @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) return 0; } +static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + int ret = rmw_mip(env, 0, ret_value, new_value, + write_mask & hip_writable_mask); + + *ret_value &= hip_writable_mask; + + return ret; +} + static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { int ret = rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); + *ret_value &= hip_writable_mask; + return ret; } @@ -916,6 +929,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) return 0; } +static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + +static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->htval; @@ -939,6 +964,18 @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) return 0; } +static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + +static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->hgatp; @@ -1341,11 +1378,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, + [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip }, [CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, [CSR_HIE] = { hmode, read_hie, write_hie }, [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, + [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie }, [CSR_HTVAL] = { hmode, read_htval, write_htval }, [CSR_HTINST] = { hmode, read_htinst, write_htinst }, + [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip }, [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta }, #if defined(TARGET_RISCV32)