From patchwork Sat Jul 11 16:16:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 278040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FCBEC433E0 for ; Sat, 11 Jul 2020 16:21:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E90C3207D4 for ; Sat, 11 Jul 2020 16:21:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E90C3207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:37398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIFp-0003y7-Vd for qemu-devel@archiver.kernel.org; Sat, 11 Jul 2020 12:21:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007Ep-DM; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:47937) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001Lo-Jo; Sat, 11 Jul 2020 12:18:55 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436779|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.499597-0.0016009-0.498802; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16378; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:39 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 02/11] riscv: Add RV64M instructions description Date: Sun, 12 Jul 2020 00:16:46 +0800 Message-Id: <20200711161655.2856-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- rv64.risu | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/rv64.risu b/rv64.risu index edf0d1f..2c4154e 100644 --- a/rv64.risu +++ b/rv64.risu @@ -139,3 +139,44 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \ SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \ !constraints { greg($rd) && greg($rs1) && greg($rs2); } + +@RV64M + +MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } From patchwork Sat Jul 11 16:16:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 278042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F9A2C433E3 for ; Sat, 11 Jul 2020 16:20:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 143EE2075F for ; Sat, 11 Jul 2020 16:20:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 143EE2075F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIES-0000U8-2j for qemu-devel@archiver.kernel.org; Sat, 11 Jul 2020 12:20:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007Ei-4J; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:58191) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDC-0001Lp-QS; Sat, 11 Jul 2020 12:18:54 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0026535-0.000506006-0.99684; FP=0|0|0|0|0|-1|-1|-1; HT=e01l10422; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:39 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 04/11] riscv: Add RV64F instructions description Date: Sun, 12 Jul 2020 00:16:48 +0800 Message-Id: <20200711161655.2856-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For supporting multi-precision, split all 32 fp registers into two groups. The RV64F instructions will use only 16 fp registers selected by gfp32(). Signed-off-by: LIU Zhiwei --- rv64.risu | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/rv64.risu b/rv64.risu index ad5dee9..0dcc9a1 100644 --- a/rv64.risu +++ b/rv64.risu @@ -270,3 +270,97 @@ AMOMINU_D RISCV 11000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ AMOMAXU_D RISCV 11100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ !constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ !memory { align(8); reg($rs1, $rd); } + +@RV64F + +FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \ +!constraints { gbase($rs1) && gfp32($rd); } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); } + +FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100111 \ +!constraints { gbase($rs1) && gfp32($rs2); } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FSQRT_S RISCV 0101100 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rd) && grm($rm); } + +FSGNJ_S RISCV 0010000 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FSGNJN_S RISCV 0010000 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FSGNJX_S RISCV 0010000 rs2:5 rs1:5 010 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FMIN_S RISCV 0010100 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FMAX_S RISCV 0010100 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FMV_X_W RISCV 1110000 00000 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1); } + +FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); } + +FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); } + +FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); } + +FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1); } + +FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } + +FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } + +FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd); } + +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } + +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } From patchwork Sat Jul 11 16:16:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 278038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12D44C433E1 for ; Sat, 11 Jul 2020 16:23:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DADBF207D4 for ; Sat, 11 Jul 2020 16:23:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DADBF207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:45210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIHG-00077c-3K for qemu-devel@archiver.kernel.org; Sat, 11 Jul 2020 12:23:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007Eu-IZ; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:46455) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001M1-K4; Sat, 11 Jul 2020 12:18:55 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436351|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.194827-0.000235336-0.804938; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03297; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:42 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 08/11] riscv: Add standard test case Date: Sun, 12 Jul 2020 00:16:52 +0800 Message-Id: <20200711161655.2856-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 test_riscv64.s diff --git a/test_riscv64.s b/test_riscv64.s new file mode 100644 index 0000000..22a22b6 --- /dev/null +++ b/test_riscv64.s @@ -0,0 +1,85 @@ +/***************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (T-Head) - initial implementation + * based on test_arm.s by Peter Maydell + *****************************************************************************/ + +/* Initialise the gp regs */ +li x1, 1 +#li x2, 2 # stack pointer +#li x3, 3 # global pointer +#li x4, 4 # thread pointer +li x5, 5 +li x6, 6 +li x7, 7 +li x8, 8 +li x9, 9 +li x10, 10 +li x11, 11 +li x12, 12 +li x13, 13 +li x14, 14 +li x15, 15 +li x16, 16 +li x17, 17 +li x18, 18 +li x19, 19 +li x20, 20 +li x21, 21 +li x22, 22 +li x23, 23 +li x24, 24 +li x25, 25 +li x26, 26 +li x27, 27 +li x28, 28 +li x29, 29 +li x30, 30 +li x31, 30 + +/* Initialise the fp regs */ +fcvt.d.lu f0, x0 +fcvt.d.lu f1, x1 +fcvt.d.lu f2, x2 +fcvt.d.lu f3, x3 +fcvt.d.lu f4, x4 +fcvt.d.lu f5, x5 +fcvt.d.lu f6, x6 +fcvt.d.lu f7, x7 +fcvt.d.lu f8, x8 +fcvt.d.lu f9, x9 +fcvt.d.lu f10, x10 +fcvt.d.lu f11, x11 +fcvt.d.lu f12, x12 +fcvt.d.lu f13, x13 +fcvt.d.lu f14, x14 +fcvt.d.lu f15, x15 +fcvt.d.lu f16, x16 +fcvt.d.lu f17, x17 +fcvt.d.lu f18, x18 +fcvt.d.lu f19, x19 +fcvt.d.lu f20, x20 +fcvt.d.lu f21, x21 +fcvt.d.lu f22, x22 +fcvt.d.lu f23, x23 +fcvt.d.lu f24, x24 +fcvt.d.lu f25, x25 +fcvt.d.lu f26, x26 +fcvt.d.lu f27, x27 +fcvt.d.lu f28, x28 +fcvt.d.lu f29, x29 +fcvt.d.lu f30, x30 +fcvt.d.lu f31, x31 + +/* do compare. + * The manual says instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED + */ +.int 0x0000006b +/* exit test */ +.int 0x0000016b From patchwork Sat Jul 11 16:16:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 278037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E887DC433E3 for ; Sat, 11 Jul 2020 16:23:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BDC8F207D4 for ; Sat, 11 Jul 2020 16:23:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BDC8F207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIHW-0007eo-0z for qemu-devel@archiver.kernel.org; Sat, 11 Jul 2020 12:23:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDX-0007cS-O5; Sat, 11 Jul 2020 12:19:11 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:41426) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDV-0001M3-Ke; Sat, 11 Jul 2020 12:19:11 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1356943|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0178803-0.00146885-0.980651; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16384; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:42 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 09/11] riscv: Define riscv struct reginfo Date: Sun, 12 Jul 2020 00:16:53 +0800 Message-Id: <20200711161655.2856-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 risu_reginfo_riscv64.h diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h new file mode 100644 index 0000000..4536480 --- /dev/null +++ b/risu_reginfo_riscv64.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(T-Head) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#ifndef RISU_REGINFO_RISCV64_H +#define RISU_REGINFO_RISCV64_H + +struct reginfo { + uint64_t fault_address; + uint64_t regs[32]; + uint64_t fregs[32]; + uint64_t pc; + uint32_t flags; + uint32_t faulting_insn; + + /* FP */ + uint32_t fcsr; +}; + +#endif /* RISU_REGINFO_RISCV64_H */ From patchwork Sat Jul 11 16:16:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 278041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E51DC433E2 for ; Sat, 11 Jul 2020 16:20:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 74DCE207D4 for ; Sat, 11 Jul 2020 16:20:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 74DCE207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIEW-0000em-JJ for qemu-devel@archiver.kernel.org; Sat, 11 Jul 2020 12:20:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007F6-Qb; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:44399) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001M9-FD; Sat, 11 Jul 2020 12:18:55 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436318|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0983034-0.000812451-0.900884; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03307; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:43 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 10/11] riscv: Implement payload load interfaces Date: Sun, 12 Jul 2020 00:16:54 +0800 Message-Id: <20200711161655.2856-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When a risu op emits, the signal handler wll take over execution before running the payload again. The signal handler need some interfaces, such as setting struct reginfo and the comparison of struct reginfo. Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.c | 132 +++++++++++++++++++++++++++++++++++++++++ risu_riscv64.c | 47 +++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 risu_reginfo_riscv64.c create mode 100644 risu_riscv64.c diff --git a/risu_reginfo_riscv64.c b/risu_reginfo_riscv64.c new file mode 100644 index 0000000..763001f --- /dev/null +++ b/risu_reginfo_riscv64.c @@ -0,0 +1,132 @@ +/****************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (T-Head) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#include +#include +#include +#include /* for FPSIMD_MAGIC */ +#include +#include +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_riscv64.h" + +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} + +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *uc) +{ + int i; + union __riscv_mc_fp_state *fp; + /* necessary to be able to compare with memcmp later */ + memset(ri, 0, sizeof(*ri)); + + for (i = 0; i < 32; i++) { + ri->regs[i] = uc->uc_mcontext.__gregs[i]; + } + + ri->regs[2] = 0xdeadbeefdeadbeef; + ri->regs[3] = 0xdeadbeefdeadbeef; + ri->regs[4] = 0xdeadbeefdeadbeef; + ri->pc = uc->uc_mcontext.__gregs[0] - image_start_address; + ri->regs[0] = ri->pc; + ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.__gregs[0]); + fp = &uc->uc_mcontext.__fpregs; +#if __riscv_flen == 64 + ri->fcsr = fp->__d.__fcsr; + + for (i = 0; i < 32; i++) { + ri->fregs[i] = fp->__d.__f[i]; + } +#else +# error "Unsupported fp length" +#endif +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) +{ + return memcmp(r1, r2, reginfo_size()) == 0; +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE * f) +{ + int i; + fprintf(f, " faulting insn %08x\n", ri->faulting_insn); + + for (i = 1; i < 32; i++) { + fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); + } + + fprintf(f, " pc : %016" PRIx64 "\n", ri->pc); + fprintf(f, " fcsr : %08x\n", ri->fcsr); + + for (i = 0; i < 32; i++) { + fprintf(f, " F%-2d : %016" PRIx64 "\n", i, ri->fregs[i]); + } + + return !ferror(f); +} + +/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */ +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) +{ + int i; + fprintf(f, "mismatch detail (master : apprentice):\n"); + if (m->faulting_insn != a->faulting_insn) { + fprintf(f, " faulting insn mismatch %08x vs %08x\n", + m->faulting_insn, a->faulting_insn); + } + for (i = 1; i < 32; i++) { + if (m->regs[i] != a->regs[i]) { + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", + i, m->regs[i], a->regs[i]); + } + } + + if (m->pc != a->pc) { + fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n", + m->pc, a->pc); + } + + if (m->fcsr != a->fcsr) { + fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr); + } + + for (i = 0; i < 32; i++) { + if (m->fregs[i] != a->fregs[i]) { + fprintf(f, " F%-2d : " + "%016" PRIx64 " vs " + "%016" PRIx64 "\n", i, + (uint64_t) m->fregs[i], + (uint64_t) a->fregs[i]); + } + } + + return !ferror(f); +} diff --git a/risu_riscv64.c b/risu_riscv64.c new file mode 100644 index 0000000..06dbb2d --- /dev/null +++ b/risu_riscv64.c @@ -0,0 +1,47 @@ +/****************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(Linaro) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#include "risu.h" + +void advance_pc(void *vuc) +{ + ucontext_t *uc = vuc; + uc->uc_mcontext.__gregs[0] += 4; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc = vuc; + uc->uc_mcontext.__gregs[10] = value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->regs[10]; +} + +int get_risuop(struct reginfo *ri) +{ + /* Return the risuop we have been asked to do + * (or -1 if this was a SIGILL for a non-risuop insn) + */ + uint32_t insn = ri->faulting_insn; + uint32_t op = (insn & 0xf00) >> 8; + uint32_t key = insn & ~0xf00; + uint32_t risukey = 0x0000006b; + return (key != risukey) ? -1 : op; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->pc; +} From patchwork Sat Jul 11 16:16:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 278039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54067C433E3 for ; Sat, 11 Jul 2020 16:21:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2CA26207D4 for ; Sat, 11 Jul 2020 16:21:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2CA26207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIG1-0004R3-BI for qemu-devel@archiver.kernel.org; Sat, 11 Jul 2020 12:21:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDI-0007FN-C5; Sat, 11 Jul 2020 12:18:56 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:60698) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001M7-Ix; Sat, 11 Jul 2020 12:18:56 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07440338|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.325301-0.00391217-0.670787; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03268; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:43 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 11/11] riscv: Add configure script Date: Sun, 12 Jul 2020 00:16:55 +0800 Message-Id: <20200711161655.2856-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For RV64 risu, make CFLAGS="-march=rv64g" Signed-off-by: LIU Zhiwei --- configure | 4 +- upstream/configure | 204 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 1 deletion(-) create mode 100644 upstream/configure diff --git a/configure b/configure index ca2d7db..00624d3 100755 --- a/configure +++ b/configure @@ -58,6 +58,8 @@ guess_arch() { ARCH="m68k" elif check_define __powerpc64__ ; then ARCH="ppc64" + elif check_define __riscv && check_define _LP64; then + ARCH="riscv64" else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -139,7 +141,7 @@ Some influential environment variables: prefixed with the given string. ARCH force target architecture instead of trying to detect it. - Valid values=[arm|aarch64|ppc64|ppc64le|m68k] + Valid values=[arm|aarch64|ppc64|ppc64le|m68k|riscv64] CC C compiler command CFLAGS C compiler flags diff --git a/upstream/configure b/upstream/configure new file mode 100644 index 0000000..297cd3a --- /dev/null +++ b/upstream/configure @@ -0,0 +1,204 @@ +#!/bin/sh +# simple risu configure script +# +# Copyright (c) 2013 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Claudio Fontana (Linaro) - initial implementation + +# Locate the directory where this configure script is +SRCDIR="$(cd "$(dirname "$0")"; pwd)" + +# Temporary directory used for files created by this script. +# Like autoconf (and like QEMU) we put this directory in the +# build directory, which means we can just give it a fixed name and +# blow it away when configure is run, and we don't need to jump +# through complicated hoops to delete it when configure exits +# abnormally (it may be useful for debug purposes on an +# abnormal exit). +tmp_dir="config-temp" +rm -rf "$tmp_dir" +mkdir -p "$tmp_dir" +if [ $? -ne 0 ]; then + echo "ERROR: could not create temporary directory" + exit 1 +fi + +compile() { + $CC $CFLAGS -c -o ${1}.o ${1}.c 2>/dev/null +} + +link() { + $LD $LDFLAGS -l${2} -o ${1} ${1}.o 2>/dev/null +} + +check_define() { + c=${tmp_dir}/check_define_${1} + cat > ${c}.c <&2 + exit 1 + fi + else + echo "This cpu is not supported by risu. Try -h. " >&2 + exit 1 + fi +} + +check_type() { + c=${tmp_dir}/check_type_${1} + cat > ${c}.c < +#include +#include +#include + +int main(void) { $1 thisone; return 0; } +EOF + compile $c +} + +check_lib() { + c=${tmp_dir}/check_lib${1} + cat > ${c}.c < +#include <$2.h> + +int main(void) { $3; return 0; } +EOF + compile $c && link $c $1 +} + +generate_config() { + cfg=config.h + echo "generating config.h..." + + echo "/* config.h - generated by the 'configure' script */" > $cfg + echo "#ifndef CONFIG_H" >> $cfg + echo "#define CONFIG_H 1" >> $cfg + + if check_lib z zlib "zlibVersion()"; then + echo "#define HAVE_ZLIB 1" >> $cfg + LDFLAGS=-lz + fi + + echo "#endif /* CONFIG_H */" >> $cfg + + echo "...done" +} + +generate_makefilein() { + m=Makefile.in + echo "generating Makefile.in..." + + echo "# Makefile.in - generated by the 'configure' script" > $m + echo "ARCH:=${ARCH}" >> $m + echo "CC:=${CC}" >> $m + echo "CPPFLAGS:=${CPPFLAGS}" >> $m + echo "LDFLAGS:=${LDFLAGS}" >> $m + echo "AS:=${AS}" >> $m + echo "OBJCOPY:=${OBJCOPY}" >> $m + echo "OBJDUMP:=${OBJDUMP}" >> $m + echo "STATIC:=${STATIC}" >> $m + echo "SRCDIR:=${SRCDIR}" >> $m + echo "BUILD_INC:=${BUILD_INC}" >> $m + + echo "...done" +} + +usage() { + cat < + + AS assembler command + OBJCOPY object copy utility command + OBJDUMP object dump utility command + +EOF +} + +# STARTUP: entry point +STATIC="" + +for opt do + case "$opt" in + --help | -h) + usage; + exit 0;; + --static | -s) + STATIC="-static" + ;; + + esac +done + +CC="${CC-${CROSS_PREFIX}gcc}" +AS="${AS-${CROSS_PREFIX}as}" +LD="${LD-${CROSS_PREFIX}ld}" +OBJCOPY="${OBJCOPY-${CROSS_PREFIX}objcopy}" +OBJDUMP="${OBJDUMP-${CROSS_PREFIX}objdump}" + +if test "x${ARCH}" = "x"; then + guess_arch +fi + +# Are we in a separate build tree? If so, link the Makefile +# so that 'make' works. +if test ! -e Makefile || test -s Makefile; then + echo "linking Makefile..." + BUILD_INC="-I $(pwd)" + ln -sf "${SRCDIR}/Makefile" . +fi + +generate_config +generate_makefilein + +rm -r "$tmp_dir" + +echo "type 'make' to start the build" +exit 0 +