From patchwork Wed Nov 8 15:32:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 118284 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5436349qgn; Wed, 8 Nov 2017 07:35:48 -0800 (PST) X-Google-Smtp-Source: ABhQp+QnI6JpWrlP9wQ+AvwyyIp/eBb0GqWxZED0Um7EBnOXBlX6kJiQNyzGhLzVA0Qyi9CGLYDz X-Received: by 10.37.208.199 with SMTP id h190mr554534ybg.515.1510155348369; Wed, 08 Nov 2017 07:35:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510155348; cv=none; d=google.com; s=arc-20160816; b=JZJGoatPR954TAmdG6hP1RyinQVnaJ/NZkgGPZQG2ZZqJwMjjUl0B+l2UoV+qJxF8X 8IyBQ0Xq25IT1XpGRMRyaZchNwKji6BZx0rW5EdQW9qaE4zYoOT9FNi74pwiLygjWySe cHVpUWPGnQUSB49w7pNNHb0qCWp2O8XrvgPiyS4nM7DxlPM9KToKiYEVicpComSghwgV ayenNJuJLG5iid4xayK14VyNdafVigdeq+KOhzfssqxozE7frdfq3IhD6J0oNzYdwU3n T1O8AE/m64dGCsmnOKTLt3fy9vOpAd+nZN/nDCgPlwa92ETWnLvvIoI5DkrPUfmp3Z5s Ro6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RdjZVKDXF1lYZFRSoSg7iXRmw6zd1GpA/QRInYksgwQ=; b=MrHYp8+e7Q4jqjPgAv8/RAY5J8vyVhwuAQoCubnt4g70ZNzn8fIFPwWDT7Gg7sR+RW rFqnFRCTnf0ggb1g1wcAfdTFwEFWoc+APNSI9gT5af3pDea3F/9/VmM/uIfW5xhZNrz5 o+cj4i1LMHm60yrSAyIzobJabW81lx50ssE65nqUWM4c2vrolDdO/2/r+BhqqlYgtbip ksRBMYZA6FeGNkEa8aKO62s09P62/sxutWbDgz/VpUWkhmd1/e8quQlji/MaNAMypO3D TIJpZdDM+e7I7F1AQPtk5dnA8b1/YR1IRVJGP8tLUSaG25IO3Rr1X1GlbhA0qony/OQ0 Lw3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cqhKza+X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 139si95923ybe.497.2017.11.08.07.35.48 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 08 Nov 2017 07:35:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cqhKza+X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60468 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSOJ-0001WY-RY for patch@linaro.org; Wed, 08 Nov 2017 10:35:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34279) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSLX-0000PI-Ku for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCSLR-00026U-F4 for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:55 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:54596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eCSLR-00025i-70 for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:49 -0500 Received: by mail-wm0-x244.google.com with SMTP id r68so11663995wmr.3 for ; Wed, 08 Nov 2017 07:32:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RdjZVKDXF1lYZFRSoSg7iXRmw6zd1GpA/QRInYksgwQ=; b=cqhKza+XajA6MQu/EHGcDb6OkLDkFo3U/kL/BFyABy020R0YlDKbzMj2f9VwfDvnvg DdTzzfzzbIuVpi5fGAnUeYejLr+Q6IbSu3dtoGJQxM5tCosNNM1/HA4FdPYc/JRT4qYF Z8lT9OVJrbyonmbTYv5Sn1wZ+fgnyhOtUx++c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RdjZVKDXF1lYZFRSoSg7iXRmw6zd1GpA/QRInYksgwQ=; b=XJu1bR9PYuD/44MtI7ch2Pc2159ph2ylLxqDJmKeybcmFtAc2IjCrUefSI1vwSdDnu wWknV0C4MO1dZtRJyFDKDUsN44mePNjz5e/gax+jWQESdz6zJBaFwitSHI4cJ9zHDtWq rkw2zlMKbtPVtCtbB6f2cz7te6ODRMDVbpeiyF9FtF4gTrLTfs30Qpmxd4J954f0NJbD 6daRNSSH+k2hd/oOJlXp3FX4w+HUolIHAbYGTo0tGb7kcuVigd5NvOl6EVylPnDj+LzW kVULM7huQnlp4fd4Y+1xpxFtRYzNDONVoMveZt2/Rd3szIsuUuIwyq0SPy3dFrq/cbV6 nMww== X-Gm-Message-State: AJaThX7hJC1G0xIokjWXhkttlcrr7jjFHyZsEyCfXCgIWdp6T2g8+qaE MD9RGUdGN/akx0RxELXT/rczMA== X-Received: by 10.28.131.200 with SMTP id f191mr775322wmd.39.1510155167897; Wed, 08 Nov 2017 07:32:47 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 89sm1383472wri.79.2017.11.08.07.32.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Nov 2017 07:32:46 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B5F8F3E03B5; Wed, 8 Nov 2017 15:32:45 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 8 Nov 2017 15:32:44 +0000 Message-Id: <20171108153245.20740-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171108153245.20740-1-alex.bennee@linaro.org> References: <20171108153245.20740-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v2 1/2] accel/tcg/translate-all: expand cpu_restore_state addr check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We are still seeing signals during translation time when we walk over a page protection boundary. This expands the check to ensure the host PC is inside the code generation buffer. The original suggestion was to check versus tcg_ctx.code_gen_ptr but as we now segment the translation buffer we have to settle for just a general check for being inside. I've also fixed up the declaration to make it clear it can deal with invalid addresses. A later patch will fix up the call sites. Signed-off-by: Alex Bennée Reported-by: Peter Maydell Suggested-by: Paolo Bonzini Cc: Richard Henderson --- v2: - add doc comment to exec-all.h - retaddr->host_pc - re-word comments on host_pc - simplify logic as per rth suggestion --- accel/tcg/translate-all.c | 52 ++++++++++++++++++++++++++--------------------- include/exec/exec-all.h | 11 ++++++++++ 2 files changed, 40 insertions(+), 23 deletions(-) -- 2.14.2 Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 34c5e28d07..e7f0329a52 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -352,36 +352,42 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, return 0; } -bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) { TranslationBlock *tb; bool r = false; + uintptr_t check_offset; - /* A retaddr of zero is invalid so we really shouldn't have ended - * up here. The target code has likely forgotten to check retaddr - * != 0 before attempting to restore state. We return early to - * avoid blowing up on a recursive tb_lock(). The target must have - * previously survived a failed cpu_restore_state because - * tb_find_pc(0) would have failed anyway. It still should be - * fixed though. + /* The host_pc has to be in the region of current code buffer. If + * it is not we will not be able to resolve it here. The two cases + * where host_pc will not be correct are: + * + * - fault during translation (instruction fetch) + * - fault from helper (not using GETPC() macro) + * + * Either way we need return early to avoid blowing up on a + * recursive tb_lock() as we can't resolve it here. + * + * We are using unsigned arithmetic so if host_pc < + * tcg_init_ctx.code_gen_buffer check_offset will wrap to way + * above the code_gen_buffer_size */ - - if (!retaddr) { - return r; - } - - tb_lock(); - tb = tb_find_pc(retaddr); - if (tb) { - cpu_restore_state_from_tb(cpu, tb, retaddr); - if (tb->cflags & CF_NOCACHE) { - /* one-shot translation, invalidate it immediately */ - tb_phys_invalidate(tb, -1); - tb_remove(tb); + check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer; + + if (check_offset < tcg_init_ctx.code_gen_buffer_size) { + tb_lock(); + tb = tb_find_pc(host_pc); + if (tb) { + cpu_restore_state_from_tb(cpu, tb, host_pc); + if (tb->cflags & CF_NOCACHE) { + /* one-shot translation, invalidate it immediately */ + tb_phys_invalidate(tb, -1); + tb_remove(tb); + } + r = true; } - r = true; + tb_unlock(); } - tb_unlock(); return r; } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 923ece3e9b..0f51c92adb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -45,6 +45,17 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, target_ulong *data); void cpu_gen_init(void); + +/** + * cpu_restore_state: + * @cpu: the vCPU state is to be restore to + * @searched_pc: the host PC the fault occurred at + * @return: true if state was restored, false otherwise + * + * Attempt to restore the state for a fault occurring in translated + * code. If the searched_pc is not in translated code no state is + * restored and the function returns false. + */ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); From patchwork Wed Nov 8 15:32:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 118282 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5433918qgn; Wed, 8 Nov 2017 07:33:38 -0800 (PST) X-Google-Smtp-Source: ABhQp+QP4VGaLNg3bn0YeAy4KDaQw2lSnpvWrMtz3+BWxscRqReBcb6iHlvMDnXwbFoMnc078Rwl X-Received: by 10.129.118.67 with SMTP id j3mr617926ywk.145.1510155218573; Wed, 08 Nov 2017 07:33:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510155218; cv=none; d=google.com; s=arc-20160816; b=tVq5y/Mm7icXnAGm4i64+gBizHGe4XQCl5OGLIvV8jVRxPtpVCZH4Qdce22z7CbDln tJFhpkzUSfyvSPBIY217PW+5s2phpD3gAaU5rWwrtyrAXNIMU6cjl/E36mhCh35G2e8L Cc79vF6+eV5OGhknvfbMSL7UKarZ0e24bDigMzkktMOoAWoPq774p3MNGPXO++HAonfq umyOf/aOySQ7nwHG3pmuazIh6c/37egRz7Nwqld4KUWTC1tT1wj00oHlC9pCTxNm3yd0 JLiUYSELHwUmF1UT5Xkodnd26emVdh8KgTnS0DagXGI3xDwvptL+qbvuG8hPcwK+U6Oe vPyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7aFad4r50/2gvUyQSqJuUtcxZtJrnOrFdDD3nkmtwFM=; b=IDSxssqlVzilILPS9Rb0VZZ2bOumdxDn3Ap5mdcGIcHdmqs2jMzFQg/4RGz4/zRW0H poMK4CVjt1KBhA1yz7FDAm230Lmt4XNX9pJy0dc/T5dLVpvmF2AxibDCl8Fi+2Rs5f/s iOHmZSq6TNkSm/w+cr1gAviYceu/vhXFF3GVv4g77b2VktOWgPGDY9cZ3iy8twFDzXWf 2GfLUFjLn1HZT8pJm9yvVYgThOcfa5WuT0poEbYAKfcTbVpayaV2wCTiX4xgwFATNqqA d4lS/DhTl+XnpgXWbMFYUXiuVstAr+OHsT9+ftHKW/H7ooIIV47KKXnyrLhelxiFqEUU xtGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QJfwbiD6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h190si691294ybg.375.2017.11.08.07.33.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 08 Nov 2017 07:33:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QJfwbiD6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSME-0000bJ-1d for patch@linaro.org; Wed, 08 Nov 2017 10:33:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34257) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSLU-0000Oc-CQ for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCSLS-00027L-JF for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:52 -0500 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:48682) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eCSLS-00026i-9P for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:50 -0500 Received: by mail-wr0-x243.google.com with SMTP id 15so2787139wrb.5 for ; Wed, 08 Nov 2017 07:32:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7aFad4r50/2gvUyQSqJuUtcxZtJrnOrFdDD3nkmtwFM=; b=QJfwbiD6WVgmPoLLX1eoMZVe6AFhhiiJIFXdeMywY1D3rMPcZIQRbUH4LuClvSXXoo 2j2fAI1gZ+zjPpB3d1mDbmx9LgTFX2+N54TNN+KOpJe4ERPi7ee9+oCbs9x6PVGp/8sf hh4HsfAagWAwCjVoRIBtMkRqSCaS+XUhV6L18= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7aFad4r50/2gvUyQSqJuUtcxZtJrnOrFdDD3nkmtwFM=; b=WhLDkZyN/RVLbicwjLDOT3XxHZQvjk6IoIXH+iWXdkcwfFkpzAXl/bmR899XRJnHzX MNmcaPolj2ux1EiSixF7ZKeP4t66yczmtlpl4vHIjnSYJLFKhcXp7TuR0hvgyXPtjVjZ +AkWCpx6T6fZOu70yFuP6JKW6t3UOI8kjb5v2bnAbsSpaDsd+9ZbRYbMOfhLxFywL2pa qc0R/7cKimTdCQ/CEvANiTGiqBF0Ziwg62/+AkuCB/d8mne/YrVBDZb80EH0UO8NrwrE vycevEObWkakx+8EN8QU0P0xT4Uh0jgP5Cf48q1+zYRzvffkyVvrYAwoTscOFl2Y3KvH 4wvw== X-Gm-Message-State: AJaThX6c74wkV23NGFCe0qvn43IhgKEc1y2inUyQ3P/VC37jmI2LU7uf 22iNdz9Tjaub7gK6r+V5AyJOZg== X-Received: by 10.223.186.202 with SMTP id w10mr884505wrg.132.1510155169080; Wed, 08 Nov 2017 07:32:49 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id c67sm3092003wmd.25.2017.11.08.07.32.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Nov 2017 07:32:48 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id D58F43E0410; Wed, 8 Nov 2017 15:32:45 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 8 Nov 2017 15:32:45 +0000 Message-Id: <20171108153245.20740-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171108153245.20740-1-alex.bennee@linaro.org> References: <20171108153245.20740-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 2/2] target/*helper: don't check retaddr before calling cpu_restore_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Alexander Graf , Eduardo Habkost , "open list:S390" , Bastian Koppelmann , Anthony Green , Chris Wulff , qemu-devel@nongnu.org, Laurent Vivier , Michael Walle , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Paolo Bonzini , Stafford Horne , Guan Xuetao , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" cpu_restore_state officially supports being passed an address it can't resolve the state for. As a result the checks in the helpers are superfluous and can be removed. This makes the code consistent with other users of cpu_restore_state. Of course this does nothing to address what to do if cpu_restore_state can't resolve the state but so far it seems this is handled elsewhere. The change was made with included coccinelle script. Signed-off-by: Alex Bennée --- scripts/coccinelle/cpu_restore_state.cocci | 12 ++++++++++++ target/alpha/mem_helper.c | 12 +++--------- target/arm/op_helper.c | 17 ++++------------- target/i386/svm_helper.c | 4 +--- target/lm32/op_helper.c | 7 ++----- target/m68k/op_helper.c | 7 ++----- target/microblaze/op_helper.c | 7 ++----- target/moxie/helper.c | 4 +--- target/nios2/mmu.c | 7 ++----- target/openrisc/mmu_helper.c | 7 ++----- target/s390x/excp_helper.c | 4 +--- target/tricore/op_helper.c | 11 +++-------- target/unicore32/op_helper.c | 7 ++----- 13 files changed, 37 insertions(+), 69 deletions(-) create mode 100644 scripts/coccinelle/cpu_restore_state.cocci -- 2.14.2 Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson diff --git a/scripts/coccinelle/cpu_restore_state.cocci b/scripts/coccinelle/cpu_restore_state.cocci new file mode 100644 index 0000000000..934a042382 --- /dev/null +++ b/scripts/coccinelle/cpu_restore_state.cocci @@ -0,0 +1,12 @@ +// Remove unneeded tests before calling cpu_restore_state +// +// spatch --macro-file scripts/cocci-macro-file.h \ +// --sp-file ./scripts/coccinelle/cpu_restore_state.cocci \ +// --keep-comments --in-place --use-gitgrep --dir target +@@ +identifier A; +expression C; +@@ +-if (A) { + cpu_restore_state(C, A); +-} diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 3c06baa93a..6cf9bba17e 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -34,9 +34,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, uint64_t pc; uint32_t insn; - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); pc = env->pc; insn = cpu_ldl_code(env, pc); @@ -58,9 +56,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); env->trap_arg0 = addr; env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; @@ -80,9 +76,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, ret = alpha_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret != 0)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); /* Exception index and error code are already set */ cpu_loop_exit(cs); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index a40a84ac24..504556a697 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -175,11 +175,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, if (unlikely(ret)) { ARMCPU *cpu = ARM_CPU(cs); uint32_t fsc; - - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); if (fsr & (1 << 9)) { /* LPAE format fault status register : bottom 6 bits are @@ -210,11 +207,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, uint32_t fsr, fsc; ARMMMUFaultInfo fi = {}; ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); - - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format @@ -244,11 +238,8 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, uint32_t fsr, fsc; ARMMMUFaultInfo fi = {}; ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); - - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); /* The EA bit in syndromes and fault status registers is an * IMPDEF classification of external aborts. ARM implementations diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index f479239875..303106981c 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -584,9 +584,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1, { CPUState *cs = CPU(x86_env_get_cpu(env)); - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016" PRIx64 ", " TARGET_FMT_lx ")!\n", diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 2177c8ad12..7b800bbeab 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -150,11 +150,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, int ret; ret = lm32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 63089511cb..3079e04c7d 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -45,11 +45,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, int ret; ret = m68k_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 1e07e21c1c..3b862faaa1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -39,11 +39,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, int ret; ret = mb_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 330299f5a7..2ecee89f11 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -36,9 +36,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, ret = moxie_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index fe9298af50..6d66a5702d 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -41,11 +41,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, int ret; ret = nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c index a44d0aa51a..47cd7775b6 100644 --- a/target/openrisc/mmu_helper.c +++ b/target/openrisc/mmu_helper.c @@ -32,11 +32,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, ret = openrisc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (ret) { - if (retaddr) { - /* now we have a real cpu fault. */ - cpu_restore_state(cs, retaddr); - } + if (ret) {/* now we have a real cpu fault. */ + cpu_restore_state(cs, retaddr); /* Raise Exception. */ cpu_loop_exit(cs); } diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index e04b670663..8584ec43c1 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -554,9 +554,7 @@ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO); } diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 7af202c8c0..b0307de1ea 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -31,9 +31,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin, { CPUState *cs = CPU(tricore_env_get_cpu(env)); /* in case we come from a helper-call we need to restore the PC */ - if (pc) { - cpu_restore_state(cs, pc); - } + cpu_restore_state(cs, pc); /* Tin is loaded into d[15] */ env->gpr_d[15] = tin; @@ -2804,11 +2802,8 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env, CPUState *cs = CPU(tricore_env_get_cpu(env)); cs->exception_index = exception; env->error_code = error_code; - - if (pc) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, pc); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, pc); cpu_loop_exit(cs); } diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index 0872c29faa..5a826b0e31 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -250,11 +250,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, int ret; ret = uc32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } }