From patchwork Tue Nov 14 08:52:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118859 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2784663qgn; Tue, 14 Nov 2017 00:53:44 -0800 (PST) X-Google-Smtp-Source: AGs4zMb9CGbR9Eh2BHqEUa1unArOIKVVwvN9n1qbKvmNnN1MVil9qtTZgKEWcZRAXh2Ify5ktvQq X-Received: by 10.101.81.196 with SMTP id i4mr11280352pgq.54.1510649624342; Tue, 14 Nov 2017 00:53:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510649624; cv=none; d=google.com; s=arc-20160816; b=HHxkVwYMFRejzjEaHcDPIWNLVR7JKVz0sdp/DUCMHBrkEJXkFVnmyWPXeqGxhWMGNa B+SyLiZniZ6T1cONnnw8cnfi/3Xx0XhSIvd+OosyHk3nWVojYeHJ2ShaPO9eZVAcaz42 /Rff7BrFJ4EyQxQBlv8Y8vVg/kLcTYChtHE6FTO/yla++9FGb7Zc9+bj/tmkJ7OZSjW4 dJOftSrxtctINiNO9rUVlZtRiJb5VhpWoFsUufGKbu6PNtJzanNrUsnAYSSNYIJ1XG/8 O3LKmwcvUYVtXXZ5MufxKE5jrxoKvKRf/tBn0VHV0p1Z8w29c1mi/jo8xq6jv3fqAoki IM8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=cv16l5k2e7xOREILQsEImDgJzjwpvIbT3BdFo0llNt4=; b=PpHMPQcIRpeT0XoQyN2dJCb+WdxCeNpLUnGagPCEiYhdc1RfQdRiArp3S7BC6Rb12f nXPr/BEK2xi0yD/sKJP+I+eeIn6h7sfuuDgDEb+XYAdfVD3tcoKFRxfM+AsuRZlWFJY5 /NKBmJBWJAsJf2nlrFmowmAx33no8Y1axkrLGc4AVIhVxe1sRdocPALyGV0Xa079qtNQ TafKixuaW1ctmevQ0fZCpxwH3nSPIrbNihb5hN09j4HA+5Fk7zz15/6E5sO5U8gyukeZ Q5zBrFLpPkY6Z1sAtn3DOOHh17HJBfLiHPPw0e2AENvpOn2FmVwAFuOwBFlpFtEgQxJa pnOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UKeJb7F5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x8si11130279pgq.460.2017.11.14.00.53.44; Tue, 14 Nov 2017 00:53:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UKeJb7F5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753544AbdKNIxh (ORCPT + 6 others); Tue, 14 Nov 2017 03:53:37 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:49977 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753137AbdKNIxU (ORCPT ); Tue, 14 Nov 2017 03:53:20 -0500 Received: by mail-wr0-f194.google.com with SMTP id o88so16759968wrb.6 for ; Tue, 14 Nov 2017 00:53:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GlBilOK4xrPCZn69luv1A0oG1iUpeKmAhROpfSnoqIA=; b=UKeJb7F53lhIEzK0WisHVYW7a+3xsQbxb/OvveUUQK0tiYvpUeiFfViCWaz2D+CAs+ srbVOjElp94NgmY/wR+LkXTlHnxPWL1ke5EXaP8nNp/1aW4DplW2sIKEV9wH5TF0pAwL Luukaq3MPOXEwyMRXSWeqPyfgmeLt4Fq7UYH0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GlBilOK4xrPCZn69luv1A0oG1iUpeKmAhROpfSnoqIA=; b=pdei2OGLVaZAo6QckgzIgcOVrQdnS3rco0D0Xdymgu/XZgKaDK7zJ8BK7cPTaWvQAb TLaw4RHFEI+0Sl2E/ujJxG7/k/iqpdgoYxqHprzvM3DSi9NFiN/2Mkw4cIOXXiwhrbwx iazf18NICb68LFE8gsysjKt6OANFeseVkReov/gp+l1RiEL/wt2JMfAk7pVy/64nru1n XMoqMDGic8SbFlzEw6dkvoFOieVx+6g8ivHkVBCFo9TMYmE91DeWn8/i7a7VU8xsOOMF JDIgVAB7qqd14fhYCjHfGoQq6ShlFTURVAgEghqAQ3s2pziCHQ8TsJFo/+7ojYo1cnQ3 XZPw== X-Gm-Message-State: AJaThX6GUNQKfO6ovU180Dg4yBta59T/vL5gD4fg9IQW8e1/HsMHKg5E Z+KSuUGIywrM7BCFE/hH/+vZnw== X-Received: by 10.223.185.33 with SMTP id k30mr9537203wrf.40.1510649599459; Tue, 14 Nov 2017 00:53:19 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.205.30]) by smtp.gmail.com with ESMTPSA id g28sm22894551wra.31.2017.11.14.00.53.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Nov 2017 00:53:18 -0800 (PST) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com, sudeep.holla@arm.com, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v8 1/6] clocksource: timer_of: rename timer_of_exit to timer_of_cleanup Date: Tue, 14 Nov 2017 09:52:38 +0100 Message-Id: <1510649563-22975-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change function name to something more explicit since it is only used in init error cases. Add __init annotation and description about the function usage. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-of.c | 9 ++++++++- drivers/clocksource/timer-of.h | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index 7c64a5c1..a319904 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -177,7 +177,14 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) return ret; } -void timer_of_exit(struct timer_of *to) +/** + * timer_of_cleanup - release timer_of ressources + * @to: timer_of structure + * + * Release the ressources that has been used in timer_of_init(). + * This function should be called in init error cases + */ +void __init timer_of_cleanup(struct timer_of *to) { if (to->flags & TIMER_OF_IRQ) timer_irq_exit(&to->of_irq); diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h index 44f57e0..f521477 100644 --- a/drivers/clocksource/timer-of.h +++ b/drivers/clocksource/timer-of.h @@ -67,6 +67,6 @@ static inline unsigned long timer_of_period(struct timer_of *to) extern int __init timer_of_init(struct device_node *np, struct timer_of *to); -extern void timer_of_exit(struct timer_of *to); +extern void __init timer_of_cleanup(struct timer_of *to); #endif From patchwork Tue Nov 14 08:52:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118857 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2784534qgn; Tue, 14 Nov 2017 00:53:34 -0800 (PST) X-Google-Smtp-Source: AGs4zMbssrBEoMgoDvcisAPu0g+jLD+nCXWEk0xPJo8sNkuhYulLLj3T8bBjcv2+ElolQ5LIubZa X-Received: by 10.84.172.195 with SMTP id n61mr5424852plb.78.1510649614053; Tue, 14 Nov 2017 00:53:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510649614; cv=none; d=google.com; s=arc-20160816; b=EZMD0Yte5Li5aaev2GR8C8Axi+N+F+7huEwin7M8JCk1c40KM7n0xOsBqtJThSJl39 BgSW4cPlTO91RanENSYvEJcw6Ajp9dHNaC+g46s2IxEMRrr/i7Sn3s+WixYH42KU/1jI QnrxZRQDhkqg6kmi7r3qHlmRTgs4C7LbsHvK4QDphvLYvorzsebXyh+kFCuZ4eHy5gn/ 1Hd6Fo2hn0qygoRQ3e3vAABM9M9MvxtEqb3NndyWF8aUrmhOMpnHf4gqh7tKOrhlcrgE bWDAlgwyalgWB5IwuFexxKdRbdy4lx6HboX+4C9w7Qf8z75XY/vts2se53I6AHJ2DEgj 7QPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=VQWs/4tVeOpkQuQCwyBMWjqDsbmDEz8IwDpxNF9OOgw=; b=BxOroYEoCWwPZtwjWfmIcnbqhGrZWeglf/CBpOAkD+ztwEBv2GPd1+E50Cy4SA9AtX twHz/H/Z3Qcp9mU29Sr2MQ73o1lLt0W6OdRZhwmIgIkF9SiJZ15naZPAtr8kvQk96SI3 YGlYl6jQf78NnWdNwLe7rVJhcjdAXZlSElvSKX+ofFCNY+Jrzc7dOIiRVZWCxYzRxg4A /Cvba8/a5DbeN37VOgxul5nggq3+ZpTAGzTXXQc9q68RkHDt5w4iJH5kTlteq93PdGBc W/lWOHtT3/pjLpceCjQ8m/N904k7cWRKykKHX6NnJ5erFFU7dUyvJvKPc//EJF0WElRU +fxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ol8cWWMU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f18si1550915pfe.25.2017.11.14.00.53.33; Tue, 14 Nov 2017 00:53:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ol8cWWMU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753376AbdKNIxc (ORCPT + 6 others); Tue, 14 Nov 2017 03:53:32 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:56260 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753220AbdKNIxY (ORCPT ); Tue, 14 Nov 2017 03:53:24 -0500 Received: by mail-wm0-f66.google.com with SMTP id 9so14701915wme.4 for ; Tue, 14 Nov 2017 00:53:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZQOqLxyvQW+PuZPAGz9Gy3QxhkIzyk3mH70t2MstKX0=; b=Ol8cWWMUPnICieQI0ofIjdj38WqlfkRsze9aQDncI2HkFfn27MAVkhI3RZgqWuK+UO qYv5Y8BMtTwaT6EoBQ9rDHH0fEs6LXn6DoO/ZQEtHBdN4WSKjgo3xu+Jw3V35Bq3PHaw HAZKzl6Q+DpFAjEL5q3BrlZqnrjtwZmJC829s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZQOqLxyvQW+PuZPAGz9Gy3QxhkIzyk3mH70t2MstKX0=; b=iNSUPRf0lTk/hSBD46d1itljc+6HfxqxCWI5mXd+PiHLiyzSK721/mwoPOZ49ae7Ny pYzBvejkAKHR6W6PHKEnB5Abp3ddhY22uEN6K6qkhTFcroVik0+G0ZuAQsktUFQUUyQS avTBMwVjzcXOLy6K2jRWpbCK5bfvF9m+yiChROR8PX4f7oarZoOLLHoGfMWRAAnKx5Jr vvZNRqEgvOttnK3whqI03ba1eSPDOEYbhE9EckZUcqLFVc18fdyEjRb9ZkcV/4Pk+i/p mi6Nomk2PsVL6AuToHoH1o4c3HVZppuuw+j1ZLI1rI4z/65TQefxRZRlh6rUMrH1PQHH IzbQ== X-Gm-Message-State: AJaThX5mRNlIYKSOC466qM2iA720jE6Jd1BGsGoykPCe9bsNBQyxXNBU q5W+THCdAIuUMevxSxBlV7xYRF6vlyU= X-Received: by 10.28.191.80 with SMTP id p77mr9194841wmf.85.1510649602404; Tue, 14 Nov 2017 00:53:22 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.205.30]) by smtp.gmail.com with ESMTPSA id g28sm22894551wra.31.2017.11.14.00.53.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Nov 2017 00:53:21 -0800 (PST) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com, sudeep.holla@arm.com, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v8 2/6] clocksource: stm32: convert driver to timer_of Date: Tue, 14 Nov 2017 09:52:39 +0100 Message-Id: <1510649563-22975-3-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert driver to use timer_of helpers. This allow to remove custom proprietary structure. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 160 ++++++++++++++------------------------ 2 files changed, 58 insertions(+), 103 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c729a88..28bc5595 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -269,6 +269,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f24237..fc61fd1 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -17,6 +17,8 @@ #include #include +#include "timer-of.h" + #define TIM_CR1 0x00 #define TIM_DIER 0x0c #define TIM_SR 0x10 @@ -34,117 +36,84 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, base + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + evt->event_handler(evt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static int __init stm32_clockevent_init(struct device_node *node) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } - - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); + unsigned long max_delta; + int ret, bits, prescaler = 1; + struct timer_of *to; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; + to->clkevt.rating = 200; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; + + to->of_irq.handler = stm32_clock_event_handler; + + ret = timer_of_init(node, to); + if (ret) + goto err; + + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; bits = 32; @@ -152,38 +121,23 @@ static int __init stm32_clockevent_init(struct device_node *np) prescaler = 1024; bits = 16; } - writel_relaxed(0, data->base + TIM_ARR); - - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); - - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } + clockevents_config_and_register(&to->clkevt, + timer_of_period(to), 0x1, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + node, bits); - return ret; + return 0; -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: +err: + kfree(to); return ret; } From patchwork Tue Nov 14 08:52:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118858 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2784594qgn; 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[209.132.180.67]) by mx.google.com with ESMTP id f18si1550915pfe.25.2017.11.14.00.53.38; Tue, 14 Nov 2017 00:53:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bXQiWB4l; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753507AbdKNIxg (ORCPT + 6 others); Tue, 14 Nov 2017 03:53:36 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:53439 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753282AbdKNIx0 (ORCPT ); Tue, 14 Nov 2017 03:53:26 -0500 Received: by mail-wm0-f65.google.com with SMTP id g141so20185174wmg.2 for ; Tue, 14 Nov 2017 00:53:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tPiCSY1XxdVRL/3HyNOPyM+f2qsOGv+RrPybQEQ2638=; b=bXQiWB4lpxtiF6SJkVMGr5v1prOB8TvDZhKTC2wyCGRXhgfRzHybID1lpwruu95bsq 8rW+uPdIsQaOIOEPR0H0EHdAx01ukasZvDMNoRyqLHXd5yAzqZyXwCIkGvx1og4GitUC 1j/F17omcgkYc4+TWkYsvOuCeFc6RtO2NUJ9k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tPiCSY1XxdVRL/3HyNOPyM+f2qsOGv+RrPybQEQ2638=; b=V0MkHyBLHA6arelM8/qdp8E1oScy9m4bCq5xoa7u+XXTHhfHqEXdpD34TaYyDXWbMm oGewJrmUXkIjOCL5gN8W05a5B12GHcjEy8VwMYg7cIT/D9wd2dsWggjgsOZ36dhCXKcd lmQPDbiSD5QUXrqnlQF5FwPmRmah5B4gLkJXiZMRGqd2uBf1Rf0tcmMLilZGj8Im355F 0wAFt+HK5fCximfUZ8kqf1cwvJ5/9v+J+u5iJ9zaiKkpgfiq923Hb/zXhcQH+kCvYYMa nxbnXJj5zT7LEFtmzhMpwu+TqB8d7k/O21D/Zhu6KuE99zSqbLQOsgq58fcYj4kl0eE2 Gtrw== X-Gm-Message-State: AJaThX5P8aaLAzR28Iui3NSXRcwtX6y9xx4avONLBnmYq07oD/glVxKO vrXLpqK7ssa9wcz4WV9/SuZvtw== X-Received: by 10.28.71.67 with SMTP id u64mr7826616wma.48.1510649605107; Tue, 14 Nov 2017 00:53:25 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.205.30]) by smtp.gmail.com with ESMTPSA id g28sm22894551wra.31.2017.11.14.00.53.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Nov 2017 00:53:24 -0800 (PST) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com, sudeep.holla@arm.com, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v8 3/6] clocksource: stm32: increase min delta value Date: Tue, 14 Nov 2017 09:52:40 +0100 Message-Id: <1510649563-22975-4-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The CPU is a CortexM4 @ 200MHZ and the clocks driving the timers are at 90MHZ with a min delta at 1 you could have an interrupt each 0.01 ms which is really to much. By increase it to 0x60 it give more time (around 1 ms) to CPU to handle the interrupt. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index fc61fd1..ae41a19 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -36,6 +36,8 @@ #define TIM_EGR_UG BIT(0) +#define MIN_DELTA 0x60 + static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); @@ -129,7 +131,7 @@ static int __init stm32_clockevent_init(struct device_node *node) writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x1, max_delta); + timer_of_period(to), MIN_DELTA, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", node, bits); From patchwork Tue Nov 14 08:52:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118860 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2784677qgn; Tue, 14 Nov 2017 00:53:45 -0800 (PST) X-Google-Smtp-Source: AGs4zMakxyHoYQVLz5F2w0i7d6Q0iReOTD0jz5qIsEXqUtHcwcNUBMlseDPUZpq1jDN+DaYhtLMI X-Received: by 10.99.183.10 with SMTP id t10mr11726527pgf.128.1510649625766; Tue, 14 Nov 2017 00:53:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510649625; cv=none; d=google.com; s=arc-20160816; b=TLt6L0mBQsSBgDpvW5BuGeIgo96b/wpz9fCLSLQHuuV2m9qkn30bsqStUbC/Q9r9+A PTUc0v7py+ueb+FaEhacL7AhqeUNZVob1Mhvt8LbWQPEj8o2fWwul66LutDHii2ISWG2 4I4dtySpKxhysmFJHqSlIgZwcGZ2W48D8ieQQUA1rigJriKvJ1Kow7iVKHbBlUyei22Z QZiDyqXA9aeZsQr5sGCfxzID2Pm80BFDRJBLEoO0wmvIIbaUcPV+bkBlWsoSf85xRTSU ri9G2Tbs+9m1Kfqd1TmCwojNMhGi7syLRLy5T9H+0DsInGAf9VVgI96HtoRBZrzP3E2E ZwCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Cm0JfxckbGav8Cmdlx5T5an8Ik1pC44e2Qhy4UDL8kc=; b=vaesh4IPcTaAKs0LTBc8aV2MhrH/rfeSiEQcKvlVLeagNGudo1FXVIR0tPfAeqk0xa izfTTuS+dUUvK0vvZhhfoBW+bS4FZB3kXFx4dPTEu30CQBHsjz10vSIocxRKSk8ONKKs 4Ov1vOizC6VcfAtxW1EjW9yK1zhDQgRMFpDcjWNy+TT4fO1D3JuQfdrb9o9jCCTwhfNh LMcdQcVp43Izh8KHDkZQEFX8H4I9LZPDQ2CU48vCW2hL1dZm5hcnpHgjAdd6WWuO8hZu lKLfSJ9pnkaytYYObCqEbaUWTYq1rE9dKmmUtFpSxOTmHQbd8HyWl2MDGnensihSy5kv Y5Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tfv2qya1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x8si11130279pgq.460.2017.11.14.00.53.45; Tue, 14 Nov 2017 00:53:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tfv2qya1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753592AbdKNIxm (ORCPT + 6 others); Tue, 14 Nov 2017 03:53:42 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:40712 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752952AbdKNIx3 (ORCPT ); Tue, 14 Nov 2017 03:53:29 -0500 Received: by mail-wm0-f66.google.com with SMTP id b189so12901367wmd.5 for ; Tue, 14 Nov 2017 00:53:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IPOdwj6QrGu1gx7nMpbAZwlPQlpdDW1hnIoGbpw7W9E=; b=Tfv2qya1pZ9agEG1lzIv1k7eyIacKP1fsh2qwCI6QUOkaTFUxFLkos0b+rDbV/8WLB tc1whMfAEaYCOztSkR7ulrLonbxmUBALAw+/1HCszfZdaK4eiZ1xYxy6AotCXBRUyVq4 iXZlABLUE947Ckrzd2xwNaxt4sLJZNLkAVnUw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IPOdwj6QrGu1gx7nMpbAZwlPQlpdDW1hnIoGbpw7W9E=; b=XHWcXvX+fGGITfmgDCmIOYH3/okX2q3Lbbazz6uQRhIkYGESkMDWL3TX5AXBuYcuqX 3fjp6uFz1K1TAtcAVx4ZYf51aM48LOOkfkzJ2EE64nk609wHEAglhB2JOYoXIbeqcVeD vl1qRg3kHvx+QUXgPkzwC6bqCdVGXaYbObTLz9AwKwP9OcgNwsIdnihdriC+cdNfrl0Z T1Qwa9dPfNvlHF3kd45QadPqU/WK0Uwr0giiNhMK8uKp7owzVd7+F2gjaJ1VGQBcYa58 fWseqMKk/663sOjzWDTVZUZmcbh38TNCcO9y65QwZQg7Zohw7b3Yif8/r+GQ6tStl560 bFtA== X-Gm-Message-State: AJaThX55Y7AgJvso7aCJ/ZLT2wO5wOx+AG/CY61ItC9LG7XEdD+UXuMy +9pW0F2ALFZRZzh/JvGnVF4mag== X-Received: by 10.28.30.2 with SMTP id e2mr8195102wme.36.1510649607832; Tue, 14 Nov 2017 00:53:27 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.205.30]) by smtp.gmail.com with ESMTPSA id g28sm22894551wra.31.2017.11.14.00.53.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Nov 2017 00:53:27 -0800 (PST) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com, sudeep.holla@arm.com, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers Date: Tue, 14 Nov 2017 09:52:41 +0100 Message-Id: <1510649563-22975-5-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock driving counters is at 90MHz so the maximum period for 16 bis counters is around 750 ms which is a short period for a clocksource. For 32 bits counters this period is close 47 secondes which is more acceptable. This patch remove 16 bits counters support and makes sure that they won't be probed anymore. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index ae41a19..8173bcf 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -83,9 +83,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static int __init stm32_clockevent_init(struct device_node *node) { struct reset_control *rstc; - unsigned long max_delta; - int ret, bits, prescaler = 1; + unsigned long max_arr; struct timer_of *to; + int ret; to = kzalloc(sizeof(*to), GFP_KERNEL); if (!to) @@ -115,29 +115,27 @@ static int __init stm32_clockevent_init(struct device_node *node) /* Detect whether the timer is 16 or 32 bits */ writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR); + if (max_arr != ~0U) { + pr_err("32 bits timer is needed\n"); + ret = -EINVAL; + goto deinit; } + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), MIN_DELTA, max_delta); - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - node, bits); + timer_of_period(to), MIN_DELTA, ~0U); return 0; +deinit: + timer_of_exit(to); err: kfree(to); return ret; From patchwork Tue Nov 14 08:52:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118862 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2785096qgn; Tue, 14 Nov 2017 00:54:21 -0800 (PST) X-Google-Smtp-Source: AGs4zMb3NQN8Yzc2HRI1EDco97BE4HP8iFMPYIxJ75NF8ZgZRXyg4EeMXVPSdDWQbqLHL4efZAQn X-Received: by 10.84.131.68 with SMTP id 62mr9955076pld.185.1510649661436; Tue, 14 Nov 2017 00:54:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510649661; cv=none; d=google.com; s=arc-20160816; b=yfnH1CUkJhSQ/lv3xDFA9TLBjKyuMvPLbQ1PWVyTkcIYEuYAi/TS65+qGkSb06U7jq 6MqE4LPkD+p1EZ46PNPgV7F6RpAcX8EbGKLe08KMom0qBJhMKOJJ5ck5ru8MrqKql9zf V28VEDvvw19mI6xq3UPdyxdvpfN04ebWm/XzzjWXRjVLYFVx+BLTuZBJ1TiISQSgVQeM +Bm/5jHlVeWDPr+9uCEagBbtX7w5n1vXV5s777dP0szblHrLUzjs1hdxu8bNkP86HNpx eDXrukGy3GTZh8BL5yjqNrXqTOJmMsqBBhEAqRGDRgO/VzhNpZqQdE1ivCNcFDAQD7+t hxEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Nfj8++k29HNoLYrhWs1J4XXQ18Xb25URUD1NYtgCZmg=; b=tu4J5lPvI9ZGFKYEwAS/oXDhWB07WbvXgi0kQdiEx/xCxc0O8fl4jR2ITsmXINLbBF aRZuEDlZKvTcG3eJEtOECN3tD7wRb9lC6rH6VqwyFON7kwtqHF6tFsLbACYIP6pMHI54 8XpCYnfneH7p5ZnchcBE2FFRH6YXcN3T1nW/ZD4xrPyu6O8wU2nExd5MibxeBfNAQiZs WbnYCCVwbiX0HojM6V9kVFa3f/o3TNOJYjAG3n1542l9fW2k0JDOv4+MDvqlw3xIv0dF WW1ByQVRNgFPHbTpFkP8sCLSMIuOL9WyhKmr60/V9m/emKph0MWc2v92Jtx2/xU0VAmS 5mQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HUDZ3akv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x8si11130279pgq.460.2017.11.14.00.54.21; Tue, 14 Nov 2017 00:54:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HUDZ3akv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753462AbdKNIyT (ORCPT + 6 others); Tue, 14 Nov 2017 03:54:19 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:46216 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753147AbdKNIxd (ORCPT ); Tue, 14 Nov 2017 03:53:33 -0500 Received: by mail-wr0-f195.google.com with SMTP id y42so16808958wrd.3 for ; Tue, 14 Nov 2017 00:53:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CNfhm8yx6x+a0f51NOrdEx0YCg7fzpeQaqJDNAp1+A4=; b=HUDZ3akv4NPiSYUhlKwryP9JV2Y2LY7NQqildsze5iFJfOvd96cKf2HhchxIgfHUlU lE1S/Fy/lLExG+GblzII2wHizI84oxUWcSyzKQRasnrz8+QfJ5KxAdrv468KADrgNq6Z GWwgPs12xD0DtbKBwWO1lc1nF/1rrj9bGKD4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CNfhm8yx6x+a0f51NOrdEx0YCg7fzpeQaqJDNAp1+A4=; b=eBtgtWFndEsZ08xelf9luoMT95wLTxgrsTIXQZQq8srvbeKuobqO+Ah85zHAyqi0ZS 01+FM6xXlMXTFoDANbgOAVLExsn2ZPUGQelA9nsvLRLsW+Bb+GddqmEBA/ciLba1KANh QsvjaYs0AgJqXahvPWcaZQ5V/av4j5CYmT05p+Y1fG/kPx4DZVbxWkfiP1WtkQPHDwyE 6n1X0wSvSBe18idit2hSrckWN82mcJ7/T2lFTayBxG+A8MA3kPDVFL/zoTI1gc/kCOxq WjPJBpCKfk7DzHHEnoNd5XbJO/hZk4WCeIRXXBe/+hgHl5NZ7l10ZZiK3RwfwKEVeZMi XoYw== X-Gm-Message-State: AJaThX6/JreXUWOwnbUfOe5btxH26apHeZ5J851n8/05OoGrJXvj7heK 5b/PYnc+DL8yfHEQG1Kz7USGJw== X-Received: by 10.223.166.103 with SMTP id k94mr9504691wrc.22.1510649610589; Tue, 14 Nov 2017 00:53:30 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.205.30]) by smtp.gmail.com with ESMTPSA id g28sm22894551wra.31.2017.11.14.00.53.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Nov 2017 00:53:30 -0800 (PST) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com, sudeep.holla@arm.com, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v8 5/6] clocksource: stm32: add clocksource support Date: Tue, 14 Nov 2017 09:52:42 +0100 Message-Id: <1510649563-22975-6-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The stm32 timer hardware is currently only used as a clock event device, but it can be utilized as a clocksource as well. Implement this by enabling the free running counter in the hardware block and converting the clock event part from a count down event timer to a comparator based timer. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 116 +++++++++++++++++++++++++++++--------- 1 file changed, 88 insertions(+), 28 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8173bcf..c0a62cd 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "timer-of.h" @@ -23,16 +25,16 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) @@ -42,28 +44,44 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; + + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long val; + + val = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(val, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } @@ -75,12 +93,57 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; } -static int __init stm32_clockevent_init(struct device_node *node) +static void __init stm32_clockevent_init(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), MIN_DELTA, ~0U); +} + +static void __iomem *stm32_timer_cnt __read_mostly; +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, + timer_of_base(to) + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), 250, 32, + clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { struct reset_control *rstc; unsigned long max_arr; @@ -92,12 +155,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -ENOMEM; to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; to->clkevt.rating = 200; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -122,23 +186,19 @@ static int __init stm32_clockevent_init(struct device_node *node) goto deinit; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); - - writel_relaxed(0, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; - clockevents_config_and_register(&to->clkevt, - timer_of_period(to), MIN_DELTA, ~0U); + stm32_clockevent_init(to); return 0; deinit: - timer_of_exit(to); + timer_of_cleanup(to); err: kfree(to); return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Tue Nov 14 08:52:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118861 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2785062qgn; Tue, 14 Nov 2017 00:54:18 -0800 (PST) X-Google-Smtp-Source: AGs4zMYZcvgoPD7XTM/9Uke4gaovgbOI1OXK+EFvXlpMPxHAKY+5P7rkC1hdt3ZS50Q1cWr5ATL4 X-Received: by 10.99.139.199 with SMTP id j190mr11271501pge.375.1510649658328; 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Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index dd7e99b..ac9a3e6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -108,14 +108,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -137,14 +129,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +178,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +194,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5633860..a9077e6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,22 +82,6 @@ status = "disabled"; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,22 +89,6 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>;