From patchwork Fri Oct 9 15:44:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 285089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B77AC433E7 for ; Fri, 9 Oct 2020 15:45:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 05E01222C3 for ; Fri, 9 Oct 2020 15:45:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="s6APqbZE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389377AbgJIPpL (ORCPT ); Fri, 9 Oct 2020 11:45:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389252AbgJIPpL (ORCPT ); Fri, 9 Oct 2020 11:45:11 -0400 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AC47C0613D7 for ; Fri, 9 Oct 2020 08:45:09 -0700 (PDT) Received: by mail-lj1-x243.google.com with SMTP id r24so10058495ljm.3 for ; Fri, 09 Oct 2020 08:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F7ROo5jyveUFbJ4E1aiSSUyCQWf3HCYhf0rLelMu0mA=; b=s6APqbZEnTICO9pYVi+tm3fAbGcyU7kTtihIho5mjQ+1TPVRCJUjPpIIXy2K5OWSYR SxInT++cmyYAdgkTGyBHO6vPAuRzJBO+FaM1lrMrtnquWmjvnJzvhEQAXpRwVRfkuQnG ZdHAFEYRW3kc/S0KlzVXBHc8T/MXIcXdXe8cpz17rDM0vBWmy2gAaBUo1kxuBu9YtIKA QxXsnd70WIoS0Pf8JHaeU0Qal70XxFVEtNxtwKOIVvNJxI20tuf9jQXvIvjHYjEhCqto dHj1n3rDKfT1fAwlD2p4T29H3XDSeQfuofSGpItkLPCbf4SF2+oYAB7toCK10KxVGynP zKeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F7ROo5jyveUFbJ4E1aiSSUyCQWf3HCYhf0rLelMu0mA=; b=NgZXJfZ57hLcOz5FqVjHWG6I6vChcE/J995Ct7SCauMAhJUnZMHmmh9q1PCNkogFIR /P9PE2YEcddH1g7lNJUSngU9wm/KC2ReFKeJW1JSaEL3sgBFscFQ0JHa9wHGA7iOy7IO /8FvUF1TkEOlPoUyvGm4FWV57IpXHPU7ciUwYXLqqx8QFsqP7tfNpMlCyAVY5JIdIBE4 lvGyinwfczrGQ1F2foIN7uPJDcTIDdrqNoNe73pilDFCf9OI7P9OzAjgCDq3eORZeh/M WHQ5THOwRfFiXi1ueCrA/Qst+uPcFFrsjdpdt2E53Cr4vZjK0EgkRUnqCAbzNXaSvmbp 3crw== X-Gm-Message-State: AOAM532ejY91jPUZ8+cEeCKGKu6FYPnL74usyU4tvkZzXP0Aw151I79J /5Z9ai5C5QgtUQ56g81EL0aqPQ== X-Google-Smtp-Source: ABdhPJxLhv4L3hFWN1w1jP2YlFIQpN/LoyBF5xhISu8ztJXBb0xvI4cOOlRNWC9Lemaw/zo/IpRm8A== X-Received: by 2002:a2e:7a09:: with SMTP id v9mr5311276ljc.82.1602258307129; Fri, 09 Oct 2020 08:45:07 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:06 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash , Rob Herring Subject: [PATCH v8 01/11] dt-bindings: thermal: qcom: add adc-thermal monitor bindings Date: Fri, 9 Oct 2020 18:44:49 +0300 Message-Id: <20201009154459.106189-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for thermal monitor, part of Qualcomm PMIC5 chips. It is a close counterpart of VADC part of those PMICs. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml new file mode 100644 index 000000000000..9da2b349030d --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC Thermal Monitoring +maintainers: + - Dmitry Baryshkov + +properties: + compatible: + const: qcom,spmi-adc-tm5 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of samples to be used for measurement. + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + default: 1 + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + enum: + - 250 + - 420 + - 840 + default: 840 + +patternProperties: + "^([-a-z0-9]*)@[0-7]$": + type: object + description: + Represent one thermal sensor. + + properties: + reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Specify the sensor channel. There are 8 channels in PMIC5's ADC TM + minimum: 0 + maximum: 7 + + io-channels: + description: + From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor + + qcom,ratiometric: + $ref: /schemas/types.yaml#/definitions/flag + description: + Channel calibration type. + If this property is specified VADC will use the VDD reference + (1.875V) and GND for channel calibration. If property is not found, + channel will be calibrated with 0V and 1.25V reference channels, + also known as absolute calibration. + + qcom,hw-settle-time-us: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Time between AMUX getting configured and the ADC starting conversion. + enum: [15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000] + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Used for scaling the channel input signal before the + signal is fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by + which input signal is multiplied. For example, <1 3> indicates the + signal is scaled down to 1/3 of its value before ADC measurement. If + property is not found default value depending on chip will be used. + items: + - const: 1 + - enum: [ 1, 3, 4, 6, 20, 8, 10 ] + + required: + - reg + - io-channels + + additionalProperties: + false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + pm8150b_adc: adc@3100 { + reg = <0x3100>; + compatible = "qcom,spmi-adc5"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Other propreties are omitted */ + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + }; + }; +... From patchwork Fri Oct 9 15:44:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A5D4C43467 for ; Fri, 9 Oct 2020 15:45:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9307222C2 for ; Fri, 9 Oct 2020 15:45:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bwohXV3Y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389382AbgJIPpM (ORCPT ); Fri, 9 Oct 2020 11:45:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389313AbgJIPpL (ORCPT ); Fri, 9 Oct 2020 11:45:11 -0400 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74324C0613D5 for ; Fri, 9 Oct 2020 08:45:11 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id a15so10073540ljk.2 for ; Fri, 09 Oct 2020 08:45:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u+ec5e/iUjJ8qDBtGE9xKBCADcm1RI8srVHT5OLXlvU=; b=bwohXV3YZo5cTz0TyNBCL/bMBJIwuPprPvrhOn48oBFgGvgBiXBPol+T7jzXJBlYAA jUNORplCm8Wgt6R/yIDhzByfIanKQaRWKUsdeKHBlp9j7NJay5EhVgnn4OsBJuW8J5rT 4jY1ipSBsKUbbkCAHXDVjb+xgwIl+w8giDNkvPSQH/N1orSMRnrH/odd77upToDSb/tZ C9bDTxulmJAh7cAMvpxWd8JWMXHySlcOgA90BBBcPtxqwOC2vrjeGvdHFEiwn/cJ+x5H pLGtSKf/BZvDTvSJ6pjLxBWYBYY0TaULkbUVShYJDXk5SqlJa8+bv3Sdc2ab16TnE7Em 2sgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u+ec5e/iUjJ8qDBtGE9xKBCADcm1RI8srVHT5OLXlvU=; b=jQbq4RxEJDIuy8mCkY0MgITMu/IpmqNCEv+tih2BqasotJu3n6dR0lr8LEDKbOBwLd kbhajyVBrdj0Rlh9bjQYNeTgkWWnVXDqHLnnN6X5XbdSMthPg98BXIgaao2jlXnPZjfl 2ikPv0sjbNKfb8y3/ZYCJDUzv3VD7pkMzYAjtLwOJOy4kDLFmwC7/xjlkjPF8hSxNqLg 4l3SFoIl3eCGPmUBD/CJ7nch6aWxSUM+MG9GOdrvSO2+tsFBwXlKkmGGfbw1uBdiV/+v r7zcC42QKt7rZIPWj0zZpYme2kwKST1W3XYcJ3ADRGxUtr9InnsKoXbDainHkC70kCrz kkNg== X-Gm-Message-State: AOAM532/yk8MhRLPcwNxA+nu+7+P/lNPisv+Qfa5Y6RGWwbHPBrHiO5O y0hh1IlZoMtrDa9k5fiGLm/VRQ== X-Google-Smtp-Source: ABdhPJx4YT06cf8vN3nDNG3Uu3PKq6LBvxoVB37Y6nn3qXNuVpxuivte4YhuJX4KuTYrszCj94VHFw== X-Received: by 2002:a2e:8042:: with SMTP id p2mr4336774ljg.90.1602258309858; Fri, 09 Oct 2020 08:45:09 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:09 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash , Craig Tatlor , Jonathan Cameron Subject: [PATCH v8 02/11] fixp-arith: add a linear interpolation function Date: Fri, 9 Oct 2020 18:44:50 +0300 Message-Id: <20201009154459.106189-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Craig Tatlor Adds a function to interpolate against two points, this is carried arount as a helper function by tons of drivers. Signed-off-by: Craig Tatlor Signed-off-by: Dmitry Baryshkov Acked-by: Jonathan Cameron --- include/linux/fixp-arith.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/fixp-arith.h b/include/linux/fixp-arith.h index 8396013785ef..281cb4f83dbe 100644 --- a/include/linux/fixp-arith.h +++ b/include/linux/fixp-arith.h @@ -141,4 +141,23 @@ static inline s32 fixp_sin32_rad(u32 radians, u32 twopi) #define fixp_cos32_rad(rad, twopi) \ fixp_sin32_rad(rad + twopi / 4, twopi) +/** + * fixp_linear_interpolate() - interpolates a value from two known points + * + * @x0: x value of point 0 + * @y0: y value of point 0 + * @x1: x value of point 1 + * @y1: y value of point 1 + * @x: the linear interpolant + */ +static inline int fixp_linear_interpolate(int x0, int y0, int x1, int y1, int x) +{ + if (y0 == y1 || x == x0) + return y0; + if (x1 == x0 || x == x1) + return y1; + + return y0 + ((y1 - y0) * (x - x0) / (x1 - x0)); +} + #endif From patchwork Fri Oct 9 15:44:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 285088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E01C4363A for ; Fri, 9 Oct 2020 15:45:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D59F222E7 for ; Fri, 9 Oct 2020 15:45:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XL2vdeWg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389441AbgJIPpQ (ORCPT ); Fri, 9 Oct 2020 11:45:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389224AbgJIPpP (ORCPT ); Fri, 9 Oct 2020 11:45:15 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F28EFC0613D5 for ; Fri, 9 Oct 2020 08:45:13 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id h20so10052743lji.9 for ; Fri, 09 Oct 2020 08:45:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JBF3uLUf/ZUhgh6mGdQvvNaF8GSfsySai+h7lBFUhRU=; b=XL2vdeWgEVe94RGhiYbFDW/ClKymnBKiFPGYOUzuBKpryBUCzgF36zed+Gr6PwqCKT F8GUMm39Krdbm/f/xZ9O6SVNbxlol+Pal9xm61+gTFypOJN/tSEZ0UOmN4t7OlswW7RO yeWs5blxicvGf5JQ+iF97HuUnElk2EsvDPQpmoHniVtOW4UcPHtSHUiug0b8wG4mWHKZ EQgPWpqRBfLd6efFQbYrsl7kILPNp5XM0yQmvnO0h0N3CKVX0jHyWZzn4+F4OVwwQfyb fq1uunlh+tQQAGlxxILJVYyY+PobE8UqXprhDEiItY1/Zaq3QaQmnluoXuUyGqniGeMY Kf9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JBF3uLUf/ZUhgh6mGdQvvNaF8GSfsySai+h7lBFUhRU=; b=LiPA9x6GF97lcxf8tGSweTD5EP460MPtE9qa27t+47wNSSEfsw9tEkQnk3sb+rASyC /Jdg+X8Sj+CAjxr4szW1JNeyuXJwflJ17WSGR3eDHjSQaXumck2d8KABq6NqSNEaFxfE fR2VEwf4n0PIqilAt284mgSeg7RwkpH7jAKCbXu+QKO79APVrRzkrUH/ux5j8dMgnFCj NHalzFm7JokuuvnzPYNDLilZfwXsTdXB6YEsvAG/NdCe+lzuC+u5eS7ApqrEWp4XnC0C JAxBTwVnK0LL6EfHb/zvwohgK2Wps7K0b5O1m3oRLoQ43Ocig2Pj53PlDIw6/f0GWTIG kXjg== X-Gm-Message-State: AOAM532A+viTRs0/bL5gRx4p/8bikzj0fsrB9Uwq5Tl12Tc4Yry+hEd/ XNsKv2cklSgjY6x0w7yjtjCJFw== X-Google-Smtp-Source: ABdhPJyJMWeonPuKWJGmws0xoWX0CZRCHIogY7XtVeD69hFBZK4q/IXkF0qff35OA6jbCBUqdsg0+Q== X-Received: by 2002:a2e:8e86:: with SMTP id z6mr1674964ljk.190.1602258312392; Fri, 09 Oct 2020 08:45:12 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:11 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash , Jonathan Cameron Subject: [PATCH v8 03/11] iio: adc: qcom-vadc: move several adc5 functions to common file Date: Fri, 9 Oct 2020 18:44:51 +0300 Message-Id: <20201009154459.106189-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org ADC-TM5 driver will make use of several functions from ADC5 driver. Move them to qcom-vadc-common driver. Signed-off-by: Dmitry Baryshkov Reviewed-by: Jonathan Cameron --- drivers/iio/adc/qcom-spmi-adc5.c | 75 +++--------------------------- drivers/iio/adc/qcom-vadc-common.c | 68 ++++++++++++++++++++++++++- drivers/iio/adc/qcom-vadc-common.h | 10 +++- 3 files changed, 82 insertions(+), 71 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index c10aa28be70a..c2da8f068b87 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -154,18 +154,6 @@ struct adc5_chip { const struct adc5_data *data; }; -static const struct vadc_prescale_ratio adc5_prescale_ratios[] = { - {.num = 1, .den = 1}, - {.num = 1, .den = 3}, - {.num = 1, .den = 4}, - {.num = 1, .den = 6}, - {.num = 1, .den = 20}, - {.num = 1, .den = 8}, - {.num = 10, .den = 81}, - {.num = 1, .den = 10}, - {.num = 1, .den = 16} -}; - static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len) { return regmap_bulk_read(adc->regmap, adc->base + offset, data, len); @@ -181,55 +169,6 @@ static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val) return regmap_update_bits(adc->regmap, adc->base + offset, mask, val); } -static int adc5_prescaling_from_dt(u32 num, u32 den) -{ - unsigned int pre; - - for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++) - if (adc5_prescale_ratios[pre].num == num && - adc5_prescale_ratios[pre].den == den) - break; - - if (pre == ARRAY_SIZE(adc5_prescale_ratios)) - return -EINVAL; - - return pre; -} - -static int adc5_hw_settle_time_from_dt(u32 value, - const unsigned int *hw_settle) -{ - unsigned int i; - - for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) { - if (value == hw_settle[i]) - return i; - } - - return -EINVAL; -} - -static int adc5_avg_samples_from_dt(u32 value) -{ - if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX) - return -EINVAL; - - return __ffs(value); -} - -static int adc5_decimation_from_dt(u32 value, - const unsigned int *decimation) -{ - unsigned int i; - - for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) { - if (value == decimation[i]) - return i; - } - - return -EINVAL; -} - static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data) { int ret; @@ -511,7 +450,7 @@ static int adc_read_raw_common(struct iio_dev *indio_dev, return ret; ret = qcom_adc5_hw_scale(prop->scale_fn_type, - &adc5_prescale_ratios[prop->prescale], + prop->prescale, adc->data, adc_code_volt, val); if (ret) @@ -717,7 +656,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32(node, "qcom,decimation", &value); if (!ret) { - ret = adc5_decimation_from_dt(value, data->decimation); + ret = qcom_adc5_decimation_from_dt(value, data->decimation); if (ret < 0) { dev_err(dev, "%02x invalid decimation %d\n", chan, value); @@ -730,7 +669,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); if (!ret) { - ret = adc5_prescaling_from_dt(varr[0], varr[1]); + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); if (ret < 0) { dev_err(dev, "%02x invalid pre-scaling <%d %d>\n", chan, varr[0], varr[1]); @@ -759,11 +698,9 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR && dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) || adc->data->info == &adc7_info) - ret = adc5_hw_settle_time_from_dt(value, - data->hw_settle_2); + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2); else - ret = adc5_hw_settle_time_from_dt(value, - data->hw_settle_1); + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); if (ret < 0) { dev_err(dev, "%02x invalid hw-settle-time %d us\n", @@ -777,7 +714,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32(node, "qcom,avg-samples", &value); if (!ret) { - ret = adc5_avg_samples_from_dt(value); + ret = qcom_adc5_avg_samples_from_dt(value); if (ret < 0) { dev_err(dev, "%02x invalid avg-samples %d\n", chan, value); diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index 5113aaa6ba67..d11f3343ad52 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -278,6 +278,18 @@ static const struct vadc_map_pt adcmap7_100k[] = { { 2420, 130048 } }; +static const struct vadc_prescale_ratio adc5_prescale_ratios[] = { + {.num = 1, .den = 1}, + {.num = 1, .den = 3}, + {.num = 1, .den = 4}, + {.num = 1, .den = 6}, + {.num = 1, .den = 20}, + {.num = 1, .den = 8}, + {.num = 10, .den = 81}, + {.num = 1, .den = 10}, + {.num = 1, .den = 16} +}; + static int qcom_vadc_scale_hw_calib_volt( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -647,10 +659,12 @@ int qcom_vadc_scale(enum vadc_scale_fn_type scaletype, EXPORT_SYMBOL(qcom_vadc_scale); int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, - const struct vadc_prescale_ratio *prescale, + unsigned int prescale_ratio, const struct adc5_data *data, u16 adc_code, int *result) { + const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; + if (!(scaletype >= SCALE_HW_CALIB_DEFAULT && scaletype < SCALE_HW_CALIB_INVALID)) { pr_err("Invalid scale type %d\n", scaletype); @@ -662,6 +676,58 @@ int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, } EXPORT_SYMBOL(qcom_adc5_hw_scale); +int qcom_adc5_prescaling_from_dt(u32 num, u32 den) +{ + unsigned int pre; + + for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++) + if (adc5_prescale_ratios[pre].num == num && + adc5_prescale_ratios[pre].den == den) + break; + + if (pre == ARRAY_SIZE(adc5_prescale_ratios)) + return -EINVAL; + + return pre; +} +EXPORT_SYMBOL(qcom_adc5_prescaling_from_dt); + +int qcom_adc5_hw_settle_time_from_dt(u32 value, + const unsigned int *hw_settle) +{ + unsigned int i; + + for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) { + if (value == hw_settle[i]) + return i; + } + + return -EINVAL; +} +EXPORT_SYMBOL(qcom_adc5_hw_settle_time_from_dt); + +int qcom_adc5_avg_samples_from_dt(u32 value) +{ + if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX) + return -EINVAL; + + return __ffs(value); +} +EXPORT_SYMBOL(qcom_adc5_avg_samples_from_dt); + +int qcom_adc5_decimation_from_dt(u32 value, const unsigned int *decimation) +{ + unsigned int i; + + for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) { + if (value == decimation[i]) + return i; + } + + return -EINVAL; +} +EXPORT_SYMBOL(qcom_adc5_decimation_from_dt); + int qcom_vadc_decimation_from_dt(u32 value) { if (!is_power_of_2(value) || value < VADC_DECIMATION_MIN || diff --git a/drivers/iio/adc/qcom-vadc-common.h b/drivers/iio/adc/qcom-vadc-common.h index 17b2fc4d8bf2..7e5f6428e311 100644 --- a/drivers/iio/adc/qcom-vadc-common.h +++ b/drivers/iio/adc/qcom-vadc-common.h @@ -168,10 +168,18 @@ struct qcom_adc5_scale_type { }; int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, - const struct vadc_prescale_ratio *prescale, + unsigned int prescale_ratio, const struct adc5_data *data, u16 adc_code, int *result_mdec); +int qcom_adc5_prescaling_from_dt(u32 num, u32 den); + +int qcom_adc5_hw_settle_time_from_dt(u32 value, const unsigned int *hw_settle); + +int qcom_adc5_avg_samples_from_dt(u32 value); + +int qcom_adc5_decimation_from_dt(u32 value, const unsigned int *decimation); + int qcom_vadc_decimation_from_dt(u32 value); #endif /* QCOM_VADC_COMMON_H */ From patchwork Fri Oct 9 15:44:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20809C2D0A3 for ; Fri, 9 Oct 2020 15:45:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D9D4E222E7 for ; Fri, 9 Oct 2020 15:45:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="a/NyN1qB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389444AbgJIPpS (ORCPT ); Fri, 9 Oct 2020 11:45:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389224AbgJIPpQ (ORCPT ); Fri, 9 Oct 2020 11:45:16 -0400 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6604FC0613D2 for ; Fri, 9 Oct 2020 08:45:16 -0700 (PDT) Received: by mail-lf1-x144.google.com with SMTP id a7so10071050lfk.9 for ; Fri, 09 Oct 2020 08:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SyrNRlrzgocwFtm4m1D+vgyjZWlJZcz7p/Dz+/oWD3I=; b=a/NyN1qBHmwcjyJPMEHdonVDKXS7DWlZT4d2U6JHV1IpNhHPzldV8MlqOoalcSg1o7 wP7ZM2ZjDX2xuQQPZ6tiOoC1DMuDODzVvubHE4+UiiVYa+Z4KoF0dueQcfjClCvF8htV RT3cQjm/revmjP/04IigW/3kt9Emqc4r6TwrviAbLEnT89/+JGBOWGIWydBCiwZxlD4s fuCdLoaEqRWPJymODD3VMw6Lg32WofShzxPapIcIAbNp9kmmc008k7iCj1ArU1tW7ISb S9ZnYEAY9T8VQmU867y1Cgr3VA2jF9w8w//KbalsQV29ed9WUH3ZCG+5kykuJR/Ws/GY beaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SyrNRlrzgocwFtm4m1D+vgyjZWlJZcz7p/Dz+/oWD3I=; b=l8ePQ4MsGLEFGsQIwtU+vXjK3nTRntWtKWA8Nqtrx8C48suwEF6NzXN3X7h8nQu8hU wghzrtGJvXZPQfDopNmgEdcW5aAPxSTfcWQrTgYYRAfQltIv3ePscPuXXy0FyvdC7Rg5 layUfjbsFvFXZptWl7jZA/W4ZdI5ce/+4hG2KLHsbQl0xEu4vLRQ46+rTjsEjTgP3a9m uXwv8ahBgQbq7rcdSV/UsgcM6AkPeTEzsSTe0e9oX0/SiqdLrt0wysim6Flkf6ybAn98 ZIevHxrk4vwFDHr1OomprLVcBIinR9PmjQmudlkvBD+hHOptlzMoqr4bQs8QDkA5MCpX hIqA== X-Gm-Message-State: AOAM530J1sLajme1mUuOrs/UQL4bVtxGRhD3HZyyx6+G3DCh5yyNZcYF mo75Q8b782S0mlC4NxfrY5mZpA== X-Google-Smtp-Source: ABdhPJxxrCCHXMIr9nzhNuBFrehzppK5IHHmaW65LXYkXPafToY0k0uv9q5i+ToAbCEPA0OZfWUAKw== X-Received: by 2002:a05:6512:1182:: with SMTP id g2mr2033086lfr.198.1602258314846; Fri, 09 Oct 2020 08:45:14 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:14 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash , Jonathan Cameron Subject: [PATCH v8 04/11] iio: adc: qcom-vadc-common: use fixp_linear_interpolate Date: Fri, 9 Oct 2020 18:44:52 +0300 Message-Id: <20201009154459.106189-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use new function fixp_linear_interpolate() instead of hand-coding the linear interpolation. Signed-off-by: Dmitry Baryshkov Reviewed-by: Jonathan Cameron --- drivers/iio/adc/qcom-vadc-common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index d11f3343ad52..40d77b3af1bb 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -368,10 +369,9 @@ static int qcom_vadc_map_voltage_temp(const struct vadc_map_pt *pts, } else { /* result is between search_index and search_index-1 */ /* interpolate linearly */ - *output = (((s32)((pts[i].y - pts[i - 1].y) * - (input - pts[i - 1].x)) / - (pts[i].x - pts[i - 1].x)) + - pts[i - 1].y); + *output = fixp_linear_interpolate(pts[i - 1].x, pts[i - 1].y, + pts[i].x, pts[i].y, + input); } return 0; From patchwork Fri Oct 9 15:44:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E4C0C433E7 for ; Fri, 9 Oct 2020 15:45:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F22B4222D9 for ; Fri, 9 Oct 2020 15:45:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yqYEPrXt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389355AbgJIPpV (ORCPT ); Fri, 9 Oct 2020 11:45:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389448AbgJIPpT (ORCPT ); Fri, 9 Oct 2020 11:45:19 -0400 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB96DC0613D8 for ; Fri, 9 Oct 2020 08:45:18 -0700 (PDT) Received: by mail-lf1-x144.google.com with SMTP id j22so5622758lfe.10 for ; Fri, 09 Oct 2020 08:45:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ppiJR77c+oyF2YPqQViuqav70ajnTqRX4XIvZy2HLv8=; b=yqYEPrXtJyHyKi78NpIfgz5NJR/HgrPDcP6uMGuIC4u0TUtMT4AA7NoczlaHwwX7B+ pYJkQ5KsqWfwbWrk2k8FosS4kEM3ogb1vLag84mjjvdf0z1htGRt/g+DqFiK4WHjIThJ StqYkJTnYYV/14APbiQylu0L9ucP1PA079pi9rF4qfixfaXbwgNvTpJ7zz2duL8pRkSn vcnc7ohe5rh7HbDCDZ3mO/5NvgFmKdA68ASpGulzI19MGJKWU2jPpCYzQIBAZPhM69yD CtQwCTD/ST2FPLV4qfVyiKgPntjmK2Z4zWtlzKFYOKZkdn0Ww5yb5A+/3NbM+lSyfMHM Fdzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ppiJR77c+oyF2YPqQViuqav70ajnTqRX4XIvZy2HLv8=; b=K+YzxltigKYIoF2+vDCqjcMPCX8G66FKYmzzlMmsjcync/QyegizO7Tr1tSUxR2mVN YuGmMQJrk+vxA1WJH9aoozEmGNr+kQtAPsM6dkSb3Zvu7PQEcBMjJwbDCyR+qBdnSpfq vWyeO779kf2T3pw+htkxvx0rtS0YobQw9sV6rkjHsgk2I6GBZHR4ZvDB1mWQPvMSKez7 2xLSY2ZY0o8sB5B8QZcIubMDayXHOJrxmPlzvov6Xo6mOvYqCR1JPQFlLias2vFANAHU AW9HcDZvVFzTUhXb4Cyw3J4IBVlbQjsIySI+Msxfu5T1ZNzPVrSp6mI+VT4yRLw040lY wDWA== X-Gm-Message-State: AOAM533tEUj6ugiKtSbzCtB1Q8SqlxCXrppMioX2TFv6U6xIAC/xj5q7 9IdaxEajKu6MsSAo/U6unVIJ2A== X-Google-Smtp-Source: ABdhPJzv6xde0hahyKDw5usEElwUcSIYhD7oBaPoeyTWik0BrSxwu6tuUQAYfGKITywwCTiMOdhtfw== X-Received: by 2002:a19:f245:: with SMTP id d5mr4100476lfk.97.1602258317288; Fri, 09 Oct 2020 08:45:17 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:16 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash Subject: [PATCH v8 05/11] iio: adc: move qcom-vadc-common.h to include dir Date: Fri, 9 Oct 2020 18:44:53 +0300 Message-Id: <20201009154459.106189-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcom-vadc-common module will be used by ADC thermal monitoring driver, so move it to global include dir. Signed-off-by: Dmitry Baryshkov --- drivers/iio/adc/qcom-pm8xxx-xoadc.c | 3 +-- drivers/iio/adc/qcom-spmi-adc5.c | 2 +- drivers/iio/adc/qcom-spmi-vadc.c | 3 +-- drivers/iio/adc/qcom-vadc-common.c | 3 +-- {drivers => include/linux}/iio/adc/qcom-vadc-common.h | 2 ++ 5 files changed, 6 insertions(+), 7 deletions(-) rename {drivers => include/linux}/iio/adc/qcom-vadc-common.h (99%) diff --git a/drivers/iio/adc/qcom-pm8xxx-xoadc.c b/drivers/iio/adc/qcom-pm8xxx-xoadc.c index 7e108da7d255..0610bf254771 100644 --- a/drivers/iio/adc/qcom-pm8xxx-xoadc.c +++ b/drivers/iio/adc/qcom-pm8xxx-xoadc.c @@ -10,6 +10,7 @@ * Author: Linus Walleij */ +#include #include #include #include @@ -21,8 +22,6 @@ #include #include -#include "qcom-vadc-common.h" - /* * Definitions for the "user processor" registers lifted from the v3.4 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC: diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index c2da8f068b87..b10a0fcf09dc 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -19,7 +20,6 @@ #include #include -#include "qcom-vadc-common.h" #define ADC5_USR_REVISION1 0x0 #define ADC5_USR_STATUS1 0x8 diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c index b0388f8a69f4..05ff948372b3 100644 --- a/drivers/iio/adc/qcom-spmi-vadc.c +++ b/drivers/iio/adc/qcom-spmi-vadc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -20,8 +21,6 @@ #include -#include "qcom-vadc-common.h" - /* VADC register and bit definitions */ #define VADC_REVISION2 0x1 #define VADC_REVISION2_SUPPORTED_VADC 1 diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index 40d77b3af1bb..ee94774b72e6 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -3,14 +3,13 @@ #include #include #include +#include #include #include #include #include #include -#include "qcom-vadc-common.h" - /* Voltage to temperature */ static const struct vadc_map_pt adcmap_100k_104ef_104fb[] = { {1758, -40}, diff --git a/drivers/iio/adc/qcom-vadc-common.h b/include/linux/iio/adc/qcom-vadc-common.h similarity index 99% rename from drivers/iio/adc/qcom-vadc-common.h rename to include/linux/iio/adc/qcom-vadc-common.h index 7e5f6428e311..03a9119edc71 100644 --- a/drivers/iio/adc/qcom-vadc-common.h +++ b/include/linux/iio/adc/qcom-vadc-common.h @@ -6,6 +6,8 @@ #ifndef QCOM_VADC_COMMON_H #define QCOM_VADC_COMMON_H +#include + #define VADC_CONV_TIME_MIN_US 2000 #define VADC_CONV_TIME_MAX_US 2100 From patchwork Fri Oct 9 15:44:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 285087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66533C35265 for ; Fri, 9 Oct 2020 15:45:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0951422365 for ; Fri, 9 Oct 2020 15:45:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yivuL4J5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389447AbgJIPpX (ORCPT ); Fri, 9 Oct 2020 11:45:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389442AbgJIPpV (ORCPT ); Fri, 9 Oct 2020 11:45:21 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 895EBC0613D6 for ; Fri, 9 Oct 2020 08:45:21 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id h20so10053136lji.9 for ; Fri, 09 Oct 2020 08:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rs/lmUbls2+lr33cOkF5wTnejEIFAqou3Xfg7WIvltg=; b=yivuL4J53m688pGDgg3WPhODsMl4KQrCp23+POmiBRLuXeQtDcUSlZ92XvU590BQT7 P+frwWWKTNat2ORIVRl6EzSIO4yV1kKedUzc/WQtJNNc4VjUJgdCqt0Z+lsflrAmoeaz 5GQ2j6Qrwh5npSETINzGpD3DBNUQZW3kodv/HgzECl5kCbkMlABTX6WdXIC1PQMYnu9A nEQcM45a98V0oH+iJl3XsdbesVmFeawRCJA4SKbfMyFsI6o6UsuzOc5TArbbVoWASB+j l1+iaFVmY2OS0FJ+zk7JqybA/GxV6e1O/oBh1zsbJsT2HFWYfuf5tRW15dV0RKlMpsoR tnNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rs/lmUbls2+lr33cOkF5wTnejEIFAqou3Xfg7WIvltg=; b=qc5SxjWAK8DaDdFu9HY2ma52nyvGLKreQuEPFJXP0U8XiTO3eSYrlFJDbsSOuBdXAr G/tGKlV1cc5G9Cgp2YZHX09ANioj352jwwo1x0JT+9AcF9lq0qVHxbtuf3+d3R2FmJlF IHSacNV80tVJP7MVL6/VV1WvE3DwaRG1cEz+pH0ylfNnnP3AQAcpbxbbVLmYR80+yqPG iDr7iY+jnlNNKwMEY64ORW5wfsk8gLrlAyK+gO+o9PHE9KO465/W4VkTFARePczQWvBd EOmPvHsjVN3QWswGj6OXWtTfqphI+xVG1fE1pc/VHrUJ8TDAThULpe+l91YW/heejWxl b4fw== X-Gm-Message-State: AOAM531ExtsIGktA0MugsJ2avT9+jCIeLG1brklJxjvM2LDslYfG/zWS LigTKK8MmY8V0NaPn0oACO1QbA== X-Google-Smtp-Source: ABdhPJz+94jCawC9y58GCaJphN4vUGBvFUR/I+I+DN1AfSLD6zRoUPSbXJ5qDQIiKn3/vjYMpY1zrg== X-Received: by 2002:a2e:3806:: with SMTP id f6mr5315337lja.93.1602258319918; Fri, 09 Oct 2020 08:45:19 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:19 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash , Jonathan Cameron Subject: [PATCH v8 06/11] iio: adc: qcom-spmi-adc5: use of_device_get_match_data Date: Fri, 9 Oct 2020 18:44:54 +0300 Message-Id: <20201009154459.106189-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use of_device_get_match_data() instead of hand-coding it manually. Signed-off-by: Dmitry Baryshkov Acked-by: Jonathan Cameron Acked-by: Manivannan Sadhasivam --- drivers/iio/adc/qcom-spmi-adc5.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index b10a0fcf09dc..87438d1e5c0b 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -807,8 +808,6 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) struct adc5_channel_prop prop, *chan_props; struct device_node *child; unsigned int index = 0; - const struct of_device_id *id; - const struct adc5_data *data; int ret; adc->nchannels = of_get_available_child_count(node); @@ -827,24 +826,21 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) chan_props = adc->chan_props; iio_chan = adc->iio_chans; - id = of_match_node(adc5_match_table, node); - if (id) - data = id->data; - else - data = &adc5_data_pmic; - adc->data = data; + adc->data = of_device_get_match_data(adc->dev); + if (!adc->data) + adc->data = &adc5_data_pmic; for_each_available_child_of_node(node, child) { - ret = adc5_get_dt_channel_data(adc, &prop, child, data); + ret = adc5_get_dt_channel_data(adc, &prop, child, adc->data); if (ret) { of_node_put(child); return ret; } prop.scale_fn_type = - data->adc_chans[prop.channel].scale_fn_type; + adc->data->adc_chans[prop.channel].scale_fn_type; *chan_props = prop; - adc_chan = &data->adc_chans[prop.channel]; + adc_chan = &adc->data->adc_chans[prop.channel]; iio_chan->channel = prop.channel; iio_chan->datasheet_name = prop.datasheet_name; From patchwork Fri Oct 9 15:44:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 285086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B45C5C433DF for ; Fri, 9 Oct 2020 15:45:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F802222C3 for ; Fri, 9 Oct 2020 15:45:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QQ8PPP7Y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389458AbgJIPp0 (ORCPT ); Fri, 9 Oct 2020 11:45:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389454AbgJIPp0 (ORCPT ); Fri, 9 Oct 2020 11:45:26 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A407AC0613D5 for ; Fri, 9 Oct 2020 08:45:25 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id p15so10054839ljj.8 for ; Fri, 09 Oct 2020 08:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T0dKj6g81Qnwj432BHav6MjrRFfi+Md37xffdodCkkE=; b=QQ8PPP7YlO0/UHr8jlsho9AweoMKViXRz4pTkwW3SQEUjoeFkUOxIDdg/IgaWdzH+S rcavuFiKA0oY/ZXTGUa17BQlobuM96TWx9uzC4NRKcvS74imqyBOceLTa+fQNTTanZMw mSI4LlNoueyl3UwjM3odRql8CSWc13kc6AJHv5l/FBUY4HFOF0uN1D3iJrgaydgpksZj IpjdmPqLCpNCDabgwbHVpsDDbeIVofaBskLzWKjAt27QqT9ZRsHHOzcUYSQDbRPs2akP oC0700AtbNXEmGrlYd0TBCfdvgIEtBfGcdwzZ78pPZnmMV4X3qs38hOVyUnTAaEprRB5 3rVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T0dKj6g81Qnwj432BHav6MjrRFfi+Md37xffdodCkkE=; b=JJE6zxZ61E50oJLEjMWnxdju1fLtMRxMk3AXhWb4YKLVuyU73eo2blCM1Xp9vGCR5V wkwAZPldARnac19/+xsObYVGD7XwhOXl3hqoR71YM27sBhbZZqDymBnN69a5QTizqukL Mz+7bf2817uX64FsTF+39H+cXLwBYLDVyXGyyXjfgxrTm39bFcsJQtLlHrekuOCrebOR JgglZKDnux+4lGeXXdetZEJFsnEeYSb10mddn9IW2JdlE0hRFVmV159vfwzNktsMq5vn VJZTxRINjhhHLoK4JGeChQnblW+On0IZ6kyAVLVICi+/Uf7o/pd6NgeBg04bdupAYgSr gTlQ== X-Gm-Message-State: AOAM531ztXTCC4MnJy/Qz7T+ID5VY4+w0q4fJvlN2HaDGaa9/ALPKFT0 MkDTqd59eMsj/thTJx3pumqUcQ== X-Google-Smtp-Source: ABdhPJw+ot79cgJnGBKDsh9dy9B+mgAcw23iJcEsnl0m6Km99RANhtxqLrcBDCakHdhI/w7B3yjBvg== X-Received: by 2002:a2e:7c09:: with SMTP id x9mr5102211ljc.192.1602258323973; Fri, 09 Oct 2020 08:45:23 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:22 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash , Jonathan Cameron Subject: [PATCH v8 07/11] iio: provide of_iio_channel_get_by_name() and devm_ version it Date: Fri, 9 Oct 2020 18:44:55 +0300 Message-Id: <20201009154459.106189-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There might be cases when the IIO channel is attached to the device subnode instead of being attached to the main device node. Allow drivers to query IIO channels by using device tree nodes. Signed-off-by: Dmitry Baryshkov Reviewed-by: Jonathan Cameron --- drivers/iio/inkern.c | 34 ++++++++++++++++++++++++++-------- include/linux/iio/consumer.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 8 deletions(-) diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c index ede99e0d5371..8ff0ac472de3 100644 --- a/drivers/iio/inkern.c +++ b/drivers/iio/inkern.c @@ -180,8 +180,8 @@ static struct iio_channel *of_iio_channel_get(struct device_node *np, int index) return ERR_PTR(err); } -static struct iio_channel *of_iio_channel_get_by_name(struct device_node *np, - const char *name) +struct iio_channel *of_iio_channel_get_by_name(struct device_node *np, + const char *name) { struct iio_channel *chan = NULL; @@ -219,6 +219,7 @@ static struct iio_channel *of_iio_channel_get_by_name(struct device_node *np, return chan; } +EXPORT_SYMBOL_GPL(of_iio_channel_get_by_name); static struct iio_channel *of_iio_channel_get_all(struct device *dev) { @@ -261,12 +262,6 @@ static struct iio_channel *of_iio_channel_get_all(struct device *dev) #else /* CONFIG_OF */ -static inline struct iio_channel * -of_iio_channel_get_by_name(struct device_node *np, const char *name) -{ - return NULL; -} - static inline struct iio_channel *of_iio_channel_get_all(struct device *dev) { return NULL; @@ -382,6 +377,29 @@ struct iio_channel *devm_iio_channel_get(struct device *dev, } EXPORT_SYMBOL_GPL(devm_iio_channel_get); +struct iio_channel *devm_of_iio_channel_get_by_name(struct device *dev, + struct device_node *np, + const char *channel_name) +{ + struct iio_channel **ptr, *channel; + + ptr = devres_alloc(devm_iio_channel_free, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + channel = of_iio_channel_get_by_name(np, channel_name); + if (IS_ERR(channel)) { + devres_free(ptr); + return channel; + } + + *ptr = channel; + devres_add(dev, ptr); + + return channel; +} +EXPORT_SYMBOL_GPL(devm_of_iio_channel_get_by_name); + struct iio_channel *iio_channel_get_all(struct device *dev) { const char *name; diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h index c4118dcb8e05..0a90ba8fa1bb 100644 --- a/include/linux/iio/consumer.h +++ b/include/linux/iio/consumer.h @@ -13,6 +13,7 @@ struct iio_dev; struct iio_chan_spec; struct device; +struct device_node; /** * struct iio_channel - everything needed for a consumer to use a channel @@ -97,6 +98,41 @@ void iio_channel_release_all(struct iio_channel *chan); */ struct iio_channel *devm_iio_channel_get_all(struct device *dev); +/** + * of_iio_channel_get_by_name() - get description of all that is needed to access channel. + * @np: Pointer to consumer device tree node + * @consumer_channel: Unique name to identify the channel on the consumer + * side. This typically describes the channels use within + * the consumer. E.g. 'battery_voltage' + */ +#ifdef CONFIG_OF +struct iio_channel *of_iio_channel_get_by_name(struct device_node *np, const char *name); +#else +static inline struct iio_channel * +of_iio_channel_get_by_name(struct device_node *np, const char *name) +{ + return NULL; +} +#endif + +/** + * devm_of_iio_channel_get_by_name() - Resource managed version of of_iio_channel_get_by_name(). + * @dev: Pointer to consumer device. + * @np: Pointer to consumer device tree node + * @consumer_channel: Unique name to identify the channel on the consumer + * side. This typically describes the channels use within + * the consumer. E.g. 'battery_voltage' + * + * Returns a pointer to negative errno if it is not able to get the iio channel + * otherwise returns valid pointer for iio channel. + * + * The allocated iio channel is automatically released when the device is + * unbound. + */ +struct iio_channel *devm_of_iio_channel_get_by_name(struct device *dev, + struct device_node *np, + const char *consumer_channel); + struct iio_cb_buffer; /** * iio_channel_get_all_cb() - register callback for triggered capture From patchwork Fri Oct 9 15:44:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E74EC2D0A4 for ; Fri, 9 Oct 2020 15:45:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12789222C2 for ; Fri, 9 Oct 2020 15:45:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="gmSv64Oh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389454AbgJIPp3 (ORCPT ); Fri, 9 Oct 2020 11:45:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389417AbgJIPp3 (ORCPT ); Fri, 9 Oct 2020 11:45:29 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97ECCC0613D6 for ; Fri, 9 Oct 2020 08:45:28 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id h6so11179436lfj.3 for ; Fri, 09 Oct 2020 08:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wfcq4WlxdUw+aTIQdd++nA2qY5PRN6cullgg/x9OXoE=; b=gmSv64OhMxwPTpvgr23ggvLXHV/aS9+HY/QsAL77dHFv/6UwXSyrrRP7sjPF+U4QOU dGlrKTpqHMH5QhCEpRCVwQHa64BwtPZhI3mzrucNlryIqWosvW0HTw0ihfFYJQ8jyknG HqTA8powBMsYUZ94ixaoN90nkv1wh0rpzXSiQy6DJLmyclOW/GCL7LGr5QN6RFWhdG8G 5kas+zfvc5RavWCx7tN0w7y39YgSkfibuL60/HXEVZZuLFsjnBZn+nQ/PwfsFSug3c/D +sVCw2HkpMVfReOvvO54twOEGo6JfnuIIc5aKY4GBE8vEn9nwvU6Whws/bA01199U1Ro mkYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wfcq4WlxdUw+aTIQdd++nA2qY5PRN6cullgg/x9OXoE=; b=Zd0x5UYS750IAUAoMupeP170I8gTCLk3MCMlfwbfQ8vMbSTyJGzkwoh5kMxlMsDtZU 8LFP/cvPsm/swUSdOxfuz3K0Jxy4rYpEbUWKUpZy6HpodM3ZveKs8MVmolQS9E48+rpT fKccAWnDHsYyQExNmp49b2xyeVKs6kP2X2SfLtRzndmvObyzJHiMfNGOJiLmU9weQnFj h1zVrh5imk7otN5o/oBLO+9UDRWieQwyaorCo5u+Mq747hdvMy66Y7ssNySSOu8c5RS5 30DVGmLqnPPIpPI7tPj+J5dZJr5uUuOEqDWNWPrBHU/U54PnA+wlFrrhjVNggYgC7jwk UX+w== X-Gm-Message-State: AOAM530C3XicJvH8u+VEnvEA6A5/0kbeqlc/jG0JoluCp1yyVs6syL0W MPEo8mttHd39FHYhRsbrpfCoMA== X-Google-Smtp-Source: ABdhPJxy+i63LFufwl1H7n0/0UU/TKcAIhZuYzMUvkhjNJqukpqklYOL7mOLdVEncNeYMnMu72HzKA== X-Received: by 2002:a19:8ad4:: with SMTP id m203mr4987329lfd.183.1602258326765; Fri, 09 Oct 2020 08:45:26 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:26 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash Subject: [PATCH v8 08/11] thermal: qcom: add support for adc-tm5 PMIC thermal monitor Date: Fri, 9 Oct 2020 18:44:56 +0300 Message-Id: <20201009154459.106189-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Thermal Monitoring part of PMIC5. This part is closely coupled with ADC, using it's channels directly. ADC-TM support generating interrupts on ADC value crossing low or high voltage bounds, which is used to support thermal trip points. Signed-off-by: Dmitry Baryshkov --- drivers/iio/adc/qcom-vadc-common.c | 62 +++ drivers/thermal/qcom/Kconfig | 11 + drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-adc-tm5.c | 619 +++++++++++++++++++++++ include/linux/iio/adc/qcom-vadc-common.h | 3 + 5 files changed, 696 insertions(+) create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5.c diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index ee94774b72e6..8ceefb079712 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -376,6 +376,42 @@ static int qcom_vadc_map_voltage_temp(const struct vadc_map_pt *pts, return 0; } +static s32 qcom_vadc_map_temp_voltage(const struct vadc_map_pt *pts, + u32 tablesize, int input) +{ + bool descending = 1; + u32 i = 0; + + /* Check if table is descending or ascending */ + if (tablesize > 1) { + if (pts[0].y < pts[1].y) + descending = 0; + } + + while (i < tablesize) { + if (descending && pts[i].y < input) { + /* table entry is less than measured*/ + /* value and table is descending, stop */ + break; + } else if ((!descending) && pts[i].y > input) { + /* table entry is greater than measured*/ + /*value and table is ascending, stop */ + break; + } + i++; + } + + if (i == 0) + return pts[0].x; + if (i == tablesize) + return pts[tablesize - 1].x; + + /* result is between search_index and search_index-1 */ + /* interpolate linearly */ + return fixp_linear_interpolate(pts[i - 1].y, pts[i - 1].x, + pts[i].y, pts[i].x, input); +} + static void qcom_vadc_scale_calib(const struct vadc_linear_graph *calib_graph, u16 adc_code, bool absolute, @@ -473,6 +509,19 @@ static int qcom_vadc_scale_chg_temp(const struct vadc_linear_graph *calib_graph, return 0; } +static u16 qcom_vadc_scale_voltage_code(int voltage, + const struct vadc_prescale_ratio *prescale, + const u32 full_scale_code_volt, + unsigned int factor) +{ + s64 volt = voltage, adc_vdd_ref_mv = 1875; + + volt *= prescale->num * factor * full_scale_code_volt; + volt = div64_s64(volt, (s64)prescale->den * adc_vdd_ref_mv * 1000); + + return volt; +} + static int qcom_vadc_scale_code_voltage_factor(u16 adc_code, const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -657,6 +706,19 @@ int qcom_vadc_scale(enum vadc_scale_fn_type scaletype, } EXPORT_SYMBOL(qcom_vadc_scale); +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp) +{ + const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; + s32 voltage; + + voltage = qcom_vadc_map_temp_voltage(adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + temp); + return qcom_vadc_scale_voltage_code(voltage, prescale, full_scale_code_volt, 1000); +} +EXPORT_SYMBOL(qcom_adc_tm5_temp_volt_scale); + int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, unsigned int prescale_ratio, const struct adc5_data *data, diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index aa9c1d80fae4..8d5ac2df26dc 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -10,6 +10,17 @@ config QCOM_TSENS Also able to set threshold temperature for both hot and cold and update when a threshold is reached. +config QCOM_SPMI_ADC_TM5 + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5" + depends on OF && SPMI && IIO + select REGMAP_SPMI + select QCOM_VADC_COMMON + help + This enables the thermal driver for the ADC thermal monitoring + device. It shows up as a thermal zone with multiple trip points. + Thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. + config QCOM_SPMI_TEMP_ALARM tristate "Qualcomm SPMI PMIC Temperature Alarm" depends on OF && SPMI && IIO diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index ec86eef7f6a6..252ea7d9da0b 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o +obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c new file mode 100644 index 000000000000..9e4d5ae5fe33 --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c @@ -0,0 +1,619 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADC5_MAX_CHANNEL 0xc0 +#define ADC_TM5_NUM_CHANNELS 8 + +#define ADC_TM5_STATUS_LOW 0x0a + +#define ADC_TM5_STATUS_HIGH 0x0b + +#define ADC_TM5_NUM_BTM 0x0f + +#define ADC_TM5_ADC_DIG_PARAM 0x42 + +#define ADC_TM5_FAST_AVG_CTL (ADC_TM5_ADC_DIG_PARAM + 1) +#define ADC_TM5_FAST_AVG_EN BIT(7) + +#define ADC_TM5_MEAS_INTERVAL_CTL (ADC_TM5_ADC_DIG_PARAM + 2) +#define ADC_TM5_TIMER1 3 /* 3.9ms */ + +#define ADC_TM5_MEAS_INTERVAL_CTL2 (ADC_TM5_ADC_DIG_PARAM + 3) +#define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0 +#define ADC_TM5_TIMER2 10 /* 1 second */ +#define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf +#define ADC_TM5_TIMER3 4 /* 4 second */ + +#define ADC_TM_EN_CTL1 0x46 +#define ADC_TM_EN BIT(7) +#define ADC_TM_CONV_REQ 0x47 +#define ADC_TM_CONV_REQ_EN BIT(7) + +#define ADC_TM5_M_CHAN_BASE 0x60 + +#define ADC_TM5_M_ADC_CH_SEL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0) +#define ADC_TM5_M_LOW_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1) +#define ADC_TM5_M_LOW_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2) +#define ADC_TM5_M_HIGH_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3) +#define ADC_TM5_M_HIGH_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4) +#define ADC_TM5_M_MEAS_INTERVAL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5) +#define ADC_TM5_M_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6) +#define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK 0xf +#define ADC_TM5_M_CTL_CAL_SEL_MASK 0x30 +#define ADC_TM5_M_CTL_CAL_VAL 0x40 +#define ADC_TM5_M_EN(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7) +#define ADC_TM5_M_MEAS_EN BIT(7) +#define ADC_TM5_M_HIGH_THR_INT_EN BIT(1) +#define ADC_TM5_M_LOW_THR_INT_EN BIT(0) + +enum adc5_timer_select { + ADC5_TIMER_SEL_1 = 0, + ADC5_TIMER_SEL_2, + ADC5_TIMER_SEL_3, + ADC5_TIMER_SEL_NONE, +}; + +struct adc_tm5_data { + const u32 full_scale_code_volt; + unsigned int *decimation; + unsigned int *hw_settle; +}; + +enum adc_tm5_cal_method { + ADC_TM5_NO_CAL = 0, + ADC_TM5_RATIOMETRIC_CAL, + ADC_TM5_ABSOLUTE_CAL +}; + +struct adc_tm5_chip; + +/** + * struct adc_tm5_channel - ADC Thermal Monitoring channel data. + * @channel: channel number. + * @adc_channel: corresponding ADC channel number. + * @cal_method: calibration method. + * @prescale: channel scaling performed on the input signal. + * @hw_settle_time: the time between AMUX being configured and the + * start of conversion. + * @iio: IIO channel instance used by this channel. + * @chip: ADC TM chip instance. + * @tzd: thermal zone device used by this channel. + */ +struct adc_tm5_channel { + unsigned int channel; + unsigned int adc_channel; + enum adc_tm5_cal_method cal_method; + unsigned int prescale; + unsigned int hw_settle_time; + struct iio_channel *iio; + struct adc_tm5_chip *chip; + struct thermal_zone_device *tzd; +}; + +/** + * struct adc_tm5_chip - ADC Thermal Monitoring properties + * @regmap: SPMI ADC5 Thermal Monitoring peripheral register map field. + * @dev: SPMI ADC5 device. + * @data: software configuration data. + * @channels: array of ADC TM channel data. + * @nchannels: amount of channels defined/allocated + * @decimation: sampling rate supported for the channel. + * @avg_samples: ability to provide single result from the ADC + * that is an average of multiple measurements. + * @base: base address of TM registers. + */ +struct adc_tm5_chip { + struct regmap *regmap; + struct device *dev; + const struct adc_tm5_data *data; + struct adc_tm5_channel *channels; + unsigned int nchannels; + unsigned int decimation; + unsigned int avg_samples; + u16 base; +}; + +static const struct adc_tm5_data adc_tm5_data_pmic = { + .full_scale_code_volt = 0x70e4, + .decimation = (unsigned int []) { 250, 420, 840 }, + .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, + 64000, 128000 }, +}; + +static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val) +{ + return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); +} + +static irqreturn_t adc_tm5_isr(int irq, void *data) +{ + struct adc_tm5_chip *chip = data; + u8 status_low, status_high, ctl; + int ret = 0, i = 0; + + ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low)); + if (unlikely(ret)) { + dev_err(chip->dev, "read status low failed with %d\n", ret); + return IRQ_HANDLED; + } + + ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high)); + if (unlikely(ret)) { + dev_err(chip->dev, "read status high failed with %d\n", ret); + return IRQ_HANDLED; + } + + for (i = 0; i < chip->nchannels; i++) { + bool upper_set = false, lower_set = false; + unsigned int ch = chip->channels[i].channel; + + if (!chip->channels[i].tzd) { + dev_err_once(chip->dev, "thermal device not found\n"); + continue; + } + + ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl)); + if (unlikely(ret)) { + dev_err(chip->dev, "ctl read failed with %d\n", ret); + continue; + } + + if (!(ctl & ADC_TM5_M_MEAS_EN)) + continue; + + lower_set = (status_low & BIT(ch)) && + (ctl & ADC_TM5_M_LOW_THR_INT_EN); + + upper_set = (status_high & BIT(ch)) && + (ctl & ADC_TM5_M_HIGH_THR_INT_EN); + + if (upper_set || lower_set) + thermal_zone_device_update(chip->channels[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } + + return IRQ_HANDLED; +} + +static int adc_tm5_get_temp(void *data, int *temp) +{ + struct adc_tm5_channel *channel = data; + int ret; + + if (!channel || !channel->iio) + return -EINVAL; + + ret = iio_read_channel_processed(channel->iio, temp); + if (ret < 0) + return ret; + + return 0; +} + +static int adc_tm5_disable_channel(struct adc_tm5_channel *channel) +{ + struct adc_tm5_chip *chip = channel->chip; + unsigned int reg = ADC_TM5_M_EN(channel->channel); + + return adc_tm5_reg_update(chip, reg, + ADC_TM5_M_MEAS_EN | + ADC_TM5_M_HIGH_THR_INT_EN | + ADC_TM5_M_LOW_THR_INT_EN, + 0); +} + +static int adc_tm5_enable(struct adc_tm5_chip *chip) +{ + int ret = 0; + u8 data = 0; + + data = ADC_TM_EN; + ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data)); + if (ret < 0) { + pr_err("adc-tm enable failed\n"); + return ret; + } + + data = ADC_TM_CONV_REQ_EN; + ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data)); + if (ret < 0) { + pr_err("adc-tm request conversion failed\n"); + return ret; + } + + return ret; +} + +static int adc_tm5_configure(struct adc_tm5_channel *channel, int low_temp, int high_temp) +{ + struct adc_tm5_chip *chip = channel->chip; + u8 buf[8]; + u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel); + int ret = 0; + + ret = adc_tm5_read(chip, reg, buf, sizeof(buf)); + if (ret) { + dev_err(chip->dev, "block read failed with %d\n", ret); + return ret; + } + + /* Update ADC channel select */ + buf[0] = channel->adc_channel; + + /* Warm temperature corresponds to low voltage threshold */ + if (high_temp != INT_MAX) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, high_temp); + + buf[1] = adc_code & 0xff; + buf[2] = adc_code >> 8; + buf[7] |= ADC_TM5_M_LOW_THR_INT_EN; + } else { + buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN; + } + + /* Cool temperature corresponds to high voltage threshold */ + if (low_temp != -INT_MAX) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, low_temp); + + buf[3] = adc_code & 0xff; + buf[4] = adc_code >> 8; + buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN; + } else { + buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN; + } + + /* Update timer select */ + buf[5] = ADC5_TIMER_SEL_2; + + /* Set calibration select, hw_settle delay */ + buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK; + buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time); + buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK; + buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method); + + buf[7] |= ADC_TM5_M_MEAS_EN; + + ret = adc_tm5_write(chip, reg, buf, sizeof(buf)); + if (ret) { + dev_err(chip->dev, "buf write failed\n"); + return ret; + } + + return adc_tm5_enable(chip); +} + +static int adc_tm5_set_trips(void *data, int low_temp, int high_temp) +{ + struct adc_tm5_channel *channel = data; + struct adc_tm5_chip *chip; + int ret; + + if (!channel) + return -EINVAL; + + chip = channel->chip; + dev_dbg(chip->dev, "%d:low_temp(mdegC):%d, high_temp(mdegC):%d\n", + channel->channel, low_temp, high_temp); + + if (high_temp == INT_MAX && low_temp <= -INT_MAX) + ret = adc_tm5_disable_channel(channel); + else + ret = adc_tm5_configure(channel, low_temp, high_temp); + + return ret; +} + +static struct thermal_zone_of_device_ops adc_tm5_ops = { + .get_temp = adc_tm5_get_temp, + .set_trips = adc_tm5_set_trips, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm) +{ + unsigned int i; + struct thermal_zone_device *tzd; + + for (i = 0; i < adc_tm->nchannels; i++) { + adc_tm->channels[i].chip = adc_tm; + + tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev, + adc_tm->channels[i].channel, + &adc_tm->channels[i], + &adc_tm5_ops); + if (IS_ERR(tzd)) { + dev_err(adc_tm->dev, "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), adc_tm->channels[i].channel); + continue; + } + adc_tm->channels[i].tzd = tzd; + } + + return 0; +} + +static int adc_tm5_init(struct adc_tm5_chip *chip) +{ + u8 buf[4], channels_available; + int ret; + unsigned int i; + + ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM, + &channels_available, sizeof(channels_available)); + if (ret) { + dev_err(chip->dev, "read failed for BTM channels\n"); + return ret; + } + + /* Select decimation */ + buf[0] = chip->decimation; + + /* Select number of samples in fast average mode */ + buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; + + /* Select timer1 */ + buf[2] = ADC_TM5_TIMER1; + + /* Select timer2 and timer3 */ + buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) | + FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3); + + ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf)); + if (ret) + dev_err(chip->dev, "block write failed with %d\n", ret); + + for (i = 0; i < chip->nchannels; i++) { + if (chip->channels[i].channel >= channels_available) { + dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); + return -EINVAL; + } + } + + return ret; +} + +static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm, + struct adc_tm5_channel *channel, + struct device_node *node) +{ + const char *name = node->name; + u32 chan, value, varr[2]; + int ret; + struct device *dev = adc_tm->dev; + struct of_phandle_args args; + + ret = of_property_read_u32(node, "reg", &chan); + if (ret) { + dev_err(dev, "%s: invalid channel number (%d)\n", name, ret); + return ret; + } + + if (chan >= ADC_TM5_NUM_CHANNELS) { + dev_err(dev, "%s: invalid channel number %d\n", name, chan); + return -EINVAL; + } + + /* the channel has DT description */ + channel->channel = chan; + + /* + * We are tied to PMIC's ADC controller, which always use single + * argument for channel number. So don't bother parsing + * #io-channel-cells, just enforce cell_count = 1. + */ + ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args); + if (ret < 0) { + dev_err(dev, "%s: invalid ADC channel number %d: %d\n", name, chan, ret); + return ret; + } + of_node_put(args.np); + + if (args.args_count != 1 || args.args[0] >= ADC5_MAX_CHANNEL) { + dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan); + return ret; + } + channel->adc_channel = args.args[0]; + + channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL); + if (IS_ERR(channel->iio)) { + ret = PTR_ERR(channel->iio); + channel->iio = NULL; + if (ret != -EPROBE_DEFER) + dev_err(dev, "%s: error getting channel: %d\n", name, ret); + return ret; + } + + ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); + if (!ret) { + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) { + dev_err(dev, "%s: invalid pre-scaling <%d %d>\n", + name, varr[0], varr[1]); + return ret; + } + channel->prescale = ret; + } else { + /* 1:1 prescale is index 0 */ + channel->prescale = 0; + } + + ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value); + if (!ret) { + ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle); + if (ret < 0) { + dev_err(dev, "%s invalid hw-settle-time-us %d us\n", + name, value); + return ret; + } + channel->hw_settle_time = ret; + } else { + channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; + } + + if (of_property_read_bool(node, "qcom,ratiometric")) + channel->cal_method = ADC_TM5_RATIOMETRIC_CAL; + else + channel->cal_method = ADC_TM5_ABSOLUTE_CAL; + + return 0; +} + +static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node) +{ + struct adc_tm5_channel *channels; + struct device_node *child; + u32 value; + int ret; + struct device *dev = adc_tm->dev; + + adc_tm->nchannels = of_get_available_child_count(node); + if (!adc_tm->nchannels) + return -EINVAL; + + adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels, + sizeof(*adc_tm->channels), GFP_KERNEL); + if (!adc_tm->channels) + return -ENOMEM; + + channels = adc_tm->channels; + + adc_tm->data = of_device_get_match_data(dev); + if (!adc_tm->data) + adc_tm->data = &adc_tm5_data_pmic; + + ret = of_property_read_u32(node, "qcom,decimation", &value); + if (!ret) { + ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); + if (ret < 0) { + dev_err(dev, "invalid decimation %d\n", value); + return ret; + } + adc_tm->decimation = ret; + } else { + adc_tm->decimation = ADC5_DECIMATION_DEFAULT; + } + + ret = of_property_read_u32(node, "qcom,avg-samples", &value); + if (!ret) { + ret = qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) { + dev_err(dev, "invalid avg-samples %d\n", value); + return ret; + } + adc_tm->avg_samples = ret; + } else { + adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES; + } + + for_each_available_child_of_node(node, child) { + ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child); + if (ret) { + of_node_put(child); + return ret; + } + + channels++; + } + + return 0; +} + +static int adc_tm5_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct adc_tm5_chip *adc_tm; + struct regmap *regmap; + int ret, irq; + u32 reg; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + ret = of_property_read_u32(node, "reg", ®); + if (ret) + return ret; + + adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL); + if (!adc_tm) + return -ENOMEM; + + adc_tm->regmap = regmap; + adc_tm->dev = dev; + adc_tm->base = reg; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "get_irq failed: %d\n", irq); + return irq; + } + + ret = adc_tm5_get_dt_data(adc_tm, node); + if (ret) { + dev_err(dev, "get dt data failed: %d\n", ret); + return ret; + } + + ret = adc_tm5_init(adc_tm); + if (ret) { + dev_err(dev, "adc-tm init failed\n"); + return ret; + } + + ret = adc_tm5_register_tzd(adc_tm); + if (ret) { + dev_err(dev, "tzd register failed\n"); + return ret; + } + + return devm_request_threaded_irq(dev, irq, NULL, adc_tm5_isr, + IRQF_ONESHOT, "pm-adc-tm5", adc_tm); +} + +static const struct of_device_id adc_tm5_match_table[] = { + { + .compatible = "qcom,spmi-adc-tm5", + .data = &adc_tm5_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc_tm5_match_table); + +static struct platform_driver adc_tm5_driver = { + .driver = { + .name = "qcom-spmi-adc-tm5", + .of_match_table = adc_tm5_match_table, + }, + .probe = adc_tm5_probe, +}; +module_platform_driver(adc_tm5_driver); + +MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/iio/adc/qcom-vadc-common.h b/include/linux/iio/adc/qcom-vadc-common.h index 03a9119edc71..041d1397995e 100644 --- a/include/linux/iio/adc/qcom-vadc-common.h +++ b/include/linux/iio/adc/qcom-vadc-common.h @@ -174,6 +174,9 @@ int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, const struct adc5_data *data, u16 adc_code, int *result_mdec); +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp); + int qcom_adc5_prescaling_from_dt(u32 num, u32 den); int qcom_adc5_hw_settle_time_from_dt(u32 value, const unsigned int *hw_settle); From patchwork Fri Oct 9 15:44:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 285084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0E7FC04EBE for ; Fri, 9 Oct 2020 15:45:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 52892222D9 for ; Fri, 9 Oct 2020 15:45:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="u69qIxza" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389464AbgJIPpb (ORCPT ); Fri, 9 Oct 2020 11:45:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389366AbgJIPpb (ORCPT ); Fri, 9 Oct 2020 11:45:31 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC227C0613D5 for ; Fri, 9 Oct 2020 08:45:30 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id m16so10068401ljo.6 for ; Fri, 09 Oct 2020 08:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rflyFynNnBW4dG747SrCFXgcIAs909F2gibnTOq3B0k=; b=u69qIxzaLMQ6zrm/tmDcArG2OSScisFcHJ16amWhTL6lmbqg620wkhSPJ1Rey3pQKf mjQ2PlKYpA75GzCj86JuyoOOC3w5r8IxoiVwcD8mjTM26CQpkmUz7fM9lYD06K7x53RX tgs8AW5H6/Dk1MWdfJaBSQBujL03ym3pEhb2Y53GR0th8LNq+zB2OZQ3m8MGiKP7PWKl m4c775q9EFMTkqS0sPKT/ERd80F9kuX51jAWEoqS6gajD/43w2FF5DQ7KbDKMpAPPKWC eyy2uS7TnTnSBhKLBhDSFz6mJK6h4boEQMBxO2R27/5nOYfBqI1IuTigaXzo4eL5bSye oB7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rflyFynNnBW4dG747SrCFXgcIAs909F2gibnTOq3B0k=; b=ei8vSDGBoWaiO5oSPXr2GASlkEIBp6TaN3LNsPJTOKhrXsRNYKVCsTpB5apjpwMHJP onU5FBtn1WfzZAYQj1gv5qyQGO4VmChr0ih0qAy/34oQoXgDgl3+iuzgncGXAotnPZi+ VYk0MMZ98HCqqz0AiSZfP2eaGyvpB6ZGT5XuGfeQNkYjUN5IXnsH5Ez9+tPtzy7jTVTy zawdaucSKwpK0weV+X7fvfHLOkUMxOXlOK6t1Lt8B8MotCEFvHIsL4Zzt/1E0DTxcPE7 dMJSZK68h8Bs6Cgaoz+0530hlpU8zFR8NqlOLxCcUkYN88jLTUUqwThqTYlmuedXzBcm wOkw== X-Gm-Message-State: AOAM532UwfRPNn4MbrWCBGwJlyuYl20UpFvB/SxOt7/DuKzJYTd3Cp6h Ry7G7zVjPh34lek8l2v/40Tu7A== X-Google-Smtp-Source: ABdhPJwZNt9ikpIfbpbi8D6Qq8jF7ekkpIUYrA8SF0v2qg/C6kGNt+B97PgdX3ffLk6aMrSWckkqvg== X-Received: by 2002:a2e:8942:: with SMTP id b2mr5828295ljk.441.1602258329108; Fri, 09 Oct 2020 08:45:29 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash Subject: [PATCH v8 09/11] arm64: dts: qcom: pm8150x: add definitions for adc-tm5 part Date: Fri, 9 Oct 2020 18:44:57 +0300 Message-Id: <20201009154459.106189-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define adc-tm5 thermal monitoring part. Individual channes and thermal zones are to be configured in per-device dts files. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm8150b.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm8150l.dtsi | 10 ++++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 1b6406927509..b1b518c6a2c9 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -97,6 +97,16 @@ die-temp@6 { }; }; + pm8150_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index e112e8876db6..8e2f3250c914 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -95,6 +95,16 @@ chg-temp@9 { }; }; + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm8150b_gpios: gpio@c000 { compatible = "qcom,pm8150b-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 62139538b7d9..9f214ceec2b7 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -89,6 +89,16 @@ die-temp@6 { }; }; + pm8150l_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm8150l_gpios: gpio@c000 { compatible = "qcom,pm8150l-gpio"; reg = <0xc000>; From patchwork Fri Oct 9 15:44:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 285085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92465C2D0A2 for ; Fri, 9 Oct 2020 15:45:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DEDF222EB for ; Fri, 9 Oct 2020 15:45:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OW/J3NuW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389469AbgJIPpe (ORCPT ); Fri, 9 Oct 2020 11:45:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389465AbgJIPpd (ORCPT ); Fri, 9 Oct 2020 11:45:33 -0400 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 218DEC0613D7 for ; Fri, 9 Oct 2020 08:45:33 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id c21so10036062ljn.13 for ; Fri, 09 Oct 2020 08:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IX5J13tHQBhV3OyuAx16FFIRHXqfdlDIoHquJV7x6Go=; b=OW/J3NuWgPhMJqoOfdBVFraYf0bvh6VUfD9NDs0qFesTezLa3BEyOQPDm1pGtDqfhz DSEiT09DGZOIOPqEKK3b9MqufIMif0m9O2l5cMWpWL3ucBxEm6H94Z9Z55IlK54twjTG ctrihc7EcyCpOGY2yWph6/DH6Ej129C5woSLKuyqaz6lngtc2ySk+XsIWBujE/2VPElr t05o0iSxbYO50tvhq2vEyMIJm1Lt0kuZBd1hmc2TWuma4fMmeRifl48Jypjild4tSnO0 JGLcb6Inxn/bpTGUVSowy1gmD8/mOZAqea6rasV0dcad/sREbxOXIjQ/jNu+E1xxloZV o7aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IX5J13tHQBhV3OyuAx16FFIRHXqfdlDIoHquJV7x6Go=; b=rfU0Cnl91L/2nTuqstUpfq+mP09hL1OOZNWZIv570wgAc7eSNScEa0aRLVAMgzABku CecqSvl/QiX/b8E6vC7Wtkum/KxRMxgzqqjgpeSy0NJBmKFakrFk0fhZStBNU+iEjUFx vrM9WteZo3Imfv1RyMGMML3uzbPvpBqU5HgVOtiOmaySYRFmX4/XKhzhYf21QlKlRnQN vS1pfW2f85OzJeHshoMrVeUsNA453D5BYLEakYh1AUl3hSK+ZfwCSWz60it3/UYznpGQ CEjQ5Hgd+dSbwBuIH0gB/TvLsiULPo5bf01SKlG0AVzjLZlTUH0tblSs1xXARD+6JnF1 0+8A== X-Gm-Message-State: AOAM533ne4y3Uj3vqR1efFvp+Pzs7hcFXNuPIxK0SKYfN8SEMNppbPuK 0ofkakyQMdbFJmagvCtkw9H6+w== X-Google-Smtp-Source: ABdhPJyvn95Q+H4xMOp8MLAZtA/DwvP5V5KUYAIXkHEuyG8JrM0WAG/hVq9f+wA8MbcHlFHscr57Dw== X-Received: by 2002:a2e:b557:: with SMTP id a23mr5586986ljn.0.1602258331537; Fri, 09 Oct 2020 08:45:31 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:30 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash Subject: [PATCH v8 10/11] arm64: dts: sm8250-mtp: add thermal zones using pmic's adc-tm5 Date: Fri, 9 Oct 2020 18:44:58 +0300 Message-Id: <20201009154459.106189-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Port thermal zones definitions from msm-4.19 tree. Enable and add channel configuration to PMIC's ADC-TM definitions. Declare thermal zones and respective trip points. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 207 ++++++++++++++++++++++++ 1 file changed, 207 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 98675e1f8204..95050f7d11f2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -24,6 +24,104 @@ chosen { stdout-path = "serial0:115200n8"; }; + thermal-zones { + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -378,6 +476,115 @@ &i2c15 { /* rtc6226 @ 64 */ }; +&pm8150_adc { + xo-therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm1@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc { + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc { + camera-flash-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-msm-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm2@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + skin-therm@1 { + reg = <1>; + io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm1@2 { + reg = <2>; + io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150b_adc_tm { + status = "okay"; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150l_adc_tm { + status = "okay"; + + camera-flash-therm@0 { + reg = <0>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + skin-msm-therm@1 { + reg = <1>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm2@2 { + reg = <2>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Fri Oct 9 15:44:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FEFCC35267 for ; Fri, 9 Oct 2020 15:45:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5240E2231B for ; Fri, 9 Oct 2020 15:45:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="FYuMO7A3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389366AbgJIPpg (ORCPT ); Fri, 9 Oct 2020 11:45:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389465AbgJIPpg (ORCPT ); Fri, 9 Oct 2020 11:45:36 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2DCDC0613D6 for ; Fri, 9 Oct 2020 08:45:35 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id a5so10039519ljj.11 for ; Fri, 09 Oct 2020 08:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IlnfeC5dNMsfRj34KVveDWWiSX6big7HcGo7tOgQ3Ps=; b=FYuMO7A3DbIUdKIEj3Z5e+A49K1QxZbLCxr6PPabiLrGw5/nDSApisnltR25JT3Ykc sdeTALeYSh6X4AssbWwtidJNvm12QReo3k0syA2akf4wthzxGVrQqFHKOO/W+NBk5NNw hbaqWCs+FUZBT0BBaR74Fbt5fDdJMwA95iMoqCVO/9t5xu3PbnXiqZD7uTotXmH7ZlLg 7leA3claJykESJBjzYY5J/CMjTUTffkCu32Po+/Cjo7zxbFK5edg1ffbwT3IEZZ3IzIO QuW6eclxuWiyZbxI5aOELRt6MWwiMBKmaNh62hnOtiPCPBrE1Ofnu/MdfThM/nH/YD4E 5vRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IlnfeC5dNMsfRj34KVveDWWiSX6big7HcGo7tOgQ3Ps=; b=Gw21HegbCgSDhVTlZRsRp7VX7QlpnB1fXK5M57bAZGBw6ouWATyhawnuOoiTkeeHqd AfWxkAouP8oxTcwhOfoBggfCkyIVP3UEKOr/EuRPVwq31R5i7lcOJPqYxUPhNZh45iaP MRoLKJNo79G5Xnisn8s5tSaNRWq1nBEOpGxQl4g6Lz1qaPR+k41EfcdMoa67Y84blMVU qaeM59VrLBjLH3VDi8BGEnQsl9fjMgft0iGMV0eenPdebbLctMXMOtfAZ3wAQM+X421L jUrnTd4+L2TgYfP88qlsE69ZbcWiFTZ/QVkW0wwMPKhJc+1es3v8KPRWID2NMxRj51fJ J24w== X-Gm-Message-State: AOAM530GzMCZrT9bToe+Fycmz4dtAtmBxPm6GnWOmhQYaDJ5yx5sq7oU QW5NfholznokkktBlh60RSe9jw== X-Google-Smtp-Source: ABdhPJy+fa5A6o4fdZFk6brAvTW+lYUg23rpxduo8Uggnk+C6MsN6JBds/yYHfg1uMdkl50I46kI+Q== X-Received: by 2002:a05:651c:1128:: with SMTP id e8mr5802681ljo.436.1602258334086; Fri, 09 Oct 2020 08:45:34 -0700 (PDT) Received: from eriador.lan ([188.162.65.231]) by smtp.gmail.com with ESMTPSA id r4sm1505597lfc.162.2020.10.09.08.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2020 08:45:33 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash Subject: [PATCH v8 11/11] arm64: dts: qrb5165-rb5: port thermal zone definitions Date: Fri, 9 Oct 2020 18:44:59 +0300 Message-Id: <20201009154459.106189-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> References: <20201009154459.106189-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add thermal zones definitions basing on the downstream kernel. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 154 +++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 1528a865f1f8..6cb8688910a2 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -58,6 +58,77 @@ bt { }; + thermal-zones { + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 0>; + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + wifi-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 1>; + trips { + active-config0 { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + conn-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 0>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + pm8150l-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 1>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + }; + vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -412,6 +483,89 @@ &i2c15 { status = "okay"; }; +&pm8150_adc { + xo-therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + wifi-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc { + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc { + skin-msm-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm8150l-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + wifi-therm@1 { + reg = <1>; + io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150b_adc_tm { + status = "okay"; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150l_adc_tm { + status = "okay"; + + skin-msm-therm@0 { + reg = <0>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pm8150l-therm@1 { + reg = <1>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pm8150_gpios { gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; gpio-line-names =