From patchwork Fri Oct 16 09:31:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 287375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EDDBC433E7 for ; Fri, 16 Oct 2020 09:31:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 28F4F20872 for ; Fri, 16 Oct 2020 09:31:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405448AbgJPJb4 (ORCPT ); Fri, 16 Oct 2020 05:31:56 -0400 Received: from mga11.intel.com ([192.55.52.93]:46684 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405206AbgJPJb4 (ORCPT ); Fri, 16 Oct 2020 05:31:56 -0400 IronPort-SDR: 7h7JBdEq58vqZmfXRegkVnGDUa8PiRoTlfn23NEjOYTExpOhTW3w6xu6Ooj1bf5ZXA63J28iD9 xBKfbQlNqa0w== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="163096340" X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="163096340" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2020 02:31:55 -0700 IronPort-SDR: HibhhbAJ2CfLA/Nu/jASRa99n2F1E3aWVCaOBoCUgcjqpzJx+y8g9zYMUJ4Md4f1eRt3SVIPBr mltMQAfCnmGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="300652507" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga007.fm.intel.com with ESMTP; 16 Oct 2020 02:31:52 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Date: Fri, 16 Oct 2020 17:31:34 +0800 Message-Id: <20201016093138.28871-3-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/ Signed-off-by: Ramuthevar Vadivel Murugan --- .../devicetree/bindings/spi/cadence-quadspi.txt | 67 ---------- .../devicetree/bindings/spi/cadence-quadspi.yaml | 148 +++++++++++++++++++++ 2 files changed, 148 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt deleted file mode 100644 index 945be7d5b236..000000000000 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Cadence Quad SPI controller - -Required properties: -- compatible : should be one of the following: - Generic default - "cdns,qspi-nor". - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". -- reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the QSPI Controller data area. -- interrupts : Unit interrupt specifier for the controller interrupt. -- clocks : phandle to the Quad SPI clock. -- cdns,fifo-depth : Size of the data FIFO in words. -- cdns,fifo-width : Bus width of the data FIFO in bytes. -- cdns,trigger-address : 32-bit indirect AHB trigger address. - -Optional properties: -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch - the read data rather than the QSPI clock. Make sure that QSPI return - clock is populated on the board before using this property. - -Optional subnodes: -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -custom properties: -- cdns,read-delay : Delay for read capture logic, in clock cycles -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master - mode chip select outputs are de-asserted between - transactions. -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being - de-activated and the activation of another. -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current - transaction and deasserting the device chip select - (qspi_n_ss_out). -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low - and first bit transfer. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include either "qspi" and/or "qspi-ocp". - -Example: - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,is-decoded-cs; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - - flash0: n25q00@0 { - ... - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml new file mode 100644 index 000000000000..6ed8122a1326 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence Quad SPI controller + +maintainers: + - Vadivel Murugan + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + items: + - const: cdns,qspi-nor + - const: ti,k2g-qspi, cdns,qspi-nor + - const: ti,am654-ospi, cdns,qspi-nor + + description: + Should be one of the above supported compatible strings. + optional properties + "cdns,is-decoded-cs" - Flag to indicate whether decoder is used or not. + "cdns,rclk-en" - Flag to indicate that QSPI return clock is used to latch + the read data rather than the QSPI clock. Make sure that QSPI return + clock is populated on the board before using this property. + + reg: + maxItems: 2 + + description: + Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the QSPI Controller data area. + + interrupts: + maxItems: 1 + description: + Unit interrupt specifier for the controller interrupt. + + clocks: + maxItems: 1 + description: + phandle to the Quad SPI clock. + + cdns,fifo-depth: + description: + Size of the data FIFO in words. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - enum: [ 128, 256 ] + - default: 128 + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bus width of the data FIFO in bytes. + multipleOf: 4 + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 32-bit indirect AHB trigger address. + + resets: + description: + Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + + reset-names: + description: + Must include either "qspi" and/or "qspi-ocp". + +# subnode's properties +patternProperties: + "@[0-9a-f]+$": + type: object + description: + flash device uses the subnodes below defined properties. + + cdns,read-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay for read capture logic, in clock cycles. + + cdns,tshsl-ns: + description: | + Delay in nanoseconds for the length that the master mode chip select + outputs are de-asserted between transactions. + + cdns,tsd2d-ns: + description: | + Delay in nanoseconds between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + description: | + Delay in nanoseconds between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + description: | + Delay in nanoseconds between setting qspi_n_ss_out low and + first bit transfer. + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + - resets + - reset-names + +examples: + - | + qspi: spi@ff705000 { + compatible = "cadence,qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + resets = <&rst 0x1>, <&rst 0x2>; + reset-names = "qspi", "qspi-ocp"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + + }; + +... From patchwork Fri Oct 16 09:31:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 287374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A55B9C433DF for ; Fri, 16 Oct 2020 09:32:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E8CD206ED for ; Fri, 16 Oct 2020 09:32:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405632AbgJPJcF (ORCPT ); Fri, 16 Oct 2020 05:32:05 -0400 Received: from mga06.intel.com ([134.134.136.31]:15842 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405578AbgJPJcF (ORCPT ); Fri, 16 Oct 2020 05:32:05 -0400 IronPort-SDR: eqNAZnWdn4jNonbMS20/OGJxJLKu3PVyffdvGLOUiMerA4dUsrmVJb3Ko2onpHjRDiIqDLWec/ ZfsIwxriyjmg== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="228222250" X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="228222250" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2020 02:32:02 -0700 IronPort-SDR: N6+x7GqTHdWw/hR2rXfmbPOtsdY/3f8IxoDk1fq5+m7DU0HsqAE0aie8wxNeG5xbX4aYggY1+C J0GVmTDYCqaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="357326277" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by FMSMGA003.fm.intel.com with ESMTP; 16 Oct 2020 02:31:56 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v1 3/6] dt-bindings: spi: Add compatible for Intel LGM SoC Date: Fri, 16 Oct 2020 17:31:35 +0800 Message-Id: <20201016093138.28871-4-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add compatible string for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- Documentation/devicetree/bindings/spi/cadence-quadspi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml index 6ed8122a1326..8b1e01159d2d 100644 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -18,6 +18,7 @@ properties: - const: cdns,qspi-nor - const: ti,k2g-qspi, cdns,qspi-nor - const: ti,am654-ospi, cdns,qspi-nor + - const: intel,lgm-qspi, cdns,qspi-nor description: Should be one of the above supported compatible strings. From patchwork Fri Oct 16 09:31:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 287373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA8E8C433DF for ; Fri, 16 Oct 2020 09:32:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8EA21206ED for ; Fri, 16 Oct 2020 09:32:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405764AbgJPJcQ (ORCPT ); Fri, 16 Oct 2020 05:32:16 -0400 Received: from mga07.intel.com ([134.134.136.100]:44810 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405685AbgJPJcO (ORCPT ); Fri, 16 Oct 2020 05:32:14 -0400 IronPort-SDR: v3iy7ApjClUBPxbRgfuVF0SH3NYbxCyBkPDy7TSIABhVrw3eSNWb40au6LAg6bf0fbODlWnAWO XK3mPzW8i0xg== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="230763033" X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="230763033" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2020 02:32:12 -0700 IronPort-SDR: Mp6Tp/RETcAlV94DqN0Aos0Zaq8oC3zpLNY589c/nNqmrGOFmO/hSoZd8NsJSSjHbdFJzrYj5Q LNNcHfajz46g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,382,1596524400"; d="scan'208";a="522175941" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2020 02:32:09 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v1 6/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC Date: Fri, 16 Oct 2020 17:31:38 +0800 Message-Id: <20201016093138.28871-7-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201016093138.28871-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 3d017b484114..3bf6d3697631 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -38,6 +38,7 @@ /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1) struct cqspi_st; @@ -75,6 +76,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + if (!cqspi->use_direct_mode) { + if (of_property_read_u32(np, "num-chipselect", + &cqspi->num_chipselect)) { + dev_err(dev, "couldn't determine number of cs\n"); + return -ENXIO; + } + } + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); @@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = { }; static const struct cqspi_driver_platdata intel_lgm_qspi = { + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT, .quirks = CQSPI_DISABLE_DAC_MODE, };