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[209.132.180.67]) by mx.google.com with ESMTP id r22si5034377pgo.706.2017.11.22.09.07.57; Wed, 22 Nov 2017 09:07:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VEhSI0BJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752055AbdKVRHz (ORCPT + 28 others); Wed, 22 Nov 2017 12:07:55 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:42503 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751796AbdKVRHx (ORCPT ); Wed, 22 Nov 2017 12:07:53 -0500 Received: by mail-wr0-f195.google.com with SMTP id o14so15175693wrf.9 for ; Wed, 22 Nov 2017 09:07:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Qp54BFdBCzBZ7SGgJL60HNSwUjNz9s60Ymc1KvsGmbE=; b=VEhSI0BJAXO/dqnBVafGlptQ1L7Ot8q5C/Yq8pGam65TpS66QoKlW7qboJWSYQ0WWS YzbrF/xIfodpmcHlRmWfReh6e/HJPlCgOvEpEDnvL09ScTScS93cnmWIK8vSV2dwfcsP 3+hoLoFSbuKwwfIrW1xKXdTEYC/O61kLbl7zg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Qp54BFdBCzBZ7SGgJL60HNSwUjNz9s60Ymc1KvsGmbE=; b=VDIxWMtjS7EqOisxGzQV8+oePThw/vKN3El+ouVlv2maEPspKQaUW1UehvSGFyN9lD gWTR5KmuwXwa5/UtQ/tuGrWXxBDTT/ProzCVcxqLZaJTAZmqZ2ZlxI+GMSF8eu5Z0/p5 kmBylRDIq9oauQ/3qLLpj2Vv1OO+RJc5D8gIuTXjwibHHFwhLQeGdsJdG/wmqZ2r0Zu1 UrpX+GxQnvXAPctLYJG61gz6TwOQ5SWCxGx6FKjCWl6b0QM8vsjggqRcyKMwFVelgiT+ zzbu7SqiUTlpl8XRMNWMpP4qfYnTwyVOnp9229Bb+be8D6YmXLLUF5hYZyla8k75tSeo LkGg== X-Gm-Message-State: AJaThX4w7PBRg/6hbfsMtXk5iP9bnNOpj+WvtOPcLqsAlUZkOxXJGRiZ CkSrGnM+wtoO6/SE86lSRr+pZw== X-Received: by 10.223.145.35 with SMTP id j32mr18154324wrj.176.1511370472479; Wed, 22 Nov 2017 09:07:52 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id r14sm7069458wra.71.2017.11.22.09.07.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Nov 2017 09:07:51 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 250EA3E025C; Wed, 22 Nov 2017 17:07:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: julien.thierry@arm.com, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Catalin Marinas , Will Deacon , David Daney , Eric Auger , James Morse , linux-kernel@vger.kernel.org (open list) Subject: [RFC PATCH] kvm: arm64: handle single-step of hyp emulated mmio instructions Date: Wed, 22 Nov 2017 17:07:46 +0000 Message-Id: <20171122170747.12192-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is a fast-path of MMIO emulation inside hyp mode. The handling of single-step is broadly the same as kvm_arm_handle_step_debug() except we just setup ESR/HSR so handle_exit() does the correct thing as we exit. For the case of an emulated illegal access causing an SError we signal to handle_exit() by clearing the DBG_SPSR_SS bit as would have actually happened had the hardware really single-stepped the instruction. [AJB: currently compile tested only] Signed-off-by: Alex Bennée --- arch/arm64/kvm/handle_exit.c | 8 +++++++- arch/arm64/kvm/hyp/switch.c | 37 ++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 8 deletions(-) -- 2.15.0 diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index af1c804742f6..128120f04e0e 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -28,6 +28,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include "trace.h" @@ -242,7 +243,12 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, return 1; case ARM_EXCEPTION_EL1_SERROR: kvm_inject_vabt(vcpu); - return 1; + /* We may still need to return for single-step */ + if (!(*vcpu_cpsr(vcpu) & DBG_SPSR_SS) + && kvm_arm_handle_step_debug(vcpu, run)) + return 0; + else + return 1; case ARM_EXCEPTION_TRAP: return handle_trap_exceptions(vcpu, run); case ARM_EXCEPTION_HYP_GONE: diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 945e79c641c4..a6712f179b52 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -22,6 +22,7 @@ #include #include #include +#include static bool __hyp_text __fpsimd_enabled_nvhe(void) { @@ -263,7 +264,11 @@ static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu) return true; } -static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu) +/* Skip an instruction which has been emulated. Returns true if + * execution can continue or false if we need to exit hyp mode because + * single-step was in effect. + */ +static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu) { *vcpu_pc(vcpu) = read_sysreg_el2(elr); @@ -276,6 +281,14 @@ static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu) } write_sysreg_el2(*vcpu_pc(vcpu), elr); + + if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { + vcpu->arch.fault.esr_el2 = + (ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT) | 0x22; + return false; + } else { + return true; + } } int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) @@ -336,13 +349,21 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) int ret = __vgic_v2_perform_cpuif_access(vcpu); if (ret == 1) { - __skip_instr(vcpu); - goto again; + if (__skip_instr(vcpu)) + goto again; + else + exit_code = ARM_EXCEPTION_TRAP; } if (ret == -1) { - /* Promote an illegal access to an SError */ - __skip_instr(vcpu); + /* Promote an illegal access to an + * SError. If we would be returning + * due to single-step clear the SS + * bit so handle_exit knows what to + * do after dealing with the error. + */ + if (!__skip_instr(vcpu)) + *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS; exit_code = ARM_EXCEPTION_EL1_SERROR; } @@ -357,8 +378,10 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) int ret = __vgic_v3_perform_cpuif_access(vcpu); if (ret == 1) { - __skip_instr(vcpu); - goto again; + if (__skip_instr(vcpu)) + goto again; + else + exit_code = ARM_EXCEPTION_TRAP; } /* 0 falls through to be handled out of EL2 */