From patchwork Fri Mar 3 06:00:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 94825 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp127378qgd; Fri, 3 Mar 2017 01:03:06 -0800 (PST) X-Received: by 10.98.92.4 with SMTP id q4mr2014858pfb.151.1488531786088; Fri, 03 Mar 2017 01:03:06 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w15si4697132pgm.303.2017.03.03.01.03.05; Fri, 03 Mar 2017 01:03:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751897AbdCCJC4 (ORCPT + 25 others); Fri, 3 Mar 2017 04:02:56 -0500 Received: from mail-pf0-f173.google.com ([209.85.192.173]:36713 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751777AbdCCJCr (ORCPT ); Fri, 3 Mar 2017 04:02:47 -0500 Received: by mail-pf0-f173.google.com with SMTP id x66so31536842pfb.3 for ; Fri, 03 Mar 2017 01:02:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/9SCxwGvYuX2uNRqqRcWCvui4Lofol1Xg+PS1JyCUXA=; b=aGNB9nXgqhZkdJCc40TOAQ/aSsi1MKwZ7vJebLfnGkh6BDA6kWAIiRGYcLDD0jsLj4 ascsOdTFDpv1GLRF2Icewv6dmT4Oyoz4GKLf5eDNBWbTcrvGMmBvrF4VWq576Rrgv0PW 8BHv+emcWU8DZ7VLDijw6WXZAsPS8peqV1jF4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/9SCxwGvYuX2uNRqqRcWCvui4Lofol1Xg+PS1JyCUXA=; b=V2HZGKOe6/6wbenDoeQsRNPmNF/FKS8Dg32n5RBM2d73CW1O9kRwtk2zkJ8ecGZL76 fdRLoamwjeSV4Y72++lV6nfFEm10Q8xzi/36vhlZ6aqR+lT4tJdvHXBQ2Ofa9yp54dzq lkM6frNZjxw80dsO3PsZ4rzv8xFtQVh5eSs7FQ7j6l0BsGRXjgR5DzLs/A5MMBQxD2Sd Z4tgBVJR8eyFQO+KCPi/jhXVJxHdlyclSDEhLIU8o//sUqnWBQvdHzmvlMsvQE6bDKu0 reP6X0eYQtf3C/fIcM2jIgjYRHTfICH6koNV3EaSE3BocLNBsM2m5yukJtPTnrFmOy/X Aexw== X-Gm-Message-State: AMke39kuf2/d7O6wKer+M187WckyClQgk2HIctsf8mEhpOkKoTz4D4WSuUcrD8satQZILz9G X-Received: by 10.84.213.137 with SMTP id g9mr1743742pli.114.1488520854787; Thu, 02 Mar 2017 22:00:54 -0800 (PST) Received: from localhost.localdomain (61-216-91-114.HINET-IP.hinet.net. [61.216.91.114]) by smtp.gmail.com with ESMTPSA id s13sm20541405pfk.26.2017.03.02.22.00.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Mar 2017 22:00:53 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Mathieu Poirier , John Stultz , Guodong Xu , Haojian Zhuang , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, mike.leach@linaro.org Cc: Leo Yan Subject: [PATCH v3 4/5] clk: hi6220: add debug APB clock Date: Fri, 3 Mar 2017 14:00:08 +0800 Message-Id: <1488520809-31670-5-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488520809-31670-1-git-send-email-leo.yan@linaro.org> References: <1488520809-31670-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The debug APB clock is absent in hi6220 driver, so this patch is to add support for it. Signed-off-by: Leo Yan --- drivers/clk/hisilicon/clk-hi6220.c | 1 + include/dt-bindings/clock/hi6220-clock.h | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.7.4 Acked-by: Stephen Boyd diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index c0e8e1f..6879c1f 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -134,6 +134,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = { { HI6220_UART4_PCLK, "uart4_pclk", "uart4_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8, 0, }, { HI6220_SPI_CLK, "spi_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9, 0, }, { HI6220_TSENSOR_CLK, "tsensor_clk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, }, + { HI6220_DAPB_CLK, "dapb_clk", "cs_dapb", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 18, 0, }, { HI6220_MMU_CLK, "mmu_clk", "ddrc_axi1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, }, { HI6220_HIFI_SEL, "hifi_sel", "hifi_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0, 0, }, { HI6220_MMC0_SYSPLL, "mmc0_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1, 0, }, diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index 6b03c84..b8ba665 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -124,7 +124,10 @@ #define HI6220_CS_DAPB 57 #define HI6220_CS_ATB_DIV 58 -#define HI6220_SYS_NR_CLKS 59 +/* gate clock */ +#define HI6220_DAPB_CLK 59 + +#define HI6220_SYS_NR_CLKS 60 /* clk in Hi6220 media controller */ /* gate clocks */