From patchwork Fri Dec 1 17:02:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120362 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1389757qgn; Fri, 1 Dec 2017 09:02:36 -0800 (PST) X-Google-Smtp-Source: AGs4zMYrfbI7Nge6XqBh+8WG+wWSVoMr4YtUnpgOG70Ev9wQD2T7yfhlrky6brBuBBl+w2da8UOT X-Received: by 10.99.3.88 with SMTP id 85mr6603446pgd.111.1512147756047; Fri, 01 Dec 2017 09:02:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512147756; cv=none; d=google.com; s=arc-20160816; b=c3kIyL3Z0xWR6NPzadEDsCNMcGEHp1s8VqCYz6OjqfygOi+cKEXDNf5EoKuYSxshA9 wpuMGQkBBex+iB0YMDUDETtGkuvKdzwTJjLNLWbsV7cL16EP/tzrWiTbN9crCfEZskD8 wlmZ4OWic33wlDgD1OzR1cC7bymOEpjg4BNEaAq2KefT7aYoMnp8cvPGsGIrT7wR2le/ G/v9WpvOexvhxljRewXtBue05RCf8Lr6Dbw00DXieU8EDxpjgS3X5Kq9suwsh2ht04JM L4i7KKaRzjVJRbzuo/P5zTzpmlFLeTNgj6Iy5/aqVb0Amvc66nyn+RMRfEhpbzU6VS4e TpKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=zE82+lMa7W1gP3c+4riT4gc5BAemK6rhdR0Rq7j3jPA=; b=BkjGSh4jeqZTGf0XhNAi7QWowu/cZPae5n4nFGKJ0BpgYuhI2gckMzzCpKxR4jl80I l/pQRu24Ugl28r8fr3/+/chXt0LtY8PHkZPo68+WLzzIjUHApnXyJL2V7meMGc6OZWgw rUUKnv7nM0HG0mfrNpu+CMSea8JOhe4JFFryTjWQ3einQ99sXFxKEROP8NveBtMn61B0 TVDhwtT/K+MVh8F7tkGwUk2URgXDgU+0sBTFOpOCDuGjUdxeKFTlwhL2mY3J1SSaYhn0 NbMM+Dkhmm2PrbfPaIVmxxWHWdrwqEStHbwkmkL3pBfS9IWAqTLFnxho7EMy3XSVi3su PlQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FFUDSAI4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q11si5207466pll.373.2017.12.01.09.02.35; Fri, 01 Dec 2017 09:02:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FFUDSAI4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751791AbdLARCd (ORCPT + 28 others); Fri, 1 Dec 2017 12:02:33 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:37795 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751104AbdLARC2 (ORCPT ); Fri, 1 Dec 2017 12:02:28 -0500 Received: by mail-wr0-f193.google.com with SMTP id k61so10803229wrc.4 for ; Fri, 01 Dec 2017 09:02:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zE82+lMa7W1gP3c+4riT4gc5BAemK6rhdR0Rq7j3jPA=; b=FFUDSAI4MVyOLzceA3px0sWPgzeRsp0yyi/9wekx3+QvPLiPOKl6XyJQOS2Lz0TYfi pQV5J7YJLkofBQCX/n0efT6BOhYXiN635w69SyU+dY4wNXXS3v0YKncIls1bgWG6PD64 cVn+p7qjBnzLIFT7HLv6y4uxbkFTZ4FJVzyfg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zE82+lMa7W1gP3c+4riT4gc5BAemK6rhdR0Rq7j3jPA=; b=uelzTNX9hmu/Odwk5OlygDdXxttUlf5BdqXtFDmocmlkzl0xWr4yHIxrTMKxGsVbLL AE74aRPmAiAQ1MFbcMcdNrKtEYeNgdKuzCvT51albAquRqXkWu1LmfQdgvjgcqMdnbDx jOy/59baEDIVcUlXQgm+nZYt30EzSMDqiHZ3XSRlZx0sbSx1OwK74TN+rflel4Tknwf6 yzYGbCk19101RwabpK5uU1VzAKkTZw+YDLejfA8A0L7pk2JVAbbnK0DXdqD2ICPqXp2/ p9Zcw3limYwsuo2rIZsgD8nJX67BALuQz/W7k/+50fKK/bFTyl4m5Rdmyz9Dg91WDCnx q4oQ== X-Gm-Message-State: AJaThX5TQ2iDLAa5OTwjeqq75QG5t4dfNj9Djp98A0adScPJkITdJa1O +HUlB2Uzeqef2qv0XV5iIGExvg== X-Received: by 10.223.195.198 with SMTP id d6mr5819639wrg.100.1512147747459; Fri, 01 Dec 2017 09:02:27 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 2sm1535253wmk.28.2017.12.01.09.02.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Dec 2017 09:02:26 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v10 1/6] mailbox: qcom: Convert APCS IPC driver to use regmap Date: Fri, 1 Dec 2017 19:02:19 +0200 Message-Id: <20171201170224.25053-2-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org> References: <20171201170224.25053-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This hardware block provides more functionalities that just IPC. Convert it to regmap to allow other child platform devices to use the same regmap. Signed-off-by: Georgi Djakov Acked-by: Bjorn Andersson --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9924c6d7f05d..ab344bc6fa63 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #define QCOM_APCS_IPC_BITS 32 @@ -26,19 +27,25 @@ struct qcom_apcs_ipc { struct mbox_controller mbox; struct mbox_chan mbox_chans[QCOM_APCS_IPC_BITS]; - void __iomem *reg; + struct regmap *regmap; unsigned long offset; }; +static const struct regmap_config apcs_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, +}; + static int qcom_apcs_ipc_send_data(struct mbox_chan *chan, void *data) { struct qcom_apcs_ipc *apcs = container_of(chan->mbox, struct qcom_apcs_ipc, mbox); unsigned long idx = (unsigned long)chan->con_priv; - writel(BIT(idx), apcs->reg); - - return 0; + return regmap_write(apcs->regmap, apcs->offset, BIT(idx)); } static const struct mbox_chan_ops qcom_apcs_ipc_ops = { @@ -47,7 +54,9 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = { static int qcom_apcs_ipc_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct qcom_apcs_ipc *apcs; + struct regmap *regmap; struct resource *res; unsigned long offset; void __iomem *base; @@ -63,9 +72,14 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + regmap = devm_regmap_init_mmio(&pdev->dev, base, &apcs_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + offset = (unsigned long)of_device_get_match_data(&pdev->dev); - apcs->reg = base + offset; + apcs->regmap = regmap; + apcs->offset = offset; /* Initialize channel identifiers */ for (i = 0; i < ARRAY_SIZE(apcs->mbox_chans); i++) From patchwork Fri Dec 1 17:02:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120366 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1391754qgn; Fri, 1 Dec 2017 09:03:59 -0800 (PST) X-Google-Smtp-Source: AGs4zMbO6g1WC8NsJE99Onwnn9YCVZJQq7Utmeddk5L/X4XHPB0pkf4QEJKhZEJZvn8MKUVzhdjY X-Received: by 10.84.133.111 with SMTP id 102mr6825814plf.136.1512147839466; Fri, 01 Dec 2017 09:03:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512147839; cv=none; d=google.com; s=arc-20160816; b=e0VdzyId3ulOKN1BK9A/WnMOKV3Kh1P19Ud1rtaA0+sPcexswxDc/qdtCyQ0Mq+pSx v5vnyZj3DXZk9qyVh6yPZDEAzcuuJKSQ0C7+x3aJvz6ECUu311prD15L3QpJyZbqarUP S0iXoXsB+hwPQW4/9EtOVXdEE2tB+MTAAT0JmBSmBex8jxqzxsv6swB+XB18fgSlzJz9 0Z2fqsmrj0dkOu0kNA9lAl982Z71TGoV9p6yCNZb0C2Wce/soyZB8UBwGbiczFafeyhJ ElIL2J86beCSZhEbQESiqDcvBWEHQKOL9WpHud7+8WYPAJiJ1T0AXVNntvbddMtCA3Ls djvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1slH2e92voQPdezAs8CuA7K+8aK867LAOOcPdZ4FYTA=; b=B6zKB81BhOjT/ss4Mp76z5JL2QTuV/FhPQ4TguJBPK0IyoUCvcQ0PBgLvb90YTyaVy I6N7DZ3TmxjSrOWKNcjVN8DcJmHxXmENS6/iyErLhoH80JXwNfRk2S/NnBITCYJhzkrC 9kjrmJe96z4F8G8Y8e4DrdjdjrqjwqeIhRZ93ZXCSDejBrlryxOTypIdnE26YsA9FoBg l2SEIDU+6c7L2E2YNLWIHWEgSXe+LD3DNN4r217J/XGJhg2c0giJkqHanU8f2Mvj0+PV 1K1ciAxABFhuX0yAxCmxk0z+DaKQTa6Uxg2LvR/bawKsPkfNuoIuxEdAj6fB+K39u+07 h9Dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HCy4FtAu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v68si5061348pgv.557.2017.12.01.09.03.59; Fri, 01 Dec 2017 09:03:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HCy4FtAu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751855AbdLARD5 (ORCPT + 28 others); Fri, 1 Dec 2017 12:03:57 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:43763 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751265AbdLARCc (ORCPT ); Fri, 1 Dec 2017 12:02:32 -0500 Received: by mail-wm0-f67.google.com with SMTP id n138so4701335wmg.2 for ; Fri, 01 Dec 2017 09:02:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1slH2e92voQPdezAs8CuA7K+8aK867LAOOcPdZ4FYTA=; b=HCy4FtAu/pUJkKqesRDxPS/ZDO2HvaD4lU8c/E4YZ+p4RwVekqm0d8nExTVsNyfNRi XEGDyRkixVcfb7/ayq+uW7omekZS8IvB6b/gPV/e4koAKlcIyslue/kVNkbQzDjWhS/0 5vNBUQBuqZYJvB4PvJvRIPqWGGjTzkyGEf7Vo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1slH2e92voQPdezAs8CuA7K+8aK867LAOOcPdZ4FYTA=; b=tsWRdOmUfmTIOQUFmoBdt3Vb39R6T/0n+0B1gw+gcN6Uk8ANk/Y0a00rahCY6n0yiR qquh9GM96GBbjnAy1NxIs5rb5wqznIS6sRnzSdv09eQZt9q8DRPszsJe2VKUwCpYo3AR mUvxwQIOy0HbUbaFKF8rD1AQ3lQIfrEzB6nNzgwYpFx3yGaizqlmJ9CBi+v2yRj2Ft6k IoDRUwf3tNUDbTlBM+HgyuzxswHnc94Zqhx2TGLsyqoSrMNEPU+4cp/uT6Wq45X9Dngf +jptXAU1FaI6cZjNp2ZpA+PIgPKklGrZQDZ4cs4nB9GZC/Qpo2IyIPn0WFesmUGCyMEH vWvw== X-Gm-Message-State: AKGB3mLCDLnvj2tsGlbHEy/dFOBeVJWstn7VuHuHhc9dYk/9rBDRv+wq J1yZM/SfG5+NWJY8eXcg0cg5maSNgR4= X-Received: by 10.28.215.71 with SMTP id o68mr1643483wmg.105.1512147750592; Fri, 01 Dec 2017 09:02:30 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 2sm1535253wmk.28.2017.12.01.09.02.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Dec 2017 09:02:29 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v10 3/6] clk: qcom: Add A53 PLL support Date: Fri, 1 Dec 2017 19:02:21 +0200 Message-Id: <20171201170224.25053-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org> References: <20171201170224.25053-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov Acked-by: Rob Herring --- .../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++ drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 109 +++++++++++++++++++++ 4 files changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt new file mode 100644 index 000000000000..e3fa8118eaee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt @@ -0,0 +1,22 @@ +Qualcomm MSM8916 A53 PLL Binding +-------------------------------- +The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies +above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,msm8916-a53pll" + +- reg : shall contain base register location and length + +- #clock-cells : must be set to <0> + +Example: + + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9f6c278deead..81ac7b9378fe 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -12,6 +12,16 @@ config COMMON_CLK_QCOM select REGMAP_MMIO select RESET_CONTROLLER +config QCOM_A53PLL + bool "MSM8916 A53 PLL" + depends on COMMON_CLK_QCOM + default ARCH_QCOM + help + Support for the A53 PLL on MSM8916 devices. It provides + the CPU with frequencies above 1GHz. + Say Y if you want to support higher CPU frequencies on MSM8916 + devices. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 26410d31446b..e767c60c24ec 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..b2bb8e9437f1 --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2017, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static const struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 63, 0x0, 0x1, 0 }, + { 1248000000, 65, 0x0, 0x1, 0 }, + { 1363200000, 71, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, +}; + +static int qcom_a53pll_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + return 0; +} + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct resource *res; + struct clk_pll *pll; + void __iomem *base; + struct clk_init_data init = { }; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04; + pll->m_reg = 0x08; + pll->n_reg = 0x0c; + pll->config_reg = 0x14; + pll->mode_reg = 0x00; + pll->status_reg = 0x1c; + pll->status_bit = 16; + pll->freq_tbl = a53pll_freq; + + init.name = "a53pll"; + init.parent_names = (const char *[]){ "xo" }; + init.num_parents = 1; + init.ops = &clk_pll_sr2_ops; + init.flags = CLK_IS_CRITICAL; + pll->clkr.hw.init = &init; + + ret = devm_clk_register_regmap(dev, &pll->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + return ret; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,msm8916-a53pll" }, + { } +}; + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .remove = qcom_a53pll_remove, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver); From patchwork Fri Dec 1 17:02:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120365 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1391072qgn; Fri, 1 Dec 2017 09:03:28 -0800 (PST) X-Google-Smtp-Source: AGs4zMZzDwSo3paDnT+zADJPZz2fc8RASlTKmO57uDxlytouaDKB6mm/hkD9bbj1g6hv7x2rOFRT X-Received: by 10.159.218.144 with SMTP id w16mr6851733plp.443.1512147808032; Fri, 01 Dec 2017 09:03:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512147808; cv=none; d=google.com; s=arc-20160816; b=h0XIOFkCwx00J5QPqCdx60LaR4TlGj7NGiL7NEXhniwR5Xq3Y9dY+JvkCzHoOy69tR 9iX+EgE0kZoxzEwXZgSZ1yNCFiLlD3Fl+Dmf82BmxD3P3rBOiN5Um+IQfoRz/ri15lkl TuoNVu/U6tp+3R1emBa3g3solbT6wTUR2ImetikiJz/bQooLXYChzJlWjqXDbxCc2Uiu qbaBGyhsbGKZUyniCH3d3aS365DUjnEegoOsVnbRfh+8vQBNDU53SYhSAHu+uYG56KJK zeaifnn1jbhdNoWOdZ7nTWCgkX5zGXpEmSjesHUTQaRaLuKMGOCPBUnYuuI4ZLVMvnMM qs0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rPpiBZ0p5nkk9kadXe66AnmTeg2Alwe1QQ7ulrca7vA=; b=AMz7gQs4uz/Ov0sJUAfw8PPSMIcfWldrAIqoXEcFowIrcJLyBt/OyGza0zOP0ktnwH FKIeYaqQj0kkfW1GGxU1vhjEzDnlWz+BsN6na8J8jw/1pPDkNjpeBt7S9JlOO+Uj20dE ByyK6Vah7RwF7fhC/f+4Nf/vOA3bUcdDWX/SziNIj/0HyRovW1fX+dXYVPm7HYpaajJw P2zxwbiXGsHZ87uQLm78CFZphrWwGQK72Vt+mHCW3HpQuXK6HFvLT4KLZLfF8SkhsH2W 5s9HJXa476ed3Ce4yRkTsW1RLO/YM8kVAHg98x3qpc9MqKFNHG28qh+gQWSNKu4LleNH mIfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e4k9J/iC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w13si5070070pgm.393.2017.12.01.09.03.27; Fri, 01 Dec 2017 09:03:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e4k9J/iC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751801AbdLARD0 (ORCPT + 28 others); Fri, 1 Dec 2017 12:03:26 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34207 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751855AbdLARCf (ORCPT ); Fri, 1 Dec 2017 12:02:35 -0500 Received: by mail-wr0-f195.google.com with SMTP id y21so10785752wrc.1 for ; Fri, 01 Dec 2017 09:02:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rPpiBZ0p5nkk9kadXe66AnmTeg2Alwe1QQ7ulrca7vA=; b=e4k9J/iCLO90Za0yBVP+sfCdrPqQ1gj0hicQ+i0qzBXHiTFSn7OrY5qAA8Q95bWIxw r4YkD5fnNDq0TxpL5gJRPnPCUMZE2ZcJHAT7eyKjZ3GZfeVh6caJpRm6bCUSVFIVHsMm QLyb+sxbFwSVv4lo9gpohy2XluWKmFcbnbl4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rPpiBZ0p5nkk9kadXe66AnmTeg2Alwe1QQ7ulrca7vA=; b=bQm8MWkm+/cZfR7KojoJZiAXYROMImKGDxCFPXXXWnqTsKyLW6nJtyB7oCKsXZqZIT D0vi9INE9DVJlw6EnMDBBc3iuVYvgRoqrY2GwF41SqRGzyj+tZKwy3guroDHymTkCg41 JfvjDW5nIv6tYH7Uv3wbvx0QzW/bxBAfkZ16ngqiY1B8ZC0VNQ/rWPKZ4Xbo6MzC+0zA u4zMICOSOmZlp9xZ0nESZna01H06IauHMZFcYb0kvJy5lcKnEyZoT/ZYUHhfWM04nA5C y85bDZIVU8YpcAJTo6MMKLPld1LGBkswd0Isa0dYyQ0tW88D2J9DarzjMn7NAidUnG60 czUw== X-Gm-Message-State: AJaThX69pRynjshdGGfZfmbcCEVUQb8/cwLIceyDssaJ7S2ZLq0/sFvl VBB7H6wK/t9LM/4CeKSvUkUWHg== X-Received: by 10.223.181.150 with SMTP id c22mr6635143wre.0.1512147753833; Fri, 01 Dec 2017 09:02:33 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 2sm1535253wmk.28.2017.12.01.09.02.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Dec 2017 09:02:33 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v10 5/6] dt-bindings: mailbox: qcom: Document the APCS clock binding Date: Fri, 1 Dec 2017 19:02:23 +0200 Message-Id: <20171201170224.25053-6-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org> References: <20171201170224.25053-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the binding documentation for APCS to mention that the APCS hardware block also expose a clock controller functionality. The APCS clock controller is a mux and half-integer divider. It has the main CPU PLL as an input and provides the clock for the application CPU. Signed-off-by: Georgi Djakov --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index fb961c310f44..16964f0c1773 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -15,12 +15,21 @@ platforms. Usage: required Value type: Definition: must specify the base address and size of the global block +- clocks: + Usage: required if #clocks-cells property is present + Value type: + Definition: phandle to the input PLL, which feeds the APCS mux/divider - #mbox-cells: Usage: required Value type: Definition: as described in mailbox.txt, must be 1 +- #clock-cells: + Usage: optional + Value type: + Definition: as described in clock.txt, must be 0 + = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the @@ -44,3 +53,12 @@ GLINK RPM referencing the "rpm_hlos" doorbell therein. mbox-names = "rpm_hlos"; }; +Below is another example of the APCS binding on MSM8916 platforms: + + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; + clocks = <&a53pll>; + #clock-cells = <0>; + }; From patchwork Fri Dec 1 17:02:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120364 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1390264qgn; Fri, 1 Dec 2017 09:02:57 -0800 (PST) X-Google-Smtp-Source: AGs4zMadpeq8ewcvrQmmpeAs2B5ezgLjOOWf0ALTYtyeci/gMyPoIOiz89/+2GJDN0SnoeBTfces X-Received: by 10.84.178.129 with SMTP id z1mr6940630plb.365.1512147777123; Fri, 01 Dec 2017 09:02:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512147777; cv=none; d=google.com; s=arc-20160816; b=mgTSvM9cHxD91rXuRNQ+poB7H/CNPSjtVEiwITtZE6Q3tz8vW7BIE1PRo4gBbH8uGa 6EuUcItRZ4v0EpikTTibKvirBtAnzesfL+4VQrdT0I89lViTpHU5miXK6bMn+nmqt0Ko kzwxD8ifRbVjZAvH2EgDsgh+tFACQc3knKay6WdSJcDlOIVGFHKVHJCAi4lBe5cLV0R2 OmwUP16Cc8pElOq+v3oOZttVouND+kCHlKTAP08/f75mGuxwId754b2xXqZWpmNfbdMp bg0reh648f98d1NWm+SHo9eLJFxrn+QQMjCK3uSo2eiJNrxSGbpDbaHK162x5qkqbbnU vGvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=HI9rmaIgyT6RG8o/i83JOnoqIXlaX8aMssiZtiNHaP0=; b=rudmrTrF0MPiSxZYSURwLbgbLhbIBob33BrO47rQaOpdiCL4TRXiy844I1hErtmZmt fX3SLJpqHbOKWLgS++sdA6eHSs8EsfXfLM5n9E6GL6xTF/2RfVO5yCS2h6uIyQAR0UYi VVG7Wl4qhWaazGX1a/Y5krBNkKPBk7djcFVhMyUMhZBdGgV8dDD7R4fV/TxGXBSZtYzA pKz8zlC2+4GeH1WdmbBQhiDaUSqA2XmJJ2QmoFAkqQiPfLhMUVt97ftANSPSWqXvLLCL a2MKS+OUWOzeg6VF6rKfgs+BeyNMEpblwJHEW6D8muKlh2sBSyEYvS+vbCIo1GyYPKS1 ggkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WTHwUfch; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d126si5006209pgc.821.2017.12.01.09.02.56; Fri, 01 Dec 2017 09:02:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WTHwUfch; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752025AbdLARCy (ORCPT + 28 others); Fri, 1 Dec 2017 12:02:54 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34944 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751894AbdLARCg (ORCPT ); Fri, 1 Dec 2017 12:02:36 -0500 Received: by mail-wr0-f195.google.com with SMTP id g53so10833026wra.2 for ; Fri, 01 Dec 2017 09:02:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HI9rmaIgyT6RG8o/i83JOnoqIXlaX8aMssiZtiNHaP0=; b=WTHwUfch3Grkx/GTRNzqhP2RPbhoNPuLwfje0+3np3ZVciIozg57jppfNv/356t0R/ /rGHzKVBKIVNtXGve8BTiyvhDIv4mFtb3H9ScQvOK/qmCip6Hy0JAbT9T8vpuXtb4I7V 4Ti2g3C1glPFUYEej8+6egvewph+vjztrxNt8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HI9rmaIgyT6RG8o/i83JOnoqIXlaX8aMssiZtiNHaP0=; b=SvnnOy5fH7Fy71KM3ZoCDxd2e4eqb8NXxjUjdF7WmrT9i0ZOfG1UOviQ69neOOSdgO o97CiNcBNqWi8VVFcSHPMHfBo1NjeboD63iqM6uxHw9hejoM2TM4n8ZYWZslmEV5V6kO Vuo/dMuWNngZnD3lHL4v+HZHigncKGqQPWcBDkb1fHr9FWzpmP14/1FBoYeL4cfov89L XEu82SmBQ4j7jDj5OoVFBYDJfN/OD4Ow8ZfNq5oxKsgsjo83NcgXoaDmKOyaT63mjnDl J09/jRsm8eu+nfSHJkTg1NB9F94be82gE2xwSYijyRJZIRGb/TFOYx3YvReGxZk8YQ7u eSXw== X-Gm-Message-State: AJaThX7hiY7eRtGjAusGo7+d7+FQLHG4nw3MhdZNr8z00lNVL2OBiojN tJvPqHeW2V9lQbk3eLs51kYb9A== X-Received: by 10.223.132.101 with SMTP id 92mr6212435wrf.85.1512147755435; Fri, 01 Dec 2017 09:02:35 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 2sm1535253wmk.28.2017.12.01.09.02.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Dec 2017 09:02:34 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v10 6/6] clk: qcom: Add APCS clock controller support Date: Fri, 1 Dec 2017 19:02:24 +0200 Message-Id: <20171201170224.25053-7-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org> References: <20171201170224.25053-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apcs-msm8916.c | 149 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/clk/qcom/apcs-msm8916.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 81ac7b9378fe..255023b439c9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -22,6 +22,17 @@ config QCOM_A53PLL Say Y if you want to support higher CPU frequencies on MSM8916 devices. +config QCOM_CLK_APCS_MSM8916 + bool "MSM8916 APCS Clock Controller" + depends on COMMON_CLK_QCOM + depends on QCOM_APCS_IPC + default ARCH_QCOM + help + Support for the APCS Clock Controller on msm8916 devices. The + APCS is managing the mux and divider which feeds the CPUs. + Say Y if you want to support CPU frequency scaling on devices + such as msm8916. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 7c51d877f967..0408cebf38d4 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -34,5 +34,6 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o +obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c new file mode 100644 index 000000000000..f71039ff2347 --- /dev/null +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -0,0 +1,149 @@ +/* + * Qualcomm APCS clock controller driver + * + * Copyright (c) 2017, Linaro Limited + * Author: Georgi Djakov + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the A53 PLL is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + if (event == PRE_RATE_CHANGE) + /* set the mux and divider to safe frequency (400mhz) */ + ret = __mux_div_set_src_div(md, 4, 3); + + return notifier_from_errno(ret); +} + +static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) +{ + struct device *dev = pdev->dev.parent; + struct device_node *np = dev->of_node; + struct clk_regmap_mux_div *a53cc; + struct regmap *regmap; + struct clk_init_data init = { }; + int ret; + + regmap = dev_get_regmap(dev, NULL); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + init.name = "a53mux"; + init.parent_names = gpll0_a53cc; + init.num_parents = ARRAY_SIZE(gpll0_a53cc); + init.ops = &clk_regmap_mux_div_ops; + init.flags = CLK_SET_RATE_PARENT; + + a53cc->clkr.hw.init = &init; + a53cc->clkr.regmap = regmap; + a53cc->reg_offset = 0x50; + a53cc->hid_width = 5; + a53cc->hid_shift = 0; + a53cc->src_width = 3; + a53cc->src_shift = 8; + a53cc->parent_map = gpll0_a53cc_map; + + a53cc->pclk = devm_clk_get(dev, NULL); + if (IS_ERR(a53cc->pclk)) { + ret = PTR_ERR(a53cc->pclk); + dev_err(dev, "failed to get clk: %d\n", ret); + return ret; + } + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + ret = devm_clk_register_regmap(dev, &a53cc->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, + &a53cc->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + platform_set_drvdata(pdev, a53cc); + + return 0; + +err: + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + return ret; +} + +static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev) +{ + struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev); + + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + of_clk_del_provider(pdev->dev.of_node); + + return 0; +} + +static struct platform_driver qcom_apcs_msm8916_clk_driver = { + .probe = qcom_apcs_msm8916_clk_probe, + .remove = qcom_apcs_msm8916_clk_remove, + .driver = { + .name = "qcom-apcs-msm8916-clk", + }, +}; +module_platform_driver(qcom_apcs_msm8916_clk_driver); + +MODULE_AUTHOR("Georgi Djakov "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");