From patchwork Fri Dec 1 17:02:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120363 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1389850qgn; Fri, 1 Dec 2017 09:02:39 -0800 (PST) X-Google-Smtp-Source: AGs4zMZWHG/t7M+z1bPTk2AIls3KX5cC+sF474hjGhZkSTnVTT4NZTZ3UTyf1tgfzg39/Ul+XEmr X-Received: by 10.98.48.3 with SMTP id w3mr10606830pfw.219.1512147759395; Fri, 01 Dec 2017 09:02:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512147759; cv=none; d=google.com; s=arc-20160816; b=uTEdmYRmEipL+GgwHYGAU2F6EPfjt3u6lPASCvaSqLiUdGkiC8edvyjXNYdkRsIVZA BSJG4nQM7XJrIyNXW5xNiPvWZiyDw3ErbqLkOdzrJk+E1zU3WpFuoJ3g6dMJGdiiN1le B6/xE333YBrYtDI9d9oG77CahEI3e6QEN7X8oMMcxnL8sYH2MqKlyndpWqbrv1z43sGZ 6Sd8k7VYFlO/kAs8r5i3xp8vkNo4+Xas7urPXcMeBEmnhZ9heATJySzCseVnQGzhfOOR soJU3vSiSGSOUZ3L9qeCnJ3Vc0jKJFaw64HUx80J72VVHowUvZMEeXkzFRKoQAMBk7m3 gIow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rZrGSGucwt2D44HeNK+vgQZeysmDzi57NEyXV4QUMSc=; b=b3n3gtA/DOU3HVYL4i9RVcniA3fqtMqYtOxV5eJJmtxcI50UCO/7v7iBMDuthm1+SE Ak91/n9foN5neHSCxSKxt9VSp6zXKx6m72Dt1YVQZVYD3pE4025gCqEjpbOl1U5GTU21 PUqV+UPWJnodL8N2hSg8bl7o5O+A1HFJhGS0zOMMfWIVwB/nwuCEPIC9KeMv1nBohE/W ySnE455bbP2Ru/YLLzpYIxBcGrF5C9aZrXF/XKJcxF3en1Ej4twk2h7xWcqfuCanqE9O Koe95cFektOZ3l7cv17+xydrG+Opan97QFHwIHrBrUdtkI1gVjDhjZuXIqM6PXd21Snt nILg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cUJjG108; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t17si5183840plo.430.2017.12.01.09.02.38; Fri, 01 Dec 2017 09:02:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cUJjG108; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751918AbdLARCg (ORCPT + 10 others); Fri, 1 Dec 2017 12:02:36 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:43772 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751746AbdLARCd (ORCPT ); Fri, 1 Dec 2017 12:02:33 -0500 Received: by mail-wm0-f68.google.com with SMTP id n138so4701522wmg.2 for ; Fri, 01 Dec 2017 09:02:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qmzl3vfTI3f1JOmLx7hG+6tJAB/8uAXPutAxnXGOBFU=; b=cUJjG108IH3fspqvmztPo1qTYeaLw3YNDRAuNQ8iB0T6i6533ZChXIZoeIyrhi6zCC tHY5VMIuWJM7O81W2NVZjmhuKSb+Bz1Bmrl2QtrPF3i5Wwm54uK1yGq3N6ELAPm2jZix Nob76YRcYch/bu5UwEka84ML0mTw7v3N4HAp0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qmzl3vfTI3f1JOmLx7hG+6tJAB/8uAXPutAxnXGOBFU=; b=OHDYaFEz66CnbZ0rz40vfquSbQ7hD/cgtqxWwRTaT3tmy9bq/bic5Cm7rUvh5Fe0pZ IU8sq4i+GQcRcyBEkzpaZv60R4xxwQt14sKnEfOEYXOpYX+qVHXjD6IvPG7cCMrXbytf EMB0m59PVoidj0/RkBAtEoMz1YcXjmw7e9ZsTrspnmnO2iGjTtnCTGR8zqPzU395i3J7 y/kJlKbAT1+O3sg9Oa39hlJp+MkXMTF/sRFO3Q8VB8DTtQs+/yhYFTqYZLlD+wzCO8hR eTu1GUstecrMwft6nbwQ1Sn8c0WC+GXFUCM08V8Vg1s8BcUOnUu4n+WHJxxmpvztJoWs W72g== X-Gm-Message-State: AKGB3mIIeiKFArfEO5L/23Id5QXMmIjCOjafA/QUFteM5Fpj92u/37nE 92k5TsAEsK0fbYHJ+zmudpiINQ== X-Received: by 10.28.95.7 with SMTP id t7mr1652119wmb.86.1512147752230; Fri, 01 Dec 2017 09:02:32 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 2sm1535253wmk.28.2017.12.01.09.02.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Dec 2017 09:02:31 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v10 4/6] clk: qcom: Add regmap mux-div clocks support Date: Fri, 1 Dec 2017 19:02:22 +0200 Message-Id: <20171201170224.25053-5-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org> References: <20171201170224.25053-1-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for hardware that can switch both parent clock and divider at the same time. This avoids generating intermediate frequencies from either the old parent clock and new divider or new parent clock and old divider combinations. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-regmap-mux-div.c | 230 ++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-regmap-mux-div.h | 47 +++++++ 3 files changed, 278 insertions(+) create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e767c60c24ec..7c51d877f967 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -10,6 +10,7 @@ clk-qcom-y += clk-rcg2.o clk-qcom-y += clk-branch.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o +clk-qcom-y += clk-regmap-mux-div.o clk-qcom-y += reset.o clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o diff --git a/drivers/clk/qcom/clk-regmap-mux-div.c b/drivers/clk/qcom/clk-regmap-mux-div.c new file mode 100644 index 000000000000..9885b8bc0890 --- /dev/null +++ b/drivers/clk/qcom/clk-regmap-mux-div.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2017, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +#include "clk-regmap-mux-div.h" + +#define CMD_RCGR 0x0 +#define CMD_RCGR_UPDATE BIT(0) +#define CMD_RCGR_DIRTY_CFG BIT(4) +#define CMD_RCGR_ROOT_OFF BIT(31) +#define CFG_RCGR 0x4 + +#define to_clk_regmap_mux_div(_hw) \ + container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr) + +int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div) +{ + int ret, count; + u32 val, mask; + const char *name = clk_hw_get_name(&md->clkr.hw); + + val = (div << md->hid_shift) | (src << md->src_shift); + mask = ((BIT(md->hid_width) - 1) << md->hid_shift) | + ((BIT(md->src_width) - 1) << md->src_shift); + + ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset, + mask, val); + if (ret) + return ret; + + ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset, + CMD_RCGR_UPDATE, CMD_RCGR_UPDATE); + if (ret) + return ret; + + /* Wait for update to take effect */ + for (count = 500; count > 0; count--) { + ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, + &val); + if (ret) + return ret; + if (!(val & CMD_RCGR_UPDATE)) + return 0; + udelay(1); + } + + pr_err("%s: RCG did not update its configuration", name); + return -EBUSY; +} + +static void __mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src, + u32 *div) +{ + u32 val, d, s; + const char *name = clk_hw_get_name(&md->clkr.hw); + + regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val); + + if (val & CMD_RCGR_DIRTY_CFG) { + pr_err("%s: RCG configuration is pending\n", name); + return; + } + + regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val); + s = (val >> md->src_shift); + s &= BIT(md->src_width) - 1; + *src = s; + + d = (val >> md->hid_shift); + d &= BIT(md->hid_width) - 1; + *div = d; +} + +static inline bool is_better_rate(unsigned long req, unsigned long best, + unsigned long new) +{ + return (req <= new && new < best) || (best < req && best < new); +} + +static int mux_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + unsigned int i, div, max_div; + unsigned long actual_rate, best_rate = 0; + unsigned long req_rate = req->rate; + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate = clk_hw_get_rate(parent); + + max_div = BIT(md->hid_width) - 1; + for (div = 1; div < max_div; div++) { + parent_rate = mult_frac(req_rate, div, 2); + parent_rate = clk_hw_round_rate(parent, parent_rate); + actual_rate = mult_frac(parent_rate, 2, div); + + if (is_better_rate(req_rate, best_rate, actual_rate)) { + best_rate = actual_rate; + req->rate = best_rate; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; + } + + if (actual_rate < req_rate || best_rate <= req_rate) + break; + } + } + + if (!best_rate) + return -EINVAL; + + return 0; +} + +static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long prate, u32 src) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + int ret; + u32 div, max_div, best_src = 0, best_div = 0; + unsigned int i; + unsigned long actual_rate, best_rate = 0; + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate = clk_hw_get_rate(parent); + + max_div = BIT(md->hid_width) - 1; + for (div = 1; div < max_div; div++) { + parent_rate = mult_frac(rate, div, 2); + parent_rate = clk_hw_round_rate(parent, parent_rate); + actual_rate = mult_frac(parent_rate, 2, div); + + if (is_better_rate(rate, best_rate, actual_rate)) { + best_rate = actual_rate; + best_src = md->parent_map[i].cfg; + best_div = div - 1; + } + + if (actual_rate < rate || best_rate <= rate) + break; + } + } + + ret = __mux_div_set_src_div(md, best_src, best_div); + if (!ret) { + md->div = best_div; + md->src = best_src; + } + + return ret; +} + +static u8 mux_div_get_parent(struct clk_hw *hw) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + const char *name = clk_hw_get_name(hw); + u32 i, div, src = 0; + + __mux_div_get_src_div(md, &src, &div); + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) + if (src == md->parent_map[i].cfg) + return i; + + pr_err("%s: Can't find parent with src %d\n", name, src); + return 0; +} + +static int mux_div_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + + return __mux_div_set_src_div(md, md->parent_map[index].cfg, md->div); +} + +static int mux_div_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long prate) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + + return __mux_div_set_rate_and_parent(hw, rate, prate, md->src); +} + +static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long prate, u8 index) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + + return __mux_div_set_rate_and_parent(hw, rate, prate, + md->parent_map[index].cfg); +} + +static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + u32 div, src; + int i, num_parents = clk_hw_get_num_parents(hw); + const char *name = clk_hw_get_name(hw); + + __mux_div_get_src_div(md, &src, &div); + for (i = 0; i < num_parents; i++) + if (src == md->parent_map[i].cfg) { + struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate = clk_hw_get_rate(p); + + return mult_frac(parent_rate, 2, div + 1); + } + + pr_err("%s: Can't find parent %d\n", name, src); + return 0; +} + +const struct clk_ops clk_regmap_mux_div_ops = { + .get_parent = mux_div_get_parent, + .set_parent = mux_div_set_parent, + .set_rate = mux_div_set_rate, + .set_rate_and_parent = mux_div_set_rate_and_parent, + .determine_rate = mux_div_determine_rate, + .recalc_rate = mux_div_recalc_rate, +}; diff --git a/drivers/clk/qcom/clk-regmap-mux-div.h b/drivers/clk/qcom/clk-regmap-mux-div.h new file mode 100644 index 000000000000..6088f8f23f45 --- /dev/null +++ b/drivers/clk/qcom/clk-regmap-mux-div.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2017, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__ +#define __QCOM_CLK_REGMAP_MUX_DIV_H__ + +#include +#include "clk-rcg.h" +#include "clk-regmap.h" + +/** + * struct mux_div_clk - combined mux/divider clock + * @reg_offset: offset of the mux/divider register + * @hid_width: number of bits in half integer divider + * @hid_shift: lowest bit of hid value field + * @src_width: number of bits in source select + * @src_shift: lowest bit of source select field + * @div: the divider raw configuration value + * @src: the mux index which will be used if the clock is enabled + * @parent_map: pointer to parent_map struct + * @clkr: handle between common and hardware-specific interfaces + * @pclk: the input PLL clock + * @clk_nb: clock notifier for rate changes of the input PLL + */ + +struct clk_regmap_mux_div { + u32 reg_offset; + u32 hid_width; + u32 hid_shift; + u32 src_width; + u32 src_shift; + u32 div; + u32 src; + const struct parent_map *parent_map; + struct clk_regmap clkr; + struct clk *pclk; + struct notifier_block clk_nb; +}; + +extern const struct clk_ops clk_regmap_mux_div_ops; +int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div); + +#endif