From patchwork Fri Dec 1 22:23:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120401 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1705934qgn; Fri, 1 Dec 2017 14:23:59 -0800 (PST) X-Google-Smtp-Source: AGs4zMZV4n+NZtuheN0Q64k3U1VueqL0cDH3gUiOv6z+u17+AvNz1p6g9kIoCXSOZsMIdB2oIRZr X-Received: by 10.99.148.1 with SMTP id m1mr7248259pge.237.1512167039143; Fri, 01 Dec 2017 14:23:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167039; cv=none; d=google.com; s=arc-20160816; b=FNK98HGzWimhMA1v2hlsqeGpWGwuz37DT9eTyQoBOKGVuZFPhLT6/zifKtl1MSEVQf 84cl/iL9QI2JuFp3zMkSHcNb7SaRRiVutNbhbOwb/gCVwbKBuGqYTEmz8iOaEdBqyXcx XXnknX1AZdoL+OczxwCdOaLS/oihHB8bBSZo1rOqhRHm4A4afLpSvjf5tgM5sb4kT5b5 kckuDp/qcyK5Erg6BXecyboQTWwKjfCDYlLiBUl3E9wc+MSEHKWXH0aUq8B/3rCQl3GU UtXNsK5XAs8lfTCA/u11FbFqkqx7Deg5EC5zpvSgNgBh4Al5Sx/CaPTWbLcZIzRJ7lY0 7Krg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=4iPvFEq+tGKe9fBR5f3REmEVUIJuzQtM7sAa4kcVxgY=; b=s9xko6Al6U/XJ5Sf8BKKS6NI7MLV6gV9uScUlZ6nMuZnjOqjgV079IDodrSHn3cMyQ pPuyCziPJGaLA8bY6e5fYccyiAkhRTSDf58tPuIT7bHKdiM4VYwNWlB3hLoR1HvLgk+7 s/XnBb9efLQgnv+5zeQEohIaR82X4jhSmqxVurfhzRv6TK9R4gHf+Za+ym3CPfBBgnzH v7HTEjEAG/9Xmx64d8PCys4h3M+PhVRbYRFbelpNa93BQ77Mhj6bXWN1iC7YZvmLORD3 NFt5XuvrxEhQRdRMrRaqf5BvauNWET3h0YjxmyzSxnVs+s1NLpakC4tzse0WAq9PzBW5 r8lw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s189si5460375pgb.104.2017.12.01.14.23.58; Fri, 01 Dec 2017 14:23:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751555AbdLAWXz (ORCPT + 28 others); Fri, 1 Dec 2017 17:23:55 -0500 Received: from foss.arm.com ([217.140.101.70]:46990 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751486AbdLAWXv (ORCPT ); Fri, 1 Dec 2017 17:23:51 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 684C815A2; Fri, 1 Dec 2017 14:23:51 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 79D063F246; Fri, 1 Dec 2017 14:23:50 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 1/9] arm64/acpi: Create arch specific cpu to acpi id helper Date: Fri, 1 Dec 2017 16:23:22 -0600 Message-Id: <20171201222330.18863-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Its helpful to be able to lookup the acpi_processor_id associated with a logical cpu. Provide an arm64 helper to do this. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/acpi.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.13.5 diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index 32f465a80e4e..0db62a4cbce2 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -86,6 +86,10 @@ static inline bool acpi_has_cpu_in_madt(void) } struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu); +static inline u32 get_acpi_id_for_cpu(unsigned int cpu) +{ + return acpi_cpu_get_madt_gicc(cpu)->uid; +} static inline void arch_fix_phys_package_id(int num, u32 slot) { } void __init acpi_init_cpus(void); From patchwork Fri Dec 1 22:23:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120402 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1705956qgn; Fri, 1 Dec 2017 14:24:01 -0800 (PST) X-Google-Smtp-Source: AGs4zMYWwWDCeccuGZkd2sDvFF9m12IMGR4s30f23uZugGIW/kQFosOf1Agw0VBEa9FTG/j4cQHd X-Received: by 10.99.120.131 with SMTP id t125mr7079458pgc.83.1512167040957; Fri, 01 Dec 2017 14:24:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167040; cv=none; d=google.com; s=arc-20160816; b=XxVbUg1mztdDjoudV4mBway3TwBA1IchGYMM5ij13+CzU72epCuypofiA3WelpEXfL Ws+txC5vL2GimXGaHqlQ9R+qdSvCaWHnAM2QrG+gi5fi9JwYpPTDSqw0yGSM3+drgbdm TGR0C1XSQm5+5GNqvL12pPXKGMOIeyBa2Wy7SdAU7H3fyddMy1QAYejZNA6exl7NlBSq OERdAlkszzXk/mzWPTPLAbLRtX7lFdeIAs76TJV2acEVouzmUuZURs8fVEDFSpLMEQS0 nHlz4IKvWDco3w+amjYEYHb2clSCoBX0PB0NmhV80sLL8qMsmF9icuL56aBzpSWE2U5r ELBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=AqzSfqB1tEPOo3+BsXdfcbWIIc/1iAntd9LlWdga4C8=; b=ApWa+pbmprg1Xr9ZEN6QC4EwrUba9hpfSJvBSNZZYwUKhU4n/CB9XGEEhflvxEeByg fdCRVAiBcUD0yXQ1P10Rk7U/4+u/AyF9adjFtuq17A0MU4esC2QNmUQqvxEQ920+ZiqX ukVIYh6q/5Me+jetU2ZvvKL41O2yxkArFw9X8CK+X4Q1Jj7uIWYrGcLWgUOBRmOOiEkO tCXAUezlO61ImIm8lbp4xFcTAAWjcdj0Bxe5D376c2o+ipEQ8hEJyqMapvIRRgzdzf2t ME99PtqqH3JZ0nc4OV7VWi4oeeCMlV86TvQtjvsxyfqEkvAG1knNjMtO3JKGZIe6dh9c AMlg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s189si5460375pgb.104.2017.12.01.14.24.00; Fri, 01 Dec 2017 14:24:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751673AbdLAWX7 (ORCPT + 28 others); Fri, 1 Dec 2017 17:23:59 -0500 Received: from foss.arm.com ([217.140.101.70]:47014 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751533AbdLAWXz (ORCPT ); Fri, 1 Dec 2017 17:23:55 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E756215AD; Fri, 1 Dec 2017 14:23:54 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0E1193F246; Fri, 1 Dec 2017 14:23:54 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 2/9] ACPI/PPTT: Add Processor Properties Topology Table parsing Date: Fri, 1 Dec 2017 16:23:23 -0600 Message-Id: <20171201222330.18863-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ACPI 6.2 adds a new table, which describes how processing units are related to each other in tree like fashion. Caches are also sprinkled throughout the tree and describe the properties of the caches in relation to other caches and processing units. Add the code to parse the cache hierarchy and report the total number of levels of cache for a given core using acpi_find_last_cache_level() as well as fill out the individual cores cache information with cache_setup_acpi() once the cpu_cacheinfo structure has been populated by the arch specific code. An additional patch later in the set adds the ability to report peers in the topology using find_acpi_cpu_topology() to report a unique ID for each processing unit at a given level in the tree. These unique id's can then be used to match related processing units which exist as threads, COD (clusters on die), within a given package, etc. Signed-off-by: Jeremy Linton --- drivers/acpi/pptt.c | 476 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 476 insertions(+) create mode 100644 drivers/acpi/pptt.c -- 2.13.5 diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c new file mode 100644 index 000000000000..0f8a1631af33 --- /dev/null +++ b/drivers/acpi/pptt.c @@ -0,0 +1,476 @@ +/* + * Copyright (C) 2017, ARM + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * This file implements parsing of Processor Properties Topology Table (PPTT) + * which is optionally used to describe the processor and cache topology. + * Due to the relative pointers used throughout the table, this doesn't + * leverage the existing subtable parsing in the kernel. + * + * The PPTT structure is an inverted tree, with each node potentially + * holding one or two inverted tree data structures describing + * the caches available at that level. Each cache structure optionally + * contains properties describing the cache at a given level which can be + * used to override hardware probed values. + */ +#define pr_fmt(fmt) "ACPI PPTT: " fmt + +#include +#include +#include + +/* total number of attributes checked by the properties code */ +#define PPTT_CHECKED_ATTRIBUTES 6 + +/* + * Given the PPTT table, find and verify that the subtable entry + * is located within the table + */ +static struct acpi_subtable_header *fetch_pptt_subtable( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + struct acpi_subtable_header *entry; + + /* there isn't a subtable at reference 0 */ + if (pptt_ref < sizeof(struct acpi_subtable_header)) + return NULL; + + if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) + return NULL; + + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, pptt_ref); + + if (pptt_ref + entry->length > table_hdr->length) + return NULL; + + return entry; +} + +static struct acpi_pptt_processor *fetch_pptt_node( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_processor *)fetch_pptt_subtable(table_hdr, + pptt_ref); +} + +static struct acpi_pptt_cache *fetch_pptt_cache( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_cache *)fetch_pptt_subtable(table_hdr, + pptt_ref); +} + +static struct acpi_subtable_header *acpi_get_pptt_resource( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *node, int resource) +{ + u32 *ref; + + if (resource >= node->number_of_priv_resources) + return NULL; + + ref = ACPI_ADD_PTR(u32, node, sizeof(struct acpi_pptt_processor)); + ref += resource; + + return fetch_pptt_subtable(table_hdr, *ref); +} + +/* + * Attempt to find a given cache level, while counting the max number + * of cache levels for the cache node. + * + * Given a pptt resource, verify that it is a cache node, then walk + * down each level of caches, counting how many levels are found + * as well as checking the cache type (icache, dcache, unified). If a + * level & type match, then we set found, and continue the search. + * Once the entire cache branch has been walked return its max + * depth. + */ +static int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr, + int local_level, + struct acpi_subtable_header *res, + struct acpi_pptt_cache **found, + int level, int type) +{ + struct acpi_pptt_cache *cache; + + if (res->type != ACPI_PPTT_TYPE_CACHE) + return 0; + + cache = (struct acpi_pptt_cache *) res; + while (cache) { + local_level++; + + if ((local_level == level) && + (cache->flags & ACPI_PPTT_CACHE_TYPE_VALID) && + ((cache->attributes & ACPI_PPTT_MASK_CACHE_TYPE) == type)) { + if ((*found != NULL) && (cache != *found)) + pr_err("Found duplicate cache level/type unable to determine uniqueness\n"); + + pr_debug("Found cache @ level %d\n", level); + *found = cache; + /* + * continue looking at this node's resource list + * to verify that we don't find a duplicate + * cache node. + */ + } + cache = fetch_pptt_cache(table_hdr, cache->next_level_of_cache); + } + return local_level; +} + +/* + * Given a CPU node look for cache levels that exist at this level, and then + * for each cache node, count how many levels exist below (logically above) it. + * If a level and type are specified, and we find that level/type, abort + * processing and return the acpi_pptt_cache structure. + */ +static struct acpi_pptt_cache *acpi_find_cache_level( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node, + int *starting_level, int level, int type) +{ + struct acpi_subtable_header *res; + int number_of_levels = *starting_level; + int resource = 0; + struct acpi_pptt_cache *ret = NULL; + int local_level; + + /* walk down from processor node */ + while ((res = acpi_get_pptt_resource(table_hdr, cpu_node, resource))) { + resource++; + + local_level = acpi_pptt_walk_cache(table_hdr, *starting_level, + res, &ret, level, type); + /* + * we are looking for the max depth. Since its potentially + * possible for a given node to have resources with differing + * depths verify that the depth we have found is the largest. + */ + if (number_of_levels < local_level) + number_of_levels = local_level; + } + if (number_of_levels > *starting_level) + *starting_level = number_of_levels; + + return ret; +} + +/* + * Given a processor node containing a processing unit, walk into it and count + * how many levels exist solely for it, and then walk up each level until we hit + * the root node (ignore the package level because it may be possible to have + * caches that exist across packages). Count the number of cache levels that + * exist at each level on the way up. + */ +static int acpi_process_node(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node) +{ + int total_levels = 0; + + do { + acpi_find_cache_level(table_hdr, cpu_node, &total_levels, 0, 0); + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } while (cpu_node); + + return total_levels; +} + +/* + * Determine if the *node parameter is a leaf node by iterating the + * PPTT table, looking for nodes which reference it. + * Return 0 if we find a node referencing the passed node, + * or 1 if we don't. + */ +static int acpi_pptt_leaf_node(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *node) +{ + struct acpi_subtable_header *entry; + unsigned long table_end; + u32 node_entry; + struct acpi_pptt_processor *cpu_node; + + table_end = (unsigned long)table_hdr + table_hdr->length; + node_entry = ACPI_PTR_DIFF(node, table_hdr); + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, + sizeof(struct acpi_table_pptt)); + + while ((unsigned long)(entry + 1) < table_end) { + cpu_node = (struct acpi_pptt_processor *)entry; + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) && + (cpu_node->parent == node_entry)) + return 0; + entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry, + entry->length); + } + return 1; +} + +/* + * Find the subtable entry describing the provided processor. + * This is done by iterating the PPTT table looking for processor nodes + * which have an acpi_processor_id that matches the acpi_cpu_id parameter + * passed into the function. If we find a node that matches this criteria + * we verify that its a leaf node in the topology rather than depending + * on the valid flag, which doesn't need to be set for leaf nodes. + */ +static struct acpi_pptt_processor *acpi_find_processor_node( + struct acpi_table_header *table_hdr, + u32 acpi_cpu_id) +{ + struct acpi_subtable_header *entry; + unsigned long table_end; + struct acpi_pptt_processor *cpu_node; + + table_end = (unsigned long)table_hdr + table_hdr->length; + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, + sizeof(struct acpi_table_pptt)); + + /* find the processor structure associated with this cpuid */ + while ((unsigned long)(entry + 1) < table_end) { + cpu_node = (struct acpi_pptt_processor *)entry; + + if (entry->length == 0) { + pr_err("Invalid zero length subtable\n"); + break; + } + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) && + (acpi_cpu_id == cpu_node->acpi_processor_id) && + acpi_pptt_leaf_node(table_hdr, cpu_node)) { + return (struct acpi_pptt_processor *)entry; + } + + entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry, + entry->length); + } + + return NULL; +} + +static int acpi_find_cache_levels(struct acpi_table_header *table_hdr, + u32 acpi_cpu_id) +{ + int number_of_levels = 0; + struct acpi_pptt_processor *cpu; + + cpu = acpi_find_processor_node(table_hdr, acpi_cpu_id); + if (cpu) + number_of_levels = acpi_process_node(table_hdr, cpu); + + return number_of_levels; +} + +/* Convert the linux cache_type to a ACPI PPTT cache type value */ +static u8 acpi_cache_type(enum cache_type type) +{ + switch (type) { + case CACHE_TYPE_DATA: + pr_debug("Looking for data cache\n"); + return ACPI_PPTT_CACHE_TYPE_DATA; + case CACHE_TYPE_INST: + pr_debug("Looking for instruction cache\n"); + return ACPI_PPTT_CACHE_TYPE_INSTR; + default: + case CACHE_TYPE_UNIFIED: + pr_debug("Looking for unified cache\n"); + /* + * It is important that ACPI_PPTT_CACHE_TYPE_UNIFIED + * contains the bit pattern that will match both + * ACPI unified bit patterns because we use it later + * to match both cases. + */ + return ACPI_PPTT_CACHE_TYPE_UNIFIED; + } +} + +/* find the ACPI node describing the cache type/level for the given CPU */ +static struct acpi_pptt_cache *acpi_find_cache_node( + struct acpi_table_header *table_hdr, u32 acpi_cpu_id, + enum cache_type type, unsigned int level, + struct acpi_pptt_processor **node) +{ + int total_levels = 0; + struct acpi_pptt_cache *found = NULL; + struct acpi_pptt_processor *cpu_node; + u8 acpi_type = acpi_cache_type(type); + + pr_debug("Looking for CPU %d's level %d cache type %d\n", + acpi_cpu_id, level, acpi_type); + + cpu_node = acpi_find_processor_node(table_hdr, acpi_cpu_id); + + while ((cpu_node) && (!found)) { + found = acpi_find_cache_level(table_hdr, cpu_node, + &total_levels, level, acpi_type); + *node = cpu_node; + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } + + return found; +} + +/* + * The ACPI spec implies that the fields in the cache structures are used to + * extend and correct the information probed from the hardware. In the case + * of arm64 the CCSIDR probing has been removed because it might be incorrect. + */ +static void update_cache_properties(struct cacheinfo *this_leaf, + struct acpi_pptt_cache *found_cache, + struct acpi_pptt_processor *cpu_node) +{ + int valid_flags = 0; + + if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) { + this_leaf->size = found_cache->size; + valid_flags++; + } + if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID) { + this_leaf->coherency_line_size = found_cache->line_size; + valid_flags++; + } + if (found_cache->flags & ACPI_PPTT_NUMBER_OF_SETS_VALID) { + this_leaf->number_of_sets = found_cache->number_of_sets; + valid_flags++; + } + if (found_cache->flags & ACPI_PPTT_ASSOCIATIVITY_VALID) { + this_leaf->ways_of_associativity = found_cache->associativity; + valid_flags++; + } + if (found_cache->flags & ACPI_PPTT_WRITE_POLICY_VALID) { + switch (found_cache->attributes & ACPI_PPTT_MASK_WRITE_POLICY) { + case ACPI_PPTT_CACHE_POLICY_WT: + this_leaf->attributes = CACHE_WRITE_THROUGH; + break; + case ACPI_PPTT_CACHE_POLICY_WB: + this_leaf->attributes = CACHE_WRITE_BACK; + break; + } + valid_flags++; + } + if (found_cache->flags & ACPI_PPTT_ALLOCATION_TYPE_VALID) { + switch (found_cache->attributes & ACPI_PPTT_MASK_ALLOCATION_TYPE) { + case ACPI_PPTT_CACHE_READ_ALLOCATE: + this_leaf->attributes |= CACHE_READ_ALLOCATE; + break; + case ACPI_PPTT_CACHE_WRITE_ALLOCATE: + this_leaf->attributes |= CACHE_WRITE_ALLOCATE; + break; + case ACPI_PPTT_CACHE_RW_ALLOCATE: + case ACPI_PPTT_CACHE_RW_ALLOCATE_ALT: + this_leaf->attributes |= + CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE; + break; + } + valid_flags++; + } + /* + * If all the above flags are valid, and the cache type is NOCACHE + * update the cache type as well. + */ + if ((this_leaf->type == CACHE_TYPE_NOCACHE) && + (valid_flags == PPTT_CHECKED_ATTRIBUTES)) + this_leaf->type = CACHE_TYPE_UNIFIED; +} + +/* + * Update the kernel cache information for each level of cache + * associated with the given acpi cpu. + */ +static void cache_setup_acpi_cpu(struct acpi_table_header *table, + unsigned int cpu) +{ + struct acpi_pptt_cache *found_cache; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + struct cacheinfo *this_leaf; + unsigned int index = 0; + struct acpi_pptt_processor *cpu_node = NULL; + + while (index < get_cpu_cacheinfo(cpu)->num_leaves) { + this_leaf = this_cpu_ci->info_list + index; + found_cache = acpi_find_cache_node(table, acpi_cpu_id, + this_leaf->type, + this_leaf->level, + &cpu_node); + pr_debug("found = %p %p\n", found_cache, cpu_node); + if (found_cache) + update_cache_properties(this_leaf, + found_cache, + cpu_node); + + index++; + } +} + +/** + * acpi_find_last_cache_level() - Determines the number of cache levels for a PE + * @cpu: Kernel logical cpu number + * + * Given a logical cpu number, returns the number of levels of cache represented + * in the PPTT. Errors caused by lack of a PPTT table, or otherwise, return 0 + * indicating we didn't find any cache levels. + * + * Return: Cache levels visible to this core. + */ +int acpi_find_last_cache_level(unsigned int cpu) +{ + u32 acpi_cpu_id; + struct acpi_table_header *table; + int number_of_levels = 0; + acpi_status status; + + pr_debug("Cache Setup find last level cpu=%d\n", cpu); + + acpi_cpu_id = get_acpi_id_for_cpu(cpu); + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + } else { + number_of_levels = acpi_find_cache_levels(table, acpi_cpu_id); + acpi_put_table(table); + } + pr_debug("Cache Setup find last level level=%d\n", number_of_levels); + + return number_of_levels; +} + +/** + * cache_setup_acpi() - Override CPU cache topology with data from the PPTT + * @cpu: Kernel logical cpu number + * + * Updates the global cache info provided by cpu_get_cacheinfo() + * when there are valid properties in the acpi_pptt_cache nodes. A + * successful parse may not result in any updates if none of the + * cache levels have any valid flags set. Futher, a unique value is + * associated with each known CPU cache entry. This unique value + * can be used to determine whether caches are shared between cpus. + * + * Return: -ENOENT on failure to find table, or 0 on success + */ +int cache_setup_acpi(unsigned int cpu) +{ + struct acpi_table_header *table; + acpi_status status; + + pr_debug("Cache Setup ACPI cpu %d\n", cpu); + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + return -ENOENT; + } + + cache_setup_acpi_cpu(table, cpu); + acpi_put_table(table); + + return status; +} From patchwork Fri Dec 1 22:23:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120409 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1707676qgn; Fri, 1 Dec 2017 14:26:18 -0800 (PST) X-Google-Smtp-Source: AGs4zMboNTkRVfK8MQxfaamueX9AzfpiPrfNAQRywU6KtHCZew26ungbSVHBnoD+0Ph8xxcGtTCZ X-Received: by 10.159.252.76 with SMTP id t12mr7645892plz.323.1512167178362; Fri, 01 Dec 2017 14:26:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167178; cv=none; d=google.com; s=arc-20160816; b=TbgKQB0IS6PsdmrYHXXgMOsj3WCankI0rnrJTeY/4clp3x0TG0C8hSCFiH8+DbYRXi XKFLhqZrUX14CmUxPI3ke8lXvMyandyE6akbzQ/m1v+14/wIY+Hy9jYsMxV8hu/2PJsn hZ8Eb1iRCQ3dU9c1vvJHEyF93reZvo6PWOqwt13AJDPPzdCGIqfbu7I0u7hKVGKl22mM c4ockfS3QjzC2+QV4LLp7K6U92AOZ9ESu45V2VeA3y60GNx6Gq5TyZ1Jm+P+PDlT3iry cTHrUMsV6d6bktlD0fw4dkQ1FCq1CXP478EVsJXutvTG0Pwa27Y5ebgHzKW0/EjOFZWc Zy7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=75jZjnx9IKvykd4+JfVGN32A5LcJNy/yC5vElPMzYXk=; b=l72AGpCgi+ukwH5awe4eFqGsZELJg9+0ZyUsGR/7a5CpoYw7ljuZHUXWW0odFF8kna 8mND5c1ZGZMC6Ih6OKlfEdSLCPLiW+9jHK0tThGZw+XwWZ0Gos+2EHDLivJ2tJqGsoZr jClJV1lTaH8MbwzQpL3vEk8nEStWTmtyhpyfC8xkBbJlhfEHpwd9o4VI/pQZyP0PGO3o kO0GjPvABulkhUM4qQFxd8R+pb0gBw4ETfniz5of42qM3VkiaFB17BjMuzp0MSzraFPu YjDTy9TDuvh0M59XQfll37uSBMannYgBWSPN/bP9U/w0qAiJNWVBSUYFMCxlkkuWTPAg wXlA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 10si5362076pga.176.2017.12.01.14.26.18; Fri, 01 Dec 2017 14:26:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752189AbdLAW0P (ORCPT + 28 others); Fri, 1 Dec 2017 17:26:15 -0500 Received: from foss.arm.com ([217.140.101.70]:47040 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751562AbdLAWX5 (ORCPT ); Fri, 1 Dec 2017 17:23:57 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A9F6715BE; Fri, 1 Dec 2017 14:23:56 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C502B3F246; Fri, 1 Dec 2017 14:23:55 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 3/9] ACPI: Enable PPTT support on ARM64 Date: Fri, 1 Dec 2017 16:23:24 -0600 Message-Id: <20171201222330.18863-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that we have a PPTT parser, in preparation for its use on arm64, lets build it. Signed-off-by: Jeremy Linton --- arch/arm64/Kconfig | 1 + drivers/acpi/Kconfig | 3 +++ drivers/acpi/Makefile | 1 + 3 files changed, 5 insertions(+) -- 2.13.5 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a93339f5178f..e62fd1e08c1f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -7,6 +7,7 @@ config ARM64 select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ACPI_MCFG if ACPI select ACPI_SPCR_TABLE if ACPI + select ACPI_PPTT if ACPI select ARCH_CLOCKSOURCE_DATA select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEVMEM_IS_ALLOWED diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 46505396869e..df7aebf0af0e 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -545,6 +545,9 @@ config ACPI_CONFIGFS if ARM64 source "drivers/acpi/arm64/Kconfig" + +config ACPI_PPTT + bool endif config TPS68470_PMIC_OPREGION diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 41954a601989..b6056b566df4 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -87,6 +87,7 @@ obj-$(CONFIG_ACPI_BGRT) += bgrt.o obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_acpi.o obj-$(CONFIG_ACPI_SPCR_TABLE) += spcr.o obj-$(CONFIG_ACPI_DEBUGGER_USER) += acpi_dbg.o +obj-$(CONFIG_ACPI_PPTT) += pptt.o # processor has its own "processor." module_param namespace processor-y := processor_driver.o From patchwork Fri Dec 1 22:23:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120403 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1705991qgn; Fri, 1 Dec 2017 14:24:03 -0800 (PST) X-Google-Smtp-Source: AGs4zMZR0LcBzD6vrH8lpADJGWERoLR86LNTkMoxoAevldUuBDOfJ8OMqYBtD1MeqSLgj72etbAi X-Received: by 10.99.127.25 with SMTP id a25mr7182815pgd.10.1512167043875; Fri, 01 Dec 2017 14:24:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167043; cv=none; d=google.com; s=arc-20160816; b=rotUBklrnOouurxT1H9Wy00BU5E9Qfr8RPxoYWWd4zTNNbB9egP4gfnQ8q8CIf4pHg DhmSF4PqtNJso9BrloHxPmBWiY3Ar/93DZTm/GsVQbl+mfyNqEWzTbFAieC8f5x9nKnT tRA7f+WPGWKi0HRj8OLzi+QNekdVVOvWFRdSUnGog/yDLW6yHG2yf6WvGllm8SrvQ5YP qZdmiqvHuTgpWhVjEr01HXYQZ6AeWeSQSiXhU/DgXOAVIT5StrF8H3xFpon3ocl4NNyc Z/lVcvD+UpoxiEIxDObKx4i1IbeB3atXwBjxhk4pL9EQFNRoqO0VW+06H1ItXwtpIXJY 10iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=PjOYFjQ7z8nQAwMhBcMkd7ArEJ/MpgWc/hpZ9IPNmGE=; b=OpKyHYXmCsFC5hKNLqj7nHY2A0wAnV8fT8uV+zaMsX7p4BzqsG7ebS4VpU6fyCNzTz 36CBFl9C5xrUbxL+b167mHM9Nh8yJnF9XlK57s+87gEDVfTXO4eHxUkuTJN6ejkTHP4h r7W279bXv59bj0PPkbIhQUCWdhdc3q7XiMBoHjpgqZpvWtWH1bSe+7O3a+zPeaTaBWQh 9A79bf00GmUSZzwxPA9dTvr0eEl7XEiRwh49dTsewL1ER441yEzL5/jXnLTivucCpOKT wJQgK8PUOvuwicxtRdUwU5AcO6YkAJLuxeJTooH6YpIts58nYT6hh4NQOFM+y+s4ttDk 8+9A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s189si5460375pgb.104.2017.12.01.14.24.03; Fri, 01 Dec 2017 14:24:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751745AbdLAWYC (ORCPT + 28 others); Fri, 1 Dec 2017 17:24:02 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:47056 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751560AbdLAWYA (ORCPT ); Fri, 1 Dec 2017 17:24:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D1251610; Fri, 1 Dec 2017 14:23:59 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B7F113F246; Fri, 1 Dec 2017 14:23:58 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 4/9] drivers: base cacheinfo: Add support for ACPI based firmware tables Date: Fri, 1 Dec 2017 16:23:25 -0600 Message-Id: <20171201222330.18863-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a entry to to struct cacheinfo to maintain a reference to the PPTT node which can be used to match identical caches across cores. Also stub out cache_setup_acpi() so that individual architectures can enable ACPI topology parsing. Signed-off-by: Jeremy Linton --- drivers/acpi/pptt.c | 1 + drivers/base/cacheinfo.c | 20 ++++++++++++++------ include/linux/cacheinfo.h | 13 ++++++++++++- 3 files changed, 27 insertions(+), 7 deletions(-) -- 2.13.5 diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index 0f8a1631af33..a35e457cefb7 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -329,6 +329,7 @@ static void update_cache_properties(struct cacheinfo *this_leaf, { int valid_flags = 0; + this_leaf->firmware_node = cpu_node; if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) { this_leaf->size = found_cache->size; valid_flags++; diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index eb3af2739537..ba89f9310e6f 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -86,7 +86,10 @@ static int cache_setup_of_node(unsigned int cpu) static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, struct cacheinfo *sib_leaf) { - return sib_leaf->of_node == this_leaf->of_node; + if (acpi_disabled) + return sib_leaf->of_node == this_leaf->of_node; + else + return sib_leaf->firmware_node == this_leaf->firmware_node; } /* OF properties to query for a given cache type */ @@ -215,6 +218,11 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, } #endif +int __weak cache_setup_acpi(unsigned int cpu) +{ + return -ENOTSUPP; +} + static int cache_shared_cpu_map_setup(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); @@ -225,11 +233,11 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) if (this_cpu_ci->cpu_map_populated) return 0; - if (of_have_populated_dt()) + if (!acpi_disabled) + ret = cache_setup_acpi(cpu); + else if (of_have_populated_dt()) ret = cache_setup_of_node(cpu); - else if (!acpi_disabled) - /* No cache property/hierarchy support yet in ACPI */ - ret = -ENOTSUPP; + if (ret) return ret; @@ -286,7 +294,7 @@ static void cache_shared_cpu_map_remove(unsigned int cpu) static void cache_override_properties(unsigned int cpu) { - if (of_have_populated_dt()) + if (acpi_disabled && of_have_populated_dt()) return cache_of_override_properties(cpu); } diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 3d9805297cda..7ebff157ae6c 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -37,6 +37,8 @@ enum cache_type { * @of_node: if devicetree is used, this represents either the cpu node in * case there's no explicit cache node or the cache node itself in the * device tree + * @firmware_node: When not using DT, this may contain pointers to other + * firmware based values. Particularly ACPI/PPTT unique values. * @disable_sysfs: indicates whether this node is visible to the user via * sysfs or not * @priv: pointer to any private data structure specific to particular @@ -65,8 +67,8 @@ struct cacheinfo { #define CACHE_ALLOCATE_POLICY_MASK \ (CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE) #define CACHE_ID BIT(4) - struct device_node *of_node; + void *firmware_node; bool disable_sysfs; void *priv; }; @@ -99,6 +101,15 @@ int func(unsigned int cpu) \ struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); int init_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); +int cache_setup_acpi(unsigned int cpu); +int acpi_find_last_cache_level(unsigned int cpu); +#ifndef CONFIG_ACPI +int acpi_find_last_cache_level(unsigned int cpu) +{ + /*ACPI kernels should be built with PPTT support*/ + return 0; +} +#endif const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf); From patchwork Fri Dec 1 22:23:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120408 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1707137qgn; Fri, 1 Dec 2017 14:25:36 -0800 (PST) X-Google-Smtp-Source: AGs4zMaAd7z1NWeOgRxR9nlWlccPYufv++5ZHZ4DyhZoDpwBQ3XvLMOkQNsK5nzmn6LlF3+H43tp X-Received: by 10.84.240.1 with SMTP id y1mr7659023plk.391.1512167136299; Fri, 01 Dec 2017 14:25:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167136; cv=none; d=google.com; s=arc-20160816; b=B/wavTXBjCqP6uebRRncVJKxSGzsU2nFMbp6TrZ9aGGzJWKvCTsDXionVIfNhcOkHe PKTdxtVo5oQ8mwtGzRueugjlL7Qt559PQ/7+/T/p2Z+t8xScBzO2zIlx6UvfBwOQ3kPa fFBDeFjGSm6Y3XqXVOJCkgqNqsCD0eDejFaOyd16WgYaSlMtWxzN8un9I1vf51e4vn30 6ip4xc+Bo2TOQDvgaY1ZXD1Fx7rs4W5petrYHQPYXCzwvTX/9ZDjOeh9rvfuL/incKY6 XT7QJcsBZhh+WO4JEe1iMUAAiHdctOqo+sFNE7xxoTaOgxCHiFI/zd28W0sw8If5S1e+ QPgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Jn5QzMcAOiQk3vK8+6S2qzrFf4rulolq+gsNTRBEJN4=; b=vLqK36t6BzBRLNfvA9KdbtK8YlUdcb90nz29tRiOU/pHE9wfOba3I0DhzPEnFYguby cspTlw5c86JN9LRV8+f82ulvRPxx4mJ1gG7SXm6FZZtL9M5/hbWbWplHHIdytJV36ALy vIr05eLwS3HGwUmZ0za0GpXIv9UEIXddkFh3tn/gcVfUx2LXLp5D+aLP5tmawWytH8jx 9sFwbi/xC4pdZZbdEtCAUZYcate5urskbz8/5eqbWcv9gRSrTisTxDXMGYRTWLb3m3VG JIAsLle24Pvz43ZyaqN2qUaJJDp6K1bhH8ZirDjxKdsb5prlg8y4kvNFYBFPjA/cHzql +tVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b16si5810435pff.393.2017.12.01.14.25.36; Fri, 01 Dec 2017 14:25:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752127AbdLAWZd (ORCPT + 28 others); Fri, 1 Dec 2017 17:25:33 -0500 Received: from foss.arm.com ([217.140.101.70]:47090 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751682AbdLAWYB (ORCPT ); Fri, 1 Dec 2017 17:24:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1AD761650; Fri, 1 Dec 2017 14:24:01 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 350243F246; Fri, 1 Dec 2017 14:24:00 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 5/9] arm64: Add support for ACPI based firmware tables Date: Fri, 1 Dec 2017 16:23:26 -0600 Message-Id: <20171201222330.18863-6-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The /sys cache entries should support ACPI/PPTT generated cache topology information. Lets detect ACPI systems and call an arch specific cache_setup_acpi() routine to update the hardware probed cache topology. For arm64, if ACPI is enabled, determine the max number of cache levels and populate them using the PPTT table if one is available. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cacheinfo.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 2.13.5 diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 380f2e2fbed5..0bf0a835122f 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -17,6 +17,7 @@ * along with this program. If not, see . */ +#include #include #include @@ -46,7 +47,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, static int __init_cache_level(unsigned int cpu) { - unsigned int ctype, level, leaves, of_level; + unsigned int ctype, level, leaves, fw_level; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { @@ -59,15 +60,19 @@ static int __init_cache_level(unsigned int cpu) leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; } - of_level = of_find_last_cache_level(cpu); - if (level < of_level) { + if (acpi_disabled) + fw_level = of_find_last_cache_level(cpu); + else + fw_level = acpi_find_last_cache_level(cpu); + + if (level < fw_level) { /* * some external caches not specified in CLIDR_EL1 * the information may be available in the device tree * only unified external caches are considered here */ - leaves += (of_level - level); - level = of_level; + leaves += (fw_level - level); + level = fw_level; } this_cpu_ci->num_levels = level; From patchwork Fri Dec 1 22:23:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120404 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1706072qgn; Fri, 1 Dec 2017 14:24:08 -0800 (PST) X-Google-Smtp-Source: AGs4zMYmYydS3/G+naVcg/ne99ZBjNRt8BQfhOfoo69gJ0dFkmKM7GMMwrjcVx78XbGYdzX3xhgx X-Received: by 10.101.83.201 with SMTP id z9mr7116021pgr.181.1512167048679; Fri, 01 Dec 2017 14:24:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167048; cv=none; d=google.com; s=arc-20160816; b=b14IEqjPp0qed6uumytptTgUiVgEJNvrdPgc1cwKdyOM6vbnp+5Vmkk7UVmQXTU9sp o0e7xsQTps1TCcfPxaA1WAKNmgZCxjfQG23Mk8yH3bDtTjk3WQuSbaqBHOFixCLCzEQU 5GDQ6CtICqoi+ce5X1MNqY4pNEqwFkYmEVH4M1D6J5jqvV2tUryO2Ryr+bloB1WM3shX 1sweHTeW/8gYkjKErnuVeNyLZss1DQLEIh+zjIbUAn8eVxSuK9W9lAjKBTYDa2rKX/jY 2kqA5klzsY1W3xgRAIdvcHyBRyfDH9eXioycaUN2Gx/jyKjcCopZP2hN/EIkWAaf9lPi BE9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=xd7lWTMS7Ws/KDK7Rb1ONxvvdaDYzm6u8dFVSrLeq/c=; b=RFrWRaaOolxhKSlsFgWsZAX0aQZpy+vGFPYcHQxg3E/v8HIcNTPUHPVHX4LIrZ49qQ iysHhZLp1TwUajzsfsUwOnls2m6qZ0C2cUe53tyw+rpUW4pzhsdijui91IssAwti3DUV 6JQ81mHDQbctUPySC5ZFwB9OV8AAzaSOjLdUvLP7SsMoL9uJ/eS0XVUqDep5IffNR8aF dIDSp9JsZc2sjflnvqEzxLwmrmGFRrhwdALd97i4gcAh1N+ggeoKgAnY6MKYeiS68MD+ 7S1HCifVx5UlMkEZhsE+xyXxoAjFEWRoBwX5Z1mB9o/WIH0zCPukcj4hOGN1C2Y6vfbc lMBA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si5623671plu.228.2017.12.01.14.24.08; Fri, 01 Dec 2017 14:24:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751810AbdLAWYG (ORCPT + 28 others); Fri, 1 Dec 2017 17:24:06 -0500 Received: from foss.arm.com ([217.140.101.70]:47098 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751680AbdLAWYC (ORCPT ); Fri, 1 Dec 2017 17:24:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A68B165C; Fri, 1 Dec 2017 14:24:02 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9520B3F246; Fri, 1 Dec 2017 14:24:01 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 6/9] ACPI/PPTT: Add topology parsing code Date: Fri, 1 Dec 2017 16:23:27 -0600 Message-Id: <20171201222330.18863-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PPTT can be used to determine the groupings of CPU's at given levels in the system. Lets add a few routines to the PPTT parsing code to return a unique id for each unique level in the processor hierarchy. This can then be matched to build thread/core/cluster/die/package/etc mappings for each processing element in the system. Signed-off-by: Jeremy Linton --- drivers/acpi/pptt.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) -- 2.13.5 diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index a35e457cefb7..b9b7b8b8ad21 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -412,6 +412,79 @@ static void cache_setup_acpi_cpu(struct acpi_table_header *table, } } +/* Passing level values greater than this will result in search termination */ +#define PPTT_ABORT_PACKAGE 0xFF + +/* + * Given an acpi_pptt_processor node, walk up until we identify the + * package that the node is associated with, or we run out of levels + * to request or the search is terminated with a flag match + * The level parameter also serves to limit possible loops within the tree. + */ +static struct acpi_pptt_processor *acpi_find_processor_package_id( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu, + int level, int flag) +{ + struct acpi_pptt_processor *prev_node; + + while (cpu && level) { + if (cpu->flags & flag) + break; + pr_debug("level %d\n", level); + prev_node = fetch_pptt_node(table_hdr, cpu->parent); + if (prev_node == NULL) + break; + cpu = prev_node; + level--; + } + return cpu; +} + +/* + * Get a unique value given a cpu, and a topology level, that can be + * matched to determine which cpus share common topological features + * at that level. + */ +static int topology_get_acpi_cpu_tag(struct acpi_table_header *table, + unsigned int cpu, int level, int flag) +{ + struct acpi_pptt_processor *cpu_node; + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); + if (cpu_node) { + cpu_node = acpi_find_processor_package_id(table, cpu_node, + level, flag); + /* Only the first level has a guaranteed id */ + if (level == 0) + return cpu_node->acpi_processor_id; + return (int)((u8 *)cpu_node - (u8 *)table); + } + pr_err_once("PPTT table found, but unable to locate core for %d\n", + cpu); + return -ENOENT; +} + +static int find_acpi_cpu_topology_tag(unsigned int cpu, int level, int flag) +{ + struct acpi_table_header *table; + acpi_status status; + int retval; + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cpu topology may be inaccurate\n"); + return -ENOENT; + } + retval = topology_get_acpi_cpu_tag(table, cpu, level, flag); + pr_debug("Topology Setup ACPI cpu %d, level %d ret = %d\n", + cpu, level, retval); + acpi_put_table(table); + + return retval; +} + /** * acpi_find_last_cache_level() - Determines the number of cache levels for a PE * @cpu: Kernel logical cpu number @@ -475,3 +548,45 @@ int cache_setup_acpi(unsigned int cpu) return status; } + +/** + * find_acpi_cpu_topology() - Determine a unique topology value for a given cpu + * @cpu: Kernel logical cpu number + * @level: The topological level for which we would like a unique ID + * + * Determine a topology unique ID for each thread/core/cluster/mc_grouping + * /socket/etc. This ID can then be used to group peers, which will have + * matching ids. + * + * The search terminates when either the requested level is found or + * we reach a root node. Levels beyond the termination point will return the + * same unique ID. The unique id for level 0 is the acpi processor id. All + * other levels beyond this use a generated value to uniquely identify + * a topological feature. + * + * Return: -ENOENT if the PPTT doesn't exist, or the cpu cannot be found. + * Otherwise returns a value which represents a unique topological feature. + */ +int find_acpi_cpu_topology(unsigned int cpu, int level) +{ + return find_acpi_cpu_topology_tag(cpu, level, 0); +} + +/** + * find_acpi_cpu_topology_package() - Determine a unique cpu package value + * @cpu: Kernel logical cpu number + * + * Determine a topology unique package ID for the given cpu. + * This ID can then be used to group peers, which will have matching ids. + * + * The search terminates when either a level is found with the PHYSICAL_PACKAGE + * flag set or we reach a root node. + * + * Return: -ENOENT if the PPTT doesn't exist, or the cpu cannot be found. + * Otherwise returns a value which represents the package for this cpu. + */ +int find_acpi_cpu_topology_package(unsigned int cpu) +{ + return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE, + ACPI_PPTT_PHYSICAL_PACKAGE); +} From patchwork Fri Dec 1 22:23:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120407 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1706628qgn; Fri, 1 Dec 2017 14:24:59 -0800 (PST) X-Google-Smtp-Source: AGs4zMbXCrITTsJtrERjNPL4Rqs3U/L7oo2+S1pfL9adH1egw0+xvE1VdjhjLn4W6NbgXKVt24ry X-Received: by 10.84.170.132 with SMTP id j4mr7658634plb.316.1512167099105; Fri, 01 Dec 2017 14:24:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167099; cv=none; d=google.com; s=arc-20160816; b=F44j3Bv6hQL2Qc5yQeUkrkOZdBg3KU8B6u64qHr4i2vvy4A191ZQ0LXG7OaOEDG3om bXoQq3Vnud/QVXNQknu0rcSuhCCnLhVkjgV2ITJZOB/I9Kj0oKGPRgLave2GnW9apAHT aG/b08XGWuC5BKj5ADF1WbMee4sfhJgfUClfPyv5bUPm0xSQ3lSBDEio5yD8NNiILR6i GAcMQQcN+M0m5HNyA49iZxgMEanLV4G4IzKpvFy/tsAGgulASMvnII36Scb2IMvgqni5 RZk+mHvX4ftg8uu8INXuMXlfmPlqjqmZ2wBUGAnMsJ4NudZ6Cng+l/NAfxc7ud/HJO56 rovQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=VORP9fwpPeCBxh17feb1Zgh/5jfaQmqjh6acX2EI20U=; b=LGQgvZBIP+DrI3TeWtCqZS39DQeeif1DTHgZjgdZAExLa78tuyp5W6+rnIVtEJSmSX 3mzcayrw47O2JKvbpQg5zERs4o6raNgLqgEc18dUqdvQQ2AbFfidecq3zZYY1Xds709F VsTctWUJbwDANWbSVY0JjtuwsuP49NGW9kv1dkE2inh6B/i/5qaixNuVuBdIKd3/J9HZ hx2yi/dDtCbIvLaH5NSvUBud/iK6Unw1mzgsQyh7R2mK1T0Je3DUSLvRf9C3rftnRLAs gWQLi51M6/STA4P6cH3YhO3btcDgq9cFpo2sSD5PshvwVj/Bcnw5QAojgTS71Se7ZGpb p3ng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t3si5755385plr.284.2017.12.01.14.24.58; Fri, 01 Dec 2017 14:24:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752012AbdLAWY5 (ORCPT + 28 others); Fri, 1 Dec 2017 17:24:57 -0500 Received: from foss.arm.com ([217.140.101.70]:47132 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751752AbdLAWYE (ORCPT ); Fri, 1 Dec 2017 17:24:04 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1673165D; Fri, 1 Dec 2017 14:24:03 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EC3D53F246; Fri, 1 Dec 2017 14:24:02 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 7/9] arm64: Topology, rename cluster_id Date: Fri, 1 Dec 2017 16:23:28 -0600 Message-Id: <20171201222330.18863-8-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Lets match the name of the arm64 topology field to the kernel macro that uses it. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/topology.h | 4 ++-- arch/arm64/kernel/topology.c | 27 ++++++++++++++------------- 2 files changed, 16 insertions(+), 15 deletions(-) -- 2.13.5 diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index c4f2d50491eb..118136268f66 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -7,14 +7,14 @@ struct cpu_topology { int thread_id; int core_id; - int cluster_id; + int physical_id; cpumask_t thread_sibling; cpumask_t core_sibling; }; extern struct cpu_topology cpu_topology[NR_CPUS]; -#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) +#define topology_physical_package_id(cpu) (cpu_topology[cpu].physical_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 8d48b233e6ce..74a8a5173a35 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -51,7 +51,7 @@ static int __init get_cpu_for_node(struct device_node *node) return -1; } -static int __init parse_core(struct device_node *core, int cluster_id, +static int __init parse_core(struct device_node *core, int physical_id, int core_id) { char name[10]; @@ -67,7 +67,7 @@ static int __init parse_core(struct device_node *core, int cluster_id, leaf = false; cpu = get_cpu_for_node(t); if (cpu >= 0) { - cpu_topology[cpu].cluster_id = cluster_id; + cpu_topology[cpu].physical_id = physical_id; cpu_topology[cpu].core_id = core_id; cpu_topology[cpu].thread_id = i; } else { @@ -89,7 +89,7 @@ static int __init parse_core(struct device_node *core, int cluster_id, return -EINVAL; } - cpu_topology[cpu].cluster_id = cluster_id; + cpu_topology[cpu].physical_id = physical_id; cpu_topology[cpu].core_id = core_id; } else if (leaf) { pr_err("%pOF: Can't get CPU for leaf core\n", core); @@ -105,7 +105,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth) bool leaf = true; bool has_cores = false; struct device_node *c; - static int cluster_id __initdata; + static int physical_id __initdata; int core_id = 0; int i, ret; @@ -144,7 +144,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth) } if (leaf) { - ret = parse_core(c, cluster_id, core_id++); + ret = parse_core(c, physical_id, core_id++); } else { pr_err("%pOF: Non-leaf cluster with core %s\n", cluster, name); @@ -162,7 +162,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth) pr_warn("%pOF: empty cluster\n", cluster); if (leaf) - cluster_id++; + physical_id++; return 0; } @@ -198,7 +198,7 @@ static int __init parse_dt_topology(void) * only mark cores described in the DT as possible. */ for_each_possible_cpu(cpu) - if (cpu_topology[cpu].cluster_id == -1) + if (cpu_topology[cpu].physical_id == -1) ret = -EINVAL; out_map: @@ -228,7 +228,7 @@ static void update_siblings_masks(unsigned int cpuid) for_each_possible_cpu(cpu) { cpu_topo = &cpu_topology[cpu]; - if (cpuid_topo->cluster_id != cpu_topo->cluster_id) + if (cpuid_topo->physical_id != cpu_topo->physical_id) continue; cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); @@ -249,7 +249,7 @@ void store_cpu_topology(unsigned int cpuid) struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; u64 mpidr; - if (cpuid_topo->cluster_id != -1) + if (cpuid_topo->physical_id != -1) goto topology_populated; mpidr = read_cpuid_mpidr(); @@ -263,19 +263,19 @@ void store_cpu_topology(unsigned int cpuid) /* Multiprocessor system : Multi-threads per core */ cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); - cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | + cpuid_topo->physical_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8; } else { /* Multiprocessor system : Single-thread per core */ cpuid_topo->thread_id = -1; cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); - cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | + cpuid_topo->physical_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16; } pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", - cpuid, cpuid_topo->cluster_id, cpuid_topo->core_id, + cpuid, cpuid_topo->physical_id, cpuid_topo->core_id, cpuid_topo->thread_id, mpidr); topology_populated: @@ -291,7 +291,7 @@ static void __init reset_cpu_topology(void) cpu_topo->thread_id = -1; cpu_topo->core_id = 0; - cpu_topo->cluster_id = -1; + cpu_topo->physical_id = -1; cpumask_clear(&cpu_topo->core_sibling); cpumask_set_cpu(cpu, &cpu_topo->core_sibling); @@ -300,6 +300,7 @@ static void __init reset_cpu_topology(void) } } + void __init init_cpu_topology(void) { reset_cpu_topology(); From patchwork Fri Dec 1 22:23:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120406 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1706460qgn; Fri, 1 Dec 2017 14:24:41 -0800 (PST) X-Google-Smtp-Source: AGs4zMaFfaYMSI7D0PnsFZ0GQNCm+msXLX76w9wJfO/cBnY+o6m/jpGxUhYheW+6WAikjJcc3WZR X-Received: by 10.98.18.88 with SMTP id a85mr11674115pfj.141.1512167081766; Fri, 01 Dec 2017 14:24:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167081; cv=none; d=google.com; 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[209.132.180.67]) by mx.google.com with ESMTP id u73si5836459pfi.245.2017.12.01.14.24.41; Fri, 01 Dec 2017 14:24:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751941AbdLAWYj (ORCPT + 28 others); Fri, 1 Dec 2017 17:24:39 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:47138 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751756AbdLAWYF (ORCPT ); Fri, 1 Dec 2017 17:24:05 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BC7C1688; Fri, 1 Dec 2017 14:24:05 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 563103F246; Fri, 1 Dec 2017 14:24:04 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton Subject: [PATCH v5 8/9] arm64: topology: Enable ACPI/PPTT based CPU topology. Date: Fri, 1 Dec 2017 16:23:29 -0600 Message-Id: <20171201222330.18863-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Propagate the topology information from the PPTT tree to the cpu_topology array. We can get the thread id, core_id and cluster_id by assuming certain levels of the PPTT tree correspond to those concepts. The package_id is flagged in the tree and can be found by calling find_acpi_cpu_topology_package() which terminates its search when it finds an ACPI node flagged as the physical package. If the tree doesn't contain enough levels to represent all of the requested levels then the root node will be returned for all subsequent levels. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/topology.c | 47 +++++++++++++++++++++++++++++++++++++++++++- include/linux/topology.h | 2 ++ 2 files changed, 48 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 74a8a5173a35..198714aca9e8 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -11,6 +11,7 @@ * for more details. */ +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -300,6 +302,47 @@ static void __init reset_cpu_topology(void) } } +#ifdef CONFIG_ACPI +/* + * Propagate the topology information of the processor_topology_node tree to the + * cpu_topology array. + */ +static int __init parse_acpi_topology(void) +{ + u64 is_threaded; + int cpu; + int topology_id; + + is_threaded = read_cpuid_mpidr() & MPIDR_MT_BITMASK; + + for_each_possible_cpu(cpu) { + topology_id = find_acpi_cpu_topology(cpu, 0); + if (topology_id < 0) + return topology_id; + + if (is_threaded) { + cpu_topology[cpu].thread_id = topology_id; + topology_id = find_acpi_cpu_topology(cpu, 1); + cpu_topology[cpu].core_id = topology_id; + topology_id = find_acpi_cpu_topology_package(cpu); + cpu_topology[cpu].physical_id = topology_id; + } else { + cpu_topology[cpu].thread_id = -1; + cpu_topology[cpu].core_id = topology_id; + topology_id = find_acpi_cpu_topology_package(cpu); + cpu_topology[cpu].physical_id = topology_id; + } + } + return 0; +} + +#else +static int __init parse_acpi_topology(void) +{ + /*ACPI kernels should be built with PPTT support*/ + return -EINVAL; +} +#endif void __init init_cpu_topology(void) { @@ -309,6 +352,8 @@ void __init init_cpu_topology(void) * Discard anything that was parsed if we hit an error so we * don't use partial information. */ - if (of_have_populated_dt() && parse_dt_topology()) + if ((!acpi_disabled) && parse_acpi_topology()) + reset_cpu_topology(); + else if (of_have_populated_dt() && parse_dt_topology()) reset_cpu_topology(); } diff --git a/include/linux/topology.h b/include/linux/topology.h index cb0775e1ee4b..170ce87edd88 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -43,6 +43,8 @@ if (nr_cpus_node(node)) int arch_update_cpu_topology(void); +int find_acpi_cpu_topology(unsigned int cpu, int level); +int find_acpi_cpu_topology_package(unsigned int cpu); /* Conform to ACPI 2.0 SLIT distance definitions */ #define LOCAL_DISTANCE 10 From patchwork Fri Dec 1 22:23:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 120405 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1706151qgn; Fri, 1 Dec 2017 14:24:13 -0800 (PST) X-Google-Smtp-Source: AGs4zMYR+w0xlx1DNLAqd1csnaoiTn55IRZHXFf+QYypGG/DilcacQCqd1RYiYWarjDKzw8lIrXc X-Received: by 10.159.198.134 with SMTP id g6mr7586534plo.42.1512167053877; Fri, 01 Dec 2017 14:24:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512167053; cv=none; d=google.com; s=arc-20160816; b=o9YIu7IsRneiOrqkar2Rc2MSiLxVpZ1eRicefmD2BHhvEai1VHeNeGWgD+immV07fg P8Cq2XmonbLZqT3SHIVCQouZWsGFPMt9BJWNeJnThN/8rE5dTtY6asytvCLodWPRADga xRI4+ojfnOwLF0+8QPoH7hcugxW4FUjc3zgqgS4OtCxRJD6g+ApEiTtZub0QgtF6aQAl jGGvxnaX+X3LVcHAkuoApIGpKZNlCmKBsNQHjw0+w6F/dmLkX3ckyhYBrRkCfGKN5b80 6gGt7eBBWU1bLgdj6AUzk6zlhMrgPPJypW1Aqj6BLXwoaAZKS4M0xkFFYJCYqtZHE7Ua d8Jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=H6arYo+q20MTgpvDcAB6MzxUA58BSwUfjErHomWl87M=; b=sOjOU9VcUt43Ns/Y3BcBNjcQJOBwB9nfCniKP0W4PTrTHzZCpmLxzz51NiEz6x2aiF GIE7WtHamo7Ekr4H5FngNKFBEfW37prqI44Zh3kCf2E6DaWmFQaEpDc+Twd70flNaii8 XHQ/h2HEYzM5dcBvXz8KrlfLLB8A7NxVRRoQqEGi0YkYz4mOVISIguv1DHOtr2Ld4i/2 Mi280+lRrRZfgkbiVDSe2wqKIzcgM0ZOJIHRe3XhOK3i7gVKeOo8pX4uAWggAwHgEJ+Z FdvzKNu3QpugcgOPUU9SRVRV30o7qFqai93qalzCeyVv4d5y+KCqkXm9sJo5i69iDSGn Pv3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p89si5817132pfd.36.2017.12.01.14.24.13; Fri, 01 Dec 2017 14:24:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751874AbdLAWYK (ORCPT + 28 others); Fri, 1 Dec 2017 17:24:10 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:47158 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751748AbdLAWYH (ORCPT ); Fri, 1 Dec 2017 17:24:07 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B380D169E; Fri, 1 Dec 2017 14:24:06 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BCC953F246; Fri, 1 Dec 2017 14:24:05 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, Jeremy Linton , Geoffrey Blake Subject: [PATCH v5 9/9] ACPI: Add PPTT to injectable table list Date: Fri, 1 Dec 2017 16:23:30 -0600 Message-Id: <20171201222330.18863-10-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171201222330.18863-1-jeremy.linton@arm.com> References: <20171201222330.18863-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add ACPI_SIG_PPTT to the table so initrd's can override the system topology. Signed-off-by: Geoffrey Blake Signed-off-by: Jeremy Linton --- drivers/acpi/tables.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 80ce2a7d224b..6d254450115b 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -456,7 +456,8 @@ static const char * const table_sigs[] = { ACPI_SIG_SLIC, ACPI_SIG_SPCR, ACPI_SIG_SPMI, ACPI_SIG_TCPA, ACPI_SIG_UEFI, ACPI_SIG_WAET, ACPI_SIG_WDAT, ACPI_SIG_WDDT, ACPI_SIG_WDRT, ACPI_SIG_DSDT, ACPI_SIG_FADT, ACPI_SIG_PSDT, - ACPI_SIG_RSDT, ACPI_SIG_XSDT, ACPI_SIG_SSDT, NULL }; + ACPI_SIG_RSDT, ACPI_SIG_XSDT, ACPI_SIG_SSDT, ACPI_SIG_PPTT, + NULL }; #define ACPI_HEADER_SIZE sizeof(struct acpi_table_header)