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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:14 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:06 +0000 Message-Id: <20171207161415.20380-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 01/10] ARM: remove unneeded gic.h inclusions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" gic.h is supposed to hold defines and prototypes for the hardware side of the GIC interrupt controller. A lot of parts in Xen should not be bothered with that, as they either only care about the VGIC or use more generic interfaces. Remove unneeded inclusions of gic.h from files where they are actually not needed. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/domain_build.c | 1 - xen/arch/arm/p2m.c | 1 - xen/arch/arm/platforms/vexpress.c | 1 - xen/arch/arm/platforms/xgene-storm.c | 1 - xen/arch/arm/time.c | 1 - xen/arch/arm/traps.c | 1 - xen/arch/arm/vpsci.c | 1 - xen/arch/arm/vtimer.c | 1 - 8 files changed, 8 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index c74f4dd69d..51e5c8d9f4 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -21,7 +21,6 @@ #include #include -#include #include #include #include "kernel.h" diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 417609ede2..7bf34aaa8c 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/xen/arch/arm/platforms/vexpress.c b/xen/arch/arm/platforms/vexpress.c index 39b6bcc70e..70839d676f 100644 --- a/xen/arch/arm/platforms/vexpress.c +++ b/xen/arch/arm/platforms/vexpress.c @@ -22,7 +22,6 @@ #include #include #include -#include #define DCC_SHIFT 26 #define FUNCTION_SHIFT 20 diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c index 3b007fe5ed..deb8479a49 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -22,7 +22,6 @@ #include #include #include -#include /* XGENE RESET Specific defines */ #define XGENE_RESET_ADDR 0x17000014UL diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 105c7410c7..36f640f0c1 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index f6f6de3691..ff3d6ff2aa 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -43,7 +43,6 @@ #include #include #include -#include #include #include #include diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 0e024f7578..cd724904ef 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 3f84893a74..f52a723a5f 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -24,7 +24,6 @@ #include #include -#include #include #include #include From patchwork Thu Dec 7 16:14:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121021 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556417qgn; Thu, 7 Dec 2017 08:16:45 -0800 (PST) X-Google-Smtp-Source: AGs4zMaSKE/gctrv5Z71vniwRQMe+h2+AkcxRUNDqqA1PhPhOE0TcSnDYKYGW9wprj1B64T1geJC X-Received: by 10.36.77.143 with SMTP id l137mr2129851itb.50.1512663405668; Thu, 07 Dec 2017 08:16:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663405; cv=none; d=google.com; s=arc-20160816; b=KCap18yiC59yqEJShUkaPr3yU4ILSbz6eC7v2Zd2GpzHx7iIQE716xMOmJjUi+35q4 6lFvfy39prCw8y1daWyRIotIJYjipb4wUDhQ7VQ/13tjx8HwnylM1eeIvK9e8jx6mNom DyzkNwTaDadgH6G86sNL6sxkhSyD2s0AuNSGRgVG8YYp/74e8OePuidRX6dqmp8tGNR1 ubea/77H+ORoH5DeUy9h7m89Sd0p1K4Ugywtlt8HdXptD6xmsCxD+YdvDo8OMzPU5TpN rs1myKWdLH5F6rI6PJa0SS/v3nnZ8p3h3TKUdIQgu7aD8yCXFGcztkgj7+3jFHTb2ugi E1RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=/eQRQZ1NqPgEej30PJMy6l46nIwopZ26kW0Dreye8Rg=; b=ldxU18esPKstQ6hVS2FSh2vsB6aSuglZgjozW+FyKOT40Su6vswVoT2Zy3Vgx0Qiqd ERWqn/9bhbYwoSwf2bHcy1MHQb+TjzJWJCZCqriO3ok1C/IUd+y762xfa0SLTftlfIQE pNVSiKLIjHg2v2e/N5nu46h20tW8sgnTMPCTB16JtE1WEXb/r7a3qLoSY3reC7PTEDKr IwE0v6DCsla2qigNFfkGIA4n2RbV9UnToG1fcEwYaJVvILIodw8SCIb1s2I88hvtMZoX PXEvUhZ4Z70gKoSpK7qN9PQIafNmHiFx4ZuXs46b5lwQikaWYxtBoxeJn+Q4ZSIPmBe2 bcZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=emoBooRc; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:15 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:07 +0000 Message-Id: <20171207161415.20380-3-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 02/10] ARM: vGIC: fix nr_irq definition X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The global variable "nr_irqs" is used for x86 and some common Xen code. To make the latter work easily for ARM, it was #defined to NR_IRQS. This not only violated the common habit of capitalizing macros, but also caused issues if one wanted to use a rather innocent "nr_irqs" as a local variable name or as a function parameter. Drop the optimization and make nr_irqs a normal variable for ARM also. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/irq.c | 2 ++ xen/include/asm-arm/irq.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index cbc7e6ebb8..7f133de549 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -27,6 +27,8 @@ #include #include +unsigned int __read_mostly nr_irqs = NR_IRQS; + static unsigned int local_irqs_type[NR_LOCAL_IRQS]; static DEFINE_SPINLOCK(local_irqs_type_lock); diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index 2de76d0f56..abc8f06a13 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -31,7 +31,7 @@ struct arch_irq_desc { /* LPIs are always numbered starting at 8192, so 0 is a good invalid case. */ #define INVALID_LPI 0 -#define nr_irqs NR_IRQS +extern unsigned int nr_irqs; #define nr_static_irqs NR_IRQS #define arch_hwdom_irqs(domid) NR_IRQS From patchwork Thu Dec 7 16:14:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121018 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556349qgn; Thu, 7 Dec 2017 08:16:42 -0800 (PST) X-Google-Smtp-Source: AGs4zMY0w18eiH7d6Y5aaGx9E2WZhmHXZW3NUlBdNmIq0bXGVW/2QEC2ei4tVKi/YTy9l6BD7HwN X-Received: by 10.107.7.224 with SMTP id g93mr3318859ioi.208.1512663402275; Thu, 07 Dec 2017 08:16:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663402; cv=none; d=google.com; s=arc-20160816; b=CEiWfVKRQR3DvBSBbcEgWYldt+zS/J5nCkpG1Gu0dBzSTfVb2vRyv9RcYivzqvnNEV b30/0fzvCxYWTcwXDpaEFcLZJ9kBIMYp5o3xonn1kLe7NCDHYCo7Sh+DF4mVIflUFD6B +bHwB/r/Zak2OkqbrSlKxaMI1WAAAbcFSIRZF31/itYNiP+07HIAt/SwqSdLxmod5MoD 57+Nnlwl5odqJPcj84Gd9vbaK0JwRWTOrM5FV7Uvfc5g0hrJa2CunFL8c09feGcqr7HU Go0YsnRenx5SdBBq+PL+3Uw+iU83Xb7/FPlH/nJNp6cyYz3WP7d9HO7eM8QvQs+ooApJ UOAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=2G0xnFIbxr12DtnY7sMsrBGkvbvlXgZUsbaC+W+p5ZE=; b=MUGNNCT5AINyK7AsRYK0RzF96eShiWOavUCjb1NjyKm9g8dx4Fsn88idRR9THZg/Zu 0FKtNhbgzXl2G7iK8JhDYgb7av5FujChN00fKNlup8DstcDHVZcBc9O3XFOh4VVC0khP zNv9tEOvSNyLY4Gw7Xer35GY5IByvS1jej032k28aZyjIkKh6mVptanoimtxQgVU9lFi hxivyhEhAAqV8gATp2J1FB64r3VJ8r7k3B/Vn5JeQtMtKxVl7sBUTS3lDH1BSvDKxDe1 hmSd2NigqIHzBoXVY6oVJwo/+ioL+WDPbdFbRkFzxDeRVpS7/UB0umVPG+/m+sP4FgT6 Lm1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SwXxOt/p; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:16 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:08 +0000 Message-Id: <20171207161415.20380-4-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 03/10] ARM: VGIC: move gic_remove_irq_from_queues() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" gic_remove_irq_from_queues() was not only misnamed, it also has the wrong abstraction, as it should not live in gic.c. Move it into vgic.c and vgic.h, where it belongs to, and rename it on the way. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic.c | 9 --------- xen/arch/arm/vgic-v3-its.c | 4 ++-- xen/arch/arm/vgic.c | 11 ++++++++++- xen/include/asm-arm/gic.h | 1 - xen/include/asm-arm/vgic.h | 1 + 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index ed363f6c37..bac8ada2bb 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -411,15 +411,6 @@ void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p) list_del_init(&p->lr_queue); } -void gic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p) -{ - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); - list_del_init(&p->inflight); - gic_remove_from_lr_pending(v, p); -} - void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) { struct pending_irq *n = irq_to_pending(v, virtual_irq); diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 72a5c70656..d8fa44258d 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -381,7 +381,7 @@ static int its_handle_clear(struct virt_its *its, uint64_t *cmdptr) * have no active state, we don't need to care about this here. */ if ( !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) - gic_remove_irq_from_queues(vcpu, p); + vgic_remove_irq_from_queues(vcpu, p); spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); ret = 0; @@ -619,7 +619,7 @@ static int its_discard_event(struct virt_its *its, } /* Cleanup the pending_irq and disconnect it from the LPI. */ - gic_remove_irq_from_queues(vcpu, p); + vgic_remove_irq_from_queues(vcpu, p); vgic_init_pending_irq(p, INVALID_LPI); spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index d8acbbeaaa..6e933a86d3 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -281,7 +281,7 @@ bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq) /* If the IRQ is still lr_pending, re-inject it to the new vcpu */ if ( !list_empty(&p->lr_queue) ) { - gic_remove_irq_from_queues(old, p); + vgic_remove_irq_from_queues(old, p); irq_set_affinity(p->desc, cpumask_of(new->processor)); spin_unlock_irqrestore(&old->arch.vgic.lock, flags); vgic_vcpu_inject_irq(new, irq); @@ -508,6 +508,15 @@ void vgic_clear_pending_irqs(struct vcpu *v) spin_unlock_irqrestore(&v->arch.vgic.lock, flags); } +void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p) +{ + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); + list_del_init(&p->inflight); + gic_remove_from_lr_pending(v, p); +} + void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq) { uint8_t priority; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index d3d7bda50d..587a14f8b9 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -244,7 +244,6 @@ extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq, unsigned int priority); extern void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq); extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); -extern void gic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); /* Accept an interrupt from the GIC and dispatch its handler */ extern void gic_interrupt(struct cpu_user_regs *regs, int is_fiq); diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index e489d0bf21..2a93a7bef9 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -204,6 +204,7 @@ extern int vcpu_vgic_init(struct vcpu *v); extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq); extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq); extern void vgic_vcpu_inject_spi(struct domain *d, unsigned int virq); +extern void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); extern void vgic_clear_pending_irqs(struct vcpu *v); extern void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); From patchwork Thu Dec 7 16:14:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121020 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556409qgn; Thu, 7 Dec 2017 08:16:45 -0800 (PST) X-Google-Smtp-Source: AGs4zMYOKmeBL6WQs9g1wV3NBV19Pv/ZVV9WJYYZQkfGluSD0ejixpw+PZLI8ETmJ4uC09VKT5PZ X-Received: by 10.107.10.69 with SMTP id u66mr37637192ioi.230.1512663405263; Thu, 07 Dec 2017 08:16:45 -0800 (PST) ARC-Seal: i=1; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:17 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:09 +0000 Message-Id: <20171207161415.20380-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 04/10] ARM: VGIC: streamline gic_restore_pending_irqs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In gic_restore_pending_irqs() we push our pending virtual IRQs into the list registers. This function is called once from a GIC context and once from a VGIC context. Refactor the calls so that we have only one callsite from the VGIC context. This will help separating the two worlds later. Signed-off-by: Andre Przywara --- xen/arch/arm/domain.c | 1 + xen/arch/arm/gic.c | 11 +++++------ xen/arch/arm/traps.c | 2 +- xen/include/asm-arm/gic.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index a74ff1c07c..73f4d4b2b2 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -185,6 +185,7 @@ static void ctxt_switch_to(struct vcpu *n) /* VGIC */ gic_restore_state(n); + gic_inject(n); /* VFP */ vfp_restore_state(n); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index bac8ada2bb..1f00654ef5 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -36,8 +36,6 @@ #include #include -static void gic_restore_pending_irqs(struct vcpu *v); - static DEFINE_PER_CPU(uint64_t, lr_mask); #define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) @@ -91,8 +89,6 @@ void gic_restore_state(struct vcpu *v) gic_hw_ops->restore_state(v); isb(); - - gic_restore_pending_irqs(v); } /* desc->irq needs to be disabled before calling this function */ @@ -715,11 +711,14 @@ out: return rc; } -void gic_inject(void) +void gic_inject(struct vcpu *v) { ASSERT(!local_irq_is_enabled()); - gic_restore_pending_irqs(current); + gic_restore_pending_irqs(v); + + if ( v != current ) + return; if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ff3d6ff2aa..7fd676ed9d 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2298,7 +2298,7 @@ void leave_hypervisor_tail(void) { local_irq_disable(); if (!softirq_pending(smp_processor_id())) { - gic_inject(); + gic_inject(current); /* * If the SErrors handle option is "DIVERSE", we have to prevent diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 587a14f8b9..28cf16654a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -235,7 +235,7 @@ extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc); -extern void gic_inject(void); +extern void gic_inject(struct vcpu *v); extern void gic_clear_pending_irqs(struct vcpu *v); extern int gic_events_need_delivery(void); From patchwork Thu Dec 7 16:14:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121023 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556530qgn; Thu, 7 Dec 2017 08:16:52 -0800 (PST) X-Google-Smtp-Source: AGs4zMb1YoMVRIL1GtZsxI7YglOj75S0ZuPhYgkoXMwj57UI4Jar1CwNkXtoB2F0y8T9vtZCuAGT X-Received: by 10.36.26.198 with SMTP id 189mr1979477iti.38.1512663412698; Thu, 07 Dec 2017 08:16:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663412; cv=none; d=google.com; s=arc-20160816; b=cHrUm7zFrY4xkgsEGLfmtYHHfBhrxhUFrJa16yvNJImaObl8kJOrXKIf+SULRtnthm 4zfaWCCNvMLzql+Wtza+jKxFa4WaTeit026tPhmx5mAKACqhR3hicQ1Ker89VD/WUkBR YQlk6RTGMQxT0eREpxgNPCPqx0KoQEyC/W6qxxcKLHnLd4I8L4QAJjgIAPyOIu96QqAl rJRrcvha5ftsS4WVEfuKkLf4GfeDh9HwfMlbaIC/4W0y3xIiZ0qGzbNB54HbZYOYKgG5 5yTDdyO8FpaEdd6Fd67tEt+AdeTNOFQtyCh7NFF9LEyxy8zDZcxCqzJc/bchAfkQYjzp ZN7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=Tvh4Jte8zfvfNaCFKutOL/B8Mu+cqxDwfglVzFKxnPQ=; b=W4R9NkmEXY/S+C1zhA5kDjyFTR2ZQS/A2KQ1hlyIEbrqoESZ7pWK0X6gikG2wRNadN NapXq6t9rLHTbZe2Dvs+YYnjhIrSx+Wty2/VtEPUQMt8DFhVBBF0CwESkLUXlrf4Ezjl OJUhtBSYQLXlbCaXF/bCrI40s446IppMmYtf9mG9VUNshE0BA8m0bbEn/+L4s2IDuBMK 79hk58sUNthT3YynABIqqeb73KMoKZKBlnyoJ1LWmmfBoOCFvd2nt+IMRlNyFuOyqdBA clT1VKStSOAaKlwzBiDI8ckXuZzT74WShXTixYD6uG54BZCaUHQuU3WzTRoiDJ9/CjM3 XihQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VDex+FaV; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:18 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:10 +0000 Message-Id: <20171207161415.20380-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 05/10] ARM: VGIC: split gic.c to observe hardware/virtual GIC separation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently gic.c holds code to handle hardware IRQs as well as code to bridge VGIC requests to the GIC virtualization hardware. Despite being named gic.c, this file reaches into the VGIC and uses data structures describing virtual IRQs. To improve abstraction, move the VGIC functions into a separate file, so that gic.c does what is says on the tin. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/Makefile | 1 + xen/arch/arm/gic-vgic.c | 413 ++++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 366 +----------------------------------------- 3 files changed, 416 insertions(+), 364 deletions(-) create mode 100644 xen/arch/arm/gic-vgic.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 30a2a6500a..41d7366527 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -16,6 +16,7 @@ obj-y += domain_build.o obj-y += domctl.o obj-$(EARLY_PRINTK) += early_printk.o obj-y += gic.o +obj-y += gic-vgic.o obj-y += gic-v2.o obj-$(CONFIG_HAS_GICV3) += gic-v3.o obj-$(CONFIG_HAS_ITS) += gic-v3-its.o diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c new file mode 100644 index 0000000000..971b3bfe37 --- /dev/null +++ b/xen/arch/arm/gic-vgic.c @@ -0,0 +1,413 @@ +/* + * xen/arch/arm/gic-vgic.c + * + * ARM Generic Interrupt Controller virtualization support + * + * Tim Deegan + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern uint64_t per_cpu__lr_mask; +extern const struct gic_hw_operations *gic_hw_ops; + +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) + +#undef GIC_DEBUG + +static void gic_update_one_lr(struct vcpu *v, int i); + +static inline void gic_set_lr(int lr, struct pending_irq *p, + unsigned int state) +{ + ASSERT(!local_irq_is_enabled()); + + clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); + + gic_hw_ops->update_lr(lr, p, state); + + set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); + p->lr = lr; +} + +static inline void gic_add_to_lr_pending(struct vcpu *v, struct pending_irq *n) +{ + struct pending_irq *iter; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( !list_empty(&n->lr_queue) ) + return; + + list_for_each_entry ( iter, &v->arch.vgic.lr_pending, lr_queue ) + { + if ( iter->priority > n->priority ) + { + list_add_tail(&n->lr_queue, &iter->lr_queue); + return; + } + } + list_add_tail(&n->lr_queue, &v->arch.vgic.lr_pending); +} + +void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p) +{ + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + list_del_init(&p->lr_queue); +} + +void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) +{ + struct pending_irq *n = irq_to_pending(v, virtual_irq); + + /* If an LPI has been removed meanwhile, there is nothing left to raise. */ + if ( unlikely(!n) ) + return; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + /* Don't try to update the LR if the interrupt is disabled */ + if ( !test_bit(GIC_IRQ_GUEST_ENABLED, &n->status) ) + return; + + if ( list_empty(&n->lr_queue) ) + { + if ( v == current ) + gic_update_one_lr(v, n->lr); + } +#ifdef GIC_DEBUG + else + gdprintk(XENLOG_DEBUG, "trying to inject irq=%u into d%dv%d, when it is still lr_pending\n", + virtual_irq, v->domain->domain_id, v->vcpu_id); +#endif +} + +/* + * Find an unused LR to insert an IRQ into, starting with the LR given + * by @lr. If this new interrupt is a PRISTINE LPI, scan the other LRs to + * avoid inserting the same IRQ twice. This situation can occur when an + * event gets discarded while the LPI is in an LR, and a new LPI with the + * same number gets mapped quickly afterwards. + */ +static unsigned int gic_find_unused_lr(struct vcpu *v, + struct pending_irq *p, + unsigned int lr) +{ + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); + struct gic_lr lr_val; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( unlikely(test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) + { + unsigned int used_lr; + + for_each_set_bit(used_lr, lr_mask, nr_lrs) + { + gic_hw_ops->read_lr(used_lr, &lr_val); + if ( lr_val.virq == p->irq ) + return used_lr; + } + } + + lr = find_next_zero_bit(lr_mask, nr_lrs, lr); + + return lr; +} + +void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, + unsigned int priority) +{ + int i; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + struct pending_irq *p = irq_to_pending(v, virtual_irq); + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( unlikely(!p) ) + /* An unmapped LPI does not need to be raised. */ + return; + + if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) + { + i = gic_find_unused_lr(v, p, 0); + + if (i < nr_lrs) { + set_bit(i, &this_cpu(lr_mask)); + gic_set_lr(i, p, GICH_LR_PENDING); + return; + } + } + + gic_add_to_lr_pending(v, p); +} + +static void gic_update_one_lr(struct vcpu *v, int i) +{ + struct pending_irq *p; + int irq; + struct gic_lr lr_val; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + ASSERT(!local_irq_is_enabled()); + + gic_hw_ops->read_lr(i, &lr_val); + irq = lr_val.virq; + p = irq_to_pending(v, irq); + /* + * An LPI might have been unmapped, in which case we just clean up here. + * If that LPI is marked as PRISTINE, the information in the LR is bogus, + * as it belongs to a previous, already unmapped LPI. So we discard it + * here as well. + */ + if ( unlikely(!p || + test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) + { + ASSERT(is_lpi(irq)); + + gic_hw_ops->clear_lr(i); + clear_bit(i, &this_cpu(lr_mask)); + + return; + } + + if ( lr_val.state & GICH_LR_ACTIVE ) + { + set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) ) + { + if ( p->desc == NULL ) + { + lr_val.state |= GICH_LR_PENDING; + gic_hw_ops->write_lr(i, &lr_val); + } + else + gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n", + irq, v->domain->domain_id, v->vcpu_id, i); + } + } + else if ( lr_val.state & GICH_LR_PENDING ) + { + int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); +#ifdef GIC_DEBUG + if ( q ) + gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n", + irq, v->domain->domain_id, v->vcpu_id, i); +#endif + } + else + { + gic_hw_ops->clear_lr(i); + clear_bit(i, &this_cpu(lr_mask)); + + if ( p->desc != NULL ) + clear_bit(_IRQ_INPROGRESS, &p->desc->status); + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); + p->lr = GIC_INVALID_LR; + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && + !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + gic_raise_guest_irq(v, irq, p->priority); + else { + list_del_init(&p->inflight); + /* + * Remove from inflight, then change physical affinity. It + * makes sure that when a new interrupt is received on the + * next pcpu, inflight is already cleared. No concurrent + * accesses to inflight. + */ + smp_wmb(); + if ( test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + { + struct vcpu *v_target = vgic_get_target_vcpu(v, irq); + irq_set_affinity(p->desc, cpumask_of(v_target->processor)); + clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); + } + } + } +} + +void gic_clear_lrs(struct vcpu *v) +{ + int i = 0; + unsigned long flags; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + + /* The idle domain has no LRs to be cleared. Since gic_restore_state + * doesn't write any LR registers for the idle domain they could be + * non-zero. */ + if ( is_idle_vcpu(v) ) + return; + + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 0); + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask), + nr_lrs, i)) < nr_lrs ) { + gic_update_one_lr(v, i); + i++; + } + + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); +} + +static void gic_restore_pending_irqs(struct vcpu *v) +{ + int lr = 0; + struct pending_irq *p, *t, *p_r; + struct list_head *inflight_r; + unsigned long flags; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + int lrs = nr_lrs; + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + if ( list_empty(&v->arch.vgic.lr_pending) ) + goto out; + + inflight_r = &v->arch.vgic.inflight_irqs; + list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) + { + lr = gic_find_unused_lr(v, p, lr); + if ( lr >= nr_lrs ) + { + /* No more free LRs: find a lower priority irq to evict */ + list_for_each_entry_reverse( p_r, inflight_r, inflight ) + { + if ( p_r->priority == p->priority ) + goto out; + if ( test_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status) && + !test_bit(GIC_IRQ_GUEST_ACTIVE, &p_r->status) ) + goto found; + } + /* We didn't find a victim this time, and we won't next + * time, so quit */ + goto out; + +found: + lr = p_r->lr; + p_r->lr = GIC_INVALID_LR; + set_bit(GIC_IRQ_GUEST_QUEUED, &p_r->status); + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); + gic_add_to_lr_pending(v, p_r); + inflight_r = &p_r->inflight; + } + + gic_set_lr(lr, p, GICH_LR_PENDING); + list_del_init(&p->lr_queue); + set_bit(lr, &this_cpu(lr_mask)); + + /* We can only evict nr_lrs entries */ + lrs--; + if ( lrs == 0 ) + break; + } + +out: + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); +} + +void gic_clear_pending_irqs(struct vcpu *v) +{ + struct pending_irq *p, *t; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + v->arch.lr_mask = 0; + list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) + gic_remove_from_lr_pending(v, p); +} + +int gic_events_need_delivery(void) +{ + struct vcpu *v = current; + struct pending_irq *p; + unsigned long flags; + const unsigned long apr = gic_hw_ops->read_apr(0); + int mask_priority; + int active_priority; + int rc = 0; + + mask_priority = gic_hw_ops->read_vmcr_priority(); + active_priority = find_next_bit(&apr, 32, 0); + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + /* TODO: We order the guest irqs by priority, but we don't change + * the priority of host irqs. */ + + /* find the first enabled non-active irq, the queue is already + * ordered by priority */ + list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) + { + if ( GIC_PRI_TO_GUEST(p->priority) >= mask_priority ) + goto out; + if ( GIC_PRI_TO_GUEST(p->priority) >= active_priority ) + goto out; + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + { + rc = 1; + goto out; + } + } + +out: + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + return rc; +} + +void gic_inject(struct vcpu *v) +{ + ASSERT(!local_irq_is_enabled()); + + gic_restore_pending_irqs(v); + + if ( v != current ) + return; + + if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 1); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 1f00654ef5..04e6d66b69 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -36,15 +36,11 @@ #include #include -static DEFINE_PER_CPU(uint64_t, lr_mask); - -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +DEFINE_PER_CPU(uint64_t, lr_mask); #undef GIC_DEBUG -static void gic_update_one_lr(struct vcpu *v, int i); - -static const struct gic_hw_operations *gic_hw_ops; +const struct gic_hw_operations *gic_hw_ops; void register_gic_ops(const struct gic_hw_operations *ops) { @@ -366,364 +362,6 @@ void gic_disable_cpu(void) gic_hw_ops->disable_interface(); } -static inline void gic_set_lr(int lr, struct pending_irq *p, - unsigned int state) -{ - ASSERT(!local_irq_is_enabled()); - - clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); - - gic_hw_ops->update_lr(lr, p, state); - - set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); - p->lr = lr; -} - -static inline void gic_add_to_lr_pending(struct vcpu *v, struct pending_irq *n) -{ - struct pending_irq *iter; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( !list_empty(&n->lr_queue) ) - return; - - list_for_each_entry ( iter, &v->arch.vgic.lr_pending, lr_queue ) - { - if ( iter->priority > n->priority ) - { - list_add_tail(&n->lr_queue, &iter->lr_queue); - return; - } - } - list_add_tail(&n->lr_queue, &v->arch.vgic.lr_pending); -} - -void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p) -{ - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - list_del_init(&p->lr_queue); -} - -void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) -{ - struct pending_irq *n = irq_to_pending(v, virtual_irq); - - /* If an LPI has been removed meanwhile, there is nothing left to raise. */ - if ( unlikely(!n) ) - return; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - /* Don't try to update the LR if the interrupt is disabled */ - if ( !test_bit(GIC_IRQ_GUEST_ENABLED, &n->status) ) - return; - - if ( list_empty(&n->lr_queue) ) - { - if ( v == current ) - gic_update_one_lr(v, n->lr); - } -#ifdef GIC_DEBUG - else - gdprintk(XENLOG_DEBUG, "trying to inject irq=%u into d%dv%d, when it is still lr_pending\n", - virtual_irq, v->domain->domain_id, v->vcpu_id); -#endif -} - -/* - * Find an unused LR to insert an IRQ into, starting with the LR given - * by @lr. If this new interrupt is a PRISTINE LPI, scan the other LRs to - * avoid inserting the same IRQ twice. This situation can occur when an - * event gets discarded while the LPI is in an LR, and a new LPI with the - * same number gets mapped quickly afterwards. - */ -static unsigned int gic_find_unused_lr(struct vcpu *v, - struct pending_irq *p, - unsigned int lr) -{ - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); - struct gic_lr lr_val; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( unlikely(test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) - { - unsigned int used_lr; - - for_each_set_bit(used_lr, lr_mask, nr_lrs) - { - gic_hw_ops->read_lr(used_lr, &lr_val); - if ( lr_val.virq == p->irq ) - return used_lr; - } - } - - lr = find_next_zero_bit(lr_mask, nr_lrs, lr); - - return lr; -} - -void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, - unsigned int priority) -{ - int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - struct pending_irq *p = irq_to_pending(v, virtual_irq); - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( unlikely(!p) ) - /* An unmapped LPI does not need to be raised. */ - return; - - if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) - { - i = gic_find_unused_lr(v, p, 0); - - if (i < nr_lrs) { - set_bit(i, &this_cpu(lr_mask)); - gic_set_lr(i, p, GICH_LR_PENDING); - return; - } - } - - gic_add_to_lr_pending(v, p); -} - -static void gic_update_one_lr(struct vcpu *v, int i) -{ - struct pending_irq *p; - int irq; - struct gic_lr lr_val; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - ASSERT(!local_irq_is_enabled()); - - gic_hw_ops->read_lr(i, &lr_val); - irq = lr_val.virq; - p = irq_to_pending(v, irq); - /* - * An LPI might have been unmapped, in which case we just clean up here. - * If that LPI is marked as PRISTINE, the information in the LR is bogus, - * as it belongs to a previous, already unmapped LPI. So we discard it - * here as well. - */ - if ( unlikely(!p || - test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) - { - ASSERT(is_lpi(irq)); - - gic_hw_ops->clear_lr(i); - clear_bit(i, &this_cpu(lr_mask)); - - return; - } - - if ( lr_val.state & GICH_LR_ACTIVE ) - { - set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && - test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) ) - { - if ( p->desc == NULL ) - { - lr_val.state |= GICH_LR_PENDING; - gic_hw_ops->write_lr(i, &lr_val); - } - else - gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n", - irq, v->domain->domain_id, v->vcpu_id, i); - } - } - else if ( lr_val.state & GICH_LR_PENDING ) - { - int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); -#ifdef GIC_DEBUG - if ( q ) - gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n", - irq, v->domain->domain_id, v->vcpu_id, i); -#endif - } - else - { - gic_hw_ops->clear_lr(i); - clear_bit(i, &this_cpu(lr_mask)); - - if ( p->desc != NULL ) - clear_bit(_IRQ_INPROGRESS, &p->desc->status); - clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); - p->lr = GIC_INVALID_LR; - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && - test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && - !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) - gic_raise_guest_irq(v, irq, p->priority); - else { - list_del_init(&p->inflight); - /* - * Remove from inflight, then change physical affinity. It - * makes sure that when a new interrupt is received on the - * next pcpu, inflight is already cleared. No concurrent - * accesses to inflight. - */ - smp_wmb(); - if ( test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) - { - struct vcpu *v_target = vgic_get_target_vcpu(v, irq); - irq_set_affinity(p->desc, cpumask_of(v_target->processor)); - clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); - } - } - } -} - -void gic_clear_lrs(struct vcpu *v) -{ - int i = 0; - unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - - /* The idle domain has no LRs to be cleared. Since gic_restore_state - * doesn't write any LR registers for the idle domain they could be - * non-zero. */ - if ( is_idle_vcpu(v) ) - return; - - gic_hw_ops->update_hcr_status(GICH_HCR_UIE, false); - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask), - nr_lrs, i)) < nr_lrs ) { - gic_update_one_lr(v, i); - i++; - } - - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); -} - -static void gic_restore_pending_irqs(struct vcpu *v) -{ - int lr = 0; - struct pending_irq *p, *t, *p_r; - struct list_head *inflight_r; - unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - int lrs = nr_lrs; - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - if ( list_empty(&v->arch.vgic.lr_pending) ) - goto out; - - inflight_r = &v->arch.vgic.inflight_irqs; - list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) - { - lr = gic_find_unused_lr(v, p, lr); - if ( lr >= nr_lrs ) - { - /* No more free LRs: find a lower priority irq to evict */ - list_for_each_entry_reverse( p_r, inflight_r, inflight ) - { - if ( p_r->priority == p->priority ) - goto out; - if ( test_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status) && - !test_bit(GIC_IRQ_GUEST_ACTIVE, &p_r->status) ) - goto found; - } - /* We didn't find a victim this time, and we won't next - * time, so quit */ - goto out; - -found: - lr = p_r->lr; - p_r->lr = GIC_INVALID_LR; - set_bit(GIC_IRQ_GUEST_QUEUED, &p_r->status); - clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); - gic_add_to_lr_pending(v, p_r); - inflight_r = &p_r->inflight; - } - - gic_set_lr(lr, p, GICH_LR_PENDING); - list_del_init(&p->lr_queue); - set_bit(lr, &this_cpu(lr_mask)); - - /* We can only evict nr_lrs entries */ - lrs--; - if ( lrs == 0 ) - break; - } - -out: - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); -} - -void gic_clear_pending_irqs(struct vcpu *v) -{ - struct pending_irq *p, *t; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - v->arch.lr_mask = 0; - list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) - gic_remove_from_lr_pending(v, p); -} - -int gic_events_need_delivery(void) -{ - struct vcpu *v = current; - struct pending_irq *p; - unsigned long flags; - const unsigned long apr = gic_hw_ops->read_apr(0); - int mask_priority; - int active_priority; - int rc = 0; - - mask_priority = gic_hw_ops->read_vmcr_priority(); - active_priority = find_next_bit(&apr, 32, 0); - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - /* TODO: We order the guest irqs by priority, but we don't change - * the priority of host irqs. */ - - /* find the first enabled non-active irq, the queue is already - * ordered by priority */ - list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) - { - if ( GIC_PRI_TO_GUEST(p->priority) >= mask_priority ) - goto out; - if ( GIC_PRI_TO_GUEST(p->priority) >= active_priority ) - goto out; - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) - { - rc = 1; - goto out; - } - } - -out: - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - return rc; -} - -void gic_inject(struct vcpu *v) -{ - ASSERT(!local_irq_is_enabled()); - - gic_restore_pending_irqs(v); - - if ( v != current ) - return; - - if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) - gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); -} - static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) { /* Lower the priority */ From patchwork Thu Dec 7 16:14:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121016 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556261qgn; Thu, 7 Dec 2017 08:16:38 -0800 (PST) X-Google-Smtp-Source: AGs4zMYYBEVSkj9fatI1gWQstb0oIs8XUThKvW7obdFN7D87gie8pYtCtUldcaRRIVV27U67oVFB X-Received: by 10.107.11.91 with SMTP id v88mr39602724ioi.179.1512663398231; Thu, 07 Dec 2017 08:16:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663398; cv=none; d=google.com; s=arc-20160816; b=ZViaHTw8qquI9jWDp68uRSKJXq3Roqt8puaho+ln+PEOKOsPn7QiZO5fxpS1rA1qzs 8+7Nq3zF52SrN/i0vAk75SDPSvzqyAcEsI+Z0SpWZ6S7NIBzfizgucwF3B8vgBEMuE1G jv4utELC6cB+Bm/sXxRh8WJe8EISvT6IDNLT+wE8QSGdq/G+KKIdUKReq+V4Xs+ahPZz 03sMkFzeFWTl5ymHzie3YvTW22IM8yiKPYiTL4HRHW0Da+P8LasIkW9KAsA52hvn0lLI UwoLSd4Q5OERWk3b6fQ/o61zSxZFc5s6lyxpv2TuWruC7PbQUtPp0T3IizHTHNQmTv0Q VOLA== ARC-Message-Signature: i=1; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:19 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:11 +0000 Message-Id: <20171207161415.20380-7-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 06/10] ARM: VGIC: split up gic_dump_info() to cover virtual part separately X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently gic_dump_info() not only dumps the hardware state of the GIC, but also the VGIC internal virtual IRQ lists. Split the latter off and move it into gic-vgic.c to observe the abstraction. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/domain.c | 1 + xen/arch/arm/gic-vgic.c | 11 +++++++++++ xen/arch/arm/gic.c | 12 ------------ xen/include/asm-arm/gic.h | 1 + 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 73f4d4b2b2..5d2943b800 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -942,6 +942,7 @@ long arch_do_vcpu_op(int cmd, struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) void arch_dump_vcpu_info(struct vcpu *v) { gic_dump_info(v); + gic_dump_vgic_info(v); } void vcpu_mark_events_pending(struct vcpu *v) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 971b3bfe37..90b827c574 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -403,6 +403,17 @@ void gic_inject(struct vcpu *v) gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 1); } +void gic_dump_vgic_info(struct vcpu *v) +{ + struct pending_irq *p; + + list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight ) + printk("Inflight irq=%u lr=%u\n", p->irq, p->lr); + + list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue ) + printk("Pending irq=%d\n", p->irq); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 04e6d66b69..4cb74d449e 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -443,20 +443,8 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r void gic_dump_info(struct vcpu *v) { - struct pending_irq *p; - printk("GICH_LRs (vcpu %d) mask=%"PRIx64"\n", v->vcpu_id, v->arch.lr_mask); gic_hw_ops->dump_state(v); - - list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight ) - { - printk("Inflight irq=%u lr=%u\n", p->irq, p->lr); - } - - list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue ) - { - printk("Pending irq=%d\n", p->irq); - } } void init_maintenance_interrupt(void) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 28cf16654a..4f4fd555c1 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -285,6 +285,7 @@ extern void send_SGI_allbutself(enum gic_sgi sgi); /* print useful debug info */ extern void gic_dump_info(struct vcpu *v); +extern void gic_dump_vgic_info(struct vcpu *v); /* Number of interrupt lines */ extern unsigned int gic_number_lines(void); From patchwork Thu Dec 7 16:14:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121015 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556196qgn; Thu, 7 Dec 2017 08:16:34 -0800 (PST) X-Google-Smtp-Source: AGs4zMbHRuGR18xgz+tkMdTa+hpjccJFeZH70zFLBqcd9Z+vm6zNrUi9pB6ehXj+DBmtxXMVH9ks X-Received: by 10.107.159.13 with SMTP id i13mr37031564ioe.300.1512663394202; Thu, 07 Dec 2017 08:16:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663394; cv=none; d=google.com; s=arc-20160816; b=TKuLC+gM0KZ+8dPSwpTWm40IjEXVy3K8HotjHfAoNhqeGfdxI3g2ya4/2Xg+rzGBWE FLzMaLap7ULDIq0aEQ3yKvyuoi93C6pZFinM+9d76Vsk9w59xNva2B1QhdhI5YVpEdsf R4tOwiXDmqOP7ppBMM57gGVC+om5GWTgu53vvLxxrFvqoPd+fQch5nJJb06yL8MV/jqA rIAC4VaRc48whfwBwWSE8F7PIPA4XVle7lXZR+Vum1w1rgT5vewIrtMI6C2TVTyVVmkR S6ZWGG7tZJlVKuyHzVZkSj5hOTdvmgladLN01WU+ELQ0cx3cG+kRivavNJc4f3AYWubT 4SCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=y5ktjJOtWPYWWuE5kkDxIRcwaIzR764pgG3fZeHlgKg=; b=tCtK02UtB7wF3C0ijGE7PuMPd7gBc5NgzT4hZ+A3TeAKrhTAfCNtxXQ1aEJl8pKW1P W+3Fyi7ZwU4MkFyqxoax5CKH3Hm5wNY3Xa/LBetyMamCjlHei+IuUJaeQ9tMs/q3yFYN szxGXYAp8JfzPlZP6XlCM6YAbeHnT/nppXYYQ2kiQ+DJQ2ZauauRSjs6vDagTlyVwt2u K1PNRlzRLnQ+wCtq/kfr3uZUxtsxKWH1pX+spoN19cBwk5Rz9ENIne5GB9kppISX/Xsb yTMhtYqnN4kk0Kw/EH22zlDdgkWFjTmjIUyhM7gJ0ULGDPa9AKtuc+/iVXEAOocAiZnk +eLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RRQj60Hs; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:20 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:12 +0000 Message-Id: <20171207161415.20380-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 07/10] ARM: VGIC: rework events_need_delivery() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In event.h we very deeply dive into the VGIC to learn if an event for a guest is pending. Rework that function to abstract the VGIC specific part out. Also reorder the queries there, as we only actually need to check for the event channel if there are no other pending IRQs. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/vgic.c | 11 +++++++++++ xen/include/asm-arm/event.h | 13 +++---------- xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 6e933a86d3..9921769b15 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -593,6 +593,17 @@ void arch_evtchn_inject(struct vcpu *v) vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); } +bool vgic_evtchn_irq_pending(struct vcpu *v) +{ + struct pending_irq *p; + + p = irq_to_pending(v, v->domain->arch.evtchn_irq); + /* Does not work for LPIs. */ + ASSERT(!is_lpi(v->domain->arch.evtchn_irq)); + + return list_empty(&p->inflight); +} + bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) { struct vcpu *v = current; diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index caefa506a9..67684e9763 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -16,12 +16,6 @@ static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) static inline int local_events_need_delivery_nomask(void) { - struct pending_irq *p = irq_to_pending(current, - current->domain->arch.evtchn_irq); - - /* Does not work for LPIs. */ - ASSERT(!is_lpi(current->domain->arch.evtchn_irq)); - /* XXX: if the first interrupt has already been delivered, we should * check whether any other interrupts with priority higher than the * one in GICV_IAR are in the lr_pending queue or in the LR @@ -33,11 +27,10 @@ static inline int local_events_need_delivery_nomask(void) if ( gic_events_need_delivery() ) return 1; - if ( vcpu_info(current, evtchn_upcall_pending) && - list_empty(&p->inflight) ) - return 1; + if ( !vcpu_info(current, evtchn_upcall_pending) ) + return 0; - return 0; + return vgic_evtchn_irq_pending(current); } static inline int local_events_need_delivery(void) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 2a93a7bef9..22c8502c95 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -218,6 +218,8 @@ extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); +bool vgic_evtchn_irq_pending(struct vcpu *v); + extern int domain_vgic_register(struct domain *d, int *mmio_count); extern int vcpu_vgic_free(struct vcpu *v); extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, From patchwork Thu Dec 7 16:14:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121019 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556366qgn; Thu, 7 Dec 2017 08:16:43 -0800 (PST) X-Google-Smtp-Source: AGs4zMZj1c5nz/G8K6vgVQY5N5Ov7ssA7Fe0NR0uu8fBspSlzpfQ6POhqK4HOoEgjXb/IWToWxks X-Received: by 10.36.60.212 with SMTP id m203mr1894166ita.96.1512663403213; Thu, 07 Dec 2017 08:16:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663403; cv=none; d=google.com; s=arc-20160816; b=Ws0zMhdCQkjaOaUNKPkfCRn8priMmBEs96GQfkALqPEAWX5luopwWS/jA1fjF92jFa 3j9iumQeAjkQWBq63zktWLAF08s28Bs5WXqo6j5bFEo72dc79D/vVcq6cNZqZRtj1Wcw GTmWza0Ouq/DJvFsckGSfcICoCQzhvILVEW5kFPc06h4SSFiJa58LZz7eYoEyZ22XtBW GbC3mCwdSkJ0xrFN/gN9uT4rIUE0pfHzs+KZT0WZLIugFisyPxh8ZcXgTwyxr1crAksw 5j9mjy+WVd4KubQ3nvZiuKZnpENv0nW2x2jVtUpRpdNrIqXR3YzBNxuuQSA7SpVMS5Ks 56dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=mu0m8YWIUGtfXqW49ihMLymcOda7ZLG/WQb1yw0mbts=; b=X1qyjJp4y3/mfbNMbHYYcMXRWT80j9b/tj7I/lCTcUs5UZ4IySMTSt9aX0vKs1pml9 p9LUCQI/L8EGGw2e43freLP7IW4AlTRomDzd7kJcocELJRanmcF9fY8XtrbCRirvHhrv rDYaEgCIjzR5k+BFUi7diBjPwxxUIu1EQ1iJw/ZdntgozE5UPISd30MH+wFLz/djidAB 7xoB2f5bil1gTa0dC0U5Pl7yogtqdV0Enc1DH9b1aaCI46XKrP85DrbF4HerQlEENBKj 8k12WYdWEhu/S8i7TWckDcpg54Sz6wpTtXIRPUSGi2zRmYlG977+NT5VZMyyO7mzi1ge yS6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=j7fB5itl; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:21 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:13 +0000 Message-Id: <20171207161415.20380-9-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 08/10] ARM: VGIC: factor out vgic_connect_hw_irq() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we happily access VGIC internal data structures like the rank and struct pending_irq in gic.c, which should be VGIC agnostic. Factor out a new function vgic_connect_hw_irq(), which allows a virtual IRQ to be connected to a hardware IRQ (using the hw bit in the LR). This removes said accesses to VGIC data structures and improves abstraction. Signed-off-by: Andre Przywara Acked-by: Stefano Stabellini --- xen/arch/arm/gic-vgic.c | 31 +++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 42 ++++++------------------------------------ xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 90b827c574..37f005d99c 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -414,6 +414,37 @@ void gic_dump_vgic_info(struct vcpu *v) printk("Pending irq=%d\n", p->irq); } +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc) +{ + unsigned long flags; + /* Use vcpu0 to retrieve the pending_irq struct. Given that we only + * route SPIs to guests, it doesn't make any difference. */ + struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); + struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); + struct pending_irq *p = irq_to_pending(v_target, virq); + int ret = 0; + + /* We are taking to rank lock to prevent parallel connections. */ + vgic_lock_rank(v_target, rank, flags); + + if ( desc ) + { + /* The VIRQ should not be already enabled by the guest */ + if ( !p->desc && + !test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + p->desc = desc; + else + ret = -EBUSY; + } + else + p->desc = NULL; + + vgic_unlock_rank(v_target, rank, flags); + + return ret; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 4cb74d449e..d46a6d54b3 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -128,27 +128,12 @@ void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) int gic_route_irq_to_guest(struct domain *d, unsigned int virq, struct irq_desc *desc, unsigned int priority) { - unsigned long flags; - /* Use vcpu0 to retrieve the pending_irq struct. Given that we only - * route SPIs to guests, it doesn't make any difference. */ - struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); - struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); - struct pending_irq *p = irq_to_pending(v_target, virq); - int res = -EBUSY; - ASSERT(spin_is_locked(&desc->lock)); /* Caller has already checked that the IRQ is an SPI */ ASSERT(virq >= 32); ASSERT(virq < vgic_num_irqs(d)); ASSERT(!is_lpi(virq)); - vgic_lock_rank(v_target, rank, flags); - - if ( p->desc || - /* The VIRQ should not be already enabled by the guest */ - test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) - goto out; - desc->handler = gic_hw_ops->gic_guest_irq_type; set_bit(_IRQ_GUEST, &desc->status); @@ -156,31 +141,19 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, gic_set_irq_type(desc, desc->arch.type); gic_set_irq_priority(desc, priority); - p->desc = desc; - res = 0; - -out: - vgic_unlock_rank(v_target, rank, flags); - - return res; + return vgic_connect_hw_irq(d, NULL, virq, desc); } /* This function only works with SPIs for now */ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc) { - struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); - struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); - struct pending_irq *p = irq_to_pending(v_target, virq); - unsigned long flags; + int ret; ASSERT(spin_is_locked(&desc->lock)); ASSERT(test_bit(_IRQ_GUEST, &desc->status)); - ASSERT(p->desc == desc); ASSERT(!is_lpi(virq)); - vgic_lock_rank(v_target, rank, flags); - if ( d->is_dying ) { desc->handler->shutdown(desc); @@ -198,19 +171,16 @@ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, */ if ( test_bit(_IRQ_INPROGRESS, &desc->status) || !test_bit(_IRQ_DISABLED, &desc->status) ) - { - vgic_unlock_rank(v_target, rank, flags); return -EBUSY; - } } + ret = vgic_connect_hw_irq(d, NULL, virq, NULL); + if ( ret ) + return ret; + clear_bit(_IRQ_GUEST, &desc->status); desc->handler = &no_irq_type; - p->desc = NULL; - - vgic_unlock_rank(v_target, rank, flags); - return 0; } diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 22c8502c95..f4240df371 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -219,6 +219,8 @@ int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); bool vgic_evtchn_irq_pending(struct vcpu *v); +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc); extern int domain_vgic_register(struct domain *d, int *mmio_count); extern int vcpu_vgic_free(struct vcpu *v); From patchwork Thu Dec 7 16:14:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121013 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556163qgn; Thu, 7 Dec 2017 08:16:32 -0800 (PST) X-Google-Smtp-Source: AGs4zMaLyoFCl7gljYbAJb5FvvCSmKDUnRu1mBrByWwmCukLElmHKzkeryKJlCpQbTr4B6TG1D8S X-Received: by 10.36.239.195 with SMTP id i186mr1849131ith.29.1512663392444; Thu, 07 Dec 2017 08:16:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663392; cv=none; d=google.com; s=arc-20160816; b=a+qyTYfqz9vSKYgYqOLvFSTYwpIFtnbPLzcV4vKOMUBVtdFFda9n/0vxPV7RKmV5rX Rkvp25cdFB74E81GFXwD6Dh4nAg/yB9tiHKusFKdyYK8BP4blFbqnUAB/m2e4z3qxDM+ IKZUQb9qH4cjS2B1kB1lHIeiXAdeglfN3GtcVtF3fYi87btUYV8cXB5fUMEA1Xq70vvk zV5NJN7QskwNAHnojMgHeM3RbsXYTnKT9OKmg215mQPyrQrvnPaW1GiSLPTpHnOCvb6T LZyoCO90N6zwnYYhgRAidpvA4W5y9TOkU7ZE54M8HyV1t1aJxnF4nCUibDiYithpvO2F TzaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=yvy2vz628LqVXmN+mc2ZRtIIHYm17yQkSSrIK59+q7w=; b=oIMJrRDzVDvN4uEd52JNWm6zO7MZGYCDrfPbvC+miZkwEJ4jcENuJHnJ+a+tQmm3ew A1gHgvImreT4fsmu0o5FQbJLNplrpBO5Yio1QaMvBD7Gq6pcbc06UVVaYUsX41U+Wivx 48fk8zjFEyjzHKr1p/iMfyDnRO75oWyTpT4azU7xxkmytl/2SzpCVaH2td3JakqdbQva cI0xBUqoipDIVysdSGc5GrSywE41eqrs3XiLCos16mRymhn8FkV3HCDMDywtEHi+W6tj NU8SkuMvWzptmu9ch+QqjY8WWlrFfXITPe0PhZnuF27UBWoC8vqhPRoG83wQwRCeb1uc ZEYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WTU2VN+E; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:22 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:14 +0000 Message-Id: <20171207161415.20380-10-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 09/10] ARM: VGIC: factor out vgic_get_hw_irq_desc() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we happily access the VGIC internal struct pending_irq (which describes a virtual IRQ) in irq.c. Factor out the actually needed functionality to learn the associated hardware IRQ and move that into gic-vgic.c to improve abstraction. Signed-off-by: Andre Przywara Acked-by: Stefano Stabellini --- xen/arch/arm/gic-vgic.c | 15 +++++++++++++++ xen/arch/arm/irq.c | 7 ++----- xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 37f005d99c..8d43a6ba76 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -414,6 +414,21 @@ void gic_dump_vgic_info(struct vcpu *v) printk("Pending irq=%d\n", p->irq); } +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq) +{ + struct pending_irq *p; + + if ( !v ) + v = d->vcpu[0]; + + p = irq_to_pending(v, virq); + if ( !p ) + return NULL; + + return p->desc; +} + int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, struct irq_desc *desc) { diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 7f133de549..62103a20e3 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -534,19 +534,16 @@ int release_guest_irq(struct domain *d, unsigned int virq) struct irq_desc *desc; struct irq_guest *info; unsigned long flags; - struct pending_irq *p; int ret; /* Only SPIs are supported */ if ( virq < NR_LOCAL_IRQS || virq >= vgic_num_irqs(d) ) return -EINVAL; - p = spi_to_pending(d, virq); - if ( !p->desc ) + desc = vgic_get_hw_irq_desc(d, NULL, virq); + if ( !desc ) return -EINVAL; - desc = p->desc; - spin_lock_irqsave(&desc->lock, flags); ret = -EINVAL; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index f4240df371..ebc0cfaee8 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -219,6 +219,8 @@ int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); bool vgic_evtchn_irq_pending(struct vcpu *v); +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq); int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, struct irq_desc *desc); From patchwork Thu Dec 7 16:14:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 121017 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8556333qgn; Thu, 7 Dec 2017 08:16:41 -0800 (PST) X-Google-Smtp-Source: AGs4zMY4Vp+2DAbEonohKAANuw2hFDkQxpf8necRurZvgCggQQIXviN8pUUrU9ck/ri0k0hgeji9 X-Received: by 10.107.17.94 with SMTP id z91mr41994060ioi.157.1512663401672; Thu, 07 Dec 2017 08:16:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512663401; cv=none; d=google.com; s=arc-20160816; b=jKgZG4LLamdu6QtDPDAp5b1yJzfEGpuCLKwFjHU2DS0uwyS1wwnkxT/6NhJmCWmmaN ub97MGLvIDGTU72W5rvEA0rxkFr2+RTd9pjsAJbZpyvSezQk4AWBBoap+bNDiblaEWYB Xq4O+1u8XLJa2GB62FPxkCxW1dOBrq4ali/+KBhnFacRc7Gu2euKa1jRdhyPFAB4fbtK m61Fm42XeqQuQOW0w90sIzI2CyN5S6tI6DwLxBDUgZFbhBQnR2kRqxK3OsWOQMjY5pmS eF0k3bz5q7B6t5sQdsi86fogcpv6DTvGLaMQNAolJVTbvVLIPJAIjXPXH/yVrbUkDrQV lfHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=8uq2piJLm+UYHPGmtm2WtGCy353lL4e8Ur58pnOehu4=; b=QQDeiyscrGRRqG9XO6vMimBvEM3+ZJ87M+dKZ6Gobg5vgXMkY1nYMEqWt2Bzko2fMc HbrLw0uaQH+BvGVT1sQBFYWWLdKttL/UtaPQMAE0mr9j3DGDaKeXRWjvhdK+zGDplFZ4 ZIeIhPkJXMckpyUje/3ovvLxYlmgjo28zTLMut0Rx1Gh6Vr2nAnLMZgiR3EL0gJeyCjo +EAQ0UkDCiuG0qEofwzPcgApEL6/KK/K6H8qdusU7Gz8tUA4c3HRzf2/udDQwIctQMde CAMJX4d0TgKpUpWDuT3okluklnwTDJ/pcrm+6NJhYvnf+1FG1+pLBFajj/fjuLqNbEYd /G5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Q+c1d0Iq; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id f18sm6090624wrg.66.2017.12.07.08.14.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 08:14:23 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 7 Dec 2017 16:14:15 +0000 Message-Id: <20171207161415.20380-11-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207161415.20380-1-andre.przywara@linaro.org> References: <20171207161415.20380-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 10/10] ARM: VGIC: rework gicv[23]_update_lr to not use pending_irq X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The functions to actually populate a list register were accessing the VGIC internal pending_irq struct, although they should be abstracting from that. Break the needed information down to remove the reference to pending_irq from gic-v[23].c. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v2.c | 14 +++++++------- xen/arch/arm/gic-v3.c | 12 ++++++------ xen/arch/arm/gic-vgic.c | 3 ++- xen/include/asm-arm/gic.h | 4 ++-- xen/include/asm-arm/irq.h | 3 +++ 5 files changed, 20 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 511c8d7294..2b271ba322 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -428,8 +428,8 @@ static void gicv2_disable_interface(void) spin_unlock(&gicv2.lock); } -static void gicv2_update_lr(int lr, const struct pending_irq *p, - unsigned int state) +static void gicv2_update_lr(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state) { uint32_t lr_reg; @@ -437,12 +437,12 @@ static void gicv2_update_lr(int lr, const struct pending_irq *p, BUG_ON(lr < 0); lr_reg = (((state & GICH_V2_LR_STATE_MASK) << GICH_V2_LR_STATE_SHIFT) | - ((GIC_PRI_TO_GUEST(p->priority) & GICH_V2_LR_PRIORITY_MASK) - << GICH_V2_LR_PRIORITY_SHIFT) | - ((p->irq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT)); + ((GIC_PRI_TO_GUEST(priority) & GICH_V2_LR_PRIORITY_MASK) + << GICH_V2_LR_PRIORITY_SHIFT) | + ((virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT)); - if ( p->desc != NULL ) - lr_reg |= GICH_V2_LR_HW | ((p->desc->irq & GICH_V2_LR_PHYSICAL_MASK ) + if ( hw_irq != INVALID_IRQ ) + lr_reg |= GICH_V2_LR_HW | ((hw_irq & GICH_V2_LR_PHYSICAL_MASK ) << GICH_V2_LR_PHYSICAL_SHIFT); writel_gich(lr_reg, GICH_LR + lr * 4); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 473e26111f..ce1e5cad25 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -962,8 +962,8 @@ static void gicv3_disable_interface(void) spin_unlock(&gicv3.lock); } -static void gicv3_update_lr(int lr, const struct pending_irq *p, - unsigned int state) +static void gicv3_update_lr(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state) { uint64_t val = 0; @@ -979,11 +979,11 @@ static void gicv3_update_lr(int lr, const struct pending_irq *p, if ( current->domain->arch.vgic.version == GIC_V3 ) val |= GICH_LR_GRP1; - val |= ((uint64_t)p->priority & 0xff) << GICH_LR_PRIORITY_SHIFT; - val |= ((uint64_t)p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT; + val |= (uint64_t)priority << GICH_LR_PRIORITY_SHIFT; + val |= ((uint64_t)virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT; - if ( p->desc != NULL ) - val |= GICH_LR_HW | (((uint64_t)p->desc->irq & GICH_LR_PHYSICAL_MASK) + if ( hw_irq != INVALID_IRQ ) + val |= GICH_LR_HW | (((uint64_t)hw_irq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT); gicv3_ich_write_lr(lr, val); diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 8d43a6ba76..60f6498092 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -52,7 +52,8 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); - gic_hw_ops->update_lr(lr, p, state); + gic_hw_ops->update_lr(lr, p->irq, p->priority, + p->desc ? p->desc->irq : INVALID_IRQ, state); set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 4f4fd555c1..ce9d1d058a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -342,8 +342,8 @@ struct gic_hw_operations { /* Disable CPU physical and virtual interfaces */ void (*disable_interface)(void); /* Update LR register with state and priority */ - void (*update_lr)(int lr, const struct pending_irq *pending_irq, - unsigned int state); + void (*update_lr)(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state); /* Update HCR status register */ void (*update_hcr_status)(uint32_t flag, bool set); /* Clear LR register */ diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index abc8f06a13..0d110ecb08 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -31,6 +31,9 @@ struct arch_irq_desc { /* LPIs are always numbered starting at 8192, so 0 is a good invalid case. */ #define INVALID_LPI 0 +/* This is a spurious interrupt ID which never makes it into the GIC code. */ +#define INVALID_IRQ 1023 + extern unsigned int nr_irqs; #define nr_static_irqs NR_IRQS #define arch_hwdom_irqs(domid) NR_IRQS