From patchwork Tue Dec 12 10:38:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121502 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890613edb; Tue, 12 Dec 2017 02:38:25 -0800 (PST) X-Google-Smtp-Source: ACJfBovxzdwojDek1OcQsL62wC0UBHwYUJuQ7DvH3kRw2MH9zsXTox6O+maW60ctEn78jWP8Eit8 X-Received: by 10.99.180.77 with SMTP id n13mr1647277pgu.317.1513075104937; Tue, 12 Dec 2017 02:38:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513075104; cv=none; d=google.com; s=arc-20160816; b=uFiXAHPCOSJZIuE0jGzX24mj2GhZyvT44K2EGczDQnkK8FcJrJKFukCJ9cmaB8IqgA Q3ox8CnUyb12iR+RVUYnE5vWrOoceSKpIbcCujo3ZvnZNY7lUiJMI3R6/RvH8AvrkS5m KO0VWG0amTMGochMnIypsiSz/MBIIjGGcqK+nffR9aFIAyisvdsGYxWcno0k57ZrMaiM x25CnvDD0RZARexitBNeJCtBRRcV35HQJlqiGMt2TtV4vQRJIws1g+frGQ5zj6DexRXF c3JpoY1bWQaOANmPif7iCzczwz6xg2RzS1U/RUwifLnx2cEJ2DcNjQHd/GghaGN6fk0t 6OLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=x4P0gS8uNKfMAwsdyTpFMydZFN5ODJkhZ0fP0T1Qy5Q=; b=sjjeGDDmMh5xSocr/w8sR1aNv97nCIciNl1xEY9V0/QT3RXoPqcCe3aMR7QdfRph6f ofIe9Ptl6vL9NrtrnhQWojCSo0uD1HsdNiYzKtlEBDLlC01Jo/G4VJMLcO7e3ahnQMYs zg3nXCYsby3e4ZCL5O0JKYfgoPdTVg8WbRnriSJsOKMdetO0ERWT2sf6oEC5p9F5gqCC Qt+tXelau/hB1VyxhNK98F8dUhcxU80QJBudN+UY/gzzOM2IdnvilHXsokzycZh2tGg5 swYsNYolm355CEpq1Emt+9ghrsObNW1r/sROV85+yLVC+Tp0OpdWtVY2GQ4kl+P7FZVw eWUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PXxxdweK; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id o11si11223236pgp.238.2017.12.12.02.38.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PXxxdweK; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BCB98220EE10F; Tue, 12 Dec 2017 02:33:45 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3906421B02825 for ; Tue, 12 Dec 2017 02:33:43 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id o2so20598044wro.5 for ; Tue, 12 Dec 2017 02:38:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3VswnviTEPXlAq8N1iExsXHH82qIEwaGOOgQ5L8fIt4=; b=PXxxdweK9aGbHya/yDIoFvVIyQbSAPenKCHPUKf+2jIrSG6pMhFsAMOvrjKs3VlGWO azzfGT6YuEY2wx3CyP8PZLUoeeJQ416LbWRGEys7Q/c5P56aKtNZ19TiGbxCL4jy5uPm GIkSlmI95hYgTKtDniRs5ISCNvkf0Eq6fHtug= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3VswnviTEPXlAq8N1iExsXHH82qIEwaGOOgQ5L8fIt4=; b=tt6xFNAKVF+zXD3FOQoBZHaKNUne40q2X6EpY6+xOQBSMBmECgk0Jt+z/pCDS1fQ+4 masMbO6/pfmXkF70Qvzeu7JXpaBDg9+n/4zoTJX7CVcFlYY8JXBTtrG7s8EKgOZZN6Xd 9aaIvUscKzEt8fuiNDaUBDYtYUqG0mjVi76EuqeDOgUxz17NhKKBaTEDedQgPgCVJ4IW SN7gHoid0KFjLNCKP/RGjalZ9ucPGPzNXnCxJbTtoHcRBVgtVBskWPd5q768Prrr9HNY NTz82RjNUbpa2bNbbEPKbvPOx7Nniwv2lBTUvFxLQHqOB34LTLpWfh1vJQQ2xKnBddOW yYBg== X-Gm-Message-State: AKGB3mJVDjMqbiOQGmawHkayt5xtg9fydPyNDD/f+GE56Wo63ydWVslL cBsjIjOstb1/YFc/ZYZCZ5UZuodW0gU= X-Received: by 10.223.150.175 with SMTP id u44mr3531195wrb.115.1513075097095; Tue, 12 Dec 2017 02:38:17 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:16 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:00 +0000 Message-Id: <20171212103807.18836-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/8] Silicon/SynQuacer: enable CPU idle states in device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" It appears that whatever was preventing us from using CPU idle with PSCI low power states has disappeared, so let's enable the low power states in the DT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 48 ++++++++++---------- 1 file changed, 24 insertions(+), 24 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index ec784c70afe7..c9fee5d1f350 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -47,168 +47,168 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x1>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x100>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x101>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x200>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU5: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x201>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x300>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU7: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x301>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU8: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x400>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU9: cpu@401 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x401>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU10: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x500>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU11: cpu@501 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x501>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU12: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x600>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU13: cpu@601 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x601>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU14: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x700>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU15: cpu@701 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x701>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU16: cpu@800 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x800>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU17: cpu@801 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x801>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU18: cpu@900 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x900>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU19: cpu@901 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x901>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU20: cpu@a00 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0xa00>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU21: cpu@a01 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0xa01>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU22: cpu@b00 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0xb00>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU23: cpu@b01 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0xb01>; enable-method = "psci"; - //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu-map { From patchwork Tue Dec 12 10:38:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121501 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890585edb; Tue, 12 Dec 2017 02:38:23 -0800 (PST) X-Google-Smtp-Source: ACJfBov8x6B/6dZju0RFVuJQJ3EF2nEcAbSQcBCegFE7pZskjO69KUw8fBDVNT8NF8WNOkLQevDZ X-Received: by 10.84.206.37 with SMTP id f34mr1734190ple.299.1513075103631; Tue, 12 Dec 2017 02:38:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513075103; cv=none; d=google.com; s=arc-20160816; b=lyG1NwX7ivpuvpisJYbcBrqWXeHTqwiqCVSZhkN6piMB0DGGsR42IjjwDTmmSgMDtj t9bawNuBAJ2J0lY5E9CK+A4AJbBcjq0nuxPRpmr5zsM7pGDwKygY0rDuerBS4UQkaqbV uFuzS9cBUl3yG/uqJ6xdjGCy4VEFq58TLtn14ClfCWcTt2izHibSw8AxCPFwYnU92n0s aQ6pZ1aihbkMwb0KigFyZSBHwO3d/HMCTvr7QNiXqQxwHX2NBTD12LWBEN3rlKbEDi/B NG7jOwMPMVGQ1bcuTVQ4Yu59IbfqdT2M4DN+JUfLESvmGoVc1Mzc6XQzEb5bIpvJfDNz foUg== ARC-Message-Signature: i=1; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id f12si11471733plo.19.2017.12.12.02.38.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=iMm+sMbR; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 78287220EE10B; Tue, 12 Dec 2017 02:33:44 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A0D6C21B02825 for ; Tue, 12 Dec 2017 02:33:42 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id i11so19299353wmf.4 for ; Tue, 12 Dec 2017 02:38:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GQz+qxBtxnX2/Ssf1t45Ut14/fFf8qj4RveaFtN6USw=; b=iMm+sMbRQZyrDvnicpAaoezg3iDb+3+QjoU+PnIiMNm33WSMu+f4R3ZXHhABfaxF2j ZRxRcs/Ihn34F4QVpA/x0ybHg1yI/8iGqmsGl2ZfhIWCtjDbsQKf1xOP8tXeCz1CLB9s bp0b2PGYIL6xvyhAIGHySbhFyCZgcU34tl0kE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GQz+qxBtxnX2/Ssf1t45Ut14/fFf8qj4RveaFtN6USw=; b=F8kif4AvdPVot4j5bm/FZKOMXQAfJihS4oXjcloojs8axedFNhymM/TmBOME3vDCk/ w8BqRtc8VHAe4N4kPThlGgDCXkE2F+WipGhF9tAaQADvJcfZ/EjBF71+BBFpgxs0srbS 8TGg4XxffY2ARuj91G0/GTb44J+Sd6FZIuDNiWrkU/oIU1sJN7pFLfi6NEFRVRubrssQ LLurno/t+w+61tuhu0wdm/gf7ZK2MvdSAhT2mRAdEyU6QV82eL1bW21m17R8CjaWK5c8 /PbqDHxwZjKPuRp8sUzgakG8W57LpagQFCLtil2HSQcUC+3LNRll1l3uTivsxCmzb3AY BqAg== X-Gm-Message-State: AKGB3mJEWJ979CstSz+szIfUwxRj8iyVo9XI4oUlCX3WRh2yLZFvuyZr 0CwDLkRrydSEMM87osW5YDqJGtKnoGs= X-Received: by 10.28.191.86 with SMTP id p83mr1422093wmf.114.1513075099465; Tue, 12 Dec 2017 02:38:19 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:18 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:01 +0000 Message-Id: <20171212103807.18836-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/8] Platform/Socionext/SynQuacer: expose build number as firmware version X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Expose the contents of the .DSC macro BUILD_NUMBER via the PCD gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString (if > 1), and as the FMP system firmware version (for capsule update). Also, set the firmware vendor to 'Linaro Enterprise Group', to distinguish our builds from builds by other parties. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 8 +++++++- Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 ++++-- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 8 +++++++- Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 ++++-- 6 files changed, 24 insertions(+), 6 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 8fbd7b2d908f..5ec26f9cdd34 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -26,6 +26,7 @@ [Defines] BUILD_TARGETS = DEBUG|RELEASE SKUID_IDENTIFIER = DEFAULT FLASH_DEFINITION = Platform/Socionext/DeveloperBox/DeveloperBox.fdf + BUILD_NUMBER = 1 [BuildOptions] RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0 @@ -222,7 +223,7 @@ [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE [PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Linaro Enterprise Group" # non-secure SRAM gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 @@ -384,6 +385,11 @@ [PcdsFixedAtBuild.common] # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 +!if $(BUILD_NUMBER) > 1 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER)" +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 diff --git a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf index f5272c0f0d37..95a5e482a713 100644 --- a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +++ b/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf @@ -38,6 +38,7 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision [Pcd] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor diff --git a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc b/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc index bc47e696da7a..fb69de078313 100644 --- a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc +++ b/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc @@ -21,8 +21,10 @@ #define PACKAGE_VERSION 0xFFFFFFFF #define PACKAGE_VERSION_STRING L"Unknown" -#define CURRENT_FIRMWARE_VERSION 0x00000001 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000001" +#define __BUILD_STRING(x) L ## #x +#define BUILD_STRING(x) L"build #" __BUILD_STRING(x) +#define CURRENT_FIRMWARE_VERSION FixedPcdGet32 (PcdFirmwareRevision) +#define CURRENT_FIRMWARE_VERSION_STRING BUILD_STRING (FixedPcdGet32 (PcdFirmwareRevision)) #define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 #define IMAGE_ID SIGNATURE_64('S', 'N', 'D', 'E', 'V', 'B', 'O', 'X') diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 895d3b09fdc9..bc8ddd452d4b 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -26,6 +26,7 @@ [Defines] BUILD_TARGETS = DEBUG|RELEASE SKUID_IDENTIFIER = DEFAULT FLASH_DEFINITION = Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf + BUILD_NUMBER = 1 [BuildOptions] RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0 @@ -214,7 +215,7 @@ [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE [PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Linaro Enterprise Group" # non-secure SRAM gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 @@ -372,6 +373,11 @@ [PcdsFixedAtBuild.common] # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 +!if $(BUILD_NUMBER) > 1 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER)" +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 diff --git a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf index f5272c0f0d37..95a5e482a713 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +++ b/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf @@ -38,6 +38,7 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision [Pcd] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor diff --git a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc b/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc index 3413f76f95c7..daf26c79dff1 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc +++ b/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc @@ -21,8 +21,10 @@ #define PACKAGE_VERSION 0xFFFFFFFF #define PACKAGE_VERSION_STRING L"Unknown" -#define CURRENT_FIRMWARE_VERSION 0x00000001 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000001" +#define __BUILD_STRING(x) L ## #x +#define BUILD_STRING(x) L"build #" __BUILD_STRING(x) +#define CURRENT_FIRMWARE_VERSION FixedPcdGet32 (PcdFirmwareRevision) +#define CURRENT_FIRMWARE_VERSION_STRING BUILD_STRING (FixedPcdGet32 (PcdFirmwareRevision)) #define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 #define IMAGE_ID SIGNATURE_64('S', 'N', 'I', 'S', 'Y', 'N', 'Q', 'U') From patchwork Tue Dec 12 10:38:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121503 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890638edb; Tue, 12 Dec 2017 02:38:27 -0800 (PST) X-Google-Smtp-Source: ACJfBos+ugvXuOH2MCKp0jnt58kkHhqazavdIpyvsYezmrvBWMl3UEIUoCkbwhVaIVBlUtYr06WK X-Received: by 10.98.8.210 with SMTP id 79mr1856116pfi.204.1513075107226; Tue, 12 Dec 2017 02:38:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513075107; cv=none; d=google.com; s=arc-20160816; b=Agj4vd/7kiVNN0wFiqbOHmSQkY3uK62pK8DX1xmsn0/DoJllSiggcX7HFBp3JieLF6 S5sZIQ6IiGtmrxU7y1kVSaNArGWoT+Aju/Rnvx6qrGOc6UFtoIYwXkef7pFkamt+/veP Cww5TrPPUNOAKqs0uN29WBKAyR0ZjmX+020ljW2IZiNyDhQBJAKFsUEO/qwI5YUSFEln 2lyvRHbwTlVBGTcF3sn9wTAKZwNWnSPolaDttZhEzYEE6N6PbD7qg24jbjuMqWQEXM0u 3PwKiunZMcfhj59DiaEL4akWEbFKt7o+1CG5ePzBvIU91CjhSVvLrvBwKSTJZS2xsDiW rDvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=APMJwyyghovOKVQLN7Bur/Itzi7T9Hvf23dLhhLuI1A=; b=hNpFGDO0bxLgIwPZ4Buy7VeVbOtefu32n1wedwlpMGGl7nkwqjzk83i8X+iZ/ctk6l IkGT36uEbn1hX6aXdZ2oXFlQ30iPutbneZVFfQGdoCYI8vTsCO1uGUN46cDfERLs2HGR WJX2M8xeXz8QkfZ36ZEBU9czxz4B0U0ZyyK7RKmHpbCXglgf98HIIBKUQs0sThc2NqbZ W6IsFeZF9eLwA/9FZSl0kJDBEnl4Q+bbwCwHVxpURelSsPpn6J6siOYq22mCAeGJfhNv u22tnzxcyJnELbwu8zq1k+BplZUwtSYO10VGhNSEClO7FMwOuggp/8HcfPxmhwA4FTmr AXjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=V76rLpFz; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id x6si11256797pgp.181.2017.12.12.02.38.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=V76rLpFz; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 07899220EE111; Tue, 12 Dec 2017 02:33:46 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 167D621B02832 for ; Tue, 12 Dec 2017 02:33:44 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id q9so20586997wre.7 for ; Tue, 12 Dec 2017 02:38:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KSsqfg8scmXSSTjNPYjvYQRQBTDdn798CCzXzjKRz1A=; b=V76rLpFzrLbqwjRVFGpH647CQ9PpSP7JdZcdJcosC7vh0fFWIiWuwse1sgP+Dd3jtx r1deuKI3yUiLfVyO5fJ9Al0ixVnlJuDPJVKiFrlYWm+LGd3eDs9SUxKalYpfMfZ37jU8 ZLvxaaZKUMbzasQQGpggL6RLec9Eif5+PVlAE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KSsqfg8scmXSSTjNPYjvYQRQBTDdn798CCzXzjKRz1A=; b=OV4TrV9G6reN4A/rJRxieqxhwbyjHSz4tFetddDca1WmXWC3tMe8QvugYTuiCm6yNs IlILNss1tn/d1qDedeWS5SHoQ5/RDmx25BJI0g4TRE6a7J54G7x/WBZLMSm0qj+vlvgW RVvuDuugdLAhY0QcHrKa2b/XgNPflCf0PrtgfglwLVWiQt4b8/IcdAmc9rI/ilyVDyc2 Gbsm67WcABYDfvX6j8GgmYzGxdBbgpxpDoOscvn5bk9uf5h0rdnGrbySkGw8qVmaGen/ sJqxyJG9kSeOpvEIsO4ZFQs/pI/ooZN+r66VQqX/dFz65EOCJLzKXKR8JnLPXPl4k1xr W5wA== X-Gm-Message-State: AKGB3mLtOdAK6COmya9ALLDffPmMCkHrK0GZEmtgSShChhNC/o5eGqLS yeaLYoLWVtGySjD+kjxurrN8hZKdZ+g= X-Received: by 10.223.136.38 with SMTP id d35mr3439705wrd.36.1513075101897; Tue, 12 Dec 2017 02:38:21 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:21 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:02 +0000 Message-Id: <20171212103807.18836-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Attempt to adhere more closely to the PCIe spec by ensuring that PERST# remains asserted for at least 100 ms. Give it a good margin, and delay for 150 ms; the additional boot time delay is not going to be noticeable by anyone anyway. So split the init routine in a pre and post part, and put the delay in the middle so we only need to do it once. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 1 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 46 +++++++++++++++----- 2 files changed, 36 insertions(+), 11 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 08484f4f8b1a..5d87727c73ba 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf @@ -45,6 +45,7 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + UefiBootServicesTableLib [FixedPcd] gArmTokenSpaceGuid.PcdPciIoTranslation diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e63b3a4bb23b..3da94945f96a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -176,6 +177,8 @@ SnPcieSetData ( } MmioWrite32 (Base + Offset, Data); + + ArmDataMemoryBarrier (); } STATIC @@ -194,6 +197,8 @@ SnPcieReadData ( Shift++; } + ArmDataMemoryBarrier (); + return (MmioRead32 (Base + Offset) >> Shift) & Mask; } @@ -219,12 +224,8 @@ SnDbiRoWrEn ( STATIC VOID -PciInitController ( - IN EFI_PHYSICAL_ADDRESS ExsBase, - IN EFI_PHYSICAL_ADDRESS DbiBase, - IN EFI_PHYSICAL_ADDRESS ConfigBase, - IN EFI_PHYSICAL_ADDRESS IoMemBase, - IN CONST PCI_ROOT_BRIDGE *RootBridge +PciInitControllerPre ( + IN EFI_PHYSICAL_ADDRESS ExsBase ) { SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0); @@ -256,7 +257,18 @@ PciInitController ( // 3: Set device_type (RC) SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4); +} +STATIC +VOID +PciInitControllerPost ( + IN EFI_PHYSICAL_ADDRESS ExsBase, + IN EFI_PHYSICAL_ADDRESS DbiBase, + IN EFI_PHYSICAL_ADDRESS ConfigBase, + IN EFI_PHYSICAL_ADDRESS IoMemBase, + IN CONST PCI_ROOT_BRIDGE *RootBridge + ) +{ // 4: Set Bifurcation 1=disable 4=able // 5: Supply Reference (It has executed) // 6: Wait for 10usec (Reference Clocks is stable) @@ -389,11 +401,23 @@ SynQuacerPciHostBridgeLibConstructor ( } for (Idx = 0; Idx < Count; Idx++) { - PciInitController (mBaseAddresses[Idx].ExsBase, - mBaseAddresses[Idx].DbiBase, - mBaseAddresses[Idx].ConfigBase, - mBaseAddresses[Idx].IoMemBase, - &RootBridges[Idx]); + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + } + + // + // The PCIe spec requires that PERST# is asserted for at least 100 ms after + // the power and clocks have become stable. So let's give a bit or margin, + // and stall for 150 ms between asserting PERST# on both controllers and + // de-asserting it again. + // + gBS->Stall (150 * 1000); + + for (Idx = 0; Idx < Count; Idx++) { + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, + mBaseAddresses[Idx].DbiBase, + mBaseAddresses[Idx].ConfigBase, + mBaseAddresses[Idx].IoMemBase, + &RootBridges[Idx]); } return EFI_SUCCESS; From patchwork Tue Dec 12 10:38:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121504 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890678edb; Tue, 12 Dec 2017 02:38:29 -0800 (PST) X-Google-Smtp-Source: ACJfBotPqh8Lxaqj+wxv1lX2HSZiqhL7z+1psXTfYw+qlr6fMAmOoFSp3nAxI5bmB6XsZMoXdk0Q X-Received: by 10.84.252.137 with SMTP id y9mr1770762pll.153.1513075109859; Tue, 12 Dec 2017 02:38:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513075109; cv=none; d=google.com; s=arc-20160816; b=QoQxbKTP+id7wO2Rf83peNlNJZOA1veb/ORCS+I9Ppfd0BGPT0a/Q7jGVE1Xi4Xlqt aq7eSpIobev/YJXflpcZG1XY1DTom1GkiJkJYQjzgtFrQEJKFwVYChNIG8OhmBxz9Qq0 5OomkDLjHujxecV+MF0oeroEFD4xzaa3ckIiI5QvVwlVaSYISyZK2FNfyW8b2Kc+tk4W bz4cTC9CmWLKxHSgy7qovMXC6x+LjSjjUknbc+jHGliOXcGBc4vHA1CjF4PnIbtEOBh1 51G/jTK9Rta4j1cPJIzmI27OPCUlhlLFdmwCeaUoHI7t7w1rkvml3syV/977bZfYZL2q vVUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=mxdQ9W9gJDndrvE9LE+HfcNwpVLQ+i32nM8TH7ULqpc=; b=xgmNuFdp3BYF/5m6savvuejBddLIK4i3/Rad6xMfouMt68qIX1hTs0axGgAjON49H9 D+nJnBqXnhTwlR3fhSJOzlTAyUUP9wInpaJ+wJ63F2Q3r2vxluGWS2wWt8vyiWTbYrQN W390LLtp1kOPCITKrWAZnvEieph2hZTli6WcdXfy4dBBFZeZGfLoqSgC/SidR5Pz3U3H PSyiNe9rMfWbPQJp0mmKaOIac32baiyH4/FLz1yjP/1P861IqTj+1Qst54+h63Ylhkbn KHyIkJJAuZvd6AbWvTZVR2LuTWwgYcpSM85rgFFRR35YdFVS5YXsusS5dnV8gXGb44rD G5EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=U/iQDIGc; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id u85si12545197pfi.278.2017.12.12.02.38.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=U/iQDIGc; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 482EA220EE10D; Tue, 12 Dec 2017 02:33:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90E5221A1099A for ; Tue, 12 Dec 2017 02:33:47 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id v22so20613913wrb.0 for ; Tue, 12 Dec 2017 02:38:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bTc5NTsvQOhQTmLQ79mDAauv6Ow4Y56JpzkqRRIqdDo=; b=U/iQDIGceXmC2wREJwHCfOLktnkUnSJelpGwpeWgGUKnhIavovtKMHAkt0GcbPbiSl nXPBi2IIzeDPNLeQ8v3NTV5ga+tSIqtXaz75mDqoZ5+UvG6DZVERR3Iac+/dfDwaF3Wv ogUEHhNPVk6YzO4gaR6oxU3K8gIT34BmKGG/4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bTc5NTsvQOhQTmLQ79mDAauv6Ow4Y56JpzkqRRIqdDo=; b=K0sFXvqU/3eGb+YzCSiW2/g41t9/OoklesWL1dofJnhk7RdcpHvFov1isg7RbiPZTd EjHlnrgPuuNsjgxgBDcBshzbIN1acg6D4zsYeRpf2nsjS3Rx4AmlwcOYqvo6v+Vs11xv 3UxP3xp6S8uN/Xppo5/GkC2opv5qtgJ0MiKAYlbavIJZ0IHIanSu+YxZzADow5BEJY6b VTeZo3vv7G0DFGkIvw0f4qfxhlcAtruUuRzQIcBilWDP5RfVljztxRu4jeSgEykXnRN0 Qesd5tfB+Rqf5ZFS9PpEvwHlRWuUzjTpkz+1v1PY8J+AnKBEMBSKx7RGT63Vdvspv8M0 GivA== X-Gm-Message-State: AKGB3mIY0XGIVj8hJs98DZAQA6mqCtd7ijFIfpiRNi2Qbz3ItHF4CRVz a3D56wrUdRTSHOVjfKJiYm46nse/uq4= X-Received: by 10.223.195.136 with SMTP id p8mr3654182wrf.4.1513075104383; Tue, 12 Dec 2017 02:38:24 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:23 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:03 +0000 Message-Id: <20171212103807.18836-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/8] Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" In order to accommodate the EVB, whose PCIe RC #0 should not be touched by software if no card is inserted, add a PCD that tells the PCIe driver code which RCs should be initialized and exposed to the PCI host bridge driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 19 ++++++++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 3 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 30 +++++++++----------- Silicon/Socionext/SynQuacer/SynQuacer.dec | 4 +++ 4 files changed, 36 insertions(+), 20 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 42cdce24b2c4..596862baf469 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -92,7 +92,7 @@ CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { #define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM #endif -STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = { +PCI_ROOT_BRIDGE mPciRootBridges[] = { { 0, // Segment 0, // Supports @@ -149,9 +149,20 @@ PciHostBridgeGetRootBridges ( OUT UINTN *Count ) { - *Count = ARRAY_SIZE (mPciRootBridges); - - return mPciRootBridges; + switch (PcdGet8 (PcdPcieEnableMask)) { + default: + ASSERT (FALSE); + case 0x0: + *Count = 0; + return NULL; + case 0x1: + case 0x2: + *Count = 1; + return &mPciRootBridges[PcdGet8 (PcdPcieEnableMask) - 1]; + case 0x3: + *Count = ARRAY_SIZE (mPciRootBridges); + return mPciRootBridges; + } } /** diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 5d87727c73ba..27fcba034418 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf @@ -49,3 +49,6 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdPciIoTranslation + +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 3da94945f96a..bea40e3dcfe8 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -120,6 +120,8 @@ #define MISC_CONTROL_1_OFF 0x8BC #define DBI_RO_WR_EN BIT0 +extern PCI_ROOT_BRIDGE mPciRootBridges[]; + STATIC VOID ConfigureWindow ( @@ -390,18 +392,12 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - PCI_ROOT_BRIDGE *RootBridges; - UINTN Count; UINTN Idx; - RootBridges = PciHostBridgeGetRootBridges (&Count); - ASSERT (Count == ARRAY_SIZE(mBaseAddresses)); - if (Count != ARRAY_SIZE(mBaseAddresses)) { - return EFI_INVALID_PARAMETER; - } - - for (Idx = 0; Idx < Count; Idx++) { - PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + } } // @@ -412,12 +408,14 @@ SynQuacerPciHostBridgeLibConstructor ( // gBS->Stall (150 * 1000); - for (Idx = 0; Idx < Count; Idx++) { - PciInitControllerPost (mBaseAddresses[Idx].ExsBase, - mBaseAddresses[Idx].DbiBase, - mBaseAddresses[Idx].ConfigBase, - mBaseAddresses[Idx].IoMemBase, - &RootBridges[Idx]); + for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, + mBaseAddresses[Idx].DbiBase, + mBaseAddresses[Idx].ConfigBase, + mBaseAddresses[Idx].IoMemBase, + &mPciRootBridges[Idx]); + } } return EFI_SUCCESS; diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 02dd6ac417f9..2e18cb33346d 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -38,3 +38,7 @@ [PcdsFixedAtBuild] gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004 gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005 + +[PcdsPatchableInModule, PcdsDynamic] + # Enable both RC #0 and RC #1 by default + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007 From patchwork Tue Dec 12 10:38:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121505 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890723edb; Tue, 12 Dec 2017 02:38:32 -0800 (PST) X-Google-Smtp-Source: ACJfBotZEOO9sIgWMI2X8I9oiMSWgZmkOLGdxC4rSIrb9g37+MGLJobqLnWqgAszqBiBzlyBQ+kz X-Received: by 10.101.97.75 with SMTP id o11mr1582618pgv.363.1513075112751; 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[198.145.21.10]) by mx.google.com with ESMTPS id j186si11282716pge.645.2017.12.12.02.38.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fqR5O+5g; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 89EB1220EE107; Tue, 12 Dec 2017 02:33:51 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A615E220EE107 for ; Tue, 12 Dec 2017 02:33:49 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id a41so20597431wra.6 for ; Tue, 12 Dec 2017 02:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3TL11bag/iZYHBcdSH5KCpn14J17x6tyE5z4O+tavlw=; b=fqR5O+5gzjsWUkBFGxQdoVWYa/Pt/27gK8DSDpkb/2wEbet0E07gjvRMrQfO9v8O5L WEL7XWm/KBNg76wq2ftVJG/3chsYfoM1OE1b91YmHedT98XSHrOTo7FzflJgMZWG4Qkv LVZbTmARL9fC7QlQgfu6Xn/1yMPW5mtVivzwg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3TL11bag/iZYHBcdSH5KCpn14J17x6tyE5z4O+tavlw=; b=V915iPRuiOfcJeXRPKuAp7u63RNQS2N1wNilFbk1XXh1q3/qh2UdeZEN/B6OclffwU ydj/txOBpUBvn8oGJalJ97DsjY4NaiYhMo/+/gag66xqFdgHeHg81CxLpR/0f5NeJrT7 V9p6/pZShbdY1bnFHOwrwyEhRpVhuF4u1C3lu68VNg08UsdUpiruqi8PwWykas525TId E5Flqwbmpe8uTqKmB+vbFfKc580JaMqIsr+ZNn0zNovJBDjJh51hhh3WETnG69KBXKqP +0kRqWSPsCKBmA88XPDrr1yQMlqKfkGOGQm5KVVlOvHOE/RxtlQSJtuxeq3enVj84g1W koPg== X-Gm-Message-State: AKGB3mIkRHqcGQJTeyGHvO5gIvIvQLwQHaiZ1WYRdU9KcNeWZA/CJJvc GEehf9pk0FD5cixaZPjIw5XIUt6DT2s= X-Received: by 10.223.156.202 with SMTP id h10mr1700685wre.174.1513075106702; Tue, 12 Dec 2017 02:38:26 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:25 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:04 +0000 Message-Id: <20171212103807.18836-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 5/8] Silicon/SynQuacer: disable PCI RC #0 DT node if disabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" If PCIe RC #0 is not enabled (due to the fact that the slot is not populated), set its DT node 'status' property to 'disabled' so that the OS will not attempt to attach to it. This means we will need to switch from the default DtPlatformDtbLoaderLib to a special one for our platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 8 +- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 3 +- Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 94 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 42 +++++++++ 4 files changed, 141 insertions(+), 6 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 5ec26f9cdd34..80728fedbc20 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -160,7 +160,8 @@ [LibraryClasses.common.DXE_CORE] PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf [LibraryClasses.common.DXE_DRIVER] - DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf + DtPlatformDtbLoaderLib|Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf @@ -611,10 +612,7 @@ [Components.common] # # Console preference selection # - EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf { - - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf - } + EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf # # DT support diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index bc8ddd452d4b..c71425664bdc 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -159,7 +159,8 @@ [LibraryClasses.common.DXE_CORE] PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf [LibraryClasses.common.DXE_DRIVER] - DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf + DtPlatformDtbLoaderLib|Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c new file mode 100644 index 000000000000..a93a6027e64d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -0,0 +1,94 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include + +#define DTB_PADDING 64 + +STATIC +VOID +DisableDtNode ( + IN VOID *Dtb, + IN CONST CHAR8 *NodePath + ) +{ + INT32 Node; + INT32 Rc; + + Node = fdt_path_offset (Dtb, NodePath); + if (Node < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Node))); + return; + } + Rc = fdt_setprop_string (Dtb, Node, "status", "disabled"); + if (Rc < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Rc))); + } +} + +/** + Return a pool allocated copy of the DTB image that is appropriate for + booting the current platform via DT. + + @param[out] Dtb Pointer to the DTB copy + @param[out] DtbSize Size of the DTB copy + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_NOT_FOUND No suitable DTB image could be located + @retval EFI_OUT_OF_RESOURCES No pool memory available + +**/ +EFI_STATUS +EFIAPI +DtPlatformLoadDtb ( + OUT VOID **Dtb, + OUT UINTN *DtbSize + ) +{ + EFI_STATUS Status; + VOID *OrigDtb; + VOID *CopyDtb; + UINTN OrigDtbSize; + + Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, + EFI_SECTION_RAW, 0, &OrigDtb, &OrigDtbSize); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + CopyDtb = AllocateCopyPool (OrigDtbSize + DTB_PADDING, OrigDtb); + if (CopyDtb == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + if (!(PcdGet8 (PcdPcieEnableMask) & BIT0)) { + DisableDtNode (CopyDtb, "/pcie@60000000"); + } + if (!(PcdGet8 (PcdPcieEnableMask) & BIT1)) { + DisableDtNode (CopyDtb, "/pcie@70000000"); + } + + *Dtb = CopyDtb; + *DtbSize = OrigDtbSize + DTB_PADDING; + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf new file mode 100644 index 000000000000..e1f564f73078 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf @@ -0,0 +1,42 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SynQuacerDtbLoaderLib + FILE_GUID = 59df69c4-8724-4e49-8974-d0691364338c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = DtPlatformDtbLoaderLib|DXE_DRIVER + +[Sources] + SynQuacerDtbLoaderLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + BaseLib + DebugLib + DxeServicesLib + FdtLib + MemoryAllocationLib + +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask + +[Guids] + gDtPlatformDefaultDtbFileGuid From patchwork Tue Dec 12 10:38:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121506 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890746edb; Tue, 12 Dec 2017 02:38:35 -0800 (PST) X-Google-Smtp-Source: ACJfBosKwuXJvtlHC5REIcbdGeHwX1x4+Hu6T34E9bWPDxf2CR7X3nTcx6LrI7UXEAxqjZdHzEYT X-Received: by 10.98.131.9 with SMTP id h9mr1853806pfe.30.1513075115259; Tue, 12 Dec 2017 02:38:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513075115; cv=none; d=google.com; s=arc-20160816; b=mICWjpPjEozvJSgg+ij/73TEythV8nGgtbfbMAzCyPXsJQOXsDptX7GxsCNFOCCwiZ sYXoQmJ9zhXPeqm9Qe6wjnbRwQD6MBI47ZwUorbtX+4bJMlgeNgIOarriIau50C8MJRs nTbZaqOnHE9lS1mHbDqZ4/OlPvfk957r8Y2WGmZJGWh9h6r7C55VAj0vRHYMUOGdu8Tl T0vHcxJM0EQUtKchIN816CDGEHlXmLk/Tc+DjoMNOoDsSb1rpImGOp6aJWottiqOcWHs rhBZTLg3wjj8piqZbCvFP6RNXahZBVtyP5mUDodt+uSla+mKYoatfPcN6stG9H5T1I5u +mdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=IwSC7gEmf+lY5QX+WgTeb4OjUw/8ar0/s8Qn76iu31E=; b=ainW4smJe8S6+SREvPiVIiSQLK6/NJ6z+XBe3Eh1r+JsPmOVgZMrDWbJvAzicF2sQa 0a+14tGLDS1PRw3rYPidWyZZW+eN3y6VdralrryVLBQ9JjgkaDOYD2FxRr+EI5n6vsjP 8SjThY5zmx3UpzuuozMAPUBZ7cb++O1SVibfRFkqdCBblP0pJNN2OZhv6ulTFdntpPKo tzDQh695/W19MfVQC/Meu/RBhcxmqRX8uTR5CKoX+YyJ1iMesqwjzwc0OkzYLAX1pt6c xfZp2VvG1i84pDc9iE7yYzIHdms8FDN6r8dChbo3GcV4V7ycVTg2fRzVOe4+hmNt9MRO CEQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=akSdxwqz; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id k11si11361682pga.340.2017.12.12.02.38.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=akSdxwqz; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C195C220EE119; Tue, 12 Dec 2017 02:33:52 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA6BC220EE115 for ; Tue, 12 Dec 2017 02:33:51 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id x49so20562434wrb.13 for ; Tue, 12 Dec 2017 02:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PU7ms/RrRVJMKOJrexx0EuB55mzzfnUUIroAJi4CSqY=; b=akSdxwqzUugnEqQbLOIMDNr9IKV2vo+VCWY8nWoczdD+bw6UNSQvZ3tRgfrRT/11e8 0Aq9mYkIeb9bN5HoclRq4eoFitAazUhXdq+2JEBiRLYofY03TXVr6vPonBX138rQJRGx Q6uWer02cRAIuczaerN3dWH4bRDtLUqOypZ5o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PU7ms/RrRVJMKOJrexx0EuB55mzzfnUUIroAJi4CSqY=; b=Gjkk9oMZ2Ydk7Z+animfgB2gI04Om+TfsW+OLAow67xdYqmZFVX/c3w8ubm0n7Yfpr 12uFGG84LHHirYcC/Y/7BxkOpNuIVXXi/CYMrHZwan3fd5Y+FSSFDTCSrv+YZVpDW2ev vu1UBAWWmel6pWxrpRU2NKHMGWkSZVgoGzYPUoq1vn+YriuPXU3ngaBi7u6b4zvMiFbk myX8pt8kKZwLc7LUXU1rnXagAbMbbl8NjVScRQ6EF2cFMF4RnkKcUWPzsomWb5WAvCc3 HKiEt94PZ1u1PA4vU8P8aPot8mYiNv/PbGFRXpwS38R9mAhBRlcII8EUf2e8HnoUNXPq /nIA== X-Gm-Message-State: AKGB3mIDoWq+QY6dVTK+mZY6oovHoIy2sBqBwShiQqBrtUm/AMsOhOwV pd9cGr66ZNj1i+Eok97H8rFCh0zo4CA= X-Received: by 10.223.175.49 with SMTP id z46mr3387635wrc.12.1513075108814; Tue, 12 Dec 2017 02:38:28 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:27 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:05 +0000 Message-Id: <20171212103807.18836-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 6/8] Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The EVB does not boot if PCI RC #0 has no card inserted, and will hang in the PCIe initialization code. So let's check the presence detect GPIO, and only enable PCI RC #0 if it is asserted. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 7 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 70 ++++++++++++++------ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 2 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 1 + 4 files changed, 59 insertions(+), 21 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index c71425664bdc..917632c2b4c1 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -374,6 +374,10 @@ [PcdsFixedAtBuild.common] # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 + # On the EVB, PCIe RC #0 should not be enabled from software if no card + # was inserted, or the boot will hang. + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|15 + !if $(BUILD_NUMBER) > 1 gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER)" !endif @@ -395,6 +399,9 @@ [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF + # enable RC #1 only by default, RC #0 will be enabled if an endpoint is detected + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x2 + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c index e4aec8b09169..7c529a22c6ef 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c @@ -24,7 +24,10 @@ #include #include -#define CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED MAX_UINT8 +#define GPIO_NOT_IMPLEMENTED MAX_UINT8 + +#define CLEAR_SETTINGS_GPIO_ASSERTED 1 +#define PCIE_GPIO_CARD_PRESENT 0 STATIC CONST DRAM_INFO *mDramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase); @@ -100,6 +103,35 @@ STATIC CONST EFI_PEI_PPI_DESCRIPTOR mDramInfoPpiDescriptor = { &mDramInfoPpi }; +STATIC +EFI_STATUS +ReadGpioInput ( + IN EMBEDDED_GPIO_PPI *Gpio, + IN UINT8 Pin, + OUT UINTN *Value + ) +{ + EFI_STATUS Status; + + if (Pin == GPIO_NOT_IMPLEMENTED) { + return EFI_NOT_FOUND; + } + + Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to set GPIO %d as input - %r\n", + __FUNCTION__, Pin, Status)); + return Status; + } + + Status = Gpio->Get (Gpio, Pin, Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to get GPIO %d state - %r\n", + __FUNCTION__, Pin, Status)); + } + return Status; +} + EFI_STATUS EFIAPI PlatformPeim ( @@ -109,30 +141,26 @@ PlatformPeim ( EMBEDDED_GPIO_PPI *Gpio; EFI_STATUS Status; UINTN Value; - UINT8 Pin; ASSERT (mDramInfo->NumRegions > 0); - Pin = FixedPcdGet8 (PcdClearSettingsGpioPin); - if (Pin != CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED) { - Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL, - (VOID **)&Gpio); - ASSERT_EFI_ERROR (Status); + Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL, + (VOID **)&Gpio); + ASSERT_EFI_ERROR (Status); - Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to set GPIO as input - %r\n", - __FUNCTION__, Status)); - } else { - Status = Gpio->Get (Gpio, Pin, &Value); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to get GPIO state - %r\n", - __FUNCTION__, Status)); - } else if (Value > 0) { - DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__)); - PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS); - } - } + Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdClearSettingsGpioPin), &Value); + if (!EFI_ERROR (Status) && Value == CLEAR_SETTINGS_GPIO_ASSERTED) { + DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__)); + PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS); + } + + Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdPcie0PresenceDetectGpioPin), + &Value); + if (!EFI_ERROR (Status) && Value == PCIE_GPIO_CARD_PRESENT) { + DEBUG ((DEBUG_INFO, + "%a: card detected in PCIe RC #0, enabling\n", __FUNCTION__)); + Status = PcdSet8S (PcdPcieEnableMask, PcdGet8 (PcdPcieEnableMask) | BIT0); + ASSERT_EFI_ERROR (Status); } // diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf index a6501fb205e1..eb6a5bf9ac1a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf @@ -43,6 +43,7 @@ [FixedPcd] gArmTokenSpaceGuid.PcdFvSize gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin gSynQuacerTokenSpaceGuid.PcdDramInfoBase + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin [Ppis] gEdkiiEmbeddedGpioPpiGuid ## CONSUMES @@ -51,6 +52,7 @@ [Ppis] [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask [Depex] gEdkiiEmbeddedGpioPpiGuid diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 2e18cb33346d..a21f12b5bc32 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -36,6 +36,7 @@ [PcdsFixedAtBuild] # GPIO pin index [0 .. 31] or MAX_UINT8 for not implemented gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004 + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|0xFF|UINT8|0x00000006 gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005 From patchwork Tue Dec 12 10:38:06 2017 Content-Type: text/plain; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id c11si12550130pfh.68.2017.12.12.02.38.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ZJfnLfkh; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 04C90220EE118; Tue, 12 Dec 2017 02:33:56 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 431A5220EE11C for ; Tue, 12 Dec 2017 02:33:54 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id h1so20548045wre.12 for ; Tue, 12 Dec 2017 02:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aeLXIMQSZpP7jzWMs6f6bdMBF8rFNik8hkTk1gyaN/w=; b=ZJfnLfkhmqvL6XVjl1r/ASMg+pkv8mWI2lTkvvqQ20HS4of13xtB4ulgB7LuulAa4G aGc+pbGQczfASUlrB0QVvAPZl+p6N9uB+yyJ6xQCqtfZNNLkwu8IySpgmr2OZn7gzf7q DdsR65nngns6UhQ0UyEbXwkIf2OAwkdxf7+xE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aeLXIMQSZpP7jzWMs6f6bdMBF8rFNik8hkTk1gyaN/w=; b=FnjQIPgev9LK6GQdPrp0mPvxfm681zbeBvlLaMsjL/sp6p2Pbxvih7WPZTOfYlgYqW 6ImthYViABoLNrvCQp+gHPj6LGcWIDGVlWrS6SgLBtQ8/QzuAVY6pSmN0CxPxntQoj5x EATFLw8SFtP9zam31hjsftKcqzgZltoF1gVvXOUbm4Eky7DqOWSoJiDag/lIvO4ZWIrH og7nZpKhj7BWX7gLuXS23kloGsl4NR8FBK6tefczl6oUSl2uBrCCdV7SwZIHtD8RwUrx YoSfMPtoE3I3xBdtdBAwtOZjSYbDVErhdwXvA0Lqh+IrlGY6vHAdnUxuOYvfR4O3iCUE SAgg== X-Gm-Message-State: AKGB3mJBXDsS3Aq7Uvv9ZTpsk/UDhULv4whSIvf0xNvy/I7Lcy1Il7YE 5F0I+cQqzw2jn0XVGIP7x20Zbui/Gx4= X-Received: by 10.223.154.43 with SMTP id z40mr3567269wrb.210.1513075111325; Tue, 12 Dec 2017 02:38:31 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:30 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:06 +0000 Message-Id: <20171212103807.18836-8-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 7/8] Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the OS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Masahisa KOJIMA , daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Masahisa KOJIMA In order to be able to use UART #0 on the DeveloperBox's 96boards low speed connector, expose it to the OS by adding a node to the device tree. This requires a CM3 firmware build that makes the SCP detach from the serial port after boot. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Masahisa KOJIMA Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index c9fee5d1f350..37a3981f0360 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -440,6 +440,15 @@ clock-names = "uartclk", "apb_pclk"; }; + fuart: fuart@51040000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x51040000 0x0 0x1000>; + interrupts = ; + clock-frequency = <62500000>; + reg-io-width = <4>; + reg-shift = <2>; + }; + clk_netsec: refclk125mhz { compatible = "fixed-clock"; clock-frequency = <125000000>; From patchwork Tue Dec 12 10:38:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121508 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890809edb; Tue, 12 Dec 2017 02:38:40 -0800 (PST) X-Google-Smtp-Source: ACJfBosF95Tr5kdP2d68lEedbTNGLCT+Lppedac3INzv7fZgZi3yD1SzmKhmDEC7GF1b3aQTUSkG X-Received: by 10.84.195.3 with SMTP id i3mr1833264pld.282.1513075120594; Tue, 12 Dec 2017 02:38:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513075120; cv=none; d=google.com; s=arc-20160816; b=FQwKaXv59lvJqNXvIwZk3ULL5oxF8OEVBBGM+Pxej/ZW5TqIaJolLt8am/+iIXZMeD N4bbkA3nkn2JRA0q1KQvgZAzGBnGAbfnPG9O2pG2wiceLOWUOfW3gWvUXwSbDkfCcCEG /6c2BbehBFlRCyV6KB2xtu3r6mqtZLELzQgcFa9p/YIXw44OAjknw/1g0hyi1UN5D0yi p/UkfblJGMKJ/nigA40hS1rqqvdZE1qVzlegis0FhVUW5ODmqq9Dg44PHvnFKskOOAzW qvGXqd/UYfURinJdGh9VnXI6mg8VYoIzsa0y5ATwbdY6XHR9z7c1g3ALiJukLCT7O4L0 CavQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=ckV7A8cBucHEaUsh5NIp1rFSEIQuyJXK0SCeC6jcsB4=; b=Kx5t1GBv5KKYIUiyV5T5nPO1xptlPo07hDNE8QQpubIu5jNOPSOQ3GdeEcRt39w88V ogumt2tT+1iHON5f/Hv0IY35xJdlxS6+cR/yoMePWXffCO5zauWakcDmn1Z/LMhoApwT dyA+1tJSgI7XEasWryN/USy+JSCpKNzpAzKHTjlJ2Rw+Cz1w0MlZm/Nu6IkPViLwDKbF UWyYD1HHOO1DRtjxL1l4YsLIJE9CRW/NQ42FhEqYNXI9OyZiIMEwhaGS44JGd0z5JZzb OTu8euEkmSX+xgz7RRxSW+Bh/sTiOtZhI+t4nf7jp/rqKnYoZ4ZwjfTkUUSMr9wxK0z4 hSKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kXO/r7ma; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id e4si11558136pln.445.2017.12.12.02.38.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kXO/r7ma; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 42FCD220EE11F; Tue, 12 Dec 2017 02:33:58 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BE227220EE115 for ; Tue, 12 Dec 2017 02:33:56 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id l22so20578441wrc.11 for ; Tue, 12 Dec 2017 02:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vR7g5PrIl3rdXaOpQHxuIsdsB8ooiiqX+hzRXtSMeDI=; b=kXO/r7ma9aPEsVzUrwYbPm26O2bSwOtyULM1Qw5mLPwIzV72WXVqvmziC5TPjZ8RMI UPVypxyTg8ANr5QAPjrttdk6GZjLE7he6nlNvIn7DfhcmWaG3kKJ4Oqtrz98uD5HHqr8 SWQENbWVYDLP21hhFa2sWsBQnxnbMrmD7f2h4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vR7g5PrIl3rdXaOpQHxuIsdsB8ooiiqX+hzRXtSMeDI=; b=ObCnQtQ5znPe1Q1PyEGd3WWZDELl/z/A4gdm5zoDA7XQwq118Plg1pen2GZhSM1iJX yiOrwK7+H/vwvbrCrx/4rqXe/iEZ2w3FblhUG+JNst9BSkJJyOWYYNcfgCC0ANF5n/+w gmSu8FejzGHQH9EiyBMsQ+NgrRtYt3SbgOqcQp3ASUkNYNePIG+16RZAE/r9gF7JJ+Bc NuDHZxTtN3hTTuEfgRqQDyQ0QkI1E+Acu2IytuBTGJJtVZ14gggRno4mX4M2NNRRG61e XdUM8TZhJ9y1F/frgBbq/bH8wdhocBjJ0UFuYE9KzM8csgQdTGN/GZHb01p7IXSt6icP Y1fQ== X-Gm-Message-State: AKGB3mJV5BfSlAfTJIps6peTyydLGabbnhQ3zveYPY2BtTYO3608AJuv QIwCBYw2SMJErVPbsO3XnZXyv1IOCG8= X-Received: by 10.223.134.216 with SMTP id 24mr3511658wry.156.1513075113571; Tue, 12 Dec 2017 02:38:33 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:32 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:07 +0000 Message-Id: <20171212103807.18836-9-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 8/8] Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" For some reason, the Asmedia 118x PCIe switch needs a little help to make sure that the downstream links train at Gen2 speed. So add a PCI I/O protocol notifier that implements this for each PCIe downstream port that is present on the system. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + 4 files changed, 184 insertions(+), 9 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c new file mode 100644 index 000000000000..b069b42d0a42 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c @@ -0,0 +1,140 @@ + /** @file + SynQuacer DXE platform driver - PCIe support + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include "PlatformDxe.h" + +#define ASMEDIA_VID 0x1b21 +#define ASM1182E_PID 0x1182 +#define ASM1184E_PID 0x1184 + +#define ASM118x_PCIE_CAPABILITY_OFFSET 0x80 +#define ASM118x_PCIE_LINK_CONTROL_OFFSET (ASM118x_PCIE_CAPABILITY_OFFSET + \ + OFFSET_OF (PCI_CAPABILITY_PCIEXP, \ + LinkControl)) + +STATIC VOID *mPciProtocolNotifyRegistration; +STATIC EFI_EVENT mPciProtocolNotifyEvent; + +#pragma pack(1) +typedef struct { + EFI_PCI_CAPABILITY_HDR CapHdr; + PCI_REG_PCIE_CAPABILITY Pcie; +} PCIE_CAP; +#pragma pack() + +STATIC +VOID +RetrainAsm1184eDownstreamPort ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINT16 PciVidPid[2]; + EFI_STATUS Status; + PCIE_CAP Cap; + PCI_REG_PCIE_LINK_CONTROL LinkControl; + + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, + ARRAY_SIZE (PciVidPid), &PciVidPid); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n", + __FUNCTION__, Status)); + return; + } + + if (PciVidPid[0] != ASMEDIA_VID || + (PciVidPid[1] != ASM1182E_PID && PciVidPid[1] != ASM1184E_PID)) { + return; + } + + // + // The upstream and downstream ports share the same PID/VID, so check + // the port type. This assumes the PCIe Express capability block lives + // at offset 0x80 in the port's config space, which is known to be the + // case for these particular chips. + // + ASSERT (sizeof (Cap) == sizeof (UINT32)); + ASSERT (sizeof (LinkControl) == sizeof (UINT16)); + + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, + ASM118x_PCIE_CAPABILITY_OFFSET, 1, &Cap); + ASSERT_EFI_ERROR (Status); + ASSERT (Cap.CapHdr.CapabilityID == EFI_PCI_CAPABILITY_ID_PCIEXP); + + if (Cap.Pcie.Bits.DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) { + return; + } + + DEBUG ((DEBUG_INFO, "%a: retraining ASM1184x downstream PCIe port\n", + __FUNCTION__)); + + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, + ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl); + ASSERT_EFI_ERROR (Status); + + LinkControl.Bits.RetrainLink = 1; + + Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, + ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID +EFIAPI +OnPciIoProtocolNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo; + EFI_STATUS Status; + EFI_HANDLE HandleBuffer; + UINTN BufferSize; + + while (TRUE) { + BufferSize = sizeof (EFI_HANDLE); + Status = gBS->LocateHandle (ByRegisterNotify, NULL, + mPciProtocolNotifyRegistration, &BufferSize, &HandleBuffer); + if (EFI_ERROR (Status)) { + break; + } + + Status = gBS->HandleProtocol (HandleBuffer, &gEfiPciIoProtocolGuid, + (VOID **)&PciIo); + ASSERT_EFI_ERROR (Status); + + // + // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its + // 2-port sibling of which samples were used in development) needs a + // little nudge to get it to train the downstream links at Gen2 speed. + // + RetrainAsm1184eDownstreamPort (PciIo); + } +} + +EFI_STATUS +EFIAPI +RegisterPcieNotifier ( + VOID + ) +{ + mPciProtocolNotifyEvent = EfiCreateProtocolNotifyEvent ( + &gEfiPciIoProtocolGuid, + TPL_CALLBACK, + OnPciIoProtocolNotify, + NULL, + &mPciProtocolNotifyRegistration); + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index e58a2093eb49..098a4dbd324e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -12,15 +12,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "PlatformDxe.h" STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] = { { @@ -202,5 +194,8 @@ PlatformDxeEntryPoint ( SmmuEnableCoherentDma (); + Status = RegisterPcieNotifier (); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h new file mode 100644 index 000000000000..d1dad2a3eace --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -0,0 +1,37 @@ +/** @file + SynQuacer DXE platform driver. + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __PLATFORM_DXE_H__ +#define __PLATFORM_DXE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +RegisterPcieNotifier ( + VOID + ); + +#endif diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 00c1130906c4..84498eaddcef 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,6 +23,7 @@ [Defines] ENTRY_POINT = PlatformDxeEntryPoint [Sources] + Pcie.c PlatformDxe.c [Packages] @@ -41,6 +42,7 @@ [LibraryClasses] MemoryAllocationLib UefiBootServicesTableLib UefiDriverEntryPoint + UefiLib [Guids] gFdtTableGuid @@ -50,6 +52,7 @@ [Guids] [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gEfiPciIoProtocolGuid ## CONSUMES gPcf8563RealTimeClockLibI2cMasterProtolGuid ## PRODUCES [FixedPcd]