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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id n3sm4588916ljj.59.2020.09.15.04.01.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Sep 2020 04:01:17 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com, "Andrew F . Davis" , Roger Quadros Subject: [PATCH v6 1/5] dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings Date: Tue, 15 Sep 2020 13:00:47 +0200 Message-Id: <1600167651-20851-2-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support up to 64 input events on most SoCs with individual control configuration and h/w prioritization. These events are mapped onto 10 output interrupt lines through two levels of many-to-one mapping support. Different interrupt lines are routed to the individual PRU cores or to the host CPU or to other PRUSS instances. The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide a higher number of host interrupts (20 vs 10) and can handle an increased number of input events (160 vs 64) from various SoC interrupt sources. Add the bindings document for these interrupt controllers on all the applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci architecture based OMAPL138 SoCs, and the K3 architecture based AM65x and J721E SoCs. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Rob Herring --- v5->v6: - No change. v4->v5: - Fix typo in commit description. - Update interrupt-cells description regarding each cells meaning. v3->v4: - Drop allOf references to interrupt-controller.yaml and interrupts.yaml. - Drop items descriptions and use only maxItems: 1 as suggested by Rob. - Convert irqs-reserved property from uint8-array to bitmask. - Minor descriptions updates. - Change interrupt-cells to 3 in order to provide 2-level mapping description for interrupts routed to the main CPU (as Marc requested). - Merge the irqs-reserved and irqs-shared to one property since they can be handled by one logic. - Drop reviewed-by due to introduced changes. - Add another example illustrating irqs-reserved property usage. v2->v3: - Convert dt-binding to YAML v1->v2: - https://patchwork.kernel.org/patch/11069767/ --- .../interrupt-controller/ti,pruss-intc.yaml | 158 +++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml -- 2.7.4 diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml new file mode 100644 index 0000000..bbf79d1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI PRU-ICSS Local Interrupt Controller + +maintainers: + - Suman Anna + +description: | + Each PRU-ICSS has a single interrupt controller instance that is common + to all the PRU cores. Most interrupt controllers can route 64 input events + which are then mapped to 10 possible output interrupts through two levels + of mapping. The input events can be triggered by either the PRUs and/or + various other PRUSS internal and external peripherals. The first 2 output + interrupts (0, 1) are fed exclusively to the internal PRU cores, with the + remaining 8 (2 through 9) connected to external interrupt controllers + including the MPU and/or other PRUSS instances, DSPs or devices. + + The property "ti,irqs-reserved" is used for denoting the connection + differences on the output interrupts 2 through 9. If this property is not + defined, it implies that all the PRUSS INTC output interrupts 2 through 9 + (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt + controller. + + The K3 family of SoCs can handle 160 input events that can be mapped to 20 + different possible output interrupts. The additional output interrupts (10 + through 19) are connected to new sub-modules within the ICSSG instances. + + This interrupt-controller node should be defined as a child node of the + corresponding PRUSS node. The node should be named "interrupt-controller". + +properties: + compatible: + enum: + - ti,pruss-intc + - ti,icssg-intc + description: | + Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, + AM335x family of SoCs, + AM437x family of SoCs, + AM57xx family of SoCs + 66AK2G family of SoCs + Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + description: | + All the interrupts generated towards the main host processor in the SoC. + A shared interrupt can be skipped if the desired destination and usage is + by a different processor/device. + + interrupt-names: + minItems: 1 + maxItems: 8 + items: + pattern: host_intr[0-7] + description: | + Should use one of the above names for each valid host event interrupt + connected to Arm interrupt controller, the name should match the + corresponding host event interrupt number. + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: | + Client users shall use the PRU System event number (the interrupt source + that the client is interested in) [cell 1], PRU channel [cell 2] and PRU + host_event (target) [cell 3] as the value of the interrupts property in + their node. The system events can be mapped to some output host + interrupts through 2 levels of many-to-one mapping i.e. events to channel + mapping and channels to host interrupts so through this property entire + mapping is provided. + + ti,irqs-reserved: + $ref: /schemas/types.yaml#definitions/uint8 + description: | + Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC + output interrupts 2 through 9) that are not connected to the Arm interrupt + controller or are shared and used by other devices or processors in the + SoC. Define this property when any of 8 interrupts should not be handled + by Arm interrupt controller. + Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt + connected to MPU + - AM65x and J721E SoCs have "host_intr5", "host_intr6" and + "host_intr7" interrupts connected to MPU, and other ICSSG + instances. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + /* AM33xx PRU-ICSS */ + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + + - | + + /* AM4376 PRU-ICSS */ + #include + pruss@0 { + compatible = "ti,am4376-pruss"; + reg = <0x0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", + "host_intr6", "host_intr7"; + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ + }; + }; From patchwork Tue Sep 15 11:00:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 312032 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp30156ilg; Tue, 15 Sep 2020 17:57:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJynzC4wPxfNI8iDczLWHNRSx0z5I45R5NlRHmCgJoPD6pZLVWx7bibrtKJRwDSQpwCSI0jK X-Received: by 2002:a17:906:e50:: with SMTP id q16mr23772463eji.544.1600217840147; Tue, 15 Sep 2020 17:57:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600217840; cv=none; d=google.com; s=arc-20160816; b=DqxzUJiBoj1TOmpRQDZboBEUJ5keOyXoeDhGjKkCu11lgFCC4wkbsNb24U/PL686rn VlYomfQjW49Tdywys6bvnCUYreoHy1t4kwmtYpmOPQJy1/8X/sJyDtB/4OPtlhLs1Om8 LKBZFIxn3D+OFh7+QQYnxVSK5K5YQHMZ3cq79taFuggfD5ScKMTtjX5y0a9R8w0wb7sb 2tw2Tkdhg/HWso24EtuZy7hB21UNTmRRABlGD1qGuaTzFaiypOIDGcIYVAdBYznWusSI 4bQNaZeUUsK6OcNBbPlum6JFkvN/strIHXAuNq6aoIiHf0rDUuBOgn1IPa560ZorX/Yq /Gvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=xSpHbTMRF5l19WgNcjU80aU88bYV7d4gSwfI8EzLalw=; b=SgLwj3CXSshnSU6Y9H0EUjlyKDV4fD7qF0PSp3w4DsvPy1Dbryz/U5OPxS2sWjIXwx W9+0iUevJgMT3DaACVcSQX5amHwcRy11ZTqyfnqFN3BjKxdVpsSngQiu2H/Aac6yIscT OdpycHg2wBJHBsa/pJbUBtPDuhFv9eSkMhEOeisl8cW17H5dAqexFWJtD9B/pNY6KM0u XzvNkV5SkDQaPNwVpHXmWqZPGKSZHwi8ArfPL9hW+Ft4M5aB/5GiSZ8yPICY4C21e29J xPF8gP0laxg9oIx0I+RhNKUVRljm+aKVmdehrMcNKv6lCRtxXi6s/Izq9CvVROLZtSt6 AyIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yyMFQuI1; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id n3sm4588916ljj.59.2020.09.15.04.01.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Sep 2020 04:01:21 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com Subject: [PATCH v6 3/5] irqchip/irq-pruss-intc: Add logic for handling reserved interrupts Date: Tue, 15 Sep 2020 13:00:49 +0200 Message-Id: <1600167651-20851-4-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The PRUSS INTC has a fixed number of output interrupt lines that are connected to a number of processors or other PRUSS instances or other devices (like DMA) on the SoC. The output interrupt lines 2 through 9 are usually connected to the main Arm host processor and are referred to as host interrupts 0 through 7 from ARM/MPU perspective. All of these 8 host interrupts are not always exclusively connected to the Arm interrupt controller. Some SoCs have some interrupt lines not connected to the Arm interrupt controller at all, while a few others have the interrupt lines connected to multiple processors in which they need to be partitioned as per SoC integration needs. For example, AM437x and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5 connected to the other PRUSS, while AM335x has host interrupt 0 shared between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and a DMA controller. Add logic to the PRUSS INTC driver to ignore both these shared and invalid interrupts. Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v5->v6: - No change. v4->v5: - Rename: s/invalid_intr/irqs_reserved/ v3->v4: - Due to changes in DT bindings which converts irqs-reserved property from uint8-array to bitmask requested by Rob introduce relevant changes in the driver. - Merge the irqs-reserved and irqs-shared to one property since they can be handled by one logic (relevant change was introduced to DT binding). - Update commit message. v2->v3: - Extra checks for (intc->irqs[i]) in error/remove path was moved from "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts" to this patch v1->v2: - https://patchwork.kernel.org/patch/11069757/ --- drivers/irqchip/irq-pruss-intc.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 319e431..396dc55 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -484,7 +484,7 @@ static int pruss_intc_probe(struct platform_device *pdev) struct pruss_intc *intc; struct pruss_host_irq_data *host_data; int i, irq, ret; - u8 max_system_events; + u8 max_system_events, irqs_reserved = 0; data = of_device_get_match_data(dev); if (!data) @@ -504,6 +504,16 @@ static int pruss_intc_probe(struct platform_device *pdev) if (IS_ERR(intc->base)) return PTR_ERR(intc->base); + ret = of_property_read_u8(dev->of_node, "ti,irqs-reserved", + &irqs_reserved); + + /* + * The irqs-reserved is used only for some SoC's therefore not having + * this property is still valid + */ + if (ret < 0 && ret != -EINVAL) + return ret; + pruss_intc_init(intc); mutex_init(&intc->lock); @@ -514,6 +524,9 @@ static int pruss_intc_probe(struct platform_device *pdev) return -ENOMEM; for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + if (irqs_reserved & BIT(i)) + continue; + irq = platform_get_irq_byname(pdev, irq_names[i]); if (irq <= 0) { ret = (irq == 0) ? -EINVAL : irq; @@ -538,8 +551,11 @@ static int pruss_intc_probe(struct platform_device *pdev) return 0; fail_irq: - while (--i >= 0) - irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); + while (--i >= 0) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } irq_domain_remove(intc->domain); @@ -553,8 +569,11 @@ static int pruss_intc_remove(struct platform_device *pdev) unsigned int hwirq; int i; - for (i = 0; i < MAX_NUM_HOST_IRQS; i++) - irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } for (hwirq = 0; hwirq < max_system_events; hwirq++) irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); From patchwork Tue Sep 15 11:00:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 303988 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2430998ilg; Tue, 15 Sep 2020 04:15:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzGjU02Ci01kbhhLNv8/d45KhUXgeWYL4oE26YFVGpR+GPuyz+M6+ii4UI/DelXtvcYp9dw X-Received: by 2002:aa7:c987:: with SMTP id c7mr22245824edt.385.1600168545590; Tue, 15 Sep 2020 04:15:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600168545; cv=none; d=google.com; s=arc-20160816; b=DB7Ca7tjc1DjJ8YKaK0C8acZAAcwLCW2B4bbl3dA+I2wKW2sfwstxGiBY28U/FSo4z IBX2CJTRcX8vBjZP757typLMagl/vO/LIVlQHaZk5tU2IilyJj9K02Kyr1BtW4W6c809 d9JB/b7RZ7INoCh4qgKZbPzXj/FYwCve/qDmght6C0Jmg53b2MiA4/odcNxaYs36CcPr hKgKseqSxn0dkRAhy6mybq09lK0S96I+AHjhHON1dCOMgvjeNwiYega7bPtP3ELvlPDC aqWnAILqwVmMdCiRXVKAaJ4zjDBSVGc53VGs2J8PMKQ5Pbj3/zUnmmzQ1KfRfmDgZ1f4 KNOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=0bFMdRSpPXTVw6FkASDzFuci7f9roVwhgsTsGiODYGg=; b=wxJnDNmdDSMo4wAh1C9pXE4Gey0ukrcUBkl3DU/s3WKZl5cDiX8pjEM2MYOCs79exi q8hT0K8cDR2gnmy7/RWTVoRLCVBSM1Tutk1VGE60IZ/Km6VIXzyln+SRAbZ4knuXu1uV 1rqrWCQuOBojvVMVVTZca3Q6gM3V2gHghoPteXVa20cCnI3GNN19UrQKub68/t4bcZH2 h6AMHPArt2D7Ew9YVnBdByJ4P8dsHXDMGTSlS2wUm2o0mhZTcwqboVWfufxxJz/3Ueen 9eHeimiCykafOmKKUfWT4/gGPkZ6ZOBIGUnb7IlXD50kG839zqKkLLY2BrpVkEB5pOGd BSkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bu9PMoyx; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id n3sm4588916ljj.59.2020.09.15.04.01.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Sep 2020 04:01:23 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com Subject: [PATCH v6 4/5] irqchip/irq-pruss-intc: Implement irq_{get, set}_irqchip_state ops Date: Tue, 15 Sep 2020 13:00:50 +0200 Message-Id: <1600167651-20851-5-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: David Lechner This implements the irq_get_irqchip_state and irq_set_irqchip_state callbacks for the TI PRUSS INTC driver. The set callback can be used by drivers to "kick" a PRU by injecting a PRU system event. Signed-off-by: David Lechner Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Lee Jones --- v5->v6: - Drop example from the commit log v4->v5: - No change. v3->v4: - Update commit message v2->v3: - Get rid of unnecessary pruss_intc_check_write() and use pruss_intc_write_reg directly. v1->v2: - https://patchwork.kernel.org/patch/11069769/ --- drivers/irqchip/irq-pruss-intc.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) -- 2.7.4 diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 396dc55..41c6271 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -12,6 +12,7 @@ * Copyright (C) 2019 David Lechner */ +#include #include #include #include @@ -323,6 +324,43 @@ static void pruss_intc_irq_relres(struct irq_data *data) module_put(THIS_MODULE); } +static int pruss_intc_irq_get_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + u32 reg, mask, srsr; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + reg = PRU_INTC_SRSR(data->hwirq / 32); + mask = BIT(data->hwirq % 32); + + srsr = pruss_intc_read_reg(intc, reg); + + *state = !!(srsr & mask); + + return 0; +} + +static int pruss_intc_irq_set_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, + bool state) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (state) + pruss_intc_write_reg(intc, PRU_INTC_SISR, data->hwirq); + else + pruss_intc_write_reg(intc, PRU_INTC_SICR, data->hwirq); + + return 0; +} + static struct irq_chip pruss_irqchip = { .name = "pruss-intc", .irq_ack = pruss_intc_irq_ack, @@ -330,6 +368,8 @@ static struct irq_chip pruss_irqchip = { .irq_unmask = pruss_intc_irq_unmask, .irq_request_resources = pruss_intc_irq_reqres, .irq_release_resources = pruss_intc_irq_relres, + .irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state, + .irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state, }; static int pruss_intc_validate_mapping(struct pruss_intc *intc, int event, From patchwork Tue Sep 15 11:00:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 303987 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2430991ilg; Tue, 15 Sep 2020 04:15:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJynnYBKQ6Wyf94Npywzgo86nItAwmJES95W8ow61FeGpEC+OdEP78CGcweepvXfADVWEwcE X-Received: by 2002:a17:906:82d1:: with SMTP id a17mr19323882ejy.385.1600168545027; Tue, 15 Sep 2020 04:15:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600168545; cv=none; d=google.com; s=arc-20160816; b=UXN1SZbQBeHhWQGlIR9Lqgu3bxLjra/bPuC5f1RyCFyu6ovFu+/W8x3grU5YrpfSA8 kh59+Uik17FmmqJt7zryu3qLLXRiIiisKpqWjzV+8GcuF27xvRV/cMaTF9Bn4s1LbdVK VBFwrQNeGuvjw4UKyQNLP2rpX8tus6toBed+C62kWbJ4+f7de9HG722MEpkM+U07OG8o Ot532D5yxbJALFTiwfC1TU0MgCAxyIOx4H600tfzYAer4JhWsAAALl4Q8fDE1zjdC6gk SiaWMUvGv3r8a3wktqELaURXfLRw/hmibq0hu1CgfRP4yR7ytreVQAssL6aUjvcFNu91 d3SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=mc2gdazpP2I7bg6WRsLz8UwRyinpHdK0stSWn7q23gw=; b=IY4uxP39My+AcEV+4VgMQBMuBmproGYeCQVICtcH9gi/00m1fL9OafzMt9S/NzEwMi 0iFiYmVFJcEj112lHU4INpP37h4rCM918oDmdCb/Ej+dpxPF224gmKXdpc2bpwtd2yG2 nGOVj+USZw1s2Tu/iSXxLLr6XLx+XwPW/KNcSYSgAWDMntVGB8koQrCsonoAYQ67lROs 1ZvCj/WL00ZDekiZJm9iqryZKJfMg2RVSIqNlv2BSnArOsZJJfB6HEXS+h+IY/ReVEDI fFugZTNaCu10xdhTSVUtbNCXhXb6jVayI+HrvX+p3nbXEUakDLZupdo00Oyg5uz+4FXk tCzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WjZlN/Kd"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id n3sm4588916ljj.59.2020.09.15.04.01.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Sep 2020 04:01:25 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com Subject: [PATCH v6 5/5] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs Date: Tue, 15 Sep 2020 13:00:51 +0200 Message-Id: <1600167651-20851-6-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1600167651-20851-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The PRUSS INTC present within the ICSSG supports more System Events (160 vs 64), more Interrupt Channels and Host Interrupts (20 vs 10) compared to the previous generation PRUSS INTC instances. The first 2 and the last 10 of these host interrupt lines are used by the PRU and other auxiliary cores and sub-modules within the ICSSG, with 8 host interrupts connected to MPU. The host interrupts 5, 6, 7 are also connected to the other ICSSG instances within the SoC and can be partitioned as per system integration through the board dts files. Enhance the PRUSS INTC driver to add support for this ICSSG INTC instance. Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v5->v6: - No change. v4->v5: - Rename: s/num_host_intrs/num_host_events/ regarding to change introduced in patch #2. v3->v4: - Move generic part to "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts" patch and leave only platform related code. v2->v3: - Change patch order: use it directly after "irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops" and before new "irqchip/irq-pruss-intc: Add event mapping support" in order to reduce diff. v1->v2: - https://patchwork.kernel.org/patch/11069773/ --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-pruss-intc.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 733e59f..25c8944 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -495,7 +495,7 @@ config TI_SCI_INTA_IRQCHIP config TI_PRUSS_INTC tristate "TI PRU-ICSS Interrupt Controller" - depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 select IRQ_DOMAIN help This enables support for the PRU-ICSS Local Interrupt Controller diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 41c6271..4be501e 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -628,11 +628,20 @@ static const struct pruss_intc_match_data pruss_intc_data = { .num_host_events = 10, }; +static const struct pruss_intc_match_data icssg_intc_data = { + .num_system_events = 160, + .num_host_events = 20, +}; + static const struct of_device_id pruss_intc_of_match[] = { { .compatible = "ti,pruss-intc", .data = &pruss_intc_data, }, + { + .compatible = "ti,icssg-intc", + .data = &icssg_intc_data, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, pruss_intc_of_match);