From patchwork Thu Oct 29 05:09:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 310749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82F9FC2D0A3 for ; Thu, 29 Oct 2020 11:50:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2265020838 for ; Thu, 29 Oct 2020 11:50:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="lx3QEvJ8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725832AbgJ2LuF (ORCPT ); Thu, 29 Oct 2020 07:50:05 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37356 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725826AbgJ2LuF (ORCPT ); Thu, 29 Oct 2020 07:50:05 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 09T59tvE118625; Thu, 29 Oct 2020 00:09:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1603948195; bh=OsdwdOWV1uhhgsrwppo6HM3IWl59ZGRmOZFrLL6GY38=; h=From:To:CC:Subject:Date; b=lx3QEvJ8Bmw8PdLOf8k6U3Vl6rh/BFiPmJ+K1Y/DswxuyZ2p7a9rJYgkSq+8Q69in ZNVcbJc9KygrXN6AvRh46TRo6SXqTKCkm5FCdAh3iYiALtvL8qTTOkCTfLg4sTpyAw yfD5aXU5NpOSrVZ7jGJ6Axore3HRcbYR9uoa6Cis= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 09T59ttu011465 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 29 Oct 2020 00:09:55 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 29 Oct 2020 00:09:54 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 29 Oct 2020 00:09:54 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 09T59p93011556; Thu, 29 Oct 2020 00:09:52 -0500 From: Vignesh Raghavendra To: Tero Kristo , Nishanth Menon , Rob Herring CC: , , , Vignesh Raghavendra Subject: [RESEND PATCH] arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support Date: Thu, 29 Oct 2020 10:39:50 +0530 Message-ID: <20201029050950.4500-1-vigneshr@ti.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node for the same. Signed-off-by: Vignesh Raghavendra Reviewed-by: Sekhar Nori --- Resending, after rebasing and testing on top of 5.10-rc1. No code change. v1: https://lore.kernel.org/r/20201013081650.26090-1-vigneshr@ti.com .../dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ef03e7636b66..7d2ff1c3b50f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -213,3 +213,9 @@ &usb0 { dr_mode = "otg"; maximum-speed = "high-speed"; }; + +&tscadc0 { + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index eb2a78a53512..bb1fe9c12e44 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -270,4 +270,23 @@ hbmc: hyperbus@47034000 { mux-controls = <&hbmc_mux 0>; }; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 1>; + assigned-clocks = <&k3_clks 0 3>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; };