From patchwork Wed Oct 28 15:16:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 314909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 719E6C56202 for ; Wed, 28 Oct 2020 22:27:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2FECB206F4 for ; Wed, 28 Oct 2020 22:27:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732649AbgJ1WYo (ORCPT ); Wed, 28 Oct 2020 18:24:44 -0400 Received: from leibniz.telenet-ops.be ([195.130.137.77]:41692 "EHLO leibniz.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732582AbgJ1WV4 (ORCPT ); Wed, 28 Oct 2020 18:21:56 -0400 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by leibniz.telenet-ops.be (Postfix) with ESMTPS id 4CLsc85sg3zMv7nV for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by xavier.telenet-ops.be with bizsmtp id lTGf2300h4C55Sk01TGf1z; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBn-000pDZ-Ii; Wed, 28 Oct 2020 16:16:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H8m-67; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/8] pinctrl: renesas: Remove superfluous goto in sh_pfc_gpio_set_direction() Date: Wed, 28 Oct 2020 16:16:30 +0100 Message-Id: <20201028151637.1734130-2-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Commit b13431ed6eab808a ("pinctrl: sh-pfc: Remove incomplete flag "cfg->type"") removed the last statement in between the goto and the label. Hence remove both. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 212a4a9c3a8fc1c7..f8d5fae66e862fd6 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -460,12 +460,7 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, } spin_lock_irqsave(&pfc->lock, flags); - ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); - if (ret < 0) - goto done; - -done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; } From patchwork Wed Oct 28 15:16:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 310896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 498C2C55179 for ; Thu, 29 Oct 2020 00:33:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03312207DE for ; Thu, 29 Oct 2020 00:33:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731905AbgJ1WXO (ORCPT ); Wed, 28 Oct 2020 18:23:14 -0400 Received: from leibniz.telenet-ops.be ([195.130.137.77]:41686 "EHLO leibniz.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732581AbgJ1WV5 (ORCPT ); Wed, 28 Oct 2020 18:21:57 -0400 X-Greylist: delayed 1499 seconds by postgrey-1.27 at vger.kernel.org; Wed, 28 Oct 2020 18:21:55 EDT Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by leibniz.telenet-ops.be (Postfix) with ESMTPS id 4CLsc85q05zMv7nN for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by baptiste.telenet-ops.be with bizsmtp id lTGf2300f4C55Sk01TGfGz; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBn-000pDa-IS; Wed, 28 Oct 2020 16:16:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H8r-7B; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 2/8] pinctrl: renesas: Singular/plural grammar fixes Date: Wed, 28 Oct 2020 16:16:31 +0100 Message-Id: <20201028151637.1734130-3-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix a few singular vs. plural grammar issues in comments. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/gpio.c | 2 +- drivers/pinctrl/renesas/pinctrl.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index 9c6e931ae766edf7..ad06f5355d1ed1c5 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -328,7 +328,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) if (pfc->info->data_regs == NULL) return 0; - /* Find the memory window that contain the GPIO registers. Boards that + /* Find the memory window that contains the GPIO registers. Boards that * register a separate GPIO device will not supply a memory resource * that covers the data registers. In that case don't try to handle * GPIOs. diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index f8d5fae66e862fd6..8e54f9b662f37f37 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -399,7 +399,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); if (!pfc->gpio) { - /* If GPIOs are handled externally the pin mux type need to be + /* If GPIOs are handled externally the pin mux type needs to be * set to GPIO here. */ const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; @@ -450,8 +450,8 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, unsigned int dir; int ret; - /* Check if the requested direction is supported by the pin. Not all SoC - * provide pin config data, so perform the check conditionally. + /* Check if the requested direction is supported by the pin. Not all + * SoCs provide pin config data, so perform the check conditionally. */ if (pin->configs) { dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; From patchwork Wed Oct 28 15:16:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 310897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 976D7C55179 for ; Wed, 28 Oct 2020 23:36:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 496CD207E8 for ; Wed, 28 Oct 2020 23:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390549AbgJ1Xgx (ORCPT ); Wed, 28 Oct 2020 19:36:53 -0400 Received: from newton.telenet-ops.be ([195.130.132.45]:54828 "EHLO newton.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390546AbgJ1XfT (ORCPT ); Wed, 28 Oct 2020 19:35:19 -0400 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by newton.telenet-ops.be (Postfix) with ESMTPS id 4CLsc85qxMzMwXV4 for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by baptiste.telenet-ops.be with bizsmtp id lTGg2300A4C55Sk01TGgH4; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBn-000pDb-T3; Wed, 28 Oct 2020 16:16:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H8w-7w; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 3/8] pinctrl: renesas: Reorder struct sh_pfc_pin to remove hole Date: Wed, 28 Oct 2020 16:16:32 +0100 Message-Id: <20201028151637.1734130-4-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is present in between the enum_id and name members of the sh_pfc_pin structure. Get rid of this hole by sorting the structure's members by decreasing size. This saves up to 1.5 KiB per enabled SoC, and reduces the size of a kernel including support for all R-Car Gen3 SoCs by more than 10 KiB. This has no size impact on SH and arm32. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/sh_pfc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index eff1bb872325ef3a..3b390dffacb4910d 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -34,10 +34,10 @@ enum { #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) struct sh_pfc_pin { - u16 pin; - u16 enum_id; const char *name; unsigned int configs; + u16 pin; + u16 enum_id; }; #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ From patchwork Wed Oct 28 15:16:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 310904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AABE3C388F7 for ; Wed, 28 Oct 2020 22:24:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66FCF20709 for ; Wed, 28 Oct 2020 22:24:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732637AbgJ1WWU (ORCPT ); Wed, 28 Oct 2020 18:22:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732596AbgJ1WV6 (ORCPT ); Wed, 28 Oct 2020 18:21:58 -0400 Received: from leibniz.telenet-ops.be (leibniz.telenet-ops.be [IPv6:2a02:1800:110:4::f00:d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2E7EC0613CF for ; Wed, 28 Oct 2020 15:21:57 -0700 (PDT) Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by leibniz.telenet-ops.be (Postfix) with ESMTPS id 4CLsc868dVzMv7nb for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by xavier.telenet-ops.be with bizsmtp id lTGg230064C55Sk01TGg24; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBn-000pDc-Ru; Wed, 28 Oct 2020 16:16:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H91-8i; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 4/8] pinctrl: renesas: Optimize sh_pfc_pin_config Date: Wed, 28 Oct 2020 16:16:33 +0100 Message-Id: <20201028151637.1734130-5-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Shrink sh_pfc_pin_config from 8 to 2 bytes: - The mux_set flag can be removed, as a non-zero mark value means the same (zero = PINMUX_RESERVED is an invalid mark value), - The gpio_enabled flag needs only a single bit, - Mark values are small integers, and can easily fit in a 15-bit bitfield. This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 8e54f9b662f37f37..d34079726039c39d 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -26,9 +26,8 @@ #include "../pinconf.h" struct sh_pfc_pin_config { - unsigned int mux_mark; - bool mux_set; - bool gpio_enabled; + u16 gpio_enabled:1; + u16 mux_mark:15; }; struct sh_pfc_pinctrl { @@ -371,12 +370,11 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, goto done; } - /* All group pins are configured, mark the pins as mux_set */ + /* All group pins are configured, mark the pins as muxed */ for (i = 0; i < grp->nr_pins; ++i) { int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - cfg->mux_set = true; cfg->mux_mark = grp->mux[i]; } @@ -432,7 +430,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); cfg->gpio_enabled = false; /* If mux is already set, this configures it here */ - if (cfg->mux_set) + if (cfg->mux_mark) sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); spin_unlock_irqrestore(&pfc->lock, flags); } From patchwork Wed Oct 28 15:16:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 310905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53F99C55179 for ; Wed, 28 Oct 2020 22:21:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7B49206D9 for ; Wed, 28 Oct 2020 22:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732595AbgJ1WV5 (ORCPT ); Wed, 28 Oct 2020 18:21:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732588AbgJ1WV4 (ORCPT ); Wed, 28 Oct 2020 18:21:56 -0400 X-Greylist: delayed 1497 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Wed, 28 Oct 2020 15:21:55 PDT Received: from leibniz.telenet-ops.be (leibniz.telenet-ops.be [IPv6:2a02:1800:110:4::f00:d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0073AC0613CF for ; Wed, 28 Oct 2020 15:21:55 -0700 (PDT) Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by leibniz.telenet-ops.be (Postfix) with ESMTPS id 4CLsc85xmxzMv7nZ for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by baptiste.telenet-ops.be with bizsmtp id lTGg230054C55Sk01TGgH2; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBn-000pDd-PD; Wed, 28 Oct 2020 16:16:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H97-9X; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 5/8] pinctrl: renesas: Factor out common R-Car Gen3 bias handling Date: Wed, 28 Oct 2020 16:16:34 +0100 Message-Id: <20201028151637.1734130-6-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org All pin control drivers for R-Car Gen3 SoCs contain identical bias handling. Reduce code duplication by moving it to the common pinctrl.c code. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/core.h | 4 +++ drivers/pinctrl/renesas/pfc-r8a77950.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a77951.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a7796.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a77965.c | 45 ++------------------------ drivers/pinctrl/renesas/pfc-r8a77990.c | 45 ++------------------------ drivers/pinctrl/renesas/pinctrl.c | 40 +++++++++++++++++++++++ 7 files changed, 54 insertions(+), 215 deletions(-) diff --git a/drivers/pinctrl/renesas/core.h b/drivers/pinctrl/renesas/core.h index b5b1d163e98ab8d4..5ca7e0830ae9de38 100644 --- a/drivers/pinctrl/renesas/core.h +++ b/drivers/pinctrl/renesas/core.h @@ -33,4 +33,8 @@ const struct pinmux_bias_reg * sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, unsigned int *bit); +unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); +void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); + #endif /* __SH_PFC_CORE_H__ */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c index 04812e62f3a476a8..32b66b9999b871eb 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ b/drivers/pinctrl/renesas/pfc-r8a77950.c @@ -5820,51 +5820,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { .pin_to_pocctrl = r8a77950_pin_to_pocctrl, - .get_bias = r8a77950_pinmux_get_bias, - .set_bias = r8a77950_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77950_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 8d1262c170af0085..72252fdcbc21b821 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -6201,51 +6201,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { .pin_to_pocctrl = r8a77951_pin_to_pocctrl, - .get_bias = r8a77951_pinmux_get_bias, - .set_bias = r8a77951_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774E1 diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 88e9c46003d93327..6e8e023410c4c298 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -6150,51 +6150,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { .pin_to_pocctrl = r8a7796_pin_to_pocctrl, - .get_bias = r8a7796_pinmux_get_bias, - .set_bias = r8a7796_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774A1 diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 38b7b844abe9cc4a..590e5f8006d4c035 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -6404,51 +6404,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { .pin_to_pocctrl = r8a77965_pin_to_pocctrl, - .get_bias = r8a77965_pinmux_get_bias, - .set_bias = r8a77965_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774B1 diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 6f9f7638703dbf60..a51c1e684439106a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -5237,51 +5237,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { .pin_to_pocctrl = r8a77990_pin_to_pocctrl, - .get_bias = r8a77990_pinmux_get_bias, - .set_bias = r8a77990_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774C0 diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index d34079726039c39d..4a030600f4fd0dd0 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -823,3 +823,43 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) return pinctrl_enable(pmx->pctl); } + +unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + u32 enable, updown; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return; + + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= BIT(bit); + + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); +} From patchwork Wed Oct 28 15:16:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 314903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27870C4363A for ; Wed, 28 Oct 2020 23:36:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE67F207E8 for ; Wed, 28 Oct 2020 23:36:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390425AbgJ1Xgx (ORCPT ); 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Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 6/8] pinctrl: renesas: r8a7778: Use physical addresses for PUPR regs Date: Wed, 28 Oct 2020 16:16:35 +0100 Message-Id: <20201028151637.1734130-7-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car M1A uses register offsets instead of register physical addresses. This is different from the handling on other R-Car parts. Convert the bias handling from register offsets to physical addresses. This increases uniformity, and prepares for consolidation of the bias handling. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a7778.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index a9875038ed9b664e..debf0c9a281cee31 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -2909,7 +2909,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }; static const struct pinmux_bias_reg pinmux_bias_regs[] = { - { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 6), /* A0 */ [ 1] = RCAR_GP_PIN(0, 7), /* A1 */ [ 2] = RCAR_GP_PIN(0, 8), /* A2 */ @@ -2943,7 +2943,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */ [31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */ } }, - { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */ [ 1] = RCAR_GP_PIN(0, 5), /* /BS */ [ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */ @@ -2977,7 +2977,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) { [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */ [ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */ [ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */ @@ -3011,7 +3011,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */ [31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */ } }, - { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) { [ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */ [ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */ [ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */ @@ -3045,7 +3045,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */ [31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */ } }, - { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) { [ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */ [ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */ [ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */ @@ -3079,7 +3079,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(1, 14), /* IRQ2 */ [31] = RCAR_GP_PIN(1, 15), /* IRQ3 */ } }, - { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) { + { PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */ [ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */ [ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */ @@ -3120,16 +3120,13 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { const struct pinmux_bias_reg *reg; - void __iomem *addr; unsigned int bit; reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); if (!reg) return PIN_CONFIG_BIAS_DISABLE; - addr = pfc->windows->virt + reg->puen; - - if (ioread32(addr) & BIT(bit)) + if (sh_pfc_read(pfc, reg->puen) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_DISABLE; @@ -3139,7 +3136,6 @@ static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { const struct pinmux_bias_reg *reg; - void __iomem *addr; unsigned int bit; u32 value; @@ -3147,12 +3143,10 @@ static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, if (!reg) return; - addr = pfc->windows->virt + reg->puen; - - value = ioread32(addr) & ~BIT(bit); + value = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) value |= BIT(bit); - iowrite32(value, addr); + sh_pfc_write(pfc, reg->puen, value); } static const struct sh_pfc_soc_operations r8a7778_pfc_ops = { From patchwork Wed Oct 28 15:16:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 314904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEFCDC388F7 for ; Wed, 28 Oct 2020 23:36:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D20E207E8 for ; Wed, 28 Oct 2020 23:36:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390555AbgJ1Xgm (ORCPT ); Wed, 28 Oct 2020 19:36:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390550AbgJ1XfT (ORCPT ); Wed, 28 Oct 2020 19:35:19 -0400 Received: from newton.telenet-ops.be (newton.telenet-ops.be [IPv6:2a02:1800:120:4::f00:d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71B83C0613D2 for ; Wed, 28 Oct 2020 16:35:19 -0700 (PDT) Received: from andre.telenet-ops.be (andre.telenet-ops.be [IPv6:2a02:1800:120:4::f00:15]) by newton.telenet-ops.be (Postfix) with ESMTPS id 4CLsc8695GzMwkhT for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by andre.telenet-ops.be with bizsmtp id lTGg230074C55Sk01TGglK; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBn-000pDh-Si; Wed, 28 Oct 2020 16:16:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H9H-CG; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 7/8] pinctrl: renesas: r8a7778: Use common R-Car bias handling Date: Wed, 28 Oct 2020 16:16:36 +0100 Message-Id: <20201028151637.1734130-8-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD) registers, like R-Car Gen3 and RZ/G2. Update the function to handle SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car Gen1/Gen2 and RZ/G1. Reduce code duplication by converting the R-Car M1A pin control driver to use the common handler. Note that this changes behavior in case the (invalid!) option "bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored silently; after this change, it is considered the same as "bias-pull-up". Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a7778.c | 37 ++------------------------- drivers/pinctrl/renesas/pinctrl.c | 13 ++++++---- 2 files changed, 10 insertions(+), 40 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index debf0c9a281cee31..75f52b1798c3c5c9 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -3116,42 +3116,9 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (sh_pfc_read(pfc, reg->puen) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_DISABLE; -} - -static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - u32 value; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - value = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - value |= BIT(bit); - sh_pfc_write(pfc, reg->puen, value); -} - static const struct sh_pfc_soc_operations r8a7778_pfc_ops = { - .get_bias = r8a7778_pinmux_get_bias, - .set_bias = r8a7778_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7778_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 4a030600f4fd0dd0..d5c798e98c18abee 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -835,7 +835,7 @@ unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -856,10 +856,13 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, if (bias != PIN_CONFIG_BIAS_DISABLE) enable |= BIT(bit); - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); + if (reg->pud) { + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + } - sh_pfc_write(pfc, reg->pud, updown); sh_pfc_write(pfc, reg->puen, enable); } From patchwork Wed Oct 28 15:16:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 310898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B36CC388F7 for ; Wed, 28 Oct 2020 23:36:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E0482080D for ; Wed, 28 Oct 2020 23:36:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390288AbgJ1Xgx (ORCPT ); Wed, 28 Oct 2020 19:36:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390549AbgJ1XfT (ORCPT ); Wed, 28 Oct 2020 19:35:19 -0400 X-Greylist: delayed 4199 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Wed, 28 Oct 2020 16:35:19 PDT Received: from newton.telenet-ops.be (newton.telenet-ops.be [IPv6:2a02:1800:120:4::f00:d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68445C0613CF for ; Wed, 28 Oct 2020 16:35:19 -0700 (PDT) Received: from andre.telenet-ops.be (andre.telenet-ops.be [IPv6:2a02:1800:120:4::f00:15]) by newton.telenet-ops.be (Postfix) with ESMTPS id 4CLsc86DLHzMwkhW for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by andre.telenet-ops.be with bizsmtp id lTGg2300T4C55Sk01TGglM; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBo-000pDo-8T; Wed, 28 Oct 2020 16:16:40 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H9M-DG; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 8/8] pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIO Date: Wed, 28 Oct 2020 16:16:37 +0100 Message-Id: <20201028151637.1734130-9-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles GPIOs, too. To reduce code size when compiling a kernel supporting only modern SoCs, most, but not all, of the GPIO functionality is protected by checks for CONFIG_PINCTRL_SH_FUNC_GPIO. Factor out the remaining parts when not needed: 1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input resp. output capabilities (SuperH and SH/R-Mobile). 2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO pins to interrupt numbers (SH/R-Mobile). 3. sh_pfc_gpio_set_direction() configures GPIO direction, called from the GPIO driver through pinctrl_gpio_direction_{in,out}put() (SH/R-Mobile). Unfortunately this function cannot just be moved to drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of sh_pfc_pinctrl, which is internal to drivers/pinctrl/renesas/pinctrl.c. While code size reduction is minimal, this does help in documenting depencies. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/core.c | 2 ++ drivers/pinctrl/renesas/pinctrl.c | 4 ++++ drivers/pinctrl/renesas/sh_pfc.h | 8 +++++--- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index c528c124fb0e9259..2cc457279345b95d 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -315,6 +315,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) range = NULL; break; +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO case PINMUX_TYPE_OUTPUT: range = &pfc->info->output; break; @@ -322,6 +323,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) case PINMUX_TYPE_INPUT: range = &pfc->info->input; break; +#endif /* CONFIG_PINCTRL_SH_PFC_GPIO */ default: return -EINVAL; diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index d5c798e98c18abee..ac542d278a387de1 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -435,6 +435,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_unlock_irqrestore(&pfc->lock, flags); } +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool input) @@ -462,6 +463,9 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, spin_unlock_irqrestore(&pfc->lock, flags); return ret; } +#else +#define sh_pfc_gpio_set_direction NULL +#endif static const struct pinmux_ops sh_pfc_pinmux_ops = { .get_functions_count = sh_pfc_get_functions_count, diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 3b390dffacb4910d..dc484c13f59c74e5 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -270,8 +270,13 @@ struct sh_pfc_soc_info { const char *name; const struct sh_pfc_soc_operations *ops; +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO struct pinmux_range input; struct pinmux_range output; + const struct pinmux_irq *gpio_irq; + unsigned int gpio_irq_size; +#endif + struct pinmux_range function; const struct sh_pfc_pin *pins; @@ -295,9 +300,6 @@ struct sh_pfc_soc_info { const u16 *pinmux_data; unsigned int pinmux_data_size; - const struct pinmux_irq *gpio_irq; - unsigned int gpio_irq_size; - u32 unlock_reg; };