From patchwork Mon Sep 28 01:05:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313605 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2908873ilg; Sun, 27 Sep 2020 18:05:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJysqX3P77mIIFoC/gsCBqvtR2OB0qwuGpPVmwugq5w6i0mBQ+FbIMGIHSASrH9zD0AbHHQc X-Received: by 2002:a50:99d6:: with SMTP id n22mr13370126edb.265.1601255147306; Sun, 27 Sep 2020 18:05:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601255147; cv=none; d=google.com; s=arc-20160816; b=lSvDi4J17Yr5o90dBQEiUaseDocCqr93Q2kqGEm2JrcwmI894DGT8/YkHsU06dt6wQ TMsKY2FgS9Tqgns23NMeP1fvgp4rIWEoFxrtenZlvEMaJR7cRjeHb7t5Dr1ekVGxFJLu Usk5zqHxhk42ljoSCZtjBWCkk5z6N9MV9nTWqKLBYdO+TUNm+GAGFhezaTrglxrTKEF6 IvlvRYLhNPFI2dV3oWq6sJqXp4CAOHpRMaB42iIV70YevbU8hY8AUfwO4ACB7y/1ejYG bTsVkgmNwztQcE8jnVcmq+diFtj8ULd0PZENtS48l5/c+KGjhz79DA7G3ePljsZMrWUo syNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=NES0+Yk8OnWgH95/pv+pL4gMwYf8bdYustHRFZhhU/U=; b=lO+Mcn3LZvYyQ4zC6hYStf6WinggPwENi+dNVuaEu2k8KSTe6ihTt4E7JM4P7emQpY XVWa65SOrmzWE70r4oVPp1A9Xt94OfdUdloZSU0JO3sEUtHj1nBuULjxwZfN6OkwVlBg 35vDeIaFJmoduif0O0l1ePzRcNfZWGXjW7T2N7MYQD3Owf4LlUM/aISpaAiTsX17dAi6 5y/ZNb8DttdGPCmjoV8t1hxg9L5cGtNhqFRVvrlo/FwzSYVreGbpdZhU19ZZ0UJrhgvd d7sNjnXluqTiXx8OLiS7uDCY96LnuJk0FTfqCIm9iS8T7zEU/FV+Prtsi0J/0vNJTv8k yctw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id md14si6221418ejb.548.2020.09.27.18.05.47; Sun, 27 Sep 2020 18:05:47 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726485AbgI1BFo (ORCPT + 6 others); Sun, 27 Sep 2020 21:05:44 -0400 Received: from mx.socionext.com ([202.248.49.38]:27511 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726421AbgI1BFo (ORCPT ); Sun, 27 Sep 2020 21:05:44 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 28 Sep 2020 10:05:43 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 109ED60060; Mon, 28 Sep 2020 10:05:43 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 28 Sep 2020 10:05:43 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 7C9631A0507; Mon, 28 Sep 2020 10:05:42 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 1/4] dt-bindings: PCI: uniphier: Add iATU register description Date: Mon, 28 Sep 2020 10:05:30 +0900 Message-Id: <1601255133-17715-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index 1fa2c59..c4b7381 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -16,6 +16,7 @@ Required properties: "dbi" - controller configuration registers "link" - SoC-specific glue layer registers "config" - PCIe configuration space + "atu" - iATU registers for DWC version 4.80 or later - clocks: A phandle to the clock gate for PCIe glue layer including the host controller. - resets: A phandle to the reset line for PCIe glue layer including From patchwork Mon Sep 28 01:05:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313607 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2908946ilg; Sun, 27 Sep 2020 18:05:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHtGMwbheY8/5FLZqk5JPnhaNDBXv2V2CgEXA0UWgJctaudVQvCQpTFxFLdsNXtPrBqhov X-Received: by 2002:a17:906:f6c9:: with SMTP id jo9mr13145754ejb.233.1601255156448; Sun, 27 Sep 2020 18:05:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601255156; cv=none; d=google.com; s=arc-20160816; b=lY3TG/87zLm7QnPQEeTCNd62BomNHstb3W3W1PlE1xvWebXiEMN2vWxa2PrQLKiJ/j HShRnozItbkJCUFMqHIR+xnzn2rCYpdA2i09EUDwHdj4JZaXNyaL1H3tqwzInXeXS4X2 oknrzFYMmqPelF15VrUOmln48lRDRAJq/KOzmEVFpBg3eZDwIBddyKK6VAzB78FikmaN n5oxVDxuFcnjS02AAhb8T5OlYkTriBt/DkEgnaQVAIGFw3Jnvdg+wxuhw0UWz7Can2TQ qZc+FzqBIGXjn3eX1t12zkha5JZHTNK/6MaoDcEUUgVEnYP0h9/RY/sSq88+MILHRxdc hsWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=JW+unfxP2dEhxOZERDQ9scjgfZAcxugzJtnyOJ6tsjw=; b=wspyk7IskL9z5q+HocxCSwxSLiA4PYcDKWHKaeUl6GOZuljdLXUYds6uxPhNnOj3Hg YA4ACUmmv5olGC8tp6bq0cW/zh7BR2tzKPiweu052g5p3Usn289Mn3Ad97jTKj6DYmFs XaJ/ItxkWPNG6N4TDxTPTCdis85X/UpZehV9gWo/W1Kwr6xccJZjWzdzBE92Dgqq2Zeh 6rkWAuhQN/kb+UE8MFRAyjmaM+M60SIGPkMuRdTwg2l381nEHvfSjxL2pK6NFXhWWS6A wuCKOym9YRUiOyC/go91gpfSGj/BnSHXM/sBr2J05usbbKpBIqNUmObu/Rsy3RZbMIRH qFyA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u15si7301922edo.55.2020.09.27.18.05.56; Sun, 27 Sep 2020 18:05:56 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726565AbgI1BFr (ORCPT + 6 others); Sun, 27 Sep 2020 21:05:47 -0400 Received: from mx.socionext.com ([202.248.49.38]:27527 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbgI1BFp (ORCPT ); Sun, 27 Sep 2020 21:05:45 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 28 Sep 2020 10:05:44 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 29B39600A0; Mon, 28 Sep 2020 10:05:44 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 28 Sep 2020 10:05:44 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 831981A050F; Mon, 28 Sep 2020 10:05:43 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 2/4] dt-bindings: PCI: uniphier-ep: Add iATU register description Date: Mon, 28 Sep 2020 10:05:31 +0900 Message-Id: <1601255133-17715-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsis DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi --- Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml index f0558b9..98d7d3b 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -23,7 +23,7 @@ properties: const: socionext,uniphier-pro5-pcie-ep reg: - maxItems: 4 + maxItems: 5 reg-names: items: @@ -31,6 +31,7 @@ properties: - const: dbi2 - const: link - const: addr_space + - const: atu clocks: maxItems: 2 From patchwork Mon Sep 28 01:05:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313606 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2908938ilg; Sun, 27 Sep 2020 18:05:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwwGkqamHruweHGdqceQ6JO19thcaNW9BIaK8hfilHhCx/U0rwl8OSxUnKV+vX/RcyPrJyK X-Received: by 2002:a50:fd83:: with SMTP id o3mr12981802edt.176.1601255155473; Sun, 27 Sep 2020 18:05:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601255155; cv=none; d=google.com; s=arc-20160816; b=xriMsXpZ2bP+iYckG3Odv2j3WuShHCOiy2JGx7ppR1d8u9MsbsZZutsvOEVPP8+F8H PF45inmeV6epko5n9rp9qbJ2NX6VKHIXQws1k4j7ZGZG5KnLbnf8VT6ZMUCPyDY6uTPn dhlABCDnYzJZdnGGC7CYm/EYQSI5Fr81Es1NCY73OEA1oQ0OP4QDWcWVYn28JXzcTsho 85ud+OzPhT7VIk0i845ES+AOjewiyFcI5rXF6TnYPwigHqAo6lyDIUAcgbZ9ZGpCYiOl d3pytdv58mEtZFlmomhOdipqWjbWT6il9EzXWPx637qx5jzEkohXqc/EbpsSYlyj+mL0 Ez0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=9sTO2+6sshoR05fbn/I8S0NStuSfvzcogMkhhjaoGUk=; b=Aw2ywoQpQKrgUZ9zfU6knaIBVXJ0AC3s6SJ9Jtg3sM5RyXnJmVuE5emf6rG+fqN1b9 y/dodcCstm+qvPmcY2id2ijHL4vS300KF0q16emBp5D9x0kDcK0NAvIHM9gsebBY+WEf vbaOLE6kRCpdLFqX8EqpvIH0HDAoEVMeXr11Fh8Ul9M78kT8pYXln/W7rVHiI5w2PYuN xX5liIm1TqbW5ZRAUwHkzKS5XgFTHKUuxynWqC30LV5aHOzBjkqoZmIYGsU455oM7CEI 9KnKkUvGE9uR8KOAtqtEme0pKDRj5ChhXWhm6GKeXyxuBMa1gfZiW1CoRkJ42wrFnfYo kLdQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u15si7301922edo.55.2020.09.27.18.05.55; Sun, 27 Sep 2020 18:05:55 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726572AbgI1BFr (ORCPT + 6 others); Sun, 27 Sep 2020 21:05:47 -0400 Received: from mx.socionext.com ([202.248.49.38]:27540 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726547AbgI1BFr (ORCPT ); Sun, 27 Sep 2020 21:05:47 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 28 Sep 2020 10:05:45 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 3542B180BE1; Mon, 28 Sep 2020 10:05:45 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 28 Sep 2020 10:05:45 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 925951A0507; Mon, 28 Sep 2020 10:05:44 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 3/4] PCI: dwc: Add common iATU register support Date: Mon, 28 Sep 2020 10:05:32 +0900 Message-Id: <1601255133-17715-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-designware.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3fe859f..b6b39af 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "../../pci.h" @@ -548,11 +549,15 @@ void dw_pcie_setup(struct dw_pcie *pci) u32 val; struct device *dev = pci->dev; struct device_node *np = dev->of_node; + struct platform_device *pdev = to_platform_device(dev); if (pci->version >= 0x480A || (!pci->version && dw_pcie_iatu_unroll_enabled(pci))) { pci->iatu_unroll_enabled = true; if (!pci->atu_base) + pci->atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(pci->atu_base)) pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; } dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? 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[23.128.96.18]) by mx.google.com with ESMTP id u16si6740492edr.507.2020.09.27.18.06.02; Sun, 27 Sep 2020 18:06:02 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726601AbgI1BF5 (ORCPT + 6 others); Sun, 27 Sep 2020 21:05:57 -0400 Received: from mx.socionext.com ([202.248.49.38]:27549 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726559AbgI1BFt (ORCPT ); Sun, 27 Sep 2020 21:05:49 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 28 Sep 2020 10:05:45 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id B0BED180BE1; Mon, 28 Sep 2020 10:05:45 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 28 Sep 2020 10:05:45 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 6F0251A0507; Mon, 28 Sep 2020 10:05:45 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 4/4] PCI: keystone: Remove iATU register mapping Date: Mon, 28 Sep 2020 10:05:33 +0900 Message-Id: <1601255133-17715-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org After applying "PCI: dwc: Add common iATU register support", there is no need to set own iATU in the Keystone driver itself. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b554812..a222728 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1154,7 +1154,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct keystone_pcie *ks_pcie; struct device_link **link; struct gpio_desc *gpiod; - void __iomem *atu_base; struct resource *res; unsigned int version; void __iomem *base; @@ -1275,23 +1274,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - if (pci->version >= 0x480A) { - atu_base = devm_platform_ioremap_resource_byname(pdev, "atu"); - if (IS_ERR(atu_base)) { - ret = PTR_ERR(atu_base); - goto err_get_sync; - } - - pci->atu_base = atu_base; - + if (pci->version >= 0x480A) ret = ks_pcie_am654_set_mode(dev, mode); - if (ret < 0) - goto err_get_sync; - } else { + else ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; - } + if (ret < 0) + goto err_get_sync; switch (mode) { case DW_PCIE_RC_TYPE: