From patchwork Wed Sep 30 05:36:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313837 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4740207ilg; Tue, 29 Sep 2020 22:36:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIrF58riTfMWWOzgqrehc2wmNDUb4hsl9lsFMIZzXuPHjNoo8rUbt4yTqqGZS7EK6U0cKW X-Received: by 2002:a17:906:370a:: with SMTP id d10mr1154434ejc.393.1601444172869; Tue, 29 Sep 2020 22:36:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601444172; cv=none; d=google.com; s=arc-20160816; b=HOO/z68H0hneKKxZvb78KLC4VPsQe/u/aJvZ6j/9v6JowIoLz+KmzPTlvLJaKiCbph DGbZsFVYik/fPPh2L8oqyey8nucvqxkGf9qHwdfnw5Pm/h2Q3B2WBt5IVMySQDgq1zFY vlfpOnpx30Y2AVx65DLuGg+NnJCqwVH5I7FAzAtRDcIo6VbfLdtCyI5NTp3nxuMaqNmd OM3RcyZ0U+wopqKxpuZx40MLTaXkW6u81fcjifAIDErWV8RZfKl08F9VlIdEcjjMUijH HM/xjdJU8EbAnlEzBOQL4lR8RqKgJk4cEdeZSXy85ETCk2+D3r9lz5hjT+q0IxohGSRa KYpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=NES0+Yk8OnWgH95/pv+pL4gMwYf8bdYustHRFZhhU/U=; b=rnZp66vrOlf/UzDP/ULgaJBp+gYRWUlGNZvytwOSXSAmaOEQQyk9+Zx7uxmSNAERox Roq7eeOy5U+K3khd8x7B9dTfFhW2ku3Pzwo9aoIADjNYFIbr4OnFpo7IhhKi+jRfOxkl jGeE+otaNmfcLKrw5sKu5C/C/qLCIY3osy0hio2fbaYNBa2rwVSSt3sRx4niK1o14q2G xFXptoQDONtw5MelqwgCgSs6HtigmyY0wW3ay4mknIJRLVJn8gd3UWzmNRr9TUf33b7L 2S5wFxX5a24Kzob3uq3IE4dfjOsdaHjsdZdkITLc0q88KIe+pneiNSsWtcJJYZYHAqg0 l33w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k4si333614edq.351.2020.09.29.22.36.12; Tue, 29 Sep 2020 22:36:12 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725779AbgI3FgM (ORCPT + 6 others); Wed, 30 Sep 2020 01:36:12 -0400 Received: from mx.socionext.com ([202.248.49.38]:57175 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725440AbgI3FgL (ORCPT ); Wed, 30 Sep 2020 01:36:11 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 30 Sep 2020 14:36:10 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id C2B9160060; Wed, 30 Sep 2020 14:36:10 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 30 Sep 2020 14:36:10 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 604661A0509; Wed, 30 Sep 2020 14:36:10 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 1/4] dt-bindings: PCI: uniphier: Add iATU register description Date: Wed, 30 Sep 2020 14:36:04 +0900 Message-Id: <1601444167-11316-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index 1fa2c59..c4b7381 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -16,6 +16,7 @@ Required properties: "dbi" - controller configuration registers "link" - SoC-specific glue layer registers "config" - PCIe configuration space + "atu" - iATU registers for DWC version 4.80 or later - clocks: A phandle to the clock gate for PCIe glue layer including the host controller. - resets: A phandle to the reset line for PCIe glue layer including From patchwork Wed Sep 30 05:36:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313840 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4740383ilg; Tue, 29 Sep 2020 22:36:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJznvCEQgbPimazWDXFitYAJyr5zVDFbgy56j5IrBNGdv73P5Ad027wwja3JvgumOdRUWyhc X-Received: by 2002:a05:6402:1d05:: with SMTP id dg5mr900312edb.67.1601444193256; Tue, 29 Sep 2020 22:36:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601444193; cv=none; d=google.com; s=arc-20160816; b=Nn0jpeTymWed8BuEDpSNCbqVNpUn//EwZ8ujFGhLyNzlEu6bH4w7JnUWuyYlVE9J0d 3wyj8bzitIJEB0NRii5zOvbe+xRPkCVy0k9p+zEKSkPdIqmzY+8PAYHRc5iJSI9iJORn OWvJtfvxPl9noQiKiQ9RwebnzYlgXzhXi9hcKiOHHiNkGyc3698EZ1SD/A9ihr0gab/6 +KZQyDIZUrjA7FnPsikDr/NDbEjF0jjCAAcT/oI3sEXdiFkHe9z6Sv2c6hmCRWozO4Bv +iX6HqQZuALQnKWcbZ5huokaASD6H9N2MW4YNBduKdOUPEOQnMFljI/keCw9QRnO791N D3nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=LN5v8NbJGZkySi+dPhk/oUYiuMmEYBotEaiePjViGaY=; b=F7++eUEVwLhwHuiQn1P576hBsOrB8ALE3aKNvcLslflzU8XNkQeBWOueYgRaFO+faE 5yuGrRilkrbGuUbu7wvSsLrt2rEL3d649d5PdnoNG+MuAt3zcnf5n9K77ghg2HPNR9n7 XFwxLAH/po7qhLVRg0fWdW1qpUkFchZ2A3F3bEQVMxPFRjfl1rDgixzZmy6kqn1gL5Pm V9xaa70ttpco67vaMu+no6sl5x+77z3nWr0wbNfQ/Uo8Q2NSP65OGSn3xecah8JIdVrl bG/nlM8XQqIo9F2y7+qy8c8a0cRKPlm3zDfvijl1+WOJ8xCtiC3MxjwaAT7UE0cEYhkL Ri+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dn12si344326ejc.536.2020.09.29.22.36.33; Tue, 29 Sep 2020 22:36:33 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728052AbgI3FgU (ORCPT + 6 others); Wed, 30 Sep 2020 01:36:20 -0400 Received: from mx.socionext.com ([202.248.49.38]:57167 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725306AbgI3FgT (ORCPT ); Wed, 30 Sep 2020 01:36:19 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 30 Sep 2020 14:36:11 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id D11D460060; Wed, 30 Sep 2020 14:36:11 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 30 Sep 2020 14:36:11 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 280871A0509; Wed, 30 Sep 2020 14:36:11 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 2/4] dt-bindings: PCI: uniphier-ep: Add iATU register description Date: Wed, 30 Sep 2020 14:36:05 +0900 Message-Id: <1601444167-11316-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsis DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi --- .../bindings/pci/socionext,uniphier-pcie-ep.yaml | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml index f0558b9..f4292d2 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -23,14 +23,22 @@ properties: const: socionext,uniphier-pro5-pcie-ep reg: - maxItems: 4 + minItems: 4 + maxItems: 5 reg-names: - items: - - const: dbi - - const: dbi2 - - const: link - - const: addr_space + oneOf: + - items: + - const: dbi + - const: dbi2 + - const: link + - const: addr_space + - items: + - const: dbi + - const: dbi2 + - const: link + - const: addr_space + - const: atu clocks: maxItems: 2 From patchwork Wed Sep 30 05:36:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313839 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4740374ilg; Tue, 29 Sep 2020 22:36:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwX8Q/8QKw+UWOy24TOg9oh4S9CxZkDU9irjccmP5znyWxJXJs+XsMTDP0K1NbTIN+jUHV9 X-Received: by 2002:a17:906:7e0e:: with SMTP id e14mr1106103ejr.238.1601444192003; Tue, 29 Sep 2020 22:36:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601444191; cv=none; d=google.com; s=arc-20160816; b=EL6L9jBXlfvdANmnAlA8v0nIep5iSaSYcn/gppYAgInZEBJEWTPDpDoQF01JWFmhUl zPC+Yxos5BDYdSmdesU6wkzx40nsB+ZOtJeLED0XBvsPKp6WNSd8d0za6DD1lxxvmTQG 2nqrpyUI7m7GdS0TA6uvcIG3yKUVTCfjGoejhaJ2H7PT+sLetHNjvN1GRS820+E0Cre9 ei3SecLzodf+w8MB/NYYKQxWBvSaM2i/ElNbZgCUejO2/GP06p4dYo/sInGTC4gz4SKo fXRBEB+DulhVyDBeGNLcd3j4F4B0iP2Vc6MxdnFYQ+yBsSFueWAB0qUUjJNeCRGeS1Qo zVFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=9sTO2+6sshoR05fbn/I8S0NStuSfvzcogMkhhjaoGUk=; b=FV+RhE71go4LNcqbg57J+QFp7eo6EDUDuCsRH/hooRsKXzIGxwOxlaO5SdwbNoOMs/ MnL5nGdautYrCmvG0jsBLfVuzTE1O4Sde51e6e5DHhy/TGKLI6tWl21DzmDtSd82+QmN aAtRFBMyClcTBrZq92+5FS8iv79qz80QU2DetfG48XqS4cEoeREvtDcFt94448hOrqJd 4pd8zv1I3G/86WYWPHXd/1JuDjXsKD6rze6bq6CwplkF9saGjyh1hN2LqZukcHZpFdT0 gG03c4DTJow5QbxSSgRgvHAqgEmVL52Vb/sBXTAtd1Ff/+BHoeNCpgIZnSPgCt4pAjyG Mj6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dn12si344326ejc.536.2020.09.29.22.36.31; Tue, 29 Sep 2020 22:36:31 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728157AbgI3FgY (ORCPT + 6 others); Wed, 30 Sep 2020 01:36:24 -0400 Received: from mx.socionext.com ([202.248.49.38]:57202 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725440AbgI3FgV (ORCPT ); Wed, 30 Sep 2020 01:36:21 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Sep 2020 14:36:12 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 58A90180BE3; Wed, 30 Sep 2020 14:36:12 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 30 Sep 2020 14:36:12 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id DE2F61A0509; Wed, 30 Sep 2020 14:36:11 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 3/4] PCI: dwc: Add common iATU register support Date: Wed, 30 Sep 2020 14:36:06 +0900 Message-Id: <1601444167-11316-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-designware.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3fe859f..b6b39af 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "../../pci.h" @@ -548,11 +549,15 @@ void dw_pcie_setup(struct dw_pcie *pci) u32 val; struct device *dev = pci->dev; struct device_node *np = dev->of_node; + struct platform_device *pdev = to_platform_device(dev); if (pci->version >= 0x480A || (!pci->version && dw_pcie_iatu_unroll_enabled(pci))) { pci->iatu_unroll_enabled = true; if (!pci->atu_base) + pci->atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(pci->atu_base)) pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; } dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? 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[23.128.96.18]) by mx.google.com with ESMTP id dn12si344326ejc.536.2020.09.29.22.36.25; Tue, 29 Sep 2020 22:36:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728126AbgI3FgY (ORCPT + 6 others); Wed, 30 Sep 2020 01:36:24 -0400 Received: from mx.socionext.com ([202.248.49.38]:57167 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727861AbgI3FgW (ORCPT ); Wed, 30 Sep 2020 01:36:22 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Sep 2020 14:36:13 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 681F9180BE3; Wed, 30 Sep 2020 14:36:13 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 30 Sep 2020 14:36:13 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id ED9781A0509; Wed, 30 Sep 2020 14:36:12 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 4/4] PCI: keystone: Remove iATU register mapping Date: Wed, 30 Sep 2020 14:36:07 +0900 Message-Id: <1601444167-11316-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org After applying "PCI: dwc: Add common iATU register support", there is no need to set own iATU in the Keystone driver itself. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b554812..a222728 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1154,7 +1154,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct keystone_pcie *ks_pcie; struct device_link **link; struct gpio_desc *gpiod; - void __iomem *atu_base; struct resource *res; unsigned int version; void __iomem *base; @@ -1275,23 +1274,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - if (pci->version >= 0x480A) { - atu_base = devm_platform_ioremap_resource_byname(pdev, "atu"); - if (IS_ERR(atu_base)) { - ret = PTR_ERR(atu_base); - goto err_get_sync; - } - - pci->atu_base = atu_base; - + if (pci->version >= 0x480A) ret = ks_pcie_am654_set_mode(dev, mode); - if (ret < 0) - goto err_get_sync; - } else { + else ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; - } + if (ret < 0) + goto err_get_sync; switch (mode) { case DW_PCIE_RC_TYPE: