From patchwork Mon Nov 2 12:01:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicola Mazzucato X-Patchwork-Id: 315241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C75DCC388F2 for ; Mon, 2 Nov 2020 12:02:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B9A1223B0 for ; Mon, 2 Nov 2020 12:02:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728632AbgKBMB7 (ORCPT ); Mon, 2 Nov 2020 07:01:59 -0500 Received: from foss.arm.com ([217.140.110.172]:58570 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728623AbgKBMB7 (ORCPT ); Mon, 2 Nov 2020 07:01:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A9CE830E; Mon, 2 Nov 2020 04:01:58 -0800 (PST) Received: from ubuntu.arm.com (unknown [10.57.53.184]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5FF6A3F66E; Mon, 2 Nov 2020 04:01:56 -0800 (PST) From: Nicola Mazzucato To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, sudeep.holla@arm.com, rjw@rjwysocki.net, vireshk@kernel.org, robh+dt@kernel.org, sboyd@kernel.org, nm@ti.com, daniel.lezcano@linaro.org Cc: morten.rasmussen@arm.com, chris.redpath@arm.com, nicola.mazzucato@arm.com Subject: [PATCH v3 1/3] dt-bindings/opp: Update documentation for opp-shared Date: Mon, 2 Nov 2020 12:01:13 +0000 Message-Id: <20201102120115.29993-2-nicola.mazzucato@arm.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201102120115.29993-1-nicola.mazzucato@arm.com> References: <20201102120115.29993-1-nicola.mazzucato@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Currently the optional property opp-shared is used within an opp table to tell that a set of devices share their clock/voltage lines (and the opp points). It is therefore possible to use an empty opp table to convey only that information, useful in situations where the opp points are provided via other means (hardware. firmware, etc). Update the documentation to remark this additional case and provide an example. Signed-off-by: Nicola Mazzucato --- Documentation/devicetree/bindings/opp/opp.txt | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index 9847dfeeffcb..a5f1f993eab9 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -72,6 +72,9 @@ Optional properties: switch their DVFS state together, i.e. they share clock/voltage/current lines. Missing property means devices have independent clock/voltage/current lines, but they share OPP tables. + This optional property can be used without any OPP nodes when its only purpose + is to describe a dependency of clock/voltage/current lines among a set of + devices. - status: Marks the OPP table enabled/disabled. @@ -568,3 +571,53 @@ Example 6: opp-microvolt-, opp-microamp-: }; }; }; + +Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware, +distinct clock controls but two sets of clock/voltage/current lines. + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 0>; + operating-points-v2 = <&cpu_opp0_table>; + }; + cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 1>; + operating-points-v2 = <&cpu_opp0_table>; + }; + cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 2>; + operating-points-v2 = <&cpu_opp1_table>; + }; + cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 3>; + operating-points-v2 = <&cpu_opp1_table>; + }; + + }; + + cpu_opp0_table: opp0_table { + compatible = "operating-points-v2"; + opp-shared; + }; + + cpu_opp1_table: opp1_table { + compatible = "operating-points-v2"; + opp-shared; + }; +};