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[209.132.180.131]) by mx.google.com with ESMTPS id t8si2897313pfh.310.2018.01.04.13.29.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Jan 2018 13:29:09 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-470184-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=H3vaAtyT; spf=pass (google.com: domain of gcc-patches-return-470184-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-470184-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=YEB6LUTMIQCRXE83u/TiFzFIVqMgZzQkAQnW7iD95kwHnP4evF mg3iM5tBCmqK0A5z2aL9psGssg/fOKWl7Bu0WAYjKBNLMlFjc/T5woapgORxI57+ 3kooiYblc53f1axExQJgJRZMpta05VId9ix0XSUJ3aw0a7oJNi+Da0GRU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=EoG2jXb2VBFm1BBibPEl5S0fThU=; b=H3vaAtyT57OgS6ExWCh6 CzK4eSz383VbWmJPFXaZs+rLWeGykBtkHSJRB+15FodR7lrwBtJPM+yVzoHmVgl3 9SJzyaVHI66RXJKKLsOEWTA2L4QHjOMF1VJe4M8OvU7tK0fq/pI7rKTcufgsIMdG Wp/o9K/XKXIXHp4cc0D+82k= Received: (qmail 4998 invoked by alias); 4 Jan 2018 21:28:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4989 invoked by uid 89); 4 Jan 2018 21:28:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Non X-HELO: mail-wm0-f46.google.com Received: from mail-wm0-f46.google.com (HELO mail-wm0-f46.google.com) (74.125.82.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 04 Jan 2018 21:28:56 +0000 Received: by mail-wm0-f46.google.com with SMTP id 9so5859679wme.4 for ; Thu, 04 Jan 2018 13:28:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:cc:subject:date :message-id:user-agent:mime-version; bh=ZAUJ0PgsFy1NSVDk9oQ7Eb6kz8dL9214nqZEJzMHkpo=; b=S84JkXWxusLn/hQuEHQh1hJGSM6UshCxhAA2uvjBEMOTnc9UEtiB1DxGsQBx+w8Pqw TjvBYaH3fkoyUQpLhoK0CpwrBVMUnaoz7y8TPHDuoywMS1symHPOSjEPN3BGfDTSY4O3 6+alC0HU3a2bDVaDbMPnCuzuG6tJzn03EQwCeGbINlDLU5VZoA+S4lf5qkdws2Xv7WsG 4OsPP6VAzTEREnAMA8GPeT7no7ICAr+RJi0xPOnBlv9XYnjFnwvGJ4IBKBmqVfpdhnsv 5Z0aMp7lM1h4Fyj3p6TZQYIZ8d067+SXht5yUk5SaNBD4/ayDf/Qhs/UegygvjVJjuiS OJaA== X-Gm-Message-State: AKGB3mKslUnSFIwg0oQgv7P8ddePaY7HfEr2S34uX5aKkGpZDJeDOx15 itwopM4TraJ1aW7wIpcYpFefkQ== X-Received: by 10.28.52.73 with SMTP id b70mr621910wma.144.1515101334039; Thu, 04 Jan 2018 13:28:54 -0800 (PST) Received: from localhost ([95.144.14.233]) by smtp.gmail.com with ESMTPSA id c2sm7858015wrc.81.2018.01.04.13.28.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Jan 2018 13:28:51 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, vmakarov@redhat.com, richard.sandiford@linaro.org Cc: vmakarov@redhat.com Subject: Tighten LRA cycling check Date: Thu, 04 Jan 2018 21:28:42 +0000 Message-ID: <87wp0x8gad.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 LRA has code to try to prevent cycling, by avoiding reloads that look too similar to the instruction being reloaded. E.g. if we have a R<-C move for some constant C, reloading the source with another R<-C move is unlikely to be a good idea. However, this safeguard unnecessarily triggered in tests like the one in the patch. We started with instructions like: (insn 12 9 13 5 (set (reg:DI 0 x0) (reg/f:DI 459)) "reg-alloc-1.c":18 47 {*movdi_aarch64} (expr_list:REG_EQUAL (symbol_ref:DI ("x00") [flags 0xc0] ) (nil))) where r459 didn't get allocated a register and is equivalent to constant x00. LRA would then handle it like this: Changing pseudo 459 in operand 1 of insn 12 on equiv `x00' 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=609,losers=1,rld_nregs=1 [...] alt=13,overall=9,losers=1,rld_nregs=1 [...] Choosing alt 13 in insn 12: (0) r (1) w {*movdi_aarch64} In other words, to avoid loading the constant x00 into another GPR, LRA decided instead to move it into a floating-point register, then move that floating-point register into x0: Creating newreg=630, assigning class FP_REGS to r630 Set class ALL_REGS for r631 12: x0:DI=r630:DI REG_EQUAL `x00' Inserting insn reload before: 815: r631:DI=high(`x00') 816: r630:DI=r631:DI+low(`x00') REG_EQUAL `x00' That's inefficient and doesn't really help to resolve a cycling problem, since the r630 destination of 816 needs to be reloaded into a GPR anyway. The cycling check already had an exception for source values that are the result of an elimination. This patch extends it to include the result of equivalence substitution. Tested on aarch64-linux-gnu, x86_64-linux-gnu and powerpc64le-linux-gnu. Also tested by comparing the before and after assembly output for at least one target per CPU directory. The targets most affected were: aarch64_be-linux-gn aarch64-linux-gnu powerpc-eabispe riscv32-elf riscv64-elf sparc64-linux-gnu sparc-linux-gnu spu-elf for which it improved code size overall. There were minor register renaming differences on some other targets. x86 and powerpc*-linux-gnu targets were unaffected. OK to install? Richard 2018-01-04 Richard Sandiford gcc/ * lra-constraints.c (process_alt_operands): Test for the equivalence substitutions when detecting a possible reload cycle. gcc/testsuite/ * gcc.target/aarch64/reg-alloc-1.c: New test. Index: gcc/lra-constraints.c =================================================================== --- gcc/lra-constraints.c 2018-01-04 21:28:22.495890864 +0000 +++ gcc/lra-constraints.c 2018-01-04 21:28:22.637885000 +0000 @@ -2866,7 +2866,12 @@ process_alt_operands (int only_alternati /* If it is a result of recent elimination in move insn we can transform it into an add still by using this alternative. */ - && GET_CODE (no_subreg_reg_operand[1]) != PLUS))) + && GET_CODE (no_subreg_reg_operand[1]) != PLUS + /* Likewise if the source has been replaced with an + equivalent value. This only happens once -- the reload + will use the equivalent value instead of the register it + replaces -- so there should be no danger of cycling. */ + && !equiv_substition_p[1]))) { /* We have a move insn and a new reload insn will be similar to the current insn. We should avoid such situation as Index: gcc/testsuite/gcc.target/aarch64/reg-alloc-1.c =================================================================== --- /dev/null 2018-01-04 17:16:45.681472446 +0000 +++ gcc/testsuite/gcc.target/aarch64/reg-alloc-1.c 2018-01-04 21:28:22.637885000 +0000 @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-reload-details" } */ + +#define R1(X, Y) X (Y##0) X (Y##1) X (Y##2) X (Y##3) \ + X (Y##4) X (Y##5) X (Y##6) X (Y##7) +#define R2(X) R1 (X, 0) R1 (X, 1) R1 (X, 2) R1 (X, 3) + +#define DEFINE(N) extern int x##N; +R2 (DEFINE) + +void b1 (int *); + +void +foo (int n) +{ + for (int i = 0; i < n; ++i) + { +#define CALL(N) b1 (&x##N); + R2 (CALL); + R2 (CALL); + } +#define INC(N) x##N += 1; + R2 (INC); +} + +/* { dg-final { scan-rtl-dump-not "DI 32 v0" "reload" } } */