From patchwork Fri Mar 17 15:02:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 95429 Delivered-To: patch@linaro.org Received: by 10.140.89.134 with SMTP id v6csp346768qgd; Fri, 17 Mar 2017 08:05:44 -0700 (PDT) X-Received: by 10.99.2.139 with SMTP id 133mr16734182pgc.168.1489763144864; Fri, 17 Mar 2017 08:05:44 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k5si8869774pgh.227.2017.03.17.08.05.44; Fri, 17 Mar 2017 08:05:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751430AbdCQPF3 (ORCPT + 12 others); Fri, 17 Mar 2017 11:05:29 -0400 Received: from mail-pg0-f50.google.com ([74.125.83.50]:36529 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751087AbdCQPEX (ORCPT ); Fri, 17 Mar 2017 11:04:23 -0400 Received: by mail-pg0-f50.google.com with SMTP id g2so42834491pge.3 for ; Fri, 17 Mar 2017 08:03:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=9X1RacVAzSXKsWvS2e4e2ehj1MFIxr+OfNyxCovT4eo=; b=ZI87j0y81r45CUkRT0svQLr0+bTUPW7LXsfBNDUfVb2nuzNtXX+oBIRwbg7M2IUMpX f4iuajK/XD6nn5n1mo3diB/bBxJNd9nSpA56z32504K7YNZfhrkv770dSWzQUC5Nlow7 rvuJKhnVtufkEQqVWVmGLLCYW16wjcFE1t06Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=9X1RacVAzSXKsWvS2e4e2ehj1MFIxr+OfNyxCovT4eo=; b=NYFveRf8VLLz7tyIvueT6qAEmzuEFcMt8TDUsERuGUnWCVoZFqdvulVT1YvfAS01zW K74UXKiaaQPucxXcykSP/NaO82oAIUm2gaz3fqhaGcShZGCTaM4lHlG9QR0Z93BwlSsF BZljXPCJA2rhnc7A92ZxpTyil9jmG26kH3DY1zavso+rH/bOE8vsOLvXJueqxQ7DCYub fys4ptIQPKmgaE2TYtTZ/X+1RCiNza5ObRq9AyfWL0nnXLUX4jMu+ACZUuf7mEcnvgr+ N6Kh2LpYQN2gFoMVFS6dtY+4KCyz0o93pBcGdkzgZEnV0iJsBQxPDK+/D+7RUcHNG26P D8Ag== X-Gm-Message-State: AFeK/H2DRleC+M/kaLNUOuZFkvoWS5dsr63DFVFaBe5sQgauSAJN/E+jlDTQRztt+NAnEl5G X-Received: by 10.84.231.135 with SMTP id g7mr111621plk.12.1489763030616; Fri, 17 Mar 2017 08:03:50 -0700 (PDT) Received: from localhost.localdomain ([103.230.219.215]) by smtp.gmail.com with ESMTPSA id f125sm17482582pfc.4.2017.03.17.08.03.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Mar 2017 08:03:49 -0700 (PDT) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Michael Turquette , Stephen Boyd , Mathieu Poirier , Leo Yan , Guodong Xu , John Stultz , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, mike.leach@linaro.org, Suzuki.Poulose@arm.com, sudeep.holla@arm.com Subject: [PATCH v4 1/7] coresight: bindings for CPU debug module Date: Fri, 17 Mar 2017 23:02:17 +0800 Message-Id: <1489762943-25849-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> References: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Signed-off-by: Leo Yan --- .../bindings/arm/coresight-cpu-debug.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 0000000..f6855c3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,46 @@ +* CoreSight CPU Debug Component: + +CoreSight cpu debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be + * "arm,coresight-cpu-debug"; supplemented with "arm,primecell" + since this driver is using the AMBA bus interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the cpu phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Optional properties: + +- power-domains: a phandle to power domain node for debug module. We can + use "nohlt" to ensure CPU power domain is enabled. + + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; From patchwork Fri Mar 17 15:02:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 95425 Delivered-To: patch@linaro.org Received: by 10.140.89.134 with SMTP id v6csp346276qgd; Fri, 17 Mar 2017 08:04:45 -0700 (PDT) X-Received: by 10.84.212.8 with SMTP id d8mr20840531pli.152.1489763084997; Fri, 17 Mar 2017 08:04:44 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c194si6340542pfc.14.2017.03.17.08.04.44; Fri, 17 Mar 2017 08:04:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751221AbdCQPE0 (ORCPT + 12 others); Fri, 17 Mar 2017 11:04:26 -0400 Received: from mail-pg0-f47.google.com ([74.125.83.47]:36604 "EHLO mail-pg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751094AbdCQPEX (ORCPT ); Fri, 17 Mar 2017 11:04:23 -0400 Received: by mail-pg0-f47.google.com with SMTP id g2so42838205pge.3 for ; Fri, 17 Mar 2017 08:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L+0TWqNd/lwJxEk+l6nkmFJFJZ+3J5TKXp7w41BiOVg=; b=RTuPa3264K/31JEfYr/aGClXC461MBHAAfdHA+r9EIuLSIfAexjcMxdzAbbD8NxHgC se29GJ4CvkSnu4T6IeWDFLhcazlgIkPiAgLmByHb4lulan5+ISRdQm7lbk6T9syRJaEV 2rTSMyTbcYqW2L9+idWtbwMy01OSzB6wwhn2g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L+0TWqNd/lwJxEk+l6nkmFJFJZ+3J5TKXp7w41BiOVg=; b=UMPNQlPsvWN1oAdAXRZJ/iBZeJqSy9G5wJFK81MANlLBb6ikTicwYjVv87AEjaM8xa 7IH7mh3OfD6H5rmBOWhin5wqRobB8Bh4+rg9gpiCl9j0ZgYSz5wXibJ2AtycyDsNnilh tEILpWc1nQkC99oynRWMqk2nvnEuL45KuS8xK7bOtcH+CIZrbXoAh1hNV9lR3xhdVRW5 7lqFXuJ6rh6mntW2wliaE4vOSOsCArQu42LOmJTK9m8r0kfAnCBRYGs8EKmulNAiswVx Bofl0x3LSfL2W0+pLPYMPqoctsLqk6NcG/gjTUAOCCXYMaYPqjsImdvCpnPypp+DOvc1 vR3Q== X-Gm-Message-State: AFeK/H1nNkIAY/zepAR/b4hbmDequnsSqS2eF6ina7SzLF/JPESSa+doABa0qC9lEPszG9A1 X-Received: by 10.99.98.2 with SMTP id w2mr16381218pgb.103.1489763039421; Fri, 17 Mar 2017 08:03:59 -0700 (PDT) Received: from localhost.localdomain ([103.230.219.215]) by smtp.gmail.com with ESMTPSA id f125sm17482582pfc.4.2017.03.17.08.03.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Mar 2017 08:03:58 -0700 (PDT) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Michael Turquette , Stephen Boyd , Mathieu Poirier , Leo Yan , Guodong Xu , John Stultz , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, mike.leach@linaro.org, Suzuki.Poulose@arm.com, sudeep.holla@arm.com Cc: Suzuki K Poulose Subject: [PATCH v4 2/7] coresight: of_get_coresight_platform_data: Add missing of_node_put Date: Fri, 17 Mar 2017 23:02:18 +0800 Message-Id: <1489762943-25849-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> References: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose The of_get_coresight_platform_data iterates over the possible CPU nodes to find a given cpu phandle. However it does not drop the reference to the node pointer returned by the of_get_coresight_platform_data. [Leo: minor tweaks for of_get_coresight_platform_data] Cc: Leo Yan Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/of_coresight.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index 629e031..917ca39 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -108,7 +108,8 @@ struct coresight_platform_data *of_get_coresight_platform_data( struct coresight_platform_data *pdata; struct of_endpoint endpoint, rendpoint; struct device *rdev; - struct device_node *dn; + bool found; + struct device_node *dn, *np; struct device_node *ep = NULL; struct device_node *rparent = NULL; struct device_node *rport = NULL; @@ -175,17 +176,19 @@ struct coresight_platform_data *of_get_coresight_platform_data( } while (ep); } - /* Affinity defaults to CPU0 */ - pdata->cpu = 0; dn = of_parse_phandle(node, "cpu", 0); - for (cpu = 0; dn && cpu < nr_cpu_ids; cpu++) { - if (dn == of_get_cpu_node(cpu, NULL)) { - pdata->cpu = cpu; + for_each_possible_cpu(cpu) { + np = of_get_cpu_node(cpu, NULL); + found = (dn == np); + of_node_put(np); + if (found) break; - } } of_node_put(dn); + /* Affinity to CPU0 if no cpu nodes are found */ + pdata->cpu = found ? cpu : 0; + return pdata; } EXPORT_SYMBOL_GPL(of_get_coresight_platform_data); From patchwork Fri Mar 17 15:02:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 95427 Delivered-To: patch@linaro.org Received: by 10.140.89.134 with SMTP id v6csp346283qgd; Fri, 17 Mar 2017 08:04:46 -0700 (PDT) X-Received: by 10.98.166.132 with SMTP id r4mr17004407pfl.191.1489763086468; Fri, 17 Mar 2017 08:04:46 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c194si6340542pfc.14.2017.03.17.08.04.46; Fri, 17 Mar 2017 08:04:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751331AbdCQPEf (ORCPT + 12 others); Fri, 17 Mar 2017 11:04:35 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:34927 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751236AbdCQPE2 (ORCPT ); Fri, 17 Mar 2017 11:04:28 -0400 Received: by mail-pg0-f52.google.com with SMTP id b129so42963858pgc.2 for ; Fri, 17 Mar 2017 08:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=tGpr+PvbML3jxbGvgFugJkFg7vK3ni5QFcgUo7RVFxg=; b=I6OK3o/vWnjfqkRE1rmImMJinttLYuwQ0tVIs1FnTTOzIscGaoWoxOWkH8+fu37sTU VLBV/4aN/ulnKowA0BYqc6sc8YF3u7KiZNQHbsozMN5jA6J89zL17LI6Q82JjPSBqLYE HwMmy/jEoJvkbq4mnFaX/kYegA/hxQIqAUbMQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=tGpr+PvbML3jxbGvgFugJkFg7vK3ni5QFcgUo7RVFxg=; b=Of+7oAeydAKqmVwmZq+8+jCP6/UxWdRJlHV+HQlu0Tk3+skm0+eWS33aoob/J9cOAV YqKp6xrDm7ExV6Jv/LluVJPYHX0anMURU9wuQLccvxEzwOmd1QNBESgHVuYpaa0+wD6r //EFoSD3kZXIIi0RTHLLWZCqal0uCPBafgJ48S+IUuxtY4Kekib6AUFAoZL09vxhoaJm TB7C9laxaxcIXYZvF46dcIOPJyKLMrz+5aW80qjuAIyBnLo0qDdLYWgF1y6QodbWQan7 n7T5+soaI/lVo9N/PUBWufbnUi2Uk+/k9QPscJucfH6Can0DWsQOWQ22O3u3is2DSCgI HiuA== X-Gm-Message-State: AFeK/H2PJwpzceLi16R4DVzppga19JqpUBD1z00YzK6J7JzKwOLAzZx/P1PTS9YhhbaitRCH X-Received: by 10.84.169.227 with SMTP id h90mr20475237plb.155.1489763065626; Fri, 17 Mar 2017 08:04:25 -0700 (PDT) Received: from localhost.localdomain ([103.230.219.215]) by smtp.gmail.com with ESMTPSA id f125sm17482582pfc.4.2017.03.17.08.04.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Mar 2017 08:04:24 -0700 (PDT) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Michael Turquette , Stephen Boyd , Mathieu Poirier , Leo Yan , Guodong Xu , John Stultz , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, mike.leach@linaro.org, Suzuki.Poulose@arm.com, sudeep.holla@arm.com Subject: [PATCH v4 4/7] coresight: add support for CPU debug module Date: Fri, 17 Mar 2017 23:02:20 +0800 Message-Id: <1489762943-25849-5-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> References: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Coresight includes debug module and usually the module connects with CPU debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has description for related info in "Part H: External Debug". Chapter H7 "The Sample-based Profiling Extension" introduces several sampling registers, e.g. we can check program counter value with combined CPU exception level, secure state, etc. So this is helpful for analysis CPU lockup scenarios, e.g. if one CPU has run into infinite loop with IRQ disabled. In this case the CPU cannot switch context and handle any interrupt (including IPIs), as the result it cannot handle SMP call for stack dump. This patch is to enable coresight debug module, so firstly this driver is to bind apb clock for debug module and this is to ensure the debug module can be accessed from program or external debugger. And the driver uses sample-based registers for debug purpose, e.g. when system detects the CPU lockup and trigger panic, the driver will dump program counter and combined context registers (EDCIDSR, EDVIDSR); by parsing context registers so can quickly get to know CPU secure state, exception level, etc. Some of the debug module registers are located in CPU power domain, so in the driver it has checked the power state for CPU before accessing registers within CPU power domain. For most safe way to use this driver, it's suggested to disable CPU low power states, this can simply set "nohlt" in kernel command line. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/Kconfig | 10 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 407 ++++++++++++++++++++++ 3 files changed, 418 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c -- 2.7.4 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 130cb21..daf80bc 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -89,4 +89,14 @@ config CORESIGHT_STM logging useful software events or data coming from various entities in the system, possibly running different OSs +config CORESIGHT_CPU_DEBUG + bool "CoreSight CPU Debug driver" + depends on ARM || ARM64 + help + This driver provides support for coresight debugging module. This + is primarily used to dump sample-based profiling registers for + panic. To avoid lockups when accessing debug module registers, + it is safer to disable CPU low power states (like "nohlt" on the + kernel command line) when using this feature. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index af480d9..433d590 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ coresight-etm4x-sysfs.o obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o +obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c new file mode 100644 index 0000000..bb1c5b6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2017 Linaro Limited. All rights reserved. + * + * Author: Leo Yan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" + +#define EDPCSR 0x0A0 +#define EDCIDSR 0x0A4 +#define EDVIDSR 0x0A8 +#define EDPCSR_HI 0x0AC +#define EDOSLAR 0x300 +#define EDPRSR 0x314 +#define EDDEVID1 0xFC4 +#define EDDEVID 0xFC8 + +#define EDPCSR_PROHIBITED 0xFFFFFFFF + +/* bits definition for EDPCSR */ +#ifndef CONFIG_64BIT +#define EDPCSR_THUMB BIT(0) +#define EDPCSR_ARM_INST_MASK GENMASK(31, 2) +#define EDPCSR_THUMB_INST_MASK GENMASK(31, 1) +#endif + +/* bits definition for EDPRSR */ +#define EDPRSR_DLK BIT(6) +#define EDPRSR_PU BIT(0) + +/* bits definition for EDVIDSR */ +#define EDVIDSR_NS BIT(31) +#define EDVIDSR_E2 BIT(30) +#define EDVIDSR_E3 BIT(29) +#define EDVIDSR_HV BIT(28) +#define EDVIDSR_VMID GENMASK(7, 0) + +/* + * bits definition for EDDEVID1 + * + * NOTE: armv8 and armv7 have different definition for the register, + * so consolidate the bits definition as below: + * + * 0b0000 - Sample offset applies based on the instruction state, we + * rely on EDDEVID to check if EDPCSR is implemented or not + * 0b0001 - No offset applies. + * 0b0010 - No offset applies, but do not use in AArch32 mode + * + */ +#define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0) +#define EDDEVID1_PCSR_OFFSET_INS_SET (0x0) +#define EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 (0x2) + +/* bits definition for EDDEVID */ +#define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0) +#define EDDEVID_IMPL_EDPCSR_EDCIDSR (0x2) +#define EDDEVID_IMPL_FULL (0x3) + +struct debug_drvdata { + void __iomem *base; + struct device *dev; + int cpu; + + bool edpcsr_present; + bool edvidsr_present; + bool pc_has_offset; + + u32 eddevid; + u32 eddevid1; + + u32 edpcsr; + u32 edpcsr_hi; + u32 edprsr; + u32 edvidsr; + u32 edcidsr; +}; + +static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata); + +static void debug_os_unlock(struct debug_drvdata *drvdata) +{ + /* Unlocks the debug registers */ + writel_relaxed(0x0, drvdata->base + EDOSLAR); + wmb(); +} + +/* + * According to ARM DDI 0487A.k, before access external debug + * registers should firstly check the access permission; if any + * below condition has been met then cannot access debug + * registers to avoid lockup issue: + * + * - CPU power domain is powered off; + * - The OS Double Lock is locked; + * + * By checking EDPRSR can get to know if meet these conditions. + */ +static bool debug_access_permitted(struct debug_drvdata *drvdata) +{ + /* CPU is powered off */ + if (!(drvdata->edprsr & EDPRSR_PU)) + return false; + + /* The OS Double Lock is locked */ + if (drvdata->edprsr & EDPRSR_DLK) + return false; + + return true; +} + +static void debug_read_regs(struct debug_drvdata *drvdata) +{ + drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR); + + if (!debug_access_permitted(drvdata)) + return; + + if (!drvdata->edpcsr_present) + return; + + CS_UNLOCK(drvdata->base); + + debug_os_unlock(drvdata); + + drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR); + + /* + * As described in ARM DDI 0487A.k, if the processing + * element (PE) is in debug state, or sample-based + * profiling is prohibited, EDPCSR reads as 0xFFFFFFFF; + * EDCIDSR, EDVIDSR and EDPCSR_HI registers also become + * UNKNOWN state. So directly bail out for this case. + */ + if (drvdata->edpcsr == EDPCSR_PROHIBITED) { + CS_LOCK(drvdata->base); + return; + } + + /* + * A read of the EDPCSR normally has the side-effect of + * indirectly writing to EDCIDSR, EDVIDSR and EDPCSR_HI; + * at this point it's safe to read value from them. + */ + drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR); +#ifdef CONFIG_64BIT + drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI); +#endif + + if (drvdata->edvidsr_present) + drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR); + + CS_LOCK(drvdata->base); +} + +#ifndef CONFIG_64BIT +static bool debug_pc_has_offset(struct debug_drvdata *drvdata) +{ + u32 pcsr_offset; + + pcsr_offset = drvdata->eddevid1 & EDDEVID1_PCSR_OFFSET_MASK; + + return (pcsr_offset == EDDEVID1_PCSR_OFFSET_INS_SET); +} + +static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata, + unsigned long pc) +{ + unsigned long arm_inst_offset = 0, thumb_inst_offset = 0; + + if (debug_pc_has_offset(drvdata)) { + arm_inst_offset = 8; + thumb_inst_offset = 4; + } + + /* Handle thumb instruction */ + if (pc & EDPCSR_THUMB) { + pc = (pc & EDPCSR_THUMB_INST_MASK) - thumb_inst_offset; + return pc; + } + + /* + * Handle arm instruction offset, if the arm instruction + * is not 4 byte alignment then it's possible the case + * for implementation defined; keep original value for this + * case and print info for notice. + */ + if (pc & BIT(1)) + pr_emerg("Instruction offset is implementation defined\n"); + else + pc = (pc & EDPCSR_ARM_INST_MASK) - arm_inst_offset; + + return pc; +} +#endif + +static void debug_dump_regs(struct debug_drvdata *drvdata) +{ + unsigned long pc; + + pr_emerg("\tEDPRSR: %08x (Power:%s DLK:%s)\n", drvdata->edprsr, + drvdata->edprsr & EDPRSR_PU ? "On" : "Off", + drvdata->edprsr & EDPRSR_DLK ? "Lock" : "Unlock"); + + if (!debug_access_permitted(drvdata) || !drvdata->edpcsr_present) { + pr_emerg("No permission to access debug registers!\n"); + return; + } + + if (drvdata->edpcsr == EDPCSR_PROHIBITED) { + pr_emerg("CPU is in Debug state or profiling is prohibited!\n"); + return; + } + +#ifdef CONFIG_64BIT + pc = (unsigned long)drvdata->edpcsr_hi << 32 | + (unsigned long)drvdata->edpcsr; +#else + pc = debug_adjust_pc(drvdata, (unsigned long)drvdata->edpcsr); +#endif + + pr_emerg("\tEDPCSR: [<%p>] %pS\n", (void *)pc, (void *)pc); + pr_emerg("\tEDCIDSR: %08x\n", drvdata->edcidsr); + + if (!drvdata->edvidsr_present) + return; + + pr_emerg("\tEDVIDSR: %08x (State:%s Mode:%s Width:%s VMID:%x)\n", + drvdata->edvidsr, + drvdata->edvidsr & EDVIDSR_NS ? "Non-secure" : "Secure", + drvdata->edvidsr & EDVIDSR_E3 ? "EL3" : + (drvdata->edvidsr & EDVIDSR_E2 ? "EL2" : "EL1/0"), + drvdata->edvidsr & EDVIDSR_HV ? "64bits" : "32bits", + drvdata->edvidsr & (u32)EDVIDSR_VMID); +} + +/* + * Dump out information on panic. + */ +static int debug_notifier_call(struct notifier_block *self, + unsigned long v, void *p) +{ + int cpu; + + pr_emerg("ARM external debug module:\n"); + + for_each_possible_cpu(cpu) { + if (!per_cpu(debug_drvdata, cpu)) + continue; + + pr_emerg("CPU[%d]:\n", per_cpu(debug_drvdata, cpu)->cpu); + + debug_read_regs(per_cpu(debug_drvdata, cpu)); + debug_dump_regs(per_cpu(debug_drvdata, cpu)); + } + + return 0; +} + +static struct notifier_block debug_notifier = { + .notifier_call = debug_notifier_call, +}; + +static void debug_init_arch_data(void *info) +{ + struct debug_drvdata *drvdata = info; + u32 mode, pcsr_offset; + + CS_UNLOCK(drvdata->base); + + debug_os_unlock(drvdata); + + /* Read device info */ + drvdata->eddevid = readl_relaxed(drvdata->base + EDDEVID); + drvdata->eddevid1 = readl_relaxed(drvdata->base + EDDEVID1); + + /* Parse implementation feature */ + mode = drvdata->eddevid & EDDEVID_PCSAMPLE_MODE; + if (mode == EDDEVID_IMPL_FULL) { + drvdata->edpcsr_present = true; + drvdata->edvidsr_present = true; + } else if (mode == EDDEVID_IMPL_EDPCSR_EDCIDSR) { + + pcsr_offset = drvdata->eddevid1 & EDDEVID1_PCSR_OFFSET_MASK; + + /* + * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to + * define if has the offset for PC sampling value; if read + * back EDDEVID1.PCSROffset == 0x2, then this means the debug + * module does not sample the instruction set state when + * armv8 CPU in AArch32 state. + */ + if (!IS_ENABLED(CONFIG_64BIT) && + (pcsr_offset == EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32)) + drvdata->edpcsr_present = false; + else + drvdata->edpcsr_present = true; + + drvdata->edvidsr_present = false; + } else { + drvdata->edpcsr_present = false; + drvdata->edvidsr_present = false; + } + + CS_LOCK(drvdata->base); +} + +static int debug_probe(struct amba_device *adev, const struct amba_id *id) +{ + void __iomem *base; + struct device *dev = &adev->dev; + struct debug_drvdata *drvdata; + struct resource *res = &adev->res; + struct device_node *np = adev->dev.of_node; + static int debug_count; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->cpu = np ? of_coresight_get_cpu(np) : 0; + drvdata->dev = &adev->dev; + + dev_set_drvdata(dev, drvdata); + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + + get_online_cpus(); + per_cpu(debug_drvdata, drvdata->cpu) = drvdata; + ret = smp_call_function_single(drvdata->cpu, + debug_init_arch_data, drvdata, 1); + put_online_cpus(); + + if (ret) { + dev_err(dev, "Debug arch init failed\n"); + return ret; + } + + if (!drvdata->edpcsr_present) { + dev_err(dev, "Sample-based profiling is not implemented\n"); + return -ENXIO; + } + + if (!debug_count++) + atomic_notifier_chain_register(&panic_notifier_list, + &debug_notifier); + + dev_info(dev, "Coresight debug-CPU%d initialized\n", drvdata->cpu); + return 0; +} + +static struct amba_id debug_ids[] = { + { /* Debug for Cortex-A53 */ + .id = 0x000bbd03, + .mask = 0x000fffff, + }, + { /* Debug for Cortex-A57 */ + .id = 0x000bbd07, + .mask = 0x000fffff, + }, + { /* Debug for Cortex-A72 */ + .id = 0x000bbd08, + .mask = 0x000fffff, + }, + { 0, 0 }, +}; + +static struct amba_driver debug_driver = { + .drv = { + .name = "coresight-cpu-debug", + .suppress_bind_attrs = true, + }, + .probe = debug_probe, + .id_table = debug_ids, +}; +builtin_amba_driver(debug_driver);