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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d142sm102010iof.43.2020.11.10.13.59.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2020 13:59:27 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/6] net: ipa: define GSI interrupt types with enums Date: Tue, 10 Nov 2020 15:59:17 -0600 Message-Id: <20201110215922.23514-2-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201110215922.23514-1-elder@linaro.org> References: <20201110215922.23514-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Define the GSI global interrupt types with an enumerated type whose values are the bit positions representing the global interrupt types. Similarly, define the GSI general interrupt types with an enumerated type whose values are the bit positions of general interrupt types. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 20 ++++++++++---------- drivers/net/ipa/gsi_reg.h | 25 +++++++++++++++---------- 2 files changed, 25 insertions(+), 20 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 961a11d4fb270..273529b69d39c 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -305,7 +305,7 @@ static void gsi_irq_enable(struct gsi *gsi) /* Global interrupts include hardware error reports. Enable * that so we can at least report the error should it occur. */ - iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); + iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GLOB_EE)); /* General GSI interrupts are reported to all EEs; if they occur @@ -313,9 +313,9 @@ static void gsi_irq_enable(struct gsi *gsi) * also exists, but we don't support that. We want to be notified * of errors so we can report them, even if they can't be handled. */ - val = BUS_ERROR_FMASK; - val |= CMD_FIFO_OVRFLOW_FMASK; - val |= MCS_STACK_OVRFLOW_FMASK; + val = BIT(BUS_ERROR); + val |= BIT(CMD_FIFO_OVRFLOW); + val |= BIT(MCS_STACK_OVRFLOW); iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GENERAL)); } @@ -1145,15 +1145,15 @@ static void gsi_isr_glob_ee(struct gsi *gsi) val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET); - if (val & ERROR_INT_FMASK) + if (val & BIT(ERROR_INT)) gsi_isr_glob_err(gsi); iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET); - val &= ~ERROR_INT_FMASK; + val &= ~BIT(ERROR_INT); - if (val & GP_INT1_FMASK) { - val ^= GP_INT1_FMASK; + if (val & BIT(GP_INT1)) { + val ^= BIT(GP_INT1); gsi_isr_gp_int1(gsi); } @@ -1626,7 +1626,7 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id, * halt a modem channel) and only from this function. So we * enable the GP_INT1 IRQ type here while we're expecting it. */ - val = ERROR_INT_FMASK | GP_INT1_FMASK; + val = BIT(ERROR_INT) | BIT(GP_INT1); iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); /* First zero the result code field */ @@ -1642,7 +1642,7 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id, success = gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val, completion); /* Disable the GP_INT1 IRQ type again */ - iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); + iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); if (success) return 0; diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index c50464984c6e3..e69ebe4aaf884 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -254,6 +254,7 @@ #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) +/* IRQ condition for each type is cleared by writing type-specific register */ #define GSI_CNTXT_TYPE_IRQ_OFFSET \ GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ @@ -330,11 +331,13 @@ enum gsi_irq_type_id { GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ (0x0001f110 + 0x4000 * (ee)) -/* The masks below are used for the general IRQ STTS, EN, and CLR registers */ -#define ERROR_INT_FMASK GENMASK(0, 0) -#define GP_INT1_FMASK GENMASK(1, 1) -#define GP_INT2_FMASK GENMASK(2, 2) -#define GP_INT3_FMASK GENMASK(3, 3) +/* Values here are bit positions in the GLOB_IRQ_* registers */ +enum gsi_global_irq_id { + ERROR_INT = 0x0, + GP_INT1 = 0x1, + GP_INT2 = 0x2, + GP_INT3 = 0x3, +}; #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) @@ -348,11 +351,13 @@ enum gsi_irq_type_id { GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ (0x0001f128 + 0x4000 * (ee)) -/* The masks below are used for the general IRQ STTS, EN, and CLR registers */ -#define BREAK_POINT_FMASK GENMASK(0, 0) -#define BUS_ERROR_FMASK GENMASK(1, 1) -#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) -#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) +/* Values here are bit positions in the (general) GSI_IRQ_* registers */ +enum gsi_general_id { + BREAK_POINT = 0x0, + BUS_ERROR = 0x1, + CMD_FIFO_OVRFLOW = 0x2, + MCS_STACK_OVRFLOW = 0x3, +}; #define GSI_CNTXT_INTSET_OFFSET \ GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) From patchwork Tue Nov 10 21:59:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 322898 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp594743ils; Tue, 10 Nov 2020 13:59:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJxqbNweVITlPCSzaWznKF4xJuR636qbcH0COZkGAuY81es4EXjgxdGJouVlM1Ndm+v3gGC/ X-Received: by 2002:aa7:ca44:: with SMTP id j4mr17028417edt.354.1605045594001; Tue, 10 Nov 2020 13:59:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605045593; cv=none; d=google.com; s=arc-20160816; b=IIvP5KbbDEB/luEAe8v22sSQYcV182ZqEBcA9ScvsJBv0dX3yHcJ/6l53RyVKxhouT gysy+DJ2Xj6qyWOLs+pRammC1MvwmoXbyq2doWUtITDiEE4n/HLCthe9gNVX02Hy12+B ii5oe3hfCaAMCipUuJnJ6EeoObJFBtu/vNyDGSz2Qv7YzwEQPp2iWRagQ24vt4/8c4WB VG4Lzp5fVMLTBp7QItMEYJ7feU08IHfz4yc/fF1pcg2xVCCB0lIrSTDKwd+RssWXj3S8 uB+PFA+PNL4swouQ2MANPM722K4lHtEGMIKGL9XU/4txDh4bRbSnVvb1daXg2zBKL3u+ IWLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f3n+KuGGWOwtr6gyDragDVV6mH7NQ4XmxKx3ZS3TxMI=; b=sSgN/HmO3EnihV8z2DZjD/GWKjkqwuE8HO70wtoceW3XE6QM35GFv8AjYZQomeREXC c7e42HA8dotn7s+VNggal6+ag0xwe+qQeU73fQtwDjAOD4KQ3HyKdPkZeZ7T4QgarB01 gf18w5BdvY9HgmkqKLvTM7wPAybTcnoHmsfbk25r7e2EoFt5dJ6neS/6bG5v/b0wAaQZ AvXKPAhUJrGKk56jq9kJqNwegV/cdIprvIiMOCv1U5nWsiagzjAR2KNE2P1UpyqjACu3 JjuHSIxtzEyS+5pZh/J0dyVMtrcqE8wwm1qecnE8oOREaPYeSY8VjT/K3mCCP34vmC9P 3ReQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vuwiPZ5G; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d142sm102010iof.43.2020.11.10.13.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2020 13:59:28 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/6] net: ipa: use common value for channel type and protocol Date: Tue, 10 Nov 2020 15:59:18 -0600 Message-Id: <20201110215922.23514-3-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201110215922.23514-1-elder@linaro.org> References: <20201110215922.23514-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The numeric values that represent the event ring channel type are identical to the values that represent the matching protocol used for a channel. Use a new gsi_channel_type enumerated type to represent the values programmed for both cases, using "CHANNEL_TYPE" in member names in place of "EVT_CHTYPE" and "CHANNEL_PROTOCOL". Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 273529b69d39c..8b476e51ab78e 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -127,20 +127,12 @@ enum gsi_err_type { GSI_ERR_TYPE_EVT = 0x3, }; -/* Hardware values used when programming an event ring */ -enum gsi_evt_chtype { - GSI_EVT_CHTYPE_MHI_EV = 0x0, - GSI_EVT_CHTYPE_XHCI_EV = 0x1, - GSI_EVT_CHTYPE_GPI_EV = 0x2, - GSI_EVT_CHTYPE_XDCI_EV = 0x3, -}; - -/* Hardware values used when programming a channel */ -enum gsi_channel_protocol { - GSI_CHANNEL_PROTOCOL_MHI = 0x0, - GSI_CHANNEL_PROTOCOL_XHCI = 0x1, - GSI_CHANNEL_PROTOCOL_GPI = 0x2, - GSI_CHANNEL_PROTOCOL_XDCI = 0x3, +/* Hardware values used when programming a channel or event ring type */ +enum gsi_channel_type { + GSI_CHANNEL_TYPE_MHI = 0x0, + GSI_CHANNEL_TYPE_XHCI = 0x1, + GSI_CHANNEL_TYPE_GPI = 0x2, + GSI_CHANNEL_TYPE_XDCI = 0x3, }; /* Hardware values representing an event ring immediate command opcode */ @@ -684,7 +676,8 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id) size_t size = evt_ring->ring.count * GSI_RING_ELEMENT_SIZE; u32 val; - val = u32_encode_bits(GSI_EVT_CHTYPE_GPI_EV, EV_CHTYPE_FMASK); + /* We program all event rings as GPI type/protocol */ + val = u32_encode_bits(GSI_CHANNEL_TYPE_GPI, EV_CHTYPE_FMASK); val |= EV_INTYPE_FMASK; val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, EV_ELEMENT_SIZE_FMASK); iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id)); @@ -791,8 +784,8 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell) /* Arbitrarily pick TRE 0 as the first channel element to use */ channel->tre_ring.index = 0; - /* We program all channels to use GPI protocol */ - val = u32_encode_bits(GSI_CHANNEL_PROTOCOL_GPI, CHTYPE_PROTOCOL_FMASK); + /* We program all channels as GPI type/protocol */ + val = u32_encode_bits(GSI_CHANNEL_TYPE_GPI, CHTYPE_PROTOCOL_FMASK); if (channel->toward_ipa) val |= CHTYPE_DIR_FMASK; val |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK); From patchwork Tue Nov 10 21:59:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 322895 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp594617ils; Tue, 10 Nov 2020 13:59:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJzFul5gb0Tg5KeVmPSu8lKTulWYAY4kUXNCDB38UDahM4H7ci17DURcFLppQG8STZcMOgQd X-Received: by 2002:a05:6402:1cb2:: with SMTP id cz18mr22496014edb.388.1605045580802; Tue, 10 Nov 2020 13:59:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605045580; cv=none; d=google.com; s=arc-20160816; b=neDjQZBMnM+Mn7ECPWxqiz9ASY+y7tEoRouS0/s22tloYKPKZJlLbgxc5XKzauLvya EE33KWZEGcUJycZl+344Dr6tYq+VT9clxGvudMugLjdx6THSuu1BsfKQySfyw+D2UsL4 iZfKINXG2F2mgBnOeej2cL1vjAgGHWkI3uBNEA+casOTxigyGZLpJnDLJQHmWg/VQvxg OuHIdrHH5POqtUmfPx6uMoz4J5zhBdjIknhxbmm6feLkBA/gheO3SpFNIEDQ3NZ/qlq2 uLRd7TybgwiSTJlAfNfY7r0O/yxnLKgXgnVWYIDBbfbNSwkxXG9CBpV4rtfTz56i6aUK fnSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5ZfCNEsX2F4ym+QjxnD265ywN9odEwbi/6080mald40=; b=yQkdgluMjehFMBhmayKmD1DAg5h9cH7PQbkR3j8kEt1VAWIEsfRc+RxZi+VlfyHDdT lNbDH3WblQecfefhf070lH2alsJjSrk3+402VOzf0euQJ/Ly/o1YOjQ/3zDsF0OTW8Uh YApOxpEu2oOmkmx7xkZotS7qplV/ABQYAZ46n2UGGjspcEhMIOVq/YGkzzPlqeJDWBnC UwUIyOIcixoWarGlXcfNKZ9XIaL/35M39bNCzdK7L0guSQV7/rNsjv6u/Kmnoayazdbe 0OR7SjAxowNKncGlA5mECrU8PZpDIYapkZszvMt330g9kg1RlV1U2uyogKzURGV9Eh1S 1waQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ypXDU5Wg; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d142sm102010iof.43.2020.11.10.13.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2020 13:59:29 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/6] net: ipa: move channel type values into "gsi_reg.h" Date: Tue, 10 Nov 2020 15:59:19 -0600 Message-Id: <20201110215922.23514-4-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201110215922.23514-1-elder@linaro.org> References: <20201110215922.23514-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The gsi_channel_type enumerated type define values used for the channel type/protocol for event rings and channels. Move its definition out of "gsi.c" and into "gsi_reg.h", alongside the definition of the CH_C_CNTXT_0 register offset and its fields. Add a comment near the definition of the EV_CH_E_CNTXT_0 register indicating this type is used for its EV_CHTYPE field. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 8 -------- drivers/net/ipa/gsi_reg.h | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 8b476e51ab78e..78b793cf8aa4c 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -127,14 +127,6 @@ enum gsi_err_type { GSI_ERR_TYPE_EVT = 0x3, }; -/* Hardware values used when programming a channel or event ring type */ -enum gsi_channel_type { - GSI_CHANNEL_TYPE_MHI = 0x0, - GSI_CHANNEL_TYPE_XHCI = 0x1, - GSI_CHANNEL_TYPE_GPI = 0x2, - GSI_CHANNEL_TYPE_XDCI = 0x3, -}; - /* Hardware values representing an event ring immediate command opcode */ enum gsi_evt_cmd_opcode { GSI_EVT_ALLOCATE = 0x0, diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index e69ebe4aaf884..9260ce99ec525 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -71,6 +71,13 @@ #define ERINDEX_FMASK GENMASK(18, 14) #define CHSTATE_FMASK GENMASK(23, 20) #define ELEMENT_SIZE_FMASK GENMASK(31, 24) +/** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ +enum gsi_channel_type { + GSI_CHANNEL_TYPE_MHI = 0x0, + GSI_CHANNEL_TYPE_XHCI = 0x1, + GSI_CHANNEL_TYPE_GPI = 0x2, + GSI_CHANNEL_TYPE_XDCI = 0x3, +}; #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) @@ -128,6 +135,7 @@ #define EV_INTYPE_FMASK GENMASK(16, 16) #define EV_CHSTATE_FMASK GENMASK(23, 20) #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) +/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) From patchwork Tue Nov 10 21:59:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 322893 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp594599ils; Tue, 10 Nov 2020 13:59:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJxwBba4XMRaqvdsJHkh7RCh1+Ff2i5Z079HtWb+m5JR9nAuH+4cLo7drj5yuA3uZp8Pjpoo X-Received: by 2002:a17:906:824a:: with SMTP id f10mr23459376ejx.167.1605045578975; Tue, 10 Nov 2020 13:59:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605045578; cv=none; d=google.com; s=arc-20160816; b=MVyJO89nhNaO0qzt40aD7EHQ5f8Ev5BIAEdtxEKeL4iIRvTs/JnTvTufO/eXIFzWe5 AfxQ4VdoOERtFFZYvozwSOcGyQXwXuVyCH75hcY/JazgFbKZcWOs1HBU66HAeeDu4RVl pJ8I0MB1C1lneuoJ5gzJJBvzLED7/eUHnpllta5kKjP8uQsOsExkmCySnuKaOmMu1ujo k/tmeSxHrrCbUS1HeeeHtFW+jCprA0WLFUf3HV5nAory3Bfh5h+LrY59nNuFr8COgj0D 3btxL1d58xJ6cnV01M7+roD1zwdfpQ6SX00xog6CNcxPWewmZfHPIMIiVnokrO3WSSVW Vk7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yUv6MmZd8PXf2CY+EM20QKTjHLCVzZRKOzmrgGW/s44=; b=GJijgfrIzx/mifUS4xAx5yGEuEf0Pk3+83KOQcXiGBUMYZiECvoaxCT4hhvhML/4oE JvwO5ZTNMY/bsC4OdpN1CJ0weOyXX4cuRNJTp+9WnFKx9lTyC6MHBFugW4RX4abJa/Qj yz0jVlgfM1ZyoAzeyfrPmAeaXDtDSaI9Hm2608/ZeGN9I5Ot0qpv5Hk0W62MJAWc7NZx aw5eERXYPI48U3efgEsu9UZD4dpLIVJpTmy5DkIV4MvnGAHKVuuoDOgYm/DgRx0vAPbM wzvtknrP2nOyIAHB9LxXw/oYP/G9roCy+WhXzxf/gGesTDpiSeapp79NhLUc5T1sNx+Q zyaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hEsngPUJ; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d142sm102010iof.43.2020.11.10.13.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2020 13:59:30 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/6] net: ipa: move GSI error values into "gsi_reg.h" Date: Tue, 10 Nov 2020 15:59:20 -0600 Message-Id: <20201110215922.23514-5-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201110215922.23514-1-elder@linaro.org> References: <20201110215922.23514-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The gsi_err_code and gsi_err_type enumerated types are values that fields in the GSI ERROR_LOG register can take on. Move their definitions out of "gsi.c" and into "gsi_reg.h", alongside the definition of the ERROR_LOG register offset and field symbols. Drop the "_ERR" suffix in the names of the gsi_err_code members. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 22 ++-------------------- drivers/net/ipa/gsi_reg.h | 17 +++++++++++++++++ 2 files changed, 19 insertions(+), 20 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 78b793cf8aa4c..179991cff8807 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -109,24 +109,6 @@ struct gsi_event { u8 chid; }; -/* Hardware values from the error log register error code field */ -enum gsi_err_code { - GSI_INVALID_TRE_ERR = 0x1, - GSI_OUT_OF_BUFFERS_ERR = 0x2, - GSI_OUT_OF_RESOURCES_ERR = 0x3, - GSI_UNSUPPORTED_INTER_EE_OP_ERR = 0x4, - GSI_EVT_RING_EMPTY_ERR = 0x5, - GSI_NON_ALLOCATED_EVT_ACCESS_ERR = 0x6, - GSI_HWO_1_ERR = 0x8, -}; - -/* Hardware values from the error log register error type field */ -enum gsi_err_type { - GSI_ERR_TYPE_GLOB = 0x1, - GSI_ERR_TYPE_CHAN = 0x2, - GSI_ERR_TYPE_EVT = 0x3, -}; - /* Hardware values representing an event ring immediate command opcode */ enum gsi_evt_cmd_opcode { GSI_EVT_ALLOCATE = 0x0, @@ -1052,7 +1034,7 @@ static void gsi_isr_evt_ctrl(struct gsi *gsi) static void gsi_isr_glob_chan_err(struct gsi *gsi, u32 err_ee, u32 channel_id, u32 code) { - if (code == GSI_OUT_OF_RESOURCES_ERR) { + if (code == GSI_OUT_OF_RESOURCES) { dev_err(gsi->dev, "channel %u out of resources\n", channel_id); complete(&gsi->channel[channel_id].completion); return; @@ -1067,7 +1049,7 @@ gsi_isr_glob_chan_err(struct gsi *gsi, u32 err_ee, u32 channel_id, u32 code) static void gsi_isr_glob_evt_err(struct gsi *gsi, u32 err_ee, u32 evt_ring_id, u32 code) { - if (code == GSI_OUT_OF_RESOURCES_ERR) { + if (code == GSI_OUT_OF_RESOURCES) { struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; u32 channel_id = gsi_channel_id(evt_ring->channel); diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 9260ce99ec525..d46e3300dff70 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -384,6 +384,23 @@ enum gsi_general_id { #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) #define ERR_TYPE_FMASK GENMASK(27, 24) #define ERR_EE_FMASK GENMASK(31, 28) +/** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ +enum gsi_err_code { + GSI_INVALID_TRE = 0x1, + GSI_OUT_OF_BUFFERS = 0x2, + GSI_OUT_OF_RESOURCES = 0x3, + GSI_UNSUPPORTED_INTER_EE_OP = 0x4, + GSI_EVT_RING_EMPTY = 0x5, + GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, + /* 7 is not assigned */ + GSI_HWO_1 = 0x8, +}; +/** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ +enum gsi_err_type { + GSI_ERR_TYPE_GLOB = 0x1, + GSI_ERR_TYPE_CHAN = 0x2, + GSI_ERR_TYPE_EVT = 0x3, +}; #define GSI_ERROR_LOG_CLR_OFFSET \ GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) From patchwork Tue Nov 10 21:59:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 322897 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp594731ils; Tue, 10 Nov 2020 13:59:52 -0800 (PST) X-Google-Smtp-Source: ABdhPJzeWuRpHITMJ/7sDrecaO65vs6rRWnXNlKuVX8f+gMGdLDwFOV031nnpoRVkfHmZ5mCP4Qi X-Received: by 2002:aa7:cc83:: with SMTP id p3mr15435778edt.349.1605045592779; Tue, 10 Nov 2020 13:59:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605045592; cv=none; d=google.com; s=arc-20160816; b=gugqioDfym1UYxm5tHNdB6et6utDJ4V2y+YRNjVKTz6Yta68po1lmMR7dTSeNzSNRF c3idax38ZBjixMA05bbv7IfLTUEOgAtq19xhN24T4A+MNUEbTkGqWHC0FPPoz/x/Acmi cgCvP1fuB9js1X4IQ+lprLimfwb1gkZoZ7DuuEnrmGg2yvZQWXSZtzOGt9eE+BkZKqvN ydKPK9XLjEgjxGLPZ4qxVZz9X9Il3yAblH2sC0FqvUqi3GObvkLe6stRkP4uhYW1+CyB IVRvNLvjGMHOauZdfIRTGj8CfwGUQSBwnI5QDLsaYu/pgoaOcAcq98jwsLcdbkW/bs+/ jVYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5o/tlc4pwKGQFxYzh+9nrDgnEDmuz8gJr7Pwn8ETUkA=; b=kaBB+JycB6tJHgakAPxSV4rH4aDBiNGG2CnFkIIvaZLH3UocT+GL0h/lbQbIEpr7AF foIJ4JpUKZzt94FNcod2dlEwBjtYn+Pn33R/fOXwrptW6ckLbO/PN6h2U83/aFrBjQtR BnnPwahM2wN18/GBF48UuTLaaHpCL25bspmsD/c8nd4u3ssA6DxjbgGA8KTuZT769xyl QgClYGv1dHWYky/HMGwsQ+rIxV/t7Aiohstk/+njotaHr6mrCxlBPoxWMlYLGWytWuOS 1igHCLcBxLr4HwttuU0ugXfY26wAJ5HZUyvwbAsK3VDnUIBsSLqohjlT62TL3mwETC70 2GuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nu0B77KF; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d142sm102010iof.43.2020.11.10.13.59.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2020 13:59:31 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/6] net: ipa: move GSI command opcode values into "gsi_reg.h" Date: Tue, 10 Nov 2020 15:59:21 -0600 Message-Id: <20201110215922.23514-6-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201110215922.23514-1-elder@linaro.org> References: <20201110215922.23514-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The gsi_ch_cmd_opcode, gsi_evt_cmd_opcode, and gsi_generic_cmd_opcode enumerated types are values that fields in the GSI command registers can take on. Move their definitions out of "gsi.c" and into "gsi_reg.h", alongside the definition of registers they are associated with. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 22 ---------------------- drivers/net/ipa/gsi_reg.h | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 179991cff8807..c6803231bf5db 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -109,28 +109,6 @@ struct gsi_event { u8 chid; }; -/* Hardware values representing an event ring immediate command opcode */ -enum gsi_evt_cmd_opcode { - GSI_EVT_ALLOCATE = 0x0, - GSI_EVT_RESET = 0x9, - GSI_EVT_DE_ALLOC = 0xa, -}; - -/* Hardware values representing a generic immediate command opcode */ -enum gsi_generic_cmd_opcode { - GSI_GENERIC_HALT_CHANNEL = 0x1, - GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, -}; - -/* Hardware values representing a channel immediate command opcode */ -enum gsi_ch_cmd_opcode { - GSI_CH_ALLOCATE = 0x0, - GSI_CH_START = 0x1, - GSI_CH_STOP = 0x2, - GSI_CH_RESET = 0x9, - GSI_CH_DE_ALLOC = 0xa, -}; - /** gsi_channel_scratch_gpi - GPI protocol scratch register * @max_outstanding_tre: * Defines the maximum number of TREs allowed in a single transaction diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index d46e3300dff70..de3d87d278a98 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -223,6 +223,14 @@ enum gsi_channel_type { (0x0001f008 + 0x4000 * (ee)) #define CH_CHID_FMASK GENMASK(7, 0) #define CH_OPCODE_FMASK GENMASK(31, 24) +/** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ +enum gsi_ch_cmd_opcode { + GSI_CH_ALLOCATE = 0x0, + GSI_CH_START = 0x1, + GSI_CH_STOP = 0x2, + GSI_CH_RESET = 0x9, + GSI_CH_DE_ALLOC = 0xa, +}; #define GSI_EV_CH_CMD_OFFSET \ GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) @@ -230,6 +238,12 @@ enum gsi_channel_type { (0x0001f010 + 0x4000 * (ee)) #define EV_CHID_FMASK GENMASK(7, 0) #define EV_OPCODE_FMASK GENMASK(31, 24) +/** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ +enum gsi_evt_cmd_opcode { + GSI_EVT_ALLOCATE = 0x0, + GSI_EVT_RESET = 0x9, + GSI_EVT_DE_ALLOC = 0xa, +}; #define GSI_GENERIC_CMD_OFFSET \ GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) @@ -238,6 +252,11 @@ enum gsi_channel_type { #define GENERIC_OPCODE_FMASK GENMASK(4, 0) #define GENERIC_CHID_FMASK GENMASK(9, 5) #define GENERIC_EE_FMASK GENMASK(13, 10) +/** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ +enum gsi_generic_cmd_opcode { + GSI_GENERIC_HALT_CHANNEL = 0x1, + GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, +}; #define GSI_GSI_HW_PARAM_2_OFFSET \ GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) From patchwork Tue Nov 10 21:59:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 322894 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp594605ils; Tue, 10 Nov 2020 13:59:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJxDeY+vsQzvx6UvX2c8G+NDzyWw2kcyuvwln7pha2wxATdlJk7YjZKKUkM1zUhJjecYwczU X-Received: by 2002:a17:906:77cc:: with SMTP id m12mr21636803ejn.139.1605045579356; Tue, 10 Nov 2020 13:59:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605045579; cv=none; d=google.com; s=arc-20160816; b=fwZG1Es7fxvI/PPXLwn2n4WsnzxrT6wQOJ0cN7CCpJSl/xCt0M64Jo8YDVjaUcmwmk 7OTjeECwN3wd1QfH5r2aPDoixKCZ1UmbPmDGbpeE2B6OizQ7FDe+j4FM2V9QXjEs0eHc dVkiwMhZTfE/KFFBMfYaYUC2MfQuxjk1y7jskdZ+3fuzLp6GrBGJay8oCt5yFt1VZ+uH JoWusK3IY2P9+w0S67lpHuKLztsZ6Z2pk192L03xMd8VnFUwbZP4FJlY6DRtBno3BuUa XR3HwHWX6vj0fYO1v9XidYG5o1lwkdju9/AxPDBN1Buo1ZfPZEMrLQJCjZki1lVerdxz 3rGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wjZ1oTD8iKXhE2RbV6xdsXrZWc/uPcQH/bhvuWmn4Bs=; b=H5D0b32Fqy6wP+zDg4U0F1z6jksBuQjZIRBhz9rN2XSX1jjTisQE/ZJ+6j3MWMXonq jdWf4DaLqexOvZD5P4WKcNnDJhth36PZn+ZSBjwINtDjUN1wWpwNGaH/rJkPiIR8BnH9 l+QFGE+3PDZsnjqW8AAh4GWtfZ4rUX7jPD/CGs8gXmLmnSELIdOeIiN9tr+VTA456Yls MLMM0pB4thcTPJrwZnhbpGfqSGG70HfCz/+CwWSZNOKx0djVV1ekM8m4hpMFBNu+5YaS nG1pXu9h39IMji/d0A0Q/Ok6C+GR/Yv3sijBKqyOzXlZAHX4+dcFTL+/yL1mkznda90X k/vQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oN5mzZTt; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d142sm102010iof.43.2020.11.10.13.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2020 13:59:32 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 6/6] net: ipa: use enumerated types for GSI field values Date: Tue, 10 Nov 2020 15:59:22 -0600 Message-Id: <20201110215922.23514-7-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201110215922.23514-1-elder@linaro.org> References: <20201110215922.23514-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Replace constants defined with an "_FVAL" suffix with values defined in enumerated types, to be consistent with other usage in the driver. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 2 +- drivers/net/ipa/gsi_reg.h | 26 +++++++++++++++++--------- 2 files changed, 18 insertions(+), 10 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index c6803231bf5db..efa40c6e8281e 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -1077,7 +1077,7 @@ static void gsi_isr_gp_int1(struct gsi *gsi) val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); result = u32_get_bits(val, GENERIC_EE_RESULT_FMASK); - if (result != GENERIC_EE_SUCCESS_FVAL) + if (result != GENERIC_EE_SUCCESS) dev_err(gsi->dev, "global INT1 generic result %u\n", result); complete(&gsi->completion); diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index de3d87d278a98..8e3a7ffd19479 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -263,11 +263,6 @@ enum gsi_generic_cmd_opcode { #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ (0x0001f040 + 0x4000 * (ee)) #define IRAM_SIZE_FMASK GENMASK(2, 0) -#define IRAM_SIZE_ONE_KB_FVAL 0 -#define IRAM_SIZE_TWO_KB_FVAL 1 -/* The next two values are available for IPA v4.0 and above */ -#define IRAM_SIZE_TWO_N_HALF_KB_FVAL 2 -#define IRAM_SIZE_THREE_KB_FVAL 3 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) @@ -280,6 +275,14 @@ enum gsi_generic_cmd_opcode { /* Fields below are present for IPA v4.2 and above */ #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) +/** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ +enum gsi_iram_size { + IRAM_SIZE_ONE_KB = 0x0, + IRAM_SIZE_TWO_KB = 0x1, +/* The next two values are available for IPA v4.0 and above */ + IRAM_SIZE_TWO_N_HALF_KB = 0x2, + IRAM_SIZE_THREE_KB = 0x3, +}; /* IRQ condition for each type is cleared by writing type-specific register */ #define GSI_CNTXT_TYPE_IRQ_OFFSET \ @@ -432,10 +435,15 @@ enum gsi_err_type { (0x0001f400 + 0x4000 * (ee)) #define INTER_EE_RESULT_FMASK GENMASK(2, 0) #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) -#define GENERIC_EE_SUCCESS_FVAL 1 -#define GENERIC_EE_INCORRECT_DIRECTION_FVAL 3 -#define GENERIC_EE_INCORRECT_CHANNEL_FVAL 5 -#define GENERIC_EE_NO_RESOURCES_FVAL 7 +enum gsi_generic_ee_result { + GENERIC_EE_SUCCESS = 0x1, + GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2, + GENERIC_EE_INCORRECT_DIRECTION = 0x3, + GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, + GENERIC_EE_INCORRECT_CHANNEL = 0x5, + GENERIC_EE_RETRY = 0x6, + GENERIC_EE_NO_RESOURCES = 0x7, +}; #define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */ #define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24)