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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id c9sm3301534lfd.98.2020.11.17.13.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Nov 2020 13:35:53 -0800 (PST) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Yash Shah , "Wesley W . Terpstra" , Marc Zyngier Subject: [PATCH 1/2 v1] gpio: sifive: Set affinity callback to parent Date: Tue, 17 Nov 2020 22:33:50 +0100 Message-Id: <20201117213351.249668-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This assigns the .irq_set_affinity to the parent callback. I assume the sifive GPIO can be used in systems with SMP. I used the pattern making the hirerarchy tolerant for missing parent as in Marc's earlier patches. Cc: Yash Shah Cc: Wesley W. Terpstra Suggested-by: Marc Zyngier Signed-off-by: Linus Walleij --- ChangeLog RFT->v1: - Make the affinity setting call return -EINVAL if there is no parent. - Real patch because now we believe in this --- drivers/gpio/gpio-sifive.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.26.2 diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c index c54dd08f2cbf..485820e4488c 100644 --- a/drivers/gpio/gpio-sifive.c +++ b/drivers/gpio/gpio-sifive.c @@ -128,6 +128,16 @@ static void sifive_gpio_irq_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } +static int sifive_gpio_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, + bool force) +{ + if (data->parent_data) + return irq_chip_set_affinity_parent(data, dest, force); + + return -EINVAL; +} + static struct irq_chip sifive_gpio_irqchip = { .name = "sifive-gpio", .irq_set_type = sifive_gpio_irq_set_type, @@ -136,6 +146,7 @@ static struct irq_chip sifive_gpio_irqchip = { .irq_enable = sifive_gpio_irq_enable, .irq_disable = sifive_gpio_irq_disable, .irq_eoi = sifive_gpio_irq_eoi, + .irq_set_affinity = sifive_gpio_irq_set_affinity, }; static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc, From patchwork Tue Nov 17 21:33:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 325532 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp4515232ils; Tue, 17 Nov 2020 13:37:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJwVOixKUOZIiUTIpodGlyGbxpemAu0p/+NrbjXzdnL/rzRS5zyL6fBJMD84IK2xSoJg5rjP X-Received: by 2002:a50:9e29:: with SMTP id z38mr23411188ede.220.1605649035921; Tue, 17 Nov 2020 13:37:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605649035; cv=none; d=google.com; s=arc-20160816; b=Mi8IQ3icoRvnGcz6lH0sdzcWF4EdpVuSabxDuF+ZKDCRoHYCJ9qjwuKAC2RpZamyZX vTtoMc/GfjJ5O/9or0NpO01X10U3NcV88IfK4bcFYIZB06Tl6YzQDRbBonaQTD7uflA0 x4iytgR6ha7o5vj1C67ri2zruasMde5knCVCFDICUboFuCp28qOSlIKBwRE9kkbiP/55 6dOlPyLHMEf87JEKjYAct79U5kNve9oegM926V/q8t8R5qRwD/eUs6IrvZ+tRnei2JCg 2Wt8mclMj1L1JjfMQvERT7TPnp5lojq/7S+sx3kM2j4WyACe1S0vtpelUuVg806DhPBz ahtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QjVQoOTt3shsLqnsVnpkhic6+UrAPp0sadOUVrw9MEU=; b=mIsKk0fOswYqMuuL0G8aRgonavmT4lTL38xTq4YqM7LJd0lEx39U7T+f7jNAEP/5Fe x5XR5MEMgSbAXlZFRzrjvbp7CLenvXgOpcrR8QgvG5wkQZEYkulc4+ocaxl9pxWPoRzg 9zDQbHTWnZvvtYZfRKZaG+mZS85/WlCgWjxKpzNQ7C2kMc/S30TplKpk9sr9rzhbIwce pyNAIwYCaZjI6ubbo+PvgIH3UHtWtXFSrMe/xrLZJwnHZfQnNOasXC7/eLLf6Rb/gz0+ kNkEeHvbQ1lli8a+Ix0NniN/iSnzcBfb0M0T77TSRMOdvVodrBDwaZqPkyeSnrFbkTz+ GbKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fyNObB9r; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id c9sm3301534lfd.98.2020.11.17.13.36.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Nov 2020 13:36:08 -0800 (PST) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Thierry Reding , Vidya Sagar , Marc Zyngier Subject: [PATCH 2/2 v1] gpio: tegra186: Set affinity callback to parent Date: Tue, 17 Nov 2020 22:33:51 +0100 Message-Id: <20201117213351.249668-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201117213351.249668-1-linus.walleij@linaro.org> References: <20201117213351.249668-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This assigns the .irq_set_affinity to the parent callback. I assume the Tegra186 is an SMP system so this would be beneficial. I used the pattern making the hirerarchy tolerant for missing parent as in Marc's earlier patch. Cc: Thierry Reding Cc: Vidya Sagar Suggested-by: Marc Zyngier Signed-off-by: Linus Walleij --- ChangeLog RFT->v1: - Make the affinity setting call return -EINVAL if there is no parent. - Real patch because now we believe in this --- drivers/gpio/gpio-tegra186.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.26.2 diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 9500074b1f1b..286e0b1f46e4 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -444,6 +444,16 @@ static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra186_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, + bool force) +{ + if (data->parent_data) + return irq_chip_set_affinity_parent(data, dest, force); + + return -EINVAL; +} + static void tegra186_gpio_irq(struct irq_desc *desc) { struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); @@ -690,6 +700,7 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->intc.irq_unmask = tegra186_irq_unmask; gpio->intc.irq_set_type = tegra186_irq_set_type; gpio->intc.irq_set_wake = tegra186_irq_set_wake; + gpio->intc.irq_set_affinity = tegra186_irq_set_affinity; irq = &gpio->gpio.irq; irq->chip = &gpio->intc;