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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:35 -0800 Message-Id: <20180122034217.19593-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 01/43] target/hppa: Skeleton support for hppa-softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller With the addition of default-configs/hppa-softmmu.mak, this will compile. It is not enabled with this patch, however. Signed-off-by: Helge Deller Signed-off-by: Richard Henderson --- include/sysemu/arch_init.h | 1 + target/hppa/cpu.h | 1 + arch_init.c | 2 ++ hw/hppa/machine.c | 39 +++++++++++++++++++++++++++++++++ target/hppa/cpu.c | 5 +++++ target/hppa/helper.c | 10 --------- target/hppa/mem_helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/op_helper.c | 13 +++++++++-- hw/hppa/Makefile.objs | 1 + target/hppa/Makefile.objs | 2 +- 10 files changed, 115 insertions(+), 13 deletions(-) create mode 100644 hw/hppa/machine.c create mode 100644 target/hppa/mem_helper.c create mode 100644 hw/hppa/Makefile.objs -- 2.14.3 diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 8751c468ed..f999bfd3be 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -24,6 +24,7 @@ enum { QEMU_ARCH_MOXIE = (1 << 15), QEMU_ARCH_TRICORE = (1 << 16), QEMU_ARCH_NIOS2 = (1 << 17), + QEMU_ARCH_HPPA = (1 << 18), }; extern const uint32_t arch_type; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8d14077763..7fad92144c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -133,6 +133,7 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env); int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); diff --git a/arch_init.c b/arch_init.c index a0b8ed6167..4c36f2b076 100644 --- a/arch_init.c +++ b/arch_init.c @@ -53,6 +53,8 @@ int graphic_depth = 32; #define QEMU_ARCH QEMU_ARCH_CRIS #elif defined(TARGET_I386) #define QEMU_ARCH QEMU_ARCH_I386 +#elif defined(TARGET_HPPA) +#define QEMU_ARCH QEMU_ARCH_HPPA #elif defined(TARGET_M68K) #define QEMU_ARCH QEMU_ARCH_M68K #elif defined(TARGET_LM32) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c new file mode 100644 index 0000000000..4625e591ea --- /dev/null +++ b/hw/hppa/machine.c @@ -0,0 +1,39 @@ +/* + * QEMU HPPA hardware system emulator. + * Copyright 2017 Helge Deller + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "elf.h" +#include "hw/loader.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "sysemu/sysemu.h" +#include "hw/timer/mc146818rtc.h" +#include "hw/ide.h" +#include "hw/timer/i8254.h" +#include "hw/char/serial.h" +#include "qemu/cutils.h" +#include "qapi/error.h" + + +static void machine_hppa_init(MachineState *machine) +{ +} + +static void machine_hppa_machine_init(MachineClass *mc) +{ + mc->desc = "HPPA generic machine"; + mc->init = machine_hppa_init; + mc->block_default_type = IF_SCSI; + mc->max_cpus = 1; + mc->is_default = 1; + mc->default_ram_size = 2048UL*1024*1024; // 2GB + mc->default_boot_order = "cd"; +} + +DEFINE_MACHINE("hppa", machine_hppa_machine_init) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9e7b0d4ccb..f6d92de972 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -132,7 +132,12 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; cc->gdb_read_register = hppa_cpu_gdb_read_register; cc->gdb_write_register = hppa_cpu_gdb_write_register; +#ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; +#else + cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; +#endif + cc->disas_set_info = hppa_cpu_disas_set_info; cc->tcg_initialize = hppa_translate_init; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index ba04a9a52b..d6d6f06cb0 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -65,16 +65,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) env->psw_cb = cb; } -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, - int rw, int mmu_idx) -{ - HPPACPU *cpu = HPPA_CPU(cs); - - cs->exception_index = EXCP_SIGSEGV; - cpu->env.ior = address; - return 1; -} - void hppa_cpu_do_interrupt(CPUState *cs) { HPPACPU *cpu = HPPA_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c new file mode 100644 index 0000000000..e0802bc935 --- /dev/null +++ b/target/hppa/mem_helper.c @@ -0,0 +1,54 @@ +/* + * HPPA memory access helper routines + * + * Copyright (c) 2017 Helge Deller + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qom/cpu.h" + +#ifdef CONFIG_USER_ONLY +int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, + int rw, int mmu_idx) +{ + HPPACPU *cpu = HPPA_CPU(cs); + + cs->exception_index = EXCP_SIGSEGV; + cpu->env.ior = address; + return 1; +} +#else +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + /* Stub */ + return addr; +} + +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, + int mmu_idx, uintptr_t retaddr) +{ + /* Stub */ + int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + hwaddr phys = addr; + + /* Success! Store the translation into the QEMU TLB. */ + tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); +} +#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 3104404e8d..9c7603588f 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -58,9 +58,9 @@ void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY uint32_t old, new, cmp; -#ifdef CONFIG_USER_ONLY uint32_t *haddr = g2h(addr - 1); old = *haddr; while (1) { @@ -72,7 +72,8 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val, old = cmp; } #else -#error "Not implemented." + /* FIXME -- we can do better. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #endif } @@ -158,12 +159,20 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, target_ulong HELPER(probe_r)(target_ulong addr) { +#ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_READ); +#else + return 1; /* FIXME */ +#endif } target_ulong HELPER(probe_w)(target_ulong addr) { +#ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_WRITE); +#else + return 1; /* FIXME */ +#endif } void HELPER(loaded_fr0)(CPUHPPAState *env) diff --git a/hw/hppa/Makefile.objs b/hw/hppa/Makefile.objs new file mode 100644 index 0000000000..46b2ae18de --- /dev/null +++ b/hw/hppa/Makefile.objs @@ -0,0 +1 @@ +obj-y += machine.o diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index 263446fa0b..d89285307b 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1 @@ -obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o +obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o From patchwork Mon Jan 22 03:41:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125291 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp942697ljf; Sun, 21 Jan 2018 19:42:57 -0800 (PST) X-Google-Smtp-Source: AH8x227bkJGq/Xwbmtc14u/NXVDkp7ROOskb4fXo12cvTgyRc4effrEvU98YC6fMO6Uz70V7ZTwc X-Received: by 10.37.68.67 with SMTP id r64mr6344308yba.247.1516592577496; Sun, 21 Jan 2018 19:42:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516592577; cv=none; d=google.com; s=arc-20160816; b=jFgTQCBtUFej97PII+ovRri1Zj2BZ6v63/dJ8UtwBYXySXgPcTVvcsxhBF6y5uW1Or /CR/PKmaFMrrhseK9w94XNQLLGzacPHBf1kE34R4ysaGF5MELmcFJ4PeL9NOi6WiBn44 cCc/j+OOj5zHweDp8LQbZEdsMk+QJnwOLE0BBkmKtxcLPRZ8o9zDcSCs/DYstZyCQh6i rC4TG2y+QVxeqcQoVhGldiDZWvsVDBztEREekErw0ilwYRIxdtTnMtyx0pi2EkcBvc77 8VHe8Q84QYRLHw8HLiwZ4vGUHQXgNsL8a+j4M83bugKLkLAtV/MQMFHIvFReIypOXSdS BUjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/D3ilS4wflTksMAoF+YKaff+lQbvvqDLvk8pG7D1+9Y=; b=I7Z6AnGeEocnUn8IDntqx/HwNY7T+JZKPJba8Zfo17S0kJFvRuNYniKCeFzbUcoe/Z SHgbKP2FnEBRoBLP0pyLddylkbMgCnT+JDDP0orh/3utua9GQsInotoC0oWE5+md+ZXT G1/WKueCMxvfCLr5JHda/tEq4SRl0XLEwBLNY0QpDPMVEp3r2Oks+OJzzFZ2nJl7hkPW /J6IvaErtdr5A+K8hl+u9M0dY+PFulo68XXoARije0MJq+3vKM0elqrzXS4BGdF2Y+cO KhAHUwrwfwWmjM9TQ1hiRaHLoDOIGmj0hxJsv6RqnFR0FdAa08HryTbdQMmVYaVQjs2u SZzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=k0qiIK8n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:36 -0800 Message-Id: <20180122034217.19593-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 02/43] target/hppa: Define the rest of the PSW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We don't actually do anything with most of the bits yet, but at least they have names and we have somewhere to store them. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/helper.c | 53 ++++++++++++++++++++++++++++++++++++++-------------- 2 files changed, 86 insertions(+), 14 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7fad92144c..ea7e495408 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -46,6 +46,52 @@ #define EXCP_SIGILL 4 #define EXCP_SIGFPE 5 +/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ +#define PSW_I 0x00000001 +#define PSW_D 0x00000002 +#define PSW_P 0x00000004 +#define PSW_Q 0x00000008 +#define PSW_R 0x00000010 +#define PSW_F 0x00000020 +#define PSW_G 0x00000040 /* PA1.x only */ +#define PSW_O 0x00000080 /* PA2.0 only */ +#define PSW_CB 0x0000ff00 +#define PSW_M 0x00010000 +#define PSW_V 0x00020000 +#define PSW_C 0x00040000 +#define PSW_B 0x00080000 +#define PSW_X 0x00100000 +#define PSW_N 0x00200000 +#define PSW_L 0x00400000 +#define PSW_H 0x00800000 +#define PSW_T 0x01000000 +#define PSW_S 0x02000000 +#define PSW_E 0x04000000 +#ifdef TARGET_HPPA64 +#define PSW_W 0x08000000 /* PA2.0 only */ +#else +#define PSW_W 0 +#endif +#define PSW_Z 0x40000000 /* PA1.x only */ +#define PSW_Y 0x80000000 /* PA1.x only */ + +#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ + | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) + +/* ssm/rsm instructions number PSW_W and PSW_E differently */ +#define PSW_SM_I PSW_I /* Enable External Interrupts */ +#define PSW_SM_D PSW_D +#define PSW_SM_P PSW_P +#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ +#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ +#ifdef TARGET_HPPA64 +#define PSW_SM_E 0x100 +#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ +#else +#define PSW_SM_E 0 +#define PSW_SM_W 0 +#endif + typedef struct CPUHPPAState CPUHPPAState; struct CPUHPPAState { @@ -56,6 +102,7 @@ struct CPUHPPAState { target_ulong cr26; target_ulong cr27; + target_long psw; /* All psw bits except the following: */ target_ulong psw_n; /* boolean */ target_long psw_v; /* in most significant bit */ diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d6d6f06cb0..4231ef3bff 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -39,10 +39,11 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) /* .........................bcdefgh */ psw |= (psw >> 12) & 0xf; psw |= env->psw_cb_msb << 7; - psw <<= 8; + psw = (psw & 0xff) << 8; - psw |= env->psw_n << 21; - psw |= (env->psw_v < 0) << 17; + psw |= env->psw_n * PSW_N; + psw |= (env->psw_v < 0) * PSW_V; + psw |= env->psw; return psw; } @@ -51,8 +52,9 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { target_ulong cb = 0; - env->psw_n = (psw >> 21) & 1; - env->psw_v = -((psw >> 17) & 1); + env->psw = psw & ~(PSW_N | PSW_V | PSW_CB); + env->psw_n = (psw / PSW_N) & 1; + env->psw_v = -((psw / PSW_V) & 1); env->psw_cb_msb = (psw >> 15) & 1; cb |= ((psw >> 14) & 1) << 28; @@ -106,22 +108,45 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; + target_ulong psw = cpu_hppa_get_psw(env); + target_ulong psw_cb; + char psw_c[20]; int i; - cpu_fprintf(f, "IA_F " TARGET_FMT_lx - " IA_B " TARGET_FMT_lx - " PSW " TARGET_FMT_lx - " [N:" TARGET_FMT_ld " V:%d" - " CB:" TARGET_FMT_lx "]\n ", - env->iaoq_f, env->iaoq_b, cpu_hppa_get_psw(env), - env->psw_n, env->psw_v < 0, - ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28)); - for (i = 1; i < 32; i++) { + cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", + env->iaoq_f, env->iaoq_b); + + psw_c[0] = (psw & PSW_W ? 'W' : '-'); + psw_c[1] = (psw & PSW_E ? 'E' : '-'); + psw_c[2] = (psw & PSW_S ? 'S' : '-'); + psw_c[3] = (psw & PSW_T ? 'T' : '-'); + psw_c[4] = (psw & PSW_H ? 'H' : '-'); + psw_c[5] = (psw & PSW_L ? 'L' : '-'); + psw_c[6] = (psw & PSW_N ? 'N' : '-'); + psw_c[7] = (psw & PSW_X ? 'X' : '-'); + psw_c[8] = (psw & PSW_B ? 'B' : '-'); + psw_c[9] = (psw & PSW_C ? 'C' : '-'); + psw_c[10] = (psw & PSW_V ? 'V' : '-'); + psw_c[11] = (psw & PSW_M ? 'M' : '-'); + psw_c[12] = (psw & PSW_F ? 'F' : '-'); + psw_c[13] = (psw & PSW_R ? 'R' : '-'); + psw_c[14] = (psw & PSW_Q ? 'Q' : '-'); + psw_c[15] = (psw & PSW_P ? 'P' : '-'); + psw_c[16] = (psw & PSW_D ? 'D' : '-'); + psw_c[17] = (psw & PSW_I ? 'I' : '-'); + psw_c[18] = '\0'; + psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); + + cpu_fprintf(f, "PSW " TARGET_FMT_lx " CB " TARGET_FMT_lx " %s\n", + psw, psw_cb, psw_c); + + for (i = 0; i < 32; i++) { cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); if ((i % 4) == 3) { cpu_fprintf(f, "\n"); } } + cpu_fprintf(f, "\n"); /* ??? FR */ } From patchwork Mon Jan 22 03:41:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125296 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp944643ljf; Sun, 21 Jan 2018 19:49:28 -0800 (PST) X-Google-Smtp-Source: AH8x224DzblANfXBYt0FijOTmgdU/jpnf3M60TRgzs1+pZfiklQave1GWu7dSKtBfCbS47RVuSBy X-Received: by 10.129.164.150 with SMTP id b144mr6089684ywh.113.1516592968890; Sun, 21 Jan 2018 19:49:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516592968; cv=none; d=google.com; s=arc-20160816; b=eGFRQSEwoxaU7/isLtw1xfbzPYFeUDOkrw/LrmzU5IE6wi4ZGjjXjJpHoA/TsAgDIz Rh0NEAGJp2KscSFIicDHcKcUYolcaJepK3fjhmTjpGeXKwVgXIrzfqoQ1W7J/5cFM7fv v6FI6NGp7a7StAGqWGh6y+LWXYXBkTfQWZrwmZHqjYPlALCSq+MhdLzM5/iiZSBiLGiO aE4zcLaDB3D+pxYKMhcZ8EkAv9mPIVbep0oIzBsCFa5ZW0sYKSoZqrgh+glZclJ4nwu9 ThXx8MXr6TwwK7ccTYThbPXiBpoS2Fvech2nXfGDPW++CkP+ORCma5Y4Y6t4+S14XFJ4 o6XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=jWlXGhyGzuQklKuZM0jR3HHQ8HHbSqFzQDbbpF04MmY=; b=lA4JeosY5fSy2W4ensARXTDUXscpDbx75ZeqV4bKuXRv9m/5q7NnvKQ/sYLiJ3poTO 4XAllHXFWtkEKIx3GKNyOE2eLuucDOS2o9+DvYLkvQSsDq0OeRfM76F1A3etJg8SVLlA k1Eqz7/k/54TL6ebhJ9JWr4j76DGMXe+PIG3Zna7o+NYG12kmZdIKs3vPdXHC7TJ+DaB YYw4q+nWaGD/r33zUko8y0Bee3KXb1/NI7HlWcgsDeE9brUpqoMW0pWjL5QciTpRmrJS Tdg6M3xWJ23xRgb5vJUX/vIV3FmVg/zjZC3DSllUThOtZcmN9QRO6ZKF6dVxXTiYvoA4 NVcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ctyEwk30; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:37 -0800 Message-Id: <20180122034217.19593-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 03/43] target/hppa: Disable gateway page emulation for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 31d9a2a31b..8e357cc60c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1543,6 +1543,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, return DISAS_NEXT; } +#ifdef CONFIG_USER_ONLY /* On Linux, page zero is normally marked execute only + gateway. Therefore normal read or write is supposed to fail, but specific offsets have kernel code mapped to raise permissions to implement @@ -1600,6 +1601,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; } } +#endif static DisasJumpType trans_nop(DisasContext *ctx, uint32_t insn, const DisasInsn *di) @@ -3787,10 +3789,13 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) int i, n; /* Execute one insn. */ +#ifdef CONFIG_USER_ONLY if (ctx->iaoq_f < TARGET_PAGE_SIZE) { ret = do_page_zero(ctx); assert(ret != DISAS_NEXT); - } else { + } else +#endif + { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f); @@ -3885,25 +3890,27 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { TranslationBlock *tb = dcbase->tb; + target_ulong pc = tb->pc; - switch (tb->pc) { +#ifdef CONFIG_USER_ONLY + switch (pc) { case 0x00: qemu_log("IN:\n0x00000000: (null)\n"); - break; + return; case 0xb0: qemu_log("IN:\n0x000000b0: light-weight-syscall\n"); - break; + return; case 0xe0: qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n"); - break; + return; case 0x100: qemu_log("IN:\n0x00000100: syscall\n"); - break; - default: - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, tb->size); - break; + return; } +#endif + + qemu_log("IN: %s\n", lookup_symbol(pc)); + log_target_disas(cs, pc, tb->size); } static const TranslatorOps hppa_tr_ops = { From patchwork Mon Jan 22 03:41:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125301 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp945639ljf; Sun, 21 Jan 2018 19:52:48 -0800 (PST) X-Google-Smtp-Source: AH8x224DhAKz8E7AWSaddEHIH3m5rmfbWI4ymI23AADcb3C4hWRG7nOQIBaM5hPRw0Bps4FXt2Hz X-Received: by 10.37.208.66 with SMTP id h63mr6178428ybg.35.1516593168116; Sun, 21 Jan 2018 19:52:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593168; cv=none; d=google.com; s=arc-20160816; b=xcGHBVGE/BeB7U1uWTgLQW+GwgnXnZuPyY31OtMeUi+aoVUZaE+W+5ryWu3fUCmTud B1S7IDRJ1YsPq2k4AW229rGAhrlv2p39q8lesN4wlgfxro4fOZHtZU5srEDAorzRGHw3 dVmBipOhxFU5QjbRlGFekMBbxrvZFYhs2YK6Yh9GlZV43/4bbXky6MENH0TnzXpF2+RL 74bC+3HiPhQ9FCKmQI1OJiLdrWItELkRTH7/8H9z7+64t9oYacn6q45Xzg0ft/Gpxjti TKFL45/MQdzbgwVTIsL5xm8sfR5KwP0I730i01Cb5EE1Kf/F4xD1jNL5hjIY82XjA92g kzig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=d85lqCspBYOiEahvyujgf0zWY50v14bxlk08GHck46o=; b=tk6gV24iIFxDa3ntvEPfElkAjI5W1l4zWVMXz7fWR0ZHhHq7bHR6ZEHKHGzWQW+AIH j+b0ESXhIccgIEPPPqinpgyhQLPn+XAOtPC0BiF0ig6d0cFjCLWV+A33cLNh560ZaBNU C0159zDOVv4ZEO6DOYJ4mtsts2aMPiKi4AEOia4KAVd+opCqW27f5g7Kz9CzsyXKa5MZ oi1Ra0TPp8iQr5WjsXVbGDY9k0NY0Cqi+qq5G+xjbfzGD/SCdIMAhHoY/lZdm0wTlpdT GX9ZhL0C5s7K3wTzWo3vdv+p3UlEwKg2ds0lOk9ZoMw7gzlqW+Cea5FXnE9IeMpaJp4y ANyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SvZDiZlB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:38 -0800 Message-Id: <20180122034217.19593-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 04/43] target/hppa: Define hardware exception types X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 39 +++++++++++++++++++++++++++---- linux-user/main.c | 26 ++++++++++++++++++--- target/hppa/helper.c | 61 ++++++++++++++++++++++++++++++++++-------------- target/hppa/mem_helper.c | 4 +++- target/hppa/op_helper.c | 6 ++--- target/hppa/translate.c | 8 +++---- 6 files changed, 111 insertions(+), 33 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index ea7e495408..d84af91860 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -40,11 +40,40 @@ #define MMU_USER_IDX 0 #define TARGET_INSN_START_EXTRA_WORDS 1 -#define EXCP_SYSCALL 1 -#define EXCP_SYSCALL_LWS 2 -#define EXCP_SIGSEGV 3 -#define EXCP_SIGILL 4 -#define EXCP_SIGFPE 5 +/* Hardware exceptions, interupts, faults, and traps. */ +#define EXCP_HPMC 1 /* high priority machine check */ +#define EXCP_POWER_FAIL 2 +#define EXCP_RC 3 /* recovery counter */ +#define EXCP_EXT_INTERRUPT 4 /* external interrupt */ +#define EXCP_LPMC 5 /* low priority machine check */ +#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ +#define EXCP_IMP 7 /* instruction memory protection trap */ +#define EXCP_ILL 8 /* illegal instruction trap */ +#define EXCP_BREAK 9 /* break instruction */ +#define EXCP_PRIV_OPR 10 /* privileged operation trap */ +#define EXCP_PRIV_REG 11 /* privileged register trap */ +#define EXCP_OVERFLOW 12 /* signed overflow trap */ +#define EXCP_COND 13 /* trap-on-condition */ +#define EXCP_ASSIST 14 /* assist exception trap */ +#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ +#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ +#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ +#define EXCP_DMP 18 /* data memory protection trap */ +#define EXCP_DMB 19 /* data memory break trap */ +#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ +#define EXCP_PAGE_REF 21 /* page reference trap */ +#define EXCP_ASSIST_EMU 22 /* assist emulation trap */ +#define EXCP_HPT 23 /* high-privilege transfer trap */ +#define EXCP_LPT 24 /* low-privilege transfer trap */ +#define EXCP_TB 25 /* taken branch trap */ +#define EXCP_DMAR 26 /* data memory access rights trap */ +#define EXCP_DMPI 27 /* data memory protection id trap */ +#define EXCP_UNALIGN 28 /* unaligned data reference trap */ +#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ + +/* Exceptions for linux-user emulation. */ +#define EXCP_SYSCALL 30 +#define EXCP_SYSCALL_LWS 31 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ #define PSW_I 0x00000001 diff --git a/linux-user/main.c b/linux-user/main.c index 450eb3ce65..42f4c66ce6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3768,21 +3768,41 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_SIGSEGV: + case EXCP_ITLB_MISS: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_IMP: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_PAGE_REF: + case EXCP_DMAR: + case EXCP_DMPI: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_ACCERR; info._sifields._sigfault._addr = env->ior; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_SIGILL: + case EXCP_UNALIGN: + info.si_signo = TARGET_SIGBUS; + info.si_errno = 0; + info.si_code = 0; + info._sifields._sigfault._addr = env->ior; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ILL: + case EXCP_PRIV_OPR: + case EXCP_PRIV_REG: info.si_signo = TARGET_SIGILL; info.si_errno = 0; info.si_code = TARGET_ILL_ILLOPN; info._sifields._sigfault._addr = env->iaoq_f; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_SIGFPE: + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; info.si_code = 0; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 4231ef3bff..6439179a0e 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -74,25 +74,52 @@ void hppa_cpu_do_interrupt(CPUState *cs) int i = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { + static const char * const names[] = { + [EXCP_HPMC] = "high priority machine check", + [EXCP_POWER_FAIL] = "power fail interrupt", + [EXCP_RC] = "recovery counter trap", + [EXCP_EXT_INTERRUPT] = "external interrupt", + [EXCP_LPMC] = "low priority machine check", + [EXCP_ITLB_MISS] = "instruction tlb miss fault", + [EXCP_IMP] = "instruction memory protection trap", + [EXCP_ILL] = "illegal instruction trap", + [EXCP_BREAK] = "break instruction trap", + [EXCP_PRIV_OPR] = "privileged operation trap", + [EXCP_PRIV_REG] = "privileged register trap", + [EXCP_OVERFLOW] = "overflow trap", + [EXCP_COND] = "conditional trap", + [EXCP_ASSIST] = "assist exception trap", + [EXCP_DTLB_MISS] = "data tlb miss fault", + [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss", + [EXCP_NA_DTLB_MISS] = "non-access data tlb miss", + [EXCP_DMP] = "data memory protection trap", + [EXCP_DMB] = "data memory break trap", + [EXCP_TLB_DIRTY] = "tlb dirty bit trap", + [EXCP_PAGE_REF] = "page reference trap", + [EXCP_ASSIST_EMU] = "assist emulation trap", + [EXCP_HPT] = "high-privilege transfer trap", + [EXCP_LPT] = "low-privilege transfer trap", + [EXCP_TB] = "taken branch trap", + [EXCP_DMAR] = "data memory access rights trap", + [EXCP_DMPI] = "data memory protection id trap", + [EXCP_UNALIGN] = "unaligned data reference trap", + [EXCP_PER_INTERRUPT] = "performance monitor interrupt", + [EXCP_SYSCALL] = "syscall", + [EXCP_SYSCALL_LWS] = "syscall-lws", + }; static int count; - const char *name = ""; - - switch (i) { - case EXCP_SYSCALL: - name = "syscall"; - break; - case EXCP_SIGSEGV: - name = "sigsegv"; - break; - case EXCP_SIGILL: - name = "sigill"; - break; - case EXCP_SIGFPE: - name = "sigfpe"; - break; + const char *name = NULL; + + if (i >= 0 && i < ARRAY_SIZE(names)) { + name = names[i]; + } + if (name) { + qemu_log("INT %6d: %s ia_f=" TARGET_FMT_lx "\n", + ++count, name, env->iaoq_f); + } else { + qemu_log("INT %6d: unknown %d ia_f=" TARGET_FMT_lx "\n", + ++count, i, env->iaoq_f); } - qemu_log("INT %6d: %s ia_f=" TARGET_FMT_lx "\n", - ++count, name, env->iaoq_f); } cs->exception_index = -1; } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index e0802bc935..2901f3e29c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,7 +29,9 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { HPPACPU *cpu = HPPA_CPU(cs); - cs->exception_index = EXCP_SIGSEGV; + /* ??? Test between data page fault and data memory protection trap, + which would affect si_code. */ + cs->exception_index = EXCP_DMP; cpu->env.ior = address; return 1; } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 9c7603588f..d6b86834c1 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -44,14 +44,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) { if (unlikely((target_long)cond < 0)) { - dynexcp(env, EXCP_SIGFPE, GETPC()); + dynexcp(env, EXCP_OVERFLOW, GETPC()); } } void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) { if (unlikely(cond)) { - dynexcp(env, EXCP_SIGFPE, GETPC()); + dynexcp(env, EXCP_COND, GETPC()); } } @@ -235,7 +235,7 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) env->fr[0] = (uint64_t)shadow << 32; if (hard_exp & shadow) { - dynexcp(env, EXCP_SIGFPE, ra); + dynexcp(env, EXCP_ASSIST, ra); } } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8e357cc60c..8d85ed9df3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -462,7 +462,7 @@ static DisasJumpType gen_excp(DisasContext *ctx, int exception) static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_SIGILL)); + return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -1578,7 +1578,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) switch (ctx->iaoq_f) { case 0x00: /* Null pointer call */ - gen_excp_1(EXCP_SIGSEGV); + gen_excp_1(EXCP_IMP); return DISAS_NORETURN; case 0xb0: /* LWS */ @@ -1597,7 +1597,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) default: do_sigill: - gen_excp_1(EXCP_SIGILL); + gen_excp_1(EXCP_ILL); return DISAS_NORETURN; } } @@ -1614,7 +1614,7 @@ static DisasJumpType trans_break(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_DEBUG)); + return nullify_end(ctx, gen_excp(ctx, EXCP_BREAK)); } static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, From patchwork Mon Jan 22 03:41:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125302 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp945856ljf; Sun, 21 Jan 2018 19:53:25 -0800 (PST) X-Google-Smtp-Source: AH8x2257N9o703sbeSmG8pir+Spw3Uf4RIrQxJ22lY9LkTqMFIVX2mMtQ6lhxgxI3NJMtNwRG8CX X-Received: by 10.129.119.11 with SMTP id s11mr6211114ywc.401.1516593205028; Sun, 21 Jan 2018 19:53:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593205; cv=none; d=google.com; s=arc-20160816; b=JhGyzco58Ayu+RBJjw5PxVXH3JXXLx3Ldy/OqaipKpLWobykkcJwrTxNY7Ox2SLhgS Ol5DfMFNB7f4wXhVZpo4st4WWe7T8AkN5Q6QnCpl0x3LUOLsDXR4gdLGbzwxHjI5y3a5 l3DcU2urjS+6dEUoay9wF1TUsVBOYqblsJyV/543wMsutc8yZCr8L3Yvcz1xryWrfNLv 4BN7w9H0Hb8pCPW2T25WV8eLImaKz0iwd13qj4wqPerMYf0I4B6d8YeFGCppZTFdPgSo LIgNmBSV6KS+nB8ONGtT2mpsWFjoQyV2PjYBEvYl4H1y5G302z+5ST8pOnoIbQK493QK Tw/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7Xl8HB1mpd43wj515ZbjVmewI76v7qnBbNhwSKgYb5w=; b=WX/uIHezZggNtLvlNQ3vL4366BrGsAm+3sTthX571o3HOGyrRjqygQGNr+b4OHdwXj hINRhJIjXoR3zZqZprYagwLxM3bNDYo/hLA0K/S3vnHg3lMUS5G99c9chEK/LU6yQaEg dCSS3pZxwVgdNn6mkRUvFW4B3uhkY/VyyeYYgPrufKPDvRNJuTmze9YDQIHcVniTozjh /OcQvPBlKGGo2aybUjS5ZxV81dorWibIyTMd+YYFk1LsxjTqBmNHN9ULzL/7o82ZCnEa a+Ax98/J1lN3Yva9cpNBb45CE0pNLIwsQYXzeQSHFYwtHKf6hdmmMOSBeU2UsnZoA9e0 krXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Eas61GXP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:39 -0800 Message-Id: <20180122034217.19593-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 05/43] target/hppa: Split address size from register size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For system mode, we will need 64-bit virtual addresses even when we have 32-bit register sizes. Since the rest of QEMU equates TARGET_LONG_BITS with the address size, redefine everything related to register size in terms of a new TARGET_REGISTER_BITS. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 48 ++- target/hppa/helper.h | 26 +- target/hppa/gdbstub.c | 19 +- target/hppa/helper.c | 18 +- target/hppa/op_helper.c | 22 +- target/hppa/translate.c | 947 ++++++++++++++++++++++++++++++------------------ 6 files changed, 669 insertions(+), 411 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d84af91860..1524ef91b6 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,10 +23,10 @@ #include "qemu-common.h" #include "cpu-qom.h" -/* We only support hppa-linux-user at present, so 32-bit only. */ -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_LONG_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_REGISTER_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define CPUArchState struct CPUHPPAState @@ -123,17 +123,29 @@ typedef struct CPUHPPAState CPUHPPAState; +#if TARGET_REGISTER_BITS == 32 +typedef uint32_t target_ureg; +typedef int32_t target_sreg; +#define TREG_FMT_lx "%08"PRIx32 +#define TREG_FMT_ld "%"PRId32 +#else +typedef uint64_t target_ureg; +typedef int64_t target_sreg; +#define TREG_FMT_lx "%016"PRIx64 +#define TREG_FMT_ld "%"PRId64 +#endif + struct CPUHPPAState { - target_ulong gr[32]; + target_ureg gr[32]; uint64_t fr[32]; - target_ulong sar; - target_ulong cr26; - target_ulong cr27; + target_ureg sar; + target_ureg cr26; + target_ureg cr27; - target_long psw; /* All psw bits except the following: */ - target_ulong psw_n; /* boolean */ - target_long psw_v; /* in most significant bit */ + target_ureg psw; /* All psw bits except the following: */ + target_ureg psw_n; /* boolean */ + target_sreg psw_v; /* in most significant bit */ /* Splitting the carry-borrow field into the MSB and "the rest", allows * for "the rest" to be deleted when it is unused, but the MSB is in use. @@ -142,13 +154,13 @@ struct CPUHPPAState { * host has the appropriate add-with-carry insn to compute the msb). * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. */ - target_ulong psw_cb; /* in least significant bit of next nibble */ - target_ulong psw_cb_msb; /* boolean */ + target_ureg psw_cb; /* in least significant bit of next nibble */ + target_ureg psw_cb_msb; /* boolean */ - target_ulong iaoq_f; /* front */ - target_ulong iaoq_b; /* back, aka next instruction */ + target_ureg iaoq_f; /* front */ + target_ureg iaoq_b; /* back, aka next instruction */ - target_ulong ior; /* interrupt offset register */ + target_ureg ior; /* interrupt offset register */ uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; @@ -201,8 +213,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, *pflags = env->psw_n; } -target_ulong cpu_hppa_get_psw(CPUHPPAState *env); -void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); +target_ureg cpu_hppa_get_psw(CPUHPPAState *env); +void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); void cpu_hppa_loaded_fr0(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 0a6b900555..c720de523b 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,14 +1,24 @@ +#if TARGET_REGISTER_BITS == 64 +# define dh_alias_tr i64 +# define dh_is_64bit_tr 1 +#else +# define dh_alias_tr i32 +# define dh_is_64bit_tr 0 +#endif +#define dh_ctype_tr target_ureg +#define dh_is_signed_tr 0 + DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr) +DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tr) -DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tr, tl) +DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tr, tl) DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index c37a56f238..228d282fe9 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -26,7 +26,7 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - target_ulong val; + target_ureg val; switch (n) { case 0: @@ -61,14 +61,25 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) } break; } - return gdb_get_regl(mem_buf, val); + + if (TARGET_REGISTER_BITS == 64) { + return gdb_get_reg64(mem_buf, val); + } else { + return gdb_get_reg32(mem_buf, val); + } } int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - target_ulong val = ldtul_p(mem_buf); + target_ureg val; + + if (TARGET_REGISTER_BITS == 64) { + val = ldq_p(mem_buf); + } else { + val = ldl_p(mem_buf); + } switch (n) { case 0: @@ -108,5 +119,5 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } break; } - return sizeof(target_ulong); + return sizeof(target_ureg); } diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 6439179a0e..b6521f61fc 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -24,9 +24,9 @@ #include "fpu/softfloat.h" #include "exec/helper-proto.h" -target_ulong cpu_hppa_get_psw(CPUHPPAState *env) +target_ureg cpu_hppa_get_psw(CPUHPPAState *env) { - target_ulong psw; + target_ureg psw; /* Fold carry bits down to 8 consecutive bits. */ /* ??? Needs tweaking for hppa64. */ @@ -48,9 +48,9 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) return psw; } -void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) +void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) { - target_ulong cb = 0; + target_ureg cb = 0; env->psw = psw & ~(PSW_N | PSW_V | PSW_CB); env->psw_n = (psw / PSW_N) & 1; @@ -135,13 +135,13 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - target_ulong psw = cpu_hppa_get_psw(env); - target_ulong psw_cb; + target_ureg psw = cpu_hppa_get_psw(env); + target_ureg psw_cb; char psw_c[20]; int i; cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", - env->iaoq_f, env->iaoq_b); + (target_ulong)env->iaoq_f, (target_ulong)env->iaoq_b); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); @@ -164,11 +164,11 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, psw_c[18] = '\0'; psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); - cpu_fprintf(f, "PSW " TARGET_FMT_lx " CB " TARGET_FMT_lx " %s\n", + cpu_fprintf(f, "PSW " TREG_FMT_lx " CB " TREG_FMT_lx " %s\n", psw, psw_cb, psw_c); for (i = 0; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); + cpu_fprintf(f, "GR%02d " TREG_FMT_lx " ", i, env->gr[i]); if ((i % 4) == 3) { cpu_fprintf(f, "\n"); } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index d6b86834c1..479bfc0fdf 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -41,14 +41,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } -void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) +void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) { - if (unlikely((target_long)cond < 0)) { + if (unlikely((target_sreg)cond < 0)) { dynexcp(env, EXCP_OVERFLOW, GETPC()); } } -void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) +void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) { if (unlikely(cond)) { dynexcp(env, EXCP_COND, GETPC()); @@ -77,7 +77,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val, #endif } -static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val, +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val, bool parallel) { uintptr_t ra = GETPC(); @@ -104,18 +104,18 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val, } } -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_b(env, addr, val, false); } void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, - target_ulong val) + target_ureg val) { do_stby_b(env, addr, val, true); } -static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val, +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val, bool parallel) { uintptr_t ra = GETPC(); @@ -146,18 +146,18 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val, } } -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_e(env, addr, val, false); } void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, - target_ulong val) + target_ureg val) { do_stby_e(env, addr, val, true); } -target_ulong HELPER(probe_r)(target_ulong addr) +target_ureg HELPER(probe_r)(target_ulong addr) { #ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_READ); @@ -166,7 +166,7 @@ target_ulong HELPER(probe_r)(target_ulong addr) #endif } -target_ulong HELPER(probe_w)(target_ulong addr) +target_ureg HELPER(probe_w)(target_ulong addr) { #ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_WRITE); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8d85ed9df3..b3996cfcdc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -30,9 +30,235 @@ #include "trace-tcg.h" #include "exec/log.h" +/* Since we have a distinction between register size and address size, + we need to redefine all of these. */ + +#undef TCGv +#undef tcg_temp_new +#undef tcg_global_reg_new +#undef tcg_global_mem_new +#undef tcg_temp_local_new +#undef tcg_temp_free + +#if TARGET_LONG_BITS == 64 +#define TCGv_tl TCGv_i64 +#define tcg_temp_new_tl tcg_temp_new_i64 +#define tcg_temp_free_tl tcg_temp_free_i64 +#if TARGET_REGISTER_BITS == 64 +#define tcg_gen_extu_reg_tl tcg_gen_mov_i64 +#else +#define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 +#endif +#else +#define TCGv_tl TCGv_i32 +#define tcg_temp_new_tl tcg_temp_new_i32 +#define tcg_temp_free_tl tcg_temp_free_i32 +#define tcg_gen_extu_reg_tl tcg_gen_mov_i32 +#endif + +#if TARGET_REGISTER_BITS == 64 +#define TCGv_reg TCGv_i64 + +#define tcg_temp_new tcg_temp_new_i64 +#define tcg_global_reg_new tcg_global_reg_new_i64 +#define tcg_global_mem_new tcg_global_mem_new_i64 +#define tcg_temp_local_new tcg_temp_local_new_i64 +#define tcg_temp_free tcg_temp_free_i64 + +#define tcg_gen_movi_reg tcg_gen_movi_i64 +#define tcg_gen_mov_reg tcg_gen_mov_i64 +#define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 +#define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 +#define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 +#define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 +#define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 +#define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 +#define tcg_gen_ld_reg tcg_gen_ld_i64 +#define tcg_gen_st8_reg tcg_gen_st8_i64 +#define tcg_gen_st16_reg tcg_gen_st16_i64 +#define tcg_gen_st32_reg tcg_gen_st32_i64 +#define tcg_gen_st_reg tcg_gen_st_i64 +#define tcg_gen_add_reg tcg_gen_add_i64 +#define tcg_gen_addi_reg tcg_gen_addi_i64 +#define tcg_gen_sub_reg tcg_gen_sub_i64 +#define tcg_gen_neg_reg tcg_gen_neg_i64 +#define tcg_gen_subfi_reg tcg_gen_subfi_i64 +#define tcg_gen_subi_reg tcg_gen_subi_i64 +#define tcg_gen_and_reg tcg_gen_and_i64 +#define tcg_gen_andi_reg tcg_gen_andi_i64 +#define tcg_gen_or_reg tcg_gen_or_i64 +#define tcg_gen_ori_reg tcg_gen_ori_i64 +#define tcg_gen_xor_reg tcg_gen_xor_i64 +#define tcg_gen_xori_reg tcg_gen_xori_i64 +#define tcg_gen_not_reg tcg_gen_not_i64 +#define tcg_gen_shl_reg tcg_gen_shl_i64 +#define tcg_gen_shli_reg tcg_gen_shli_i64 +#define tcg_gen_shr_reg tcg_gen_shr_i64 +#define tcg_gen_shri_reg tcg_gen_shri_i64 +#define tcg_gen_sar_reg tcg_gen_sar_i64 +#define tcg_gen_sari_reg tcg_gen_sari_i64 +#define tcg_gen_brcond_reg tcg_gen_brcond_i64 +#define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 +#define tcg_gen_setcond_reg tcg_gen_setcond_i64 +#define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 +#define tcg_gen_mul_reg tcg_gen_mul_i64 +#define tcg_gen_muli_reg tcg_gen_muli_i64 +#define tcg_gen_div_reg tcg_gen_div_i64 +#define tcg_gen_rem_reg tcg_gen_rem_i64 +#define tcg_gen_divu_reg tcg_gen_divu_i64 +#define tcg_gen_remu_reg tcg_gen_remu_i64 +#define tcg_gen_discard_reg tcg_gen_discard_i64 +#define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 +#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 +#define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 +#define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 +#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 +#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 +#define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 +#define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 +#define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 +#define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 +#define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 +#define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 +#define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 +#define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 +#define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 +#define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 +#define tcg_gen_andc_reg tcg_gen_andc_i64 +#define tcg_gen_eqv_reg tcg_gen_eqv_i64 +#define tcg_gen_nand_reg tcg_gen_nand_i64 +#define tcg_gen_nor_reg tcg_gen_nor_i64 +#define tcg_gen_orc_reg tcg_gen_orc_i64 +#define tcg_gen_clz_reg tcg_gen_clz_i64 +#define tcg_gen_ctz_reg tcg_gen_ctz_i64 +#define tcg_gen_clzi_reg tcg_gen_clzi_i64 +#define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 +#define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 +#define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 +#define tcg_gen_rotl_reg tcg_gen_rotl_i64 +#define tcg_gen_rotli_reg tcg_gen_rotli_i64 +#define tcg_gen_rotr_reg tcg_gen_rotr_i64 +#define tcg_gen_rotri_reg tcg_gen_rotri_i64 +#define tcg_gen_deposit_reg tcg_gen_deposit_i64 +#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 +#define tcg_gen_extract_reg tcg_gen_extract_i64 +#define tcg_gen_sextract_reg tcg_gen_sextract_i64 +#define tcg_const_reg tcg_const_i64 +#define tcg_const_local_reg tcg_const_local_i64 +#define tcg_gen_movcond_reg tcg_gen_movcond_i64 +#define tcg_gen_add2_reg tcg_gen_add2_i64 +#define tcg_gen_sub2_reg tcg_gen_sub2_i64 +#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 +#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 +#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 +#if UINTPTR_MAX == UINT32_MAX +# define tcg_gen_trunc_reg_ptr(p,r) tcg_gen_trunc_i64_i32(TCGV_PTR_TO_NAT(p),r) +#else +# define tcg_gen_trunc_reg_ptr(p,r) tcg_gen_mov_i64(TCGV_PTR_TO_NAT(p),r) +#endif +#else +#define TCGv_reg TCGv_i32 +#define tcg_temp_new tcg_temp_new_i32 +#define tcg_global_reg_new tcg_global_reg_new_i32 +#define tcg_global_mem_new tcg_global_mem_new_i32 +#define tcg_temp_local_new tcg_temp_local_new_i32 +#define tcg_temp_free tcg_temp_free_i32 + +#define tcg_gen_movi_reg tcg_gen_movi_i32 +#define tcg_gen_mov_reg tcg_gen_mov_i32 +#define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 +#define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 +#define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 +#define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 +#define tcg_gen_ld32u_reg tcg_gen_ld_i32 +#define tcg_gen_ld32s_reg tcg_gen_ld_i32 +#define tcg_gen_ld_reg tcg_gen_ld_i32 +#define tcg_gen_st8_reg tcg_gen_st8_i32 +#define tcg_gen_st16_reg tcg_gen_st16_i32 +#define tcg_gen_st32_reg tcg_gen_st32_i32 +#define tcg_gen_st_reg tcg_gen_st_i32 +#define tcg_gen_add_reg tcg_gen_add_i32 +#define tcg_gen_addi_reg tcg_gen_addi_i32 +#define tcg_gen_sub_reg tcg_gen_sub_i32 +#define tcg_gen_neg_reg tcg_gen_neg_i32 +#define tcg_gen_subfi_reg tcg_gen_subfi_i32 +#define tcg_gen_subi_reg tcg_gen_subi_i32 +#define tcg_gen_and_reg tcg_gen_and_i32 +#define tcg_gen_andi_reg tcg_gen_andi_i32 +#define tcg_gen_or_reg tcg_gen_or_i32 +#define tcg_gen_ori_reg tcg_gen_ori_i32 +#define tcg_gen_xor_reg tcg_gen_xor_i32 +#define tcg_gen_xori_reg tcg_gen_xori_i32 +#define tcg_gen_not_reg tcg_gen_not_i32 +#define tcg_gen_shl_reg tcg_gen_shl_i32 +#define tcg_gen_shli_reg tcg_gen_shli_i32 +#define tcg_gen_shr_reg tcg_gen_shr_i32 +#define tcg_gen_shri_reg tcg_gen_shri_i32 +#define tcg_gen_sar_reg tcg_gen_sar_i32 +#define tcg_gen_sari_reg tcg_gen_sari_i32 +#define tcg_gen_brcond_reg tcg_gen_brcond_i32 +#define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 +#define tcg_gen_setcond_reg tcg_gen_setcond_i32 +#define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 +#define tcg_gen_mul_reg tcg_gen_mul_i32 +#define tcg_gen_muli_reg tcg_gen_muli_i32 +#define tcg_gen_div_reg tcg_gen_div_i32 +#define tcg_gen_rem_reg tcg_gen_rem_i32 +#define tcg_gen_divu_reg tcg_gen_divu_i32 +#define tcg_gen_remu_reg tcg_gen_remu_i32 +#define tcg_gen_discard_reg tcg_gen_discard_i32 +#define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 +#define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 +#define tcg_gen_extu_i32_reg tcg_gen_mov_i32 +#define tcg_gen_ext_i32_reg tcg_gen_mov_i32 +#define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 +#define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 +#define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 +#define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 +#define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 +#define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 +#define tcg_gen_ext32u_reg tcg_gen_mov_i32 +#define tcg_gen_ext32s_reg tcg_gen_mov_i32 +#define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 +#define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 +#define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 +#define tcg_gen_andc_reg tcg_gen_andc_i32 +#define tcg_gen_eqv_reg tcg_gen_eqv_i32 +#define tcg_gen_nand_reg tcg_gen_nand_i32 +#define tcg_gen_nor_reg tcg_gen_nor_i32 +#define tcg_gen_orc_reg tcg_gen_orc_i32 +#define tcg_gen_clz_reg tcg_gen_clz_i32 +#define tcg_gen_ctz_reg tcg_gen_ctz_i32 +#define tcg_gen_clzi_reg tcg_gen_clzi_i32 +#define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 +#define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 +#define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 +#define tcg_gen_rotl_reg tcg_gen_rotl_i32 +#define tcg_gen_rotli_reg tcg_gen_rotli_i32 +#define tcg_gen_rotr_reg tcg_gen_rotr_i32 +#define tcg_gen_rotri_reg tcg_gen_rotri_i32 +#define tcg_gen_deposit_reg tcg_gen_deposit_i32 +#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 +#define tcg_gen_extract_reg tcg_gen_extract_i32 +#define tcg_gen_sextract_reg tcg_gen_sextract_i32 +#define tcg_const_reg tcg_const_i32 +#define tcg_const_local_reg tcg_const_local_i32 +#define tcg_gen_movcond_reg tcg_gen_movcond_i32 +#define tcg_gen_add2_reg tcg_gen_add2_i32 +#define tcg_gen_sub2_reg tcg_gen_sub2_i32 +#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 +#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 +#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 +#if UINTPTR_MAX == UINT32_MAX +# define tcg_gen_trunc_reg_ptr(p,r) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(p),r) +#else +# define tcg_gen_trunc_reg_ptr(p,r) tcg_gen_extu_i32_i64(TCGV_PTR_TO_NAT(p),r) +#endif +#endif /* TARGET_REGISTER_BITS */ + typedef struct DisasCond { TCGCond c; - TCGv a0, a1; + TCGv_reg a0, a1; bool a0_is_n; bool a1_is_0; } DisasCond; @@ -41,13 +267,13 @@ typedef struct DisasContext { DisasContextBase base; CPUState *cs; - target_ulong iaoq_f; - target_ulong iaoq_b; - target_ulong iaoq_n; - TCGv iaoq_n_var; + target_ureg iaoq_f; + target_ureg iaoq_b; + target_ureg iaoq_n; + TCGv_reg iaoq_n_var; int ntemps; - TCGv temps[8]; + TCGv_reg temps[8]; DisasCond null_cond; TCGLabel *null_lab; @@ -72,7 +298,7 @@ typedef struct DisasInsn { DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, const struct DisasInsn *f); union { - void (*ttt)(TCGv, TCGv, TCGv); + void (*ttt)(TCGv_reg, TCGv_reg, TCGv_reg); void (*weww)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32); void (*dedd)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64); void (*wew)(TCGv_i32, TCGv_env, TCGv_i32); @@ -83,16 +309,16 @@ typedef struct DisasInsn { } DisasInsn; /* global register indexes */ -static TCGv cpu_gr[32]; -static TCGv cpu_iaoq_f; -static TCGv cpu_iaoq_b; -static TCGv cpu_sar; -static TCGv cpu_psw_n; -static TCGv cpu_psw_v; -static TCGv cpu_psw_cb; -static TCGv cpu_psw_cb_msb; -static TCGv cpu_cr26; -static TCGv cpu_cr27; +static TCGv_reg cpu_gr[32]; +static TCGv_reg cpu_iaoq_f; +static TCGv_reg cpu_iaoq_b; +static TCGv_reg cpu_sar; +static TCGv_reg cpu_psw_n; +static TCGv_reg cpu_psw_v; +static TCGv_reg cpu_psw_cb; +static TCGv_reg cpu_psw_cb_msb; +static TCGv_reg cpu_cr26; +static TCGv_reg cpu_cr27; #include "exec/gen-icount.h" @@ -100,7 +326,7 @@ void hppa_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } - typedef struct { TCGv *var; const char *name; int ofs; } GlobalVar; + typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] = { DEF_VAR(sar), DEF_VAR(cr26), @@ -158,26 +384,26 @@ static DisasCond cond_make_n(void) }; } -static DisasCond cond_make_0(TCGCond c, TCGv a0) +static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) { DisasCond r = { .c = c, .a1 = NULL, .a1_is_0 = true }; assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); r.a0 = tcg_temp_new(); - tcg_gen_mov_tl(r.a0, a0); + tcg_gen_mov_reg(r.a0, a0); return r; } -static DisasCond cond_make(TCGCond c, TCGv a0, TCGv a1) +static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) { DisasCond r = { .c = c }; assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); r.a0 = tcg_temp_new(); - tcg_gen_mov_tl(r.a0, a0); + tcg_gen_mov_reg(r.a0, a0); r.a1 = tcg_temp_new(); - tcg_gen_mov_tl(r.a1, a1); + tcg_gen_mov_reg(r.a1, a1); return r; } @@ -186,7 +412,7 @@ static void cond_prep(DisasCond *cond) { if (cond->a1_is_0) { cond->a1_is_0 = false; - cond->a1 = tcg_const_tl(0); + cond->a1 = tcg_const_reg(0); } } @@ -213,32 +439,32 @@ static void cond_free(DisasCond *cond) } } -static TCGv get_temp(DisasContext *ctx) +static TCGv_reg get_temp(DisasContext *ctx) { unsigned i = ctx->ntemps++; g_assert(i < ARRAY_SIZE(ctx->temps)); return ctx->temps[i] = tcg_temp_new(); } -static TCGv load_const(DisasContext *ctx, target_long v) +static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { - TCGv t = get_temp(ctx); - tcg_gen_movi_tl(t, v); + TCGv_reg t = get_temp(ctx); + tcg_gen_movi_reg(t, v); return t; } -static TCGv load_gpr(DisasContext *ctx, unsigned reg) +static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) { if (reg == 0) { - TCGv t = get_temp(ctx); - tcg_gen_movi_tl(t, 0); + TCGv_reg t = get_temp(ctx); + tcg_gen_movi_reg(t, 0); return t; } else { return cpu_gr[reg]; } } -static TCGv dest_gpr(DisasContext *ctx, unsigned reg) +static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) { if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { return get_temp(ctx); @@ -247,18 +473,18 @@ static TCGv dest_gpr(DisasContext *ctx, unsigned reg) } } -static void save_or_nullify(DisasContext *ctx, TCGv dest, TCGv t) +static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) { if (ctx->null_cond.c != TCG_COND_NEVER) { cond_prep(&ctx->null_cond); - tcg_gen_movcond_tl(ctx->null_cond.c, dest, ctx->null_cond.a0, + tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, ctx->null_cond.a1, dest, t); } else { - tcg_gen_mov_tl(dest, t); + tcg_gen_mov_reg(dest, t); } } -static void save_gpr(DisasContext *ctx, unsigned reg, TCGv t) +static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) { if (reg != 0) { save_or_nullify(ctx, cpu_gr[reg], t); @@ -350,17 +576,17 @@ static void nullify_over(DisasContext *ctx) if (ctx->null_cond.a0_is_n) { ctx->null_cond.a0_is_n = false; ctx->null_cond.a0 = tcg_temp_new(); - tcg_gen_mov_tl(ctx->null_cond.a0, cpu_psw_n); + tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); } /* ... we clear it before branching over the implementation, so that (1) it's clear after nullifying this insn and (2) if this insn nullifies the next, PSW[N] is valid. */ if (ctx->psw_n_nonzero) { ctx->psw_n_nonzero = false; - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); } - tcg_gen_brcond_tl(ctx->null_cond.c, ctx->null_cond.a0, + tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); cond_free(&ctx->null_cond); } @@ -371,13 +597,13 @@ static void nullify_save(DisasContext *ctx) { if (ctx->null_cond.c == TCG_COND_NEVER) { if (ctx->psw_n_nonzero) { - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); } return; } if (!ctx->null_cond.a0_is_n) { cond_prep(&ctx->null_cond); - tcg_gen_setcond_tl(ctx->null_cond.c, cpu_psw_n, + tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero = true; } @@ -390,7 +616,7 @@ static void nullify_save(DisasContext *ctx) static void nullify_set(DisasContext *ctx, bool x) { if (ctx->psw_n_nonzero || x) { - tcg_gen_movi_tl(cpu_psw_n, x); + tcg_gen_movi_reg(cpu_psw_n, x); } } @@ -429,16 +655,16 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) return status; } -static void copy_iaoq_entry(TCGv dest, target_ulong ival, TCGv vval) +static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) { if (unlikely(ival == -1)) { - tcg_gen_mov_tl(dest, vval); + tcg_gen_mov_reg(dest, vval); } else { - tcg_gen_movi_tl(dest, ival); + tcg_gen_movi_reg(dest, ival); } } -static inline target_ulong iaoq_dest(DisasContext *ctx, target_long disp) +static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) { return ctx->iaoq_f + disp + 8; } @@ -465,7 +691,7 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } -static bool use_goto_tb(DisasContext *ctx, target_ulong dest) +static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ if ((tb_cflags(ctx->base.tb) & CF_LAST_IO) || ctx->base.singlestep_enabled) { @@ -485,12 +711,12 @@ static bool use_nullify_skip(DisasContext *ctx) } static void gen_goto_tb(DisasContext *ctx, int which, - target_ulong f, target_ulong b) + target_ureg f, target_ureg b) { if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { tcg_gen_goto_tb(which); - tcg_gen_movi_tl(cpu_iaoq_f, f); - tcg_gen_movi_tl(cpu_iaoq_b, b); + tcg_gen_movi_reg(cpu_iaoq_f, f); + tcg_gen_movi_reg(cpu_iaoq_b, b); tcg_gen_exit_tb((uintptr_t)ctx->base.tb + which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); @@ -505,9 +731,9 @@ static void gen_goto_tb(DisasContext *ctx, int which, /* PA has a habit of taking the LSB of a field and using that as the sign, with the rest of the field becoming the least significant bits. */ -static target_long low_sextract(uint32_t val, int pos, int len) +static target_sreg low_sextract(uint32_t val, int pos, int len) { - target_ulong x = -(target_ulong)extract32(val, pos, 1); + target_ureg x = -(target_ureg)extract32(val, pos, 1); x = (x << (len - 1)) | extract32(val, pos + 1, len - 1); return x; } @@ -541,15 +767,15 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } -static target_long assemble_12(uint32_t insn) +static target_sreg assemble_12(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 1) | extract32(insn, 2, 1); x = (x << 10) | extract32(insn, 3, 10); return x; } -static target_long assemble_16(uint32_t insn) +static target_sreg assemble_16(uint32_t insn) { /* Take the name from PA2.0, which produces a 16-bit number only with wide mode; otherwise a 14-bit number. Since we don't @@ -557,28 +783,28 @@ static target_long assemble_16(uint32_t insn) return low_sextract(insn, 0, 14); } -static target_long assemble_16a(uint32_t insn) +static target_sreg assemble_16a(uint32_t insn) { /* Take the name from PA2.0, which produces a 14-bit shifted number only with wide mode; otherwise a 12-bit shifted number. Since we don't implement wide mode, this is always the 12-bit number. */ - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 11) | extract32(insn, 2, 11); return x << 2; } -static target_long assemble_17(uint32_t insn) +static target_sreg assemble_17(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 5) | extract32(insn, 16, 5); x = (x << 1) | extract32(insn, 2, 1); x = (x << 10) | extract32(insn, 3, 10); return x << 2; } -static target_long assemble_21(uint32_t insn) +static target_sreg assemble_21(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 11) | extract32(insn, 1, 11); x = (x << 2) | extract32(insn, 14, 2); x = (x << 5) | extract32(insn, 16, 5); @@ -586,9 +812,9 @@ static target_long assemble_21(uint32_t insn) return x << 11; } -static target_long assemble_22(uint32_t insn) +static target_sreg assemble_22(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 10) | extract32(insn, 16, 10); x = (x << 1) | extract32(insn, 2, 1); x = (x << 10) | extract32(insn, 3, 10); @@ -602,10 +828,10 @@ static target_long assemble_22(uint32_t insn) as a whole it would appear that these relations are similar to what a traditional NZCV set of flags would produce. */ -static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) +static DisasCond do_cond(unsigned cf, TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) { DisasCond cond; - TCGv tmp; + TCGv_reg tmp; switch (cf >> 1) { case 0: /* Never / TR */ @@ -625,8 +851,8 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp = tcg_temp_new(); - tcg_gen_neg_tl(tmp, cb_msb); - tcg_gen_and_tl(tmp, tmp, res); + tcg_gen_neg_reg(tmp, cb_msb); + tcg_gen_and_reg(tmp, tmp, res); cond = cond_make_0(TCG_COND_EQ, tmp); tcg_temp_free(tmp); break; @@ -635,7 +861,7 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) break; case 7: /* OD / EV */ tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, res, 1); + tcg_gen_andi_reg(tmp, res, 1); cond = cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; @@ -653,7 +879,7 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) can use the inputs directly. This can allow other computation to be deleted as unused. */ -static DisasCond do_sub_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2, TCGv sv) +static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) { DisasCond cond; @@ -686,7 +912,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2, TCGv sv) /* Similar, but for logicals, where the carry and overflow bits are not computed, and use of them is undefined. */ -static DisasCond do_log_cond(unsigned cf, TCGv res) +static DisasCond do_log_cond(unsigned cf, TCGv_reg res) { switch (cf >> 1) { case 4: case 5: case 6: @@ -698,7 +924,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv res) /* Similar, but for shift/extract/deposit conditions. */ -static DisasCond do_sed_cond(unsigned orig, TCGv res) +static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) { unsigned c, f; @@ -716,10 +942,10 @@ static DisasCond do_sed_cond(unsigned orig, TCGv res) /* Similar, but for unit conditions. */ -static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) +static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { DisasCond cond; - TCGv tmp, cb = NULL; + TCGv_reg tmp, cb = NULL; if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not @@ -728,10 +954,10 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) */ cb = tcg_temp_new(); tmp = tcg_temp_new(); - tcg_gen_or_tl(cb, in1, in2); - tcg_gen_and_tl(tmp, in1, in2); - tcg_gen_andc_tl(cb, cb, res); - tcg_gen_or_tl(cb, cb, tmp); + tcg_gen_or_reg(cb, in1, in2); + tcg_gen_and_reg(tmp, in1, in2); + tcg_gen_andc_reg(cb, cb, res); + tcg_gen_or_reg(cb, cb, tmp); tcg_temp_free(tmp); } @@ -747,34 +973,34 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ tmp = tcg_temp_new(); - tcg_gen_subi_tl(tmp, res, 0x01010101u); - tcg_gen_andc_tl(tmp, tmp, res); - tcg_gen_andi_tl(tmp, tmp, 0x80808080u); + tcg_gen_subi_reg(tmp, res, 0x01010101u); + tcg_gen_andc_reg(tmp, tmp, res); + tcg_gen_andi_reg(tmp, tmp, 0x80808080u); cond = cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; case 3: /* SHZ / NHZ */ tmp = tcg_temp_new(); - tcg_gen_subi_tl(tmp, res, 0x00010001u); - tcg_gen_andc_tl(tmp, tmp, res); - tcg_gen_andi_tl(tmp, tmp, 0x80008000u); + tcg_gen_subi_reg(tmp, res, 0x00010001u); + tcg_gen_andc_reg(tmp, tmp, res); + tcg_gen_andi_reg(tmp, tmp, 0x80008000u); cond = cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; case 4: /* SDC / NDC */ - tcg_gen_andi_tl(cb, cb, 0x88888888u); + tcg_gen_andi_reg(cb, cb, 0x88888888u); cond = cond_make_0(TCG_COND_NE, cb); break; case 6: /* SBC / NBC */ - tcg_gen_andi_tl(cb, cb, 0x80808080u); + tcg_gen_andi_reg(cb, cb, 0x80808080u); cond = cond_make_0(TCG_COND_NE, cb); break; case 7: /* SHC / NHC */ - tcg_gen_andi_tl(cb, cb, 0x80008000u); + tcg_gen_andi_reg(cb, cb, 0x80008000u); cond = cond_make_0(TCG_COND_NE, cb); break; @@ -792,38 +1018,38 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) } /* Compute signed overflow for addition. */ -static TCGv do_add_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2) +static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { - TCGv sv = get_temp(ctx); - TCGv tmp = tcg_temp_new(); + TCGv_reg sv = get_temp(ctx); + TCGv_reg tmp = tcg_temp_new(); - tcg_gen_xor_tl(sv, res, in1); - tcg_gen_xor_tl(tmp, in1, in2); - tcg_gen_andc_tl(sv, sv, tmp); + tcg_gen_xor_reg(sv, res, in1); + tcg_gen_xor_reg(tmp, in1, in2); + tcg_gen_andc_reg(sv, sv, tmp); tcg_temp_free(tmp); return sv; } /* Compute signed overflow for subtraction. */ -static TCGv do_sub_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2) +static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { - TCGv sv = get_temp(ctx); - TCGv tmp = tcg_temp_new(); + TCGv_reg sv = get_temp(ctx); + TCGv_reg tmp = tcg_temp_new(); - tcg_gen_xor_tl(sv, res, in1); - tcg_gen_xor_tl(tmp, in1, in2); - tcg_gen_and_tl(sv, sv, tmp); + tcg_gen_xor_reg(sv, res, in1); + tcg_gen_xor_reg(tmp, in1, in2); + tcg_gen_and_reg(sv, sv, tmp); tcg_temp_free(tmp); return sv; } -static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, +static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf) { - TCGv dest, cb, cb_msb, sv, tmp; + TCGv_reg dest, cb, cb_msb, sv, tmp; unsigned c = cf >> 1; DisasCond cond; @@ -833,27 +1059,27 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, if (shift) { tmp = get_temp(ctx); - tcg_gen_shli_tl(tmp, in1, shift); + tcg_gen_shli_reg(tmp, in1, shift); in1 = tmp; } if (!is_l || c == 4 || c == 5) { - TCGv zero = tcg_const_tl(0); + TCGv_reg zero = tcg_const_reg(0); cb_msb = get_temp(ctx); - tcg_gen_add2_tl(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { - tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); } tcg_temp_free(zero); if (!is_l) { cb = get_temp(ctx); - tcg_gen_xor_tl(cb, in1, in2); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_xor_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); } } else { - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); if (is_c) { - tcg_gen_add_tl(dest, dest, cpu_psw_cb_msb); + tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); } } @@ -872,7 +1098,7 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, if (is_tc) { cond_prep(&cond); tmp = tcg_temp_new(); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -891,10 +1117,10 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } -static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, +static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf) { - TCGv dest, sv, cb, cb_msb, zero, tmp; + TCGv_reg dest, sv, cb, cb_msb, zero, tmp; unsigned c = cf >> 1; DisasCond cond; @@ -902,21 +1128,21 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, cb = tcg_temp_new(); cb_msb = tcg_temp_new(); - zero = tcg_const_tl(0); + zero = tcg_const_reg(0); if (is_b) { /* DEST,C = IN1 + ~IN2 + C. */ - tcg_gen_not_tl(cb, in2); - tcg_gen_add2_tl(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); - tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cb, zero); - tcg_gen_xor_tl(cb, cb, in1); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_not_reg(cb, in2); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_xor_reg(cb, cb, in1); + tcg_gen_xor_reg(cb, cb, dest); } else { /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer operations by seeding the high word with 1 and subtracting. */ - tcg_gen_movi_tl(cb_msb, 1); - tcg_gen_sub2_tl(dest, cb_msb, in1, cb_msb, in2, zero); - tcg_gen_eqv_tl(cb, in1, in2); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_movi_reg(cb_msb, 1); + tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); + tcg_gen_eqv_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); } tcg_temp_free(zero); @@ -940,7 +1166,7 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, if (is_tc) { cond_prep(&cond); tmp = tcg_temp_new(); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -957,14 +1183,14 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } -static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf) +static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned cf) { - TCGv dest, sv; + TCGv_reg dest, sv; DisasCond cond; dest = tcg_temp_new(); - tcg_gen_sub_tl(dest, in1, in2); + tcg_gen_sub_reg(dest, in1, in2); /* Compute signed overflow if required. */ sv = NULL; @@ -976,7 +1202,7 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, cond = do_sub_cond(cf, dest, in1, in2, sv); /* Clear. */ - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); tcg_temp_free(dest); @@ -986,10 +1212,10 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, return DISAS_NEXT; } -static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, - unsigned cf, void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, + unsigned cf, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { - TCGv dest = dest_gpr(ctx, rt); + TCGv_reg dest = dest_gpr(ctx, rt); /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1003,11 +1229,11 @@ static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } -static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf, bool is_tc, - void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned cf, bool is_tc, + void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { - TCGv dest; + TCGv_reg dest; DisasCond cond; if (cf == 0) { @@ -1022,9 +1248,9 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, cond = do_unit_cond(cf, dest, in1, in2); if (is_tc) { - TCGv tmp = tcg_temp_new(); + TCGv_reg tmp = tcg_temp_new(); cond_prep(&cond); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -1042,10 +1268,10 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, * = 0 for no base register update. */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1055,10 +1281,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } if (modify == 0) { @@ -1072,10 +1298,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, } static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1085,10 +1311,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } if (modify == 0) { @@ -1102,10 +1328,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, } static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1115,10 +1341,10 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); @@ -1130,10 +1356,10 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, } static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1143,10 +1369,10 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); @@ -1157,19 +1383,19 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, tcg_temp_free(addr); } -#if TARGET_LONG_BITS == 64 -#define do_load_tl do_load_64 -#define do_store_tl do_store_64 +#if TARGET_REGISTER_BITS == 64 +#define do_load_reg do_load_64 +#define do_store_reg do_store_64 #else -#define do_load_tl do_load_32 -#define do_store_tl do_store_32 +#define do_load_reg do_load_32 +#define do_store_reg do_store_32 #endif static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv dest; + TCGv_reg dest; nullify_over(ctx); @@ -1180,14 +1406,14 @@ static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, /* Make sure if RT == RB, we see the result of the load. */ dest = get_temp(ctx); } - do_load_tl(ctx, dest, rb, rx, scale, disp, modify, mop); + do_load_reg(ctx, dest, rb, rx, scale, disp, modify, mop); save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i32 tmp; @@ -1207,7 +1433,7 @@ static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i64 tmp; @@ -1227,15 +1453,15 @@ static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_long disp, int modify, TCGMemOp mop) + target_sreg disp, int modify, TCGMemOp mop) { nullify_over(ctx); - do_store_tl(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); + do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i32 tmp; @@ -1250,7 +1476,7 @@ static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i64 tmp; @@ -1370,7 +1596,7 @@ static DisasJumpType do_fop_dedd(DisasContext *ctx, unsigned rt, /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static DisasJumpType do_dbranch(DisasContext *ctx, target_ulong dest, +static DisasJumpType do_dbranch(DisasContext *ctx, target_ureg dest, unsigned link, bool is_n) { if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { @@ -1407,10 +1633,10 @@ static DisasJumpType do_dbranch(DisasContext *ctx, target_ulong dest, /* Emit a conditional branch to a direct target. If the branch itself is nullified, we should have already used nullify_over. */ -static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool is_n, +static DisasJumpType do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, DisasCond *cond) { - target_ulong dest = iaoq_dest(ctx, disp); + target_ureg dest = iaoq_dest(ctx, disp); TCGLabel *taken = NULL; TCGCond c = cond->c; bool n; @@ -1427,7 +1653,7 @@ static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool is_n, taken = gen_new_label(); cond_prep(cond); - tcg_gen_brcond_tl(c, cond->a0, cond->a1, taken); + tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); cond_free(cond); /* Not taken: Condition not satisfied; nullify on backward branches. */ @@ -1468,10 +1694,10 @@ static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool is_n, /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, +static DisasJumpType do_ibranch(DisasContext *ctx, TCGv_reg dest, unsigned link, bool is_n) { - TCGv a0, a1, next, tmp; + TCGv_reg a0, a1, next, tmp; TCGCond c; assert(ctx->null_lab == NULL); @@ -1481,7 +1707,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } next = get_temp(ctx); - tcg_gen_mov_tl(next, dest); + tcg_gen_mov_reg(next, dest); ctx->iaoq_n = -1; ctx->iaoq_n_var = next; if (is_n) { @@ -1500,12 +1726,12 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, /* We do have to handle the non-local temporary, DEST, before branching. Since IOAQ_F is not really live at this point, we can simply store DEST optimistically. Similarly with IAOQ_B. */ - tcg_gen_mov_tl(cpu_iaoq_f, dest); - tcg_gen_addi_tl(cpu_iaoq_b, dest, 4); + tcg_gen_mov_reg(cpu_iaoq_f, dest); + tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); nullify_over(ctx); if (link != 0) { - tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); + tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); } tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, DISAS_NEXT); @@ -1519,19 +1745,19 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, next = get_temp(ctx); copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_tl(c, next, a0, a1, tmp, dest); + tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); ctx->iaoq_n = -1; ctx->iaoq_n_var = next; if (link != 0) { - tcg_gen_movcond_tl(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); + tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); } if (is_n) { /* The branch nullifies the next insn, which means the state of N after the branch is the inverse of the state of N that applied to the branch. */ - tcg_gen_setcond_tl(tcg_invert_cond(c), cpu_psw_n, a0, a1); + tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); cond_free(&ctx->null_cond); ctx->null_cond = cond_make_n(); ctx->psw_n_nonzero = true; @@ -1560,7 +1786,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) case TCG_COND_NEVER: break; case TCG_COND_ALWAYS: - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); goto do_sigill; default: /* Since this is always the first (and only) insn within the @@ -1586,9 +1812,9 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_mov_tl(cpu_cr27, cpu_gr[26]); - tcg_gen_mov_tl(cpu_iaoq_f, cpu_gr[31]); - tcg_gen_addi_tl(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_reg(cpu_cr27, cpu_gr[26]); + tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); + tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; case 0x100: /* SYSCALL */ @@ -1631,8 +1857,8 @@ static DisasJumpType trans_mfia(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv tmp = dest_gpr(ctx, rt); - tcg_gen_movi_tl(tmp, ctx->iaoq_f); + TCGv_reg tmp = dest_gpr(ctx, rt); + tcg_gen_movi_reg(tmp, ctx->iaoq_f); save_gpr(ctx, rt, tmp); cond_free(&ctx->null_cond); @@ -1643,10 +1869,10 @@ static DisasJumpType trans_mfsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv tmp = dest_gpr(ctx, rt); + TCGv_reg tmp = dest_gpr(ctx, rt); /* ??? We don't implement space registers. */ - tcg_gen_movi_tl(tmp, 0); + tcg_gen_movi_reg(tmp, 0); save_gpr(ctx, rt, tmp); cond_free(&ctx->null_cond); @@ -1658,7 +1884,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, { unsigned rt = extract32(insn, 0, 5); unsigned ctl = extract32(insn, 21, 5); - TCGv tmp; + TCGv_reg tmp; switch (ctl) { case 11: /* SAR */ @@ -1666,7 +1892,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, if (extract32(insn, 14, 1) == 0) { /* MFSAR without ,W masks low 5 bits. */ tmp = dest_gpr(ctx, rt); - tcg_gen_andi_tl(tmp, cpu_sar, 31); + tcg_gen_andi_reg(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); break; } @@ -1698,11 +1924,11 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, { unsigned rin = extract32(insn, 16, 5); unsigned ctl = extract32(insn, 21, 5); - TCGv tmp; + TCGv_reg tmp; if (ctl == 11) { /* SAR */ tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, load_gpr(ctx, rin), TARGET_LONG_BITS - 1); + tcg_gen_andi_reg(tmp, load_gpr(ctx, rin), TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); } else { @@ -1718,10 +1944,10 @@ static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rin = extract32(insn, 16, 5); - TCGv tmp = tcg_temp_new(); + TCGv_reg tmp = tcg_temp_new(); - tcg_gen_not_tl(tmp, load_gpr(ctx, rin)); - tcg_gen_andi_tl(tmp, tmp, TARGET_LONG_BITS - 1); + tcg_gen_not_reg(tmp, load_gpr(ctx, rin)); + tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); @@ -1733,10 +1959,10 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv dest = dest_gpr(ctx, rt); + TCGv_reg dest = dest_gpr(ctx, rt); /* Since we don't implement space registers, this returns zero. */ - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); cond_free(&ctx->null_cond); @@ -1761,12 +1987,12 @@ static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rx = extract32(insn, 16, 5); - TCGv dest = dest_gpr(ctx, rb); - TCGv src1 = load_gpr(ctx, rb); - TCGv src2 = load_gpr(ctx, rx); + TCGv_reg dest = dest_gpr(ctx, rb); + TCGv_reg src1 = load_gpr(ctx, rb); + TCGv_reg src2 = load_gpr(ctx, rx); /* The only thing we need to do is the base register modification. */ - tcg_gen_add_tl(dest, src1, src2); + tcg_gen_add_reg(dest, src1, src2); save_gpr(ctx, rb, dest); cond_free(&ctx->null_cond); @@ -1779,7 +2005,7 @@ static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); unsigned rb = extract32(insn, 21, 5); unsigned is_write = extract32(insn, 6, 1); - TCGv dest; + TCGv_reg dest; nullify_over(ctx); @@ -1821,7 +2047,7 @@ static DisasJumpType trans_add(DisasContext *ctx, uint32_t insn, unsigned ext = extract32(insn, 8, 4); unsigned shift = extract32(insn, 6, 2); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; bool is_c = false; bool is_l = false; bool is_tc = false; @@ -1864,7 +2090,7 @@ static DisasJumpType trans_sub(DisasContext *ctx, uint32_t insn, unsigned cf = extract32(insn, 12, 4); unsigned ext = extract32(insn, 6, 6); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; bool is_b = false; bool is_tc = false; bool is_tsv = false; @@ -1908,7 +2134,7 @@ static DisasJumpType trans_log(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; if (cf) { @@ -1928,8 +2154,8 @@ static DisasJumpType trans_copy(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); if (r1 == 0) { - TCGv dest = dest_gpr(ctx, rt); - tcg_gen_movi_tl(dest, 0); + TCGv_reg dest = dest_gpr(ctx, rt); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); } else { save_gpr(ctx, rt, cpu_gr[r1]); @@ -1945,7 +2171,7 @@ static DisasJumpType trans_cmpclr(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; if (cf) { @@ -1964,7 +2190,7 @@ static DisasJumpType trans_uxor(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; if (cf) { @@ -1972,7 +2198,7 @@ static DisasJumpType trans_uxor(DisasContext *ctx, uint32_t insn, } tcg_r1 = load_gpr(ctx, r1); tcg_r2 = load_gpr(ctx, r2); - ret = do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_tl); + ret = do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_reg); return nullify_end(ctx, ret); } @@ -1984,7 +2210,7 @@ static DisasJumpType trans_uaddcm(DisasContext *ctx, uint32_t insn, unsigned cf = extract32(insn, 12, 4); unsigned is_tc = extract32(insn, 6, 1); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2, tmp; + TCGv_reg tcg_r1, tcg_r2, tmp; DisasJumpType ret; if (cf) { @@ -1993,8 +2219,8 @@ static DisasJumpType trans_uaddcm(DisasContext *ctx, uint32_t insn, tcg_r1 = load_gpr(ctx, r1); tcg_r2 = load_gpr(ctx, r2); tmp = get_temp(ctx); - tcg_gen_not_tl(tmp, tcg_r2); - ret = do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_tl); + tcg_gen_not_reg(tmp, tcg_r2); + ret = do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_reg); return nullify_end(ctx, ret); } @@ -2005,20 +2231,20 @@ static DisasJumpType trans_dcor(DisasContext *ctx, uint32_t insn, unsigned cf = extract32(insn, 12, 4); unsigned is_i = extract32(insn, 6, 1); unsigned rt = extract32(insn, 0, 5); - TCGv tmp; + TCGv_reg tmp; DisasJumpType ret; nullify_over(ctx); tmp = get_temp(ctx); - tcg_gen_shri_tl(tmp, cpu_psw_cb, 3); + tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); if (!is_i) { - tcg_gen_not_tl(tmp, tmp); + tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_tl(tmp, tmp, 0x11111111); - tcg_gen_muli_tl(tmp, tmp, 6); + tcg_gen_andi_reg(tmp, tmp, 0x11111111); + tcg_gen_muli_reg(tmp, tmp, 6); ret = do_unit(ctx, rt, tmp, load_gpr(ctx, r2), cf, false, - is_i ? tcg_gen_add_tl : tcg_gen_sub_tl); + is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); return nullify_end(ctx, ret); } @@ -2030,7 +2256,7 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv dest, add1, add2, addc, zero, in1, in2; + TCGv_reg dest, add1, add2, addc, zero, in1, in2; nullify_over(ctx); @@ -2041,19 +2267,19 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, add2 = tcg_temp_new(); addc = tcg_temp_new(); dest = tcg_temp_new(); - zero = tcg_const_tl(0); + zero = tcg_const_reg(0); /* Form R1 << 1 | PSW[CB]{8}. */ - tcg_gen_add_tl(add1, in1, in1); - tcg_gen_add_tl(add1, add1, cpu_psw_cb_msb); + tcg_gen_add_reg(add1, in1, in1); + tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); /* Add or subtract R2, depending on PSW[V]. Proper computation of carry{8} requires that we subtract via + ~R2 + 1, as described in the manual. By extracting and masking V, we can produce the proper inputs to the addition without movcond. */ - tcg_gen_sari_tl(addc, cpu_psw_v, TARGET_LONG_BITS - 1); - tcg_gen_xor_tl(add2, in2, addc); - tcg_gen_andi_tl(addc, addc, 1); + tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); + tcg_gen_xor_reg(add2, in2, addc); + tcg_gen_andi_reg(addc, addc, 1); /* ??? This is only correct for 32-bit. */ tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); @@ -2065,16 +2291,16 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, save_gpr(ctx, rt, dest); /* Write back PSW[CB]. */ - tcg_gen_xor_tl(cpu_psw_cb, add1, add2); - tcg_gen_xor_tl(cpu_psw_cb, cpu_psw_cb, dest); + tcg_gen_xor_reg(cpu_psw_cb, add1, add2); + tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); /* Write back PSW[V] for the division step. */ - tcg_gen_neg_tl(cpu_psw_v, cpu_psw_cb_msb); - tcg_gen_xor_tl(cpu_psw_v, cpu_psw_v, in2); + tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); + tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); /* Install the new nullification. */ if (cf) { - TCGv sv = NULL; + TCGv_reg sv = NULL; if (cf >> 1 == 6) { /* ??? The lshift is supposed to contribute to overflow. */ sv = do_add_sv(ctx, dest, add1, add2); @@ -2092,10 +2318,10 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, static const DisasInsn table_arith_log[] = { { 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */ { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */ - { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_tl }, - { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_tl }, - { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_tl }, - { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_xor_tl }, + { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_reg }, + { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_reg }, + { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_reg }, + { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_xor_reg }, { 0x08000880u, 0xfc000fe0u, trans_cmpclr }, { 0x08000380u, 0xfc000fe0u, trans_uxor }, { 0x08000980u, 0xfc000fa0u, trans_uaddcm }, @@ -2109,13 +2335,13 @@ static const DisasInsn table_arith_log[] = { static DisasJumpType trans_addi(DisasContext *ctx, uint32_t insn) { - target_long im = low_sextract(insn, 0, 11); + target_sreg im = low_sextract(insn, 0, 11); unsigned e1 = extract32(insn, 11, 1); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); unsigned o1 = extract32(insn, 26, 1); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; if (cf) { @@ -2131,12 +2357,12 @@ static DisasJumpType trans_addi(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_subi(DisasContext *ctx, uint32_t insn) { - target_long im = low_sextract(insn, 0, 11); + target_sreg im = low_sextract(insn, 0, 11); unsigned e1 = extract32(insn, 11, 1); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; if (cf) { @@ -2152,11 +2378,11 @@ static DisasJumpType trans_subi(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_cmpiclr(DisasContext *ctx, uint32_t insn) { - target_long im = low_sextract(insn, 0, 11); + target_sreg im = low_sextract(insn, 0, 11); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; if (cf) { @@ -2224,7 +2450,7 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); TCGMemOp mop = MO_TEUL | MO_ALIGN_16; - TCGv zero, addr, base, dest; + TCGv_reg zero, addr, base, dest; int modify, disp = 0, scale = 0; nullify_over(ctx); @@ -2252,15 +2478,15 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, addr = tcg_temp_new(); base = load_gpr(ctx, rb); if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } - zero = tcg_const_tl(0); - tcg_gen_atomic_xchg_tl(dest, (modify <= 0 ? addr : base), - zero, MMU_USER_IDX, mop); + zero = tcg_const_reg(0); + tcg_gen_atomic_xchg_reg(dest, (modify <= 0 ? addr : base), + zero, MMU_USER_IDX, mop); if (modify) { save_gpr(ctx, rb, addr); } @@ -2272,20 +2498,20 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { - target_long disp = low_sextract(insn, 0, 5); + target_sreg disp = low_sextract(insn, 0, 5); unsigned m = extract32(insn, 5, 1); unsigned a = extract32(insn, 13, 1); unsigned rt = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); - TCGv addr, val; + TCGv_reg addr, val; nullify_over(ctx); addr = tcg_temp_new(); if (m || disp == 0) { - tcg_gen_mov_tl(addr, load_gpr(ctx, rb)); + tcg_gen_mov_reg(addr, load_gpr(ctx, rb)); } else { - tcg_gen_addi_tl(addr, load_gpr(ctx, rb), disp); + tcg_gen_addi_reg(addr, load_gpr(ctx, rb), disp); } val = load_gpr(ctx, rt); @@ -2304,8 +2530,8 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, } if (m) { - tcg_gen_addi_tl(addr, addr, disp); - tcg_gen_andi_tl(addr, addr, ~3); + tcg_gen_addi_reg(addr, addr, disp); + tcg_gen_andi_reg(addr, addr, ~3); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -2324,10 +2550,10 @@ static const DisasInsn table_index_mem[] = { static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) { unsigned rt = extract32(insn, 21, 5); - target_long i = assemble_21(insn); - TCGv tcg_rt = dest_gpr(ctx, rt); + target_sreg i = assemble_21(insn); + TCGv_reg tcg_rt = dest_gpr(ctx, rt); - tcg_gen_movi_tl(tcg_rt, i); + tcg_gen_movi_reg(tcg_rt, i); save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); @@ -2337,11 +2563,11 @@ static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_addil(DisasContext *ctx, uint32_t insn) { unsigned rt = extract32(insn, 21, 5); - target_long i = assemble_21(insn); - TCGv tcg_rt = load_gpr(ctx, rt); - TCGv tcg_r1 = dest_gpr(ctx, 1); + target_sreg i = assemble_21(insn); + TCGv_reg tcg_rt = load_gpr(ctx, rt); + TCGv_reg tcg_r1 = dest_gpr(ctx, 1); - tcg_gen_addi_tl(tcg_r1, tcg_rt, i); + tcg_gen_addi_reg(tcg_r1, tcg_rt, i); save_gpr(ctx, 1, tcg_r1); cond_free(&ctx->null_cond); @@ -2352,15 +2578,15 @@ static DisasJumpType trans_ldo(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16(insn); - TCGv tcg_rt = dest_gpr(ctx, rt); + target_sreg i = assemble_16(insn); + TCGv_reg tcg_rt = dest_gpr(ctx, rt); /* Special case rb == 0, for the LDI pseudo-op. The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ if (rb == 0) { - tcg_gen_movi_tl(tcg_rt, i); + tcg_gen_movi_reg(tcg_rt, i); } else { - tcg_gen_addi_tl(tcg_rt, cpu_gr[rb], i); + tcg_gen_addi_reg(tcg_rt, cpu_gr[rb], i); } save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); @@ -2373,7 +2599,7 @@ static DisasJumpType trans_load(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16(insn); + target_sreg i = assemble_16(insn); return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } @@ -2382,7 +2608,7 @@ static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); switch (ext2) { @@ -2401,7 +2627,7 @@ static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_fload_mod(DisasContext *ctx, uint32_t insn) { - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); unsigned t0 = extract32(insn, 16, 5); @@ -2416,7 +2642,7 @@ static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16(insn); + target_sreg i = assemble_16(insn); return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } @@ -2425,7 +2651,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); switch (ext2) { @@ -2443,7 +2669,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_fstore_mod(DisasContext *ctx, uint32_t insn) { - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); unsigned t0 = extract32(insn, 16, 5); @@ -2525,12 +2751,12 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, bool is_true, bool is_imm, bool is_dw) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 13, 3); unsigned r = extract32(insn, 21, 5); unsigned cf = c * 2 + !is_true; - TCGv dest, in1, in2, sv; + TCGv_reg dest, in1, in2, sv; DisasCond cond; nullify_over(ctx); @@ -2543,7 +2769,7 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, in2 = load_gpr(ctx, r); dest = get_temp(ctx); - tcg_gen_sub_tl(dest, in1, in2); + tcg_gen_sub_reg(dest, in1, in2); sv = NULL; if (c == 6) { @@ -2557,12 +2783,12 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, bool is_true, bool is_imm) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 13, 3); unsigned r = extract32(insn, 21, 5); unsigned cf = c * 2 + !is_true; - TCGv dest, in1, in2, sv, cb_msb; + TCGv_reg dest, in1, in2, sv, cb_msb; DisasCond cond; nullify_over(ctx); @@ -2579,15 +2805,15 @@ static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, switch (c) { default: - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); break; case 4: case 5: cb_msb = get_temp(ctx); - tcg_gen_movi_tl(cb_msb, 0); - tcg_gen_add2_tl(dest, cb_msb, in1, cb_msb, in2, cb_msb); + tcg_gen_movi_reg(cb_msb, 0); + tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); break; case 6: - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); sv = do_add_sv(ctx, dest, in1, in2); break; } @@ -2598,13 +2824,13 @@ static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 15, 1); unsigned r = extract32(insn, 16, 5); unsigned p = extract32(insn, 21, 5); unsigned i = extract32(insn, 26, 1); - TCGv tmp, tcg_r; + TCGv_reg tmp, tcg_r; DisasCond cond; nullify_over(ctx); @@ -2612,9 +2838,9 @@ static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) tmp = tcg_temp_new(); tcg_r = load_gpr(ctx, r); if (i) { - tcg_gen_shli_tl(tmp, tcg_r, p); + tcg_gen_shli_reg(tmp, tcg_r, p); } else { - tcg_gen_shl_tl(tmp, tcg_r, cpu_sar); + tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); } cond = cond_make_0(c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -2624,23 +2850,23 @@ static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_movb(DisasContext *ctx, uint32_t insn, bool is_imm) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 13, 3); unsigned t = extract32(insn, 16, 5); unsigned r = extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; DisasCond cond; nullify_over(ctx); dest = dest_gpr(ctx, r); if (is_imm) { - tcg_gen_movi_tl(dest, low_sextract(t, 0, 5)); + tcg_gen_movi_reg(dest, low_sextract(t, 0, 5)); } else if (t == 0) { - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); } else { - tcg_gen_mov_tl(dest, cpu_gr[t]); + tcg_gen_mov_reg(dest, cpu_gr[t]); } cond = do_sed_cond(c, dest); @@ -2654,7 +2880,7 @@ static DisasJumpType trans_shrpw_sar(DisasContext *ctx, uint32_t insn, unsigned c = extract32(insn, 13, 3); unsigned r1 = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; if (c) { nullify_over(ctx); @@ -2662,22 +2888,22 @@ static DisasJumpType trans_shrpw_sar(DisasContext *ctx, uint32_t insn, dest = dest_gpr(ctx, rt); if (r1 == 0) { - tcg_gen_ext32u_tl(dest, load_gpr(ctx, r2)); - tcg_gen_shr_tl(dest, dest, cpu_sar); + tcg_gen_ext32u_reg(dest, load_gpr(ctx, r2)); + tcg_gen_shr_reg(dest, dest, cpu_sar); } else if (r1 == r2) { TCGv_i32 t32 = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t32, load_gpr(ctx, r2)); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, r2)); tcg_gen_rotr_i32(t32, t32, cpu_sar); - tcg_gen_extu_i32_tl(dest, t32); + tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); } else { TCGv_i64 t = tcg_temp_new_i64(); TCGv_i64 s = tcg_temp_new_i64(); - tcg_gen_concat_tl_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); - tcg_gen_extu_tl_i64(s, cpu_sar); + tcg_gen_concat_reg_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); + tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_shr_i64(t, t, s); - tcg_gen_trunc_i64_tl(dest, t); + tcg_gen_trunc_i64_reg(dest, t); tcg_temp_free_i64(t); tcg_temp_free_i64(s); @@ -2701,7 +2927,7 @@ static DisasJumpType trans_shrpw_imm(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); unsigned sa = 31 - cpos; - TCGv dest, t2; + TCGv_reg dest, t2; if (c) { nullify_over(ctx); @@ -2711,16 +2937,16 @@ static DisasJumpType trans_shrpw_imm(DisasContext *ctx, uint32_t insn, t2 = load_gpr(ctx, r2); if (r1 == r2) { TCGv_i32 t32 = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t32, t2); + tcg_gen_trunc_reg_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_tl(dest, t32); + tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); } else if (r1 == 0) { - tcg_gen_extract_tl(dest, t2, sa, 32 - sa); + tcg_gen_extract_reg(dest, t2, sa, 32 - sa); } else { - TCGv t0 = tcg_temp_new(); - tcg_gen_extract_tl(t0, t2, sa, 32 - sa); - tcg_gen_deposit_tl(dest, t0, cpu_gr[r1], 32 - sa, sa); + TCGv_reg t0 = tcg_temp_new(); + tcg_gen_extract_reg(t0, t2, sa, 32 - sa); + tcg_gen_deposit_reg(dest, t0, cpu_gr[r1], 32 - sa, sa); tcg_temp_free(t0); } save_gpr(ctx, rt, dest); @@ -2742,7 +2968,7 @@ static DisasJumpType trans_extrw_sar(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 16, 5); unsigned rr = extract32(insn, 21, 5); unsigned len = 32 - clen; - TCGv dest, src, tmp; + TCGv_reg dest, src, tmp; if (c) { nullify_over(ctx); @@ -2753,13 +2979,13 @@ static DisasJumpType trans_extrw_sar(DisasContext *ctx, uint32_t insn, tmp = tcg_temp_new(); /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_xori_tl(tmp, cpu_sar, TARGET_LONG_BITS - 1); + tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); if (is_se) { - tcg_gen_sar_tl(dest, src, tmp); - tcg_gen_sextract_tl(dest, dest, 0, len); + tcg_gen_sar_reg(dest, src, tmp); + tcg_gen_sextract_reg(dest, dest, 0, len); } else { - tcg_gen_shr_tl(dest, src, tmp); - tcg_gen_extract_tl(dest, dest, 0, len); + tcg_gen_shr_reg(dest, src, tmp); + tcg_gen_extract_reg(dest, dest, 0, len); } tcg_temp_free(tmp); save_gpr(ctx, rt, dest); @@ -2783,7 +3009,7 @@ static DisasJumpType trans_extrw_imm(DisasContext *ctx, uint32_t insn, unsigned rr = extract32(insn, 21, 5); unsigned len = 32 - clen; unsigned cpos = 31 - pos; - TCGv dest, src; + TCGv_reg dest, src; if (c) { nullify_over(ctx); @@ -2792,9 +3018,9 @@ static DisasJumpType trans_extrw_imm(DisasContext *ctx, uint32_t insn, dest = dest_gpr(ctx, rt); src = load_gpr(ctx, rr); if (is_se) { - tcg_gen_sextract_tl(dest, src, cpos, len); + tcg_gen_sextract_reg(dest, src, cpos, len); } else { - tcg_gen_extract_tl(dest, src, cpos, len); + tcg_gen_extract_reg(dest, src, cpos, len); } save_gpr(ctx, rt, dest); @@ -2820,11 +3046,11 @@ static DisasJumpType trans_depw_imm_c(DisasContext *ctx, uint32_t insn, unsigned cpos = extract32(insn, 5, 5); unsigned nz = extract32(insn, 10, 1); unsigned c = extract32(insn, 13, 3); - target_long val = low_sextract(insn, 16, 5); + target_sreg val = low_sextract(insn, 16, 5); unsigned rt = extract32(insn, 21, 5); unsigned len = 32 - clen; - target_long mask0, mask1; - TCGv dest; + target_sreg mask0, mask1; + TCGv_reg dest; if (c) { nullify_over(ctx); @@ -2838,14 +3064,14 @@ static DisasJumpType trans_depw_imm_c(DisasContext *ctx, uint32_t insn, mask1 = deposit64(-1, cpos, len, val); if (nz) { - TCGv src = load_gpr(ctx, rt); + TCGv_reg src = load_gpr(ctx, rt); if (mask1 != -1) { - tcg_gen_andi_tl(dest, src, mask1); + tcg_gen_andi_reg(dest, src, mask1); src = dest; } - tcg_gen_ori_tl(dest, src, mask0); + tcg_gen_ori_reg(dest, src, mask0); } else { - tcg_gen_movi_tl(dest, mask0); + tcg_gen_movi_reg(dest, mask0); } save_gpr(ctx, rt, dest); @@ -2868,7 +3094,7 @@ static DisasJumpType trans_depw_imm(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 21, 5); unsigned rs = nz ? rt : 0; unsigned len = 32 - clen; - TCGv dest, val; + TCGv_reg dest, val; if (c) { nullify_over(ctx); @@ -2880,9 +3106,9 @@ static DisasJumpType trans_depw_imm(DisasContext *ctx, uint32_t insn, dest = dest_gpr(ctx, rt); val = load_gpr(ctx, rr); if (rs == 0) { - tcg_gen_deposit_z_tl(dest, val, cpos, len); + tcg_gen_deposit_z_reg(dest, val, cpos, len); } else { - tcg_gen_deposit_tl(dest, cpu_gr[rs], val, cpos, len); + tcg_gen_deposit_reg(dest, cpu_gr[rs], val, cpos, len); } save_gpr(ctx, rt, dest); @@ -2904,7 +3130,7 @@ static DisasJumpType trans_depw_sar(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 21, 5); unsigned rs = nz ? rt : 0; unsigned len = 32 - clen; - TCGv val, mask, tmp, shift, dest; + TCGv_reg val, mask, tmp, shift, dest; unsigned msb = 1U << (len - 1); if (c) { @@ -2921,17 +3147,17 @@ static DisasJumpType trans_depw_sar(DisasContext *ctx, uint32_t insn, tmp = tcg_temp_new(); /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_xori_tl(shift, cpu_sar, TARGET_LONG_BITS - 1); + tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); - mask = tcg_const_tl(msb + (msb - 1)); - tcg_gen_and_tl(tmp, val, mask); + mask = tcg_const_reg(msb + (msb - 1)); + tcg_gen_and_reg(tmp, val, mask); if (rs) { - tcg_gen_shl_tl(mask, mask, shift); - tcg_gen_shl_tl(tmp, tmp, shift); - tcg_gen_andc_tl(dest, cpu_gr[rs], mask); - tcg_gen_or_tl(dest, dest, tmp); + tcg_gen_shl_reg(mask, mask, shift); + tcg_gen_shl_reg(tmp, tmp, shift); + tcg_gen_andc_reg(dest, cpu_gr[rs], mask); + tcg_gen_or_reg(dest, dest, tmp); } else { - tcg_gen_shl_tl(dest, tmp, shift); + tcg_gen_shl_reg(dest, tmp, shift); } tcg_temp_free(shift); tcg_temp_free(mask); @@ -2956,7 +3182,7 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) { unsigned n = extract32(insn, 1, 1); unsigned b = extract32(insn, 21, 5); - target_long disp = assemble_17(insn); + target_sreg disp = assemble_17(insn); /* unsigned s = low_uextract(insn, 13, 3); */ /* ??? It seems like there should be a good way of using @@ -2971,8 +3197,8 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) if (b == 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); } else { - TCGv tmp = get_temp(ctx); - tcg_gen_addi_tl(tmp, load_gpr(ctx, b), disp); + TCGv_reg tmp = get_temp(ctx); + tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } } @@ -2982,7 +3208,7 @@ static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, { unsigned n = extract32(insn, 1, 1); unsigned link = extract32(insn, 21, 5); - target_long disp = assemble_17(insn); + target_sreg disp = assemble_17(insn); return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } @@ -2991,7 +3217,7 @@ static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned n = extract32(insn, 1, 1); - target_long disp = assemble_22(insn); + target_sreg disp = assemble_22(insn); return do_dbranch(ctx, iaoq_dest(ctx, disp), 2, n); } @@ -3002,10 +3228,10 @@ static DisasJumpType trans_blr(DisasContext *ctx, uint32_t insn, unsigned n = extract32(insn, 1, 1); unsigned rx = extract32(insn, 16, 5); unsigned link = extract32(insn, 21, 5); - TCGv tmp = get_temp(ctx); + TCGv_reg tmp = get_temp(ctx); - tcg_gen_shli_tl(tmp, load_gpr(ctx, rx), 3); - tcg_gen_addi_tl(tmp, tmp, ctx->iaoq_f + 8); + tcg_gen_shli_reg(tmp, load_gpr(ctx, rx), 3); + tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); return do_ibranch(ctx, tmp, link, n); } @@ -3015,14 +3241,14 @@ static DisasJumpType trans_bv(DisasContext *ctx, uint32_t insn, unsigned n = extract32(insn, 1, 1); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; if (rx == 0) { dest = load_gpr(ctx, rb); } else { dest = get_temp(ctx); - tcg_gen_shli_tl(dest, load_gpr(ctx, rx), 3); - tcg_gen_add_tl(dest, dest, load_gpr(ctx, rb)); + tcg_gen_shli_reg(dest, load_gpr(ctx, rx), 3); + tcg_gen_add_reg(dest, dest, load_gpr(ctx, rb)); } return do_ibranch(ctx, dest, 0, n); } @@ -3242,13 +3468,13 @@ static DisasJumpType trans_ftest_t(DisasContext *ctx, uint32_t insn, { unsigned y = extract32(insn, 13, 3); unsigned cbit = (y ^ 1) - 1; - TCGv t; + TCGv_reg t; nullify_over(ctx); t = tcg_temp_new(); - tcg_gen_ld32u_tl(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); - tcg_gen_extract_tl(t, t, 21 - cbit, 1); + tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_extract_reg(t, t, 21 - cbit, 1); ctx->null_cond = cond_make_0(TCG_COND_NE, t); tcg_temp_free(t); @@ -3261,16 +3487,16 @@ static DisasJumpType trans_ftest_q(DisasContext *ctx, uint32_t insn, unsigned c = extract32(insn, 0, 5); int mask; bool inv = false; - TCGv t; + TCGv_reg t; nullify_over(ctx); t = tcg_temp_new(); - tcg_gen_ld32u_tl(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); switch (c) { case 0: /* simple */ - tcg_gen_andi_tl(t, t, 0x4000000); + tcg_gen_andi_reg(t, t, 0x4000000); ctx->null_cond = cond_make_0(TCG_COND_NE, t); goto done; case 2: /* rej */ @@ -3298,11 +3524,11 @@ static DisasJumpType trans_ftest_q(DisasContext *ctx, uint32_t insn, return gen_illegal(ctx); } if (inv) { - TCGv c = load_const(ctx, mask); - tcg_gen_or_tl(t, t, c); + TCGv_reg c = load_const(ctx, mask); + tcg_gen_or_reg(t, t, c); ctx->null_cond = cond_make(TCG_COND_EQ, t, c); } else { - tcg_gen_andi_tl(t, t, mask); + tcg_gen_andi_reg(t, t, mask); ctx->null_cond = cond_make_0(TCG_COND_EQ, t); } done: @@ -3805,7 +4031,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) if (ctx->iaoq_b == -1) { ctx->iaoq_n = -1; ctx->iaoq_n_var = get_temp(ctx); - tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4); + tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n = ctx->iaoq_b + 4; ctx->iaoq_n_var = NULL; @@ -3849,12 +4075,12 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } if (ctx->iaoq_f == -1) { - tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); + tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); nullify_save(ctx); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; } else if (ctx->iaoq_b == -1) { - tcg_gen_mov_tl(cpu_iaoq_b, ctx->iaoq_n_var); + tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); } } @@ -3889,8 +4115,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { - TranslationBlock *tb = dcbase->tb; - target_ulong pc = tb->pc; + target_ureg pc = dcbase->pc_first; #ifdef CONFIG_USER_ONLY switch (pc) { @@ -3910,7 +4135,7 @@ static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) #endif qemu_log("IN: %s\n", lookup_symbol(pc)); - log_target_disas(cs, pc, tb->size); + log_target_disas(cs, pc, dcbase->tb->size); } static const TranslatorOps hppa_tr_ops = { From patchwork Mon Jan 22 03:41:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125295 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp944640ljf; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:40 -0800 Message-Id: <20180122034217.19593-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 06/43] target/hppa: Implement mmu_idx from IA privilege level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most aspects of privilege are not yet handled. But this gives us the start from which to begin checking. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 19 +++++++++++++---- target/hppa/cpu.c | 2 +- target/hppa/translate.c | 55 ++++++++++++++++++++++++++++++------------------- 3 files changed, 50 insertions(+), 26 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1524ef91b6..805c93db9c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -36,8 +36,10 @@ #define TARGET_PAGE_BITS 12 #define ALIGNED_ONLY -#define NB_MMU_MODES 1 -#define MMU_USER_IDX 0 +#define NB_MMU_MODES 5 +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 3 +#define MMU_PHYS_IDX 4 #define TARGET_INSN_START_EXTRA_WORDS 1 /* Hardware exceptions, interupts, faults, and traps. */ @@ -195,7 +197,14 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { - return 0; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return env->iaoq_f & 3; + } + return MMU_PHYS_IDX; /* mmu disabled */ +#endif } void hppa_translate_init(void); @@ -210,7 +219,9 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, { *pc = env->iaoq_f; *cs_base = env->iaoq_b; - *pflags = env->psw_n; + /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ + *pflags = (env->psw & (PSW_W | PSW_C | PSW_D)) + | env->psw_n * PSW_N; } target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index f6d92de972..9962ab71ee 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -39,7 +39,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.iaoq_f = tb->pc; cpu->env.iaoq_b = tb->cs_base; - cpu->env.psw_n = tb->flags & 1; + cpu->env.psw_n = (tb->flags & PSW_N) != 0; } static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b3996cfcdc..8a40c3f46b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -278,6 +278,8 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; + int mmu_idx; + int privilege; bool psw_n_nonzero; } DisasContext; @@ -1288,10 +1290,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, } if (modify == 0) { - tcg_gen_qemu_ld_i32(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i32(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1318,10 +1320,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, } if (modify == 0) { - tcg_gen_qemu_ld_i64(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i64(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1347,7 +1349,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } - tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); + tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); if (modify != 0) { save_gpr(ctx, rb, addr); @@ -1375,7 +1377,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } - tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); + tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); if (modify != 0) { save_gpr(ctx, rb, addr); @@ -2486,7 +2488,7 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, zero = tcg_const_reg(0); tcg_gen_atomic_xchg_reg(dest, (modify <= 0 ? addr : base), - zero, MMU_USER_IDX, mop); + zero, ctx->mmu_idx, mop); if (modify) { save_gpr(ctx, rb, addr); } @@ -3960,30 +3962,43 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs, int max_insns) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - TranslationBlock *tb = ctx->base.tb; int bound; ctx->cs = cs; - ctx->iaoq_f = tb->pc; - ctx->iaoq_b = tb->cs_base; + +#ifdef CONFIG_USER_ONLY + ctx->privilege = MMU_USER_IDX; + ctx->mmu_idx = MMU_USER_IDX; +#else + ctx->privilege = ctx->base.pc_first & 3; + ctx->mmu_idx = (ctx->base.tb->flags & PSW_D + ? ctx->privilege : MMU_PHYS_IDX); +#endif + ctx->iaoq_f = ctx->base.pc_first; + ctx->iaoq_b = ctx->base.tb->cs_base; + ctx->base.pc_first &= -4; + ctx->iaoq_n = -1; ctx->iaoq_n_var = NULL; + /* Bound the number of instructions by those left on the page. */ + bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; + bound = MIN(max_insns, bound); + ctx->ntemps = 0; memset(ctx->temps, 0, sizeof(ctx->temps)); - bound = -(tb->pc | TARGET_PAGE_MASK) / 4; - return MIN(max_insns, bound); + return bound; } static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - /* Seed the nullification status from PSW[N], as shown in TB->FLAGS. */ + /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ ctx->null_cond = cond_make_f(); ctx->psw_n_nonzero = false; - if (ctx->base.tb->flags & 1) { + if (ctx->base.tb->flags & PSW_N) { ctx->null_cond.c = TCG_COND_ALWAYS; ctx->psw_n_nonzero = true; } @@ -4003,7 +4018,7 @@ static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next = ctx->iaoq_f + 4; + ctx->base.pc_next = (ctx->iaoq_f & -4) + 4; return true; } @@ -4024,7 +4039,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f); + uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f & -4); /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ @@ -4053,10 +4068,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } ctx->ntemps = 0; - /* Advance the insn queue. */ - /* ??? The non-linear instruction restriction is purely due to - the debugging dump. Otherwise we *could* follow unconditional - branches within the same page. */ + /* Advance the insn queue. Note that this check also detects + a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { if (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS) { @@ -4110,7 +4123,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* We don't actually use this during normal translation, but we should interact with the generic main loop. */ - ctx->base.pc_next = ctx->base.tb->pc + 4 * ctx->base.num_insns; + ctx->base.pc_next = ctx->base.pc_first + 4 * ctx->base.num_insns; } static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) From patchwork Mon Jan 22 03:41:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125297 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp944662ljf; Sun, 21 Jan 2018 19:49:32 -0800 (PST) X-Google-Smtp-Source: AH8x225KgKpLAczQ8nF4YE3WxflYy25ITGhe1LTPSIrmK+9AslpfxeMtp23veML27IxzSamO1AlD X-Received: by 10.37.82.9 with SMTP id g9mr5270390ybb.238.1516592972643; Sun, 21 Jan 2018 19:49:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516592972; cv=none; d=google.com; s=arc-20160816; b=DXCQpVtpWYeZ3CKIlnDpap2s6k4liUMgnmIfDa8onXhwaX68t12ee2cSiaonWe+XRP zpbfjAd2VTS+bjuCXiKkIwqmzM0SE2HatdNWa8bceG2ayPBhVrplZBnvlbQQCwpJ6n18 Vq2NK7geGECxNeCKK2ulZNimhshxKpHes1yX5KLsXw/G1oO+Du7cXOy1B0H5Sqw1lv2b J4sg1k80AMphu3SLApEe0WxV+kmC7rb1xpnxkb+ia4WdGZTrO+CW62HBAJeYEaenK7Tm mwe1Gk+mLiQnsCTslbPgI88B7TUIZFPEyGUe41b6EikUCc2devlIgr0aBsPs19KNlAog uuoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=exbg9wf3Jf+eXQueDoelCpDBevuBwgH4hqxIz1Ny4ZY=; b=r9SQhROTlLEC6yO2rtn3xPygLxrVvFBUGoDQWCmAOHnLDW0GIYiM4kgj9wdDgyTM/h FZGbWA0y5P6PZl6TsQZZ3ar0z+sNe9IFIRX5FAL+sODBgBmBN2hUnq53c92pO8T8J4jH CC1Bcro6Sba+TrLb3QuJHVe2a8M751UG7rrXzcFeVx58PkM5OADLNGFdCCrtiUe5TucR LmnVnDOD3d1I8QlOD1f0htff/HQ3h/G3Kfd3YuUMa23JnAcewQsZHoyh0R+cXJOq+DK0 qrWjqTZzxgfw7fglu0XfXC6hmkZFTeiQd/PH/9NuuYvhjUHWS5vH7NF87cRWPOovaxZT j2qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hLpfsavx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:41 -0800 Message-Id: <20180122034217.19593-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 07/43] target/hppa: Implement the system mask instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 4 +++ target/hppa/op_helper.c | 14 ++++++++ target/hppa/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 113 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c720de523b..254a4da133 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -76,3 +76,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) + +#ifndef CONFIG_USER_ONLY +DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +#endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 479bfc0fdf..1c3e043cc0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -601,3 +601,17 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c) update_fr0_op(env, GETPC()); return ret; } + +#ifndef CONFIG_USER_ONLY +target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) +{ + target_ulong psw = env->psw; + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (nsm & ~psw & PSW_Q) { + dynexcp(env, EXCP_ILL, GETPC()); + } + env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); + return psw & PSW_SM; +} +#endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8a40c3f46b..0c6d7898a2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -295,6 +295,10 @@ typedef struct DisasContext { updated the iaq for the next instruction to be executed. */ #define DISAS_IAQ_N_STALE DISAS_TARGET_1 +/* Similarly, but we want to return to the main loop immediately + to recognize unmasked interrupts. */ +#define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 + typedef struct DisasInsn { uint32_t insn, mask; DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, @@ -693,6 +697,14 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } +#define CHECK_MOST_PRIVILEGED(EXCP) \ + do { \ + if (ctx->privilege != 0) { \ + nullify_over(ctx); \ + return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + } \ + } while (0) + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ @@ -1971,6 +1983,79 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, return DISAS_NEXT; } +#ifndef CONFIG_USER_ONLY +/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ +static target_ureg extract_sm_imm(uint32_t insn) +{ + target_ureg val = extract32(insn, 16, 10); + + if (val & PSW_SM_E) { + val = (val & ~PSW_SM_E) | PSW_E; + } + if (val & PSW_SM_W) { + val = (val & ~PSW_SM_W) | PSW_W; + } + return val; +} + +static DisasJumpType trans_rsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_andi_reg(tmp, tmp, ~sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_ssm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ori_reg(tmp, tmp, sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr = extract32(insn, 16, 5); + TCGv_reg tmp, reg; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + reg = load_gpr(ctx, rr); + tmp = get_temp(ctx); + gen_helper_swap_system_mask(tmp, cpu_env, reg); + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_system[] = { { 0x00000000u, 0xfc001fe0u, trans_break }, /* We don't implement space register, so MTSP is a nop. */ @@ -1982,6 +2067,11 @@ static const DisasInsn table_system[] = { { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, +#ifndef CONFIG_USER_ONLY + { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, + { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, + { 0x00001860u, 0xffe0ffffu, trans_mtsm }, +#endif }; static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, @@ -4100,12 +4190,14 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + DisasJumpType is_jmp = ctx->base.is_jmp; - switch (ctx->base.is_jmp) { + switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: + case DISAS_IAQ_N_STALE_EXIT: copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); @@ -4113,6 +4205,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_IAQ_N_UPDATED: if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); + } else if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(0); } else { tcg_gen_lookup_and_goto_ptr(); } From patchwork Mon Jan 22 03:41:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125294 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp943615ljf; Sun, 21 Jan 2018 19:46:07 -0800 (PST) X-Google-Smtp-Source: AH8x2260BjYYNZRyfhlSlEtU19q3dEWwuL+D2BYeEF3r04DvIWAKJc8mqz2PL1bRcUCR37o9ff8b X-Received: by 10.37.117.84 with SMTP id q81mr6165463ybc.263.1516592767667; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:42 -0800 Message-Id: <20180122034217.19593-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 08/43] target/hppa: Add space registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not used where they should be yet, but we can copy them. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.c | 14 ++++++---- target/hppa/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 77 insertions(+), 11 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 805c93db9c..24c728c0d2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -140,6 +140,7 @@ typedef int64_t target_sreg; struct CPUHPPAState { target_ureg gr[32]; uint64_t fr[32]; + uint64_t sr[8]; /* stored shifted into place for gva */ target_ureg sar; target_ureg cr26; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index b6521f61fc..48ac80cb2d 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -168,12 +168,16 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, psw, psw_cb, psw_c); for (i = 0; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TREG_FMT_lx " ", i, env->gr[i]); - if ((i % 4) == 3) { - cpu_fprintf(f, "\n"); - } + cpu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i], + (i & 3) == 3 ? '\n' : ' '); + } +#ifndef CONFIG_USER_ONLY + for (i = 0; i < 8; i++) { + cpu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), + (i & 3) == 3 ? '\n' : ' '); } - cpu_fprintf(f, "\n"); +#endif + cpu_fprintf(f, "\n"); /* ??? FR */ } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 0c6d7898a2..1b03573292 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -316,6 +316,7 @@ typedef struct DisasInsn { /* global register indexes */ static TCGv_reg cpu_gr[32]; +static TCGv_i64 cpu_sr[4]; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_reg cpu_sar; @@ -354,6 +355,10 @@ void hppa_translate_init(void) "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; + /* SR[4-7] are not global registers so that we can index them. */ + static const char sr_names[4][4] = { + "sr0", "sr1", "sr2", "sr3" + }; int i; @@ -363,6 +368,11 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, gr[i]), gr_names[i]); } + for (i = 0; i < 4; i++) { + cpu_sr[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[i]), + sr_names[i]); + } for (i = 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v = &vars[i]; @@ -567,6 +577,19 @@ static void save_frd(unsigned rt, TCGv_i64 val) tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); } +static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) +{ +#ifdef CONFIG_USER_ONLY + tcg_gen_movi_i64(dest, 0); +#else + if (reg < 4) { + tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else { + tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); + } +#endif +} + /* Skip over the implementation of an insn that has been nullified. Use this when the insn is too complex for a conditional move. */ static void nullify_over(DisasContext *ctx) @@ -781,6 +804,13 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } +static unsigned assemble_sr3(uint32_t insn) +{ + unsigned s2 = extract32(insn, 13, 1); + unsigned s0 = extract32(insn, 14, 2); + return s2 * 4 + s0; +} + static target_sreg assemble_12(uint32_t insn) { target_ureg x = -(target_ureg)(insn & 1); @@ -1883,11 +1913,17 @@ static DisasJumpType trans_mfsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv_reg tmp = dest_gpr(ctx, rt); + unsigned rs = assemble_sr3(insn); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_reg t1 = tcg_temp_new(); - /* ??? We don't implement space registers. */ - tcg_gen_movi_reg(tmp, 0); - save_gpr(ctx, rt, tmp); + load_spr(ctx, t0, rs); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_reg(t1, t0); + + save_gpr(ctx, rt, t1); + tcg_temp_free(t1); + tcg_temp_free_i64(t0); cond_free(&ctx->null_cond); return DISAS_NEXT; @@ -1933,6 +1969,32 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, return DISAS_NEXT; } +static DisasJumpType trans_mtsp(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr = extract32(insn, 16, 5); + unsigned rs = assemble_sr3(insn); + TCGv_i64 t64; + + if (rs >= 5) { + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + } + nullify_over(ctx); + + t64 = tcg_temp_new_i64(); + tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); + tcg_gen_shli_i64(t64, t64, 32); + + if (rs >= 4) { + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + } else { + tcg_gen_mov_i64(cpu_sr[rs], t64); + } + tcg_temp_free_i64(t64); + + return nullify_end(ctx, DISAS_NEXT); +} + static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -2058,8 +2120,7 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, static const DisasInsn table_system[] = { { 0x00000000u, 0xfc001fe0u, trans_break }, - /* We don't implement space register, so MTSP is a nop. */ - { 0x00001820u, 0xffe01fffu, trans_nop }, + { 0x00001820u, 0xffe01fffu, trans_mtsp }, { 0x00001840u, 0xfc00ffffu, trans_mtctl }, { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, { 0x000014a0u, 0xffffffe0u, trans_mfia }, From patchwork Mon Jan 22 03:41:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125300 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp944849ljf; Sun, 21 Jan 2018 19:50:10 -0800 (PST) X-Google-Smtp-Source: AH8x225CLbWx9WFSSE6OXP2W0ytSO2TXuY8CNmJvtrM2nNg2MuE4EG2IOXU7De7F6GzMRBC9FRNY X-Received: by 10.13.203.88 with SMTP id n85mr6166538ywd.158.1516593010808; Sun, 21 Jan 2018 19:50:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593010; cv=none; d=google.com; s=arc-20160816; b=ZXCQrvBOfihiS5D5nd6txVO985wped/7p/TmDJ1oRwpIKgHaAqcwmYCLGR/w1Y6xYN 8EoLH1JPRtEZo4X4Y1C9elSYFLfiZ/y0yttlKLdJX2kB8Z5Wt2iupc34uQAQZhNS7N+3 rFkrfjYtOAIb9uvj1vAbcn5AtAHisu281VuLfbyKfUhzJjX2Gq2gwSDmq+LGCC23cJ+e +Fl2RoZIgVlLSJzK9sGejZc7rYHbkxERmInZQVZa7kzDu43FrzGoYIjuYu6RnPX8kmtc SqMqoq+ElSmYm7ogVoOGpxsow6AtyyG8j6vj/oyd/n/Qxl5aiEdBgU/PD1ESZq0KkJhm qTAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=XtWn9+imzFBzrSnq3vFVZrvayGvZlwPe6bZv7lrfWHg=; b=LoYW9w3m164QDmH2xq0IBeRcOYpuy+6SlJt88BdEGf5XGUzDRLjVKk4N3xur/iCeJm n9lRyNhhWrB052JKePJqI6a47WZ03wo+VohR5fzPkoPaUQ1CDRd9vbrTocyoULFSdI0A ozgbU9c3+bqFCsDh/+uZ26lHCwic/m9LQJ/VG6DVDWEnWRO3F41qkeoaJdKTccr0yLZn Njy46wGC0Ww9qOIrYXV4tYH1fz8iaML6PteWd9FPvQ9lstE3eEOPD7vBQeKh+v+F6tbU 9H7P1EqObyr6C3szet3vnLsvt8KdehMLHNuP9dVtKhixSgNEodD67rc9mMS1JPNS0ErL /cvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OO2TeFEV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:43 -0800 Message-Id: <20180122034217.19593-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 09/43] target/hppa: Add control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/hppa/target_cpu.h | 2 +- target/hppa/cpu.h | 23 +++++++++++---- linux-user/main.c | 4 +-- linux-user/signal.c | 4 +-- target/hppa/gdbstub.c | 12 ++++---- target/hppa/mem_helper.c | 2 +- target/hppa/translate.c | 70 ++++++++++++++++++++++++++++++-------------- 7 files changed, 77 insertions(+), 40 deletions(-) -- 2.14.3 diff --git a/linux-user/hppa/target_cpu.h b/linux-user/hppa/target_cpu.h index e50522eae9..7b78bbea80 100644 --- a/linux-user/hppa/target_cpu.h +++ b/linux-user/hppa/target_cpu.h @@ -33,7 +33,7 @@ static inline void cpu_clone_regs(CPUHPPAState *env, target_ulong newsp) static inline void cpu_set_tls(CPUHPPAState *env, target_ulong newtls) { - env->cr27 = newtls; + env->cr[27] = newtls; } #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 24c728c0d2..c92c564a7f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -123,6 +123,20 @@ #define PSW_SM_W 0 #endif +#define CR_RC 0 +#define CR_SCRCCR 10 +#define CR_SAR 11 +#define CR_IVA 14 +#define CR_EIEM 15 +#define CR_IT 16 +#define CR_IIASQ 17 +#define CR_IIAOQ 18 +#define CR_IIR 19 +#define CR_ISR 20 +#define CR_IOR 21 +#define CR_IPSW 22 +#define CR_EIRR 23 + typedef struct CPUHPPAState CPUHPPAState; #if TARGET_REGISTER_BITS == 32 @@ -142,10 +156,6 @@ struct CPUHPPAState { uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ - target_ureg sar; - target_ureg cr26; - target_ureg cr27; - target_ureg psw; /* All psw bits except the following: */ target_ureg psw_n; /* boolean */ target_sreg psw_v; /* in most significant bit */ @@ -163,11 +173,12 @@ struct CPUHPPAState { target_ureg iaoq_f; /* front */ target_ureg iaoq_b; /* back, aka next instruction */ - target_ureg ior; /* interrupt offset register */ - uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; + target_ureg cr[32]; /* control registers */ + target_ureg cr_back[2]; /* back of cr17/cr18 */ + /* Those resources are used only in QEMU core */ CPU_COMMON }; diff --git a/linux-user/main.c b/linux-user/main.c index 42f4c66ce6..90ae447368 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3781,14 +3781,14 @@ void cpu_loop(CPUHPPAState *env) info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->ior; + info._sifields._sigfault._addr = env->cr[CR_IOR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; info.si_code = 0; - info._sifields._sigfault._addr = env->ior; + info._sifields._sigfault._addr = env->cr[CR_IOR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_ILL: diff --git a/linux-user/signal.c b/linux-user/signal.c index f85f0dd780..40d5d849f0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -6440,7 +6440,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUArchState *env) __put_user(env->fr[i], &sc->sc_fr[i]); } - __put_user(env->sar, &sc->sc_sar); + __put_user(env->cr[CR_SAR], &sc->sc_sar); } static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc) @@ -6461,7 +6461,7 @@ static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc) __get_user(env->iaoq_f, &sc->sc_iaoq[0]); __get_user(env->iaoq_b, &sc->sc_iaoq[1]); - __get_user(env->sar, &sc->sc_sar); + __get_user(env->cr[CR_SAR], &sc->sc_sar); } /* No, this doesn't look right, but it's copied straight from the kernel. */ diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 228d282fe9..fc27aec073 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -36,7 +36,7 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) val = env->gr[n]; break; case 32: - val = env->sar; + val = env->cr[CR_SAR]; break; case 33: val = env->iaoq_f; @@ -45,10 +45,10 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) val = env->iaoq_b; break; case 59: - val = env->cr26; + val = env->cr[26]; break; case 60: - val = env->cr27; + val = env->cr[27]; break; case 64 ... 127: val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32); @@ -89,7 +89,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->gr[n] = val; break; case 32: - env->sar = val; + env->cr[CR_SAR] = val; break; case 33: env->iaoq_f = val; @@ -98,10 +98,10 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->iaoq_b = val; break; case 59: - env->cr26 = val; + env->cr[26] = val; break; case 60: - env->cr27 = val; + env->cr[27] = val; break; case 64: env->fr[0] = deposit64(env->fr[0], 32, 32, val); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2901f3e29c..1afaf89539 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -32,7 +32,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, /* ??? Test between data page fault and data memory protection trap, which would affect si_code. */ cs->exception_index = EXCP_DMP; - cpu->env.ior = address; + cpu->env.cr[CR_IOR] = address; return 1; } #else diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1b03573292..0408dbedf1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -324,8 +324,6 @@ static TCGv_reg cpu_psw_n; static TCGv_reg cpu_psw_v; static TCGv_reg cpu_psw_cb; static TCGv_reg cpu_psw_cb_msb; -static TCGv_reg cpu_cr26; -static TCGv_reg cpu_cr27; #include "exec/gen-icount.h" @@ -335,9 +333,7 @@ void hppa_translate_init(void) typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] = { - DEF_VAR(sar), - DEF_VAR(cr26), - DEF_VAR(cr27), + { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, DEF_VAR(psw_n), DEF_VAR(psw_v), DEF_VAR(psw_cb), @@ -1856,7 +1852,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_mov_reg(cpu_cr27, cpu_gr[26]); + tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])); tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; @@ -1937,34 +1933,39 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, TCGv_reg tmp; switch (ctl) { - case 11: /* SAR */ + case CR_SAR: #ifdef TARGET_HPPA64 if (extract32(insn, 14, 1) == 0) { /* MFSAR without ,W masks low 5 bits. */ tmp = dest_gpr(ctx, rt); tcg_gen_andi_reg(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); - break; + goto done; } #endif save_gpr(ctx, rt, cpu_sar); - break; - case 16: /* Interval Timer */ + goto done; + case CR_IT: /* Interval Timer */ + /* FIXME: Respect PSW_S bit. */ + nullify_over(ctx); tmp = dest_gpr(ctx, rt); - tcg_gen_movi_tl(tmp, 0); /* FIXME */ + tcg_gen_movi_reg(tmp, 0); /* FIXME */ save_gpr(ctx, rt, tmp); break; case 26: - save_gpr(ctx, rt, cpu_cr26); - break; case 27: - save_gpr(ctx, rt, cpu_cr27); break; default: /* All other control registers are privileged. */ - return gen_illegal(ctx); + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + break; } + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + save_gpr(ctx, rt, tmp); + + done: cond_free(&ctx->null_cond); return DISAS_NEXT; } @@ -2000,20 +2001,45 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, { unsigned rin = extract32(insn, 16, 5); unsigned ctl = extract32(insn, 21, 5); + TCGv_reg reg = load_gpr(ctx, rin); TCGv_reg tmp; - if (ctl == 11) { /* SAR */ + if (ctl == CR_SAR) { tmp = tcg_temp_new(); - tcg_gen_andi_reg(tmp, load_gpr(ctx, rin), TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); - } else { - /* All other control registers are privileged or read-only. */ - return gen_illegal(ctx); + + cond_free(&ctx->null_cond); + return DISAS_NEXT; } - cond_free(&ctx->null_cond); - return DISAS_NEXT; + /* All other control registers are privileged or read-only. */ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + + nullify_over(ctx); + switch (ctl) { + case CR_IT: + /* ??? modify interval timer offset */ + break; + + case CR_IIASQ: + case CR_IIAOQ: + /* FIXME: Respect PSW_Q bit */ + /* The write advances the queue and stores to the back element. */ + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, + offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); + tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_reg(reg, cpu_env, + offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); + break; + + default: + tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + break; + } + return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, From patchwork Mon Jan 22 03:41:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125299 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp944823ljf; Sun, 21 Jan 2018 19:50:07 -0800 (PST) X-Google-Smtp-Source: AH8x226F/7qRA0EQSysd9fUYZX2nE73Fd1cKEatVRoRN+sjy/CgfNX8Yl8x+CBLVdSMaSQclEXvD X-Received: by 10.37.26.133 with SMTP id a127mr6135916yba.74.1516593006981; Sun, 21 Jan 2018 19:50:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593006; cv=none; d=google.com; s=arc-20160816; b=a+tTEOvU8fpnfZzUF2Vy8KRasmihDOo6k4LXI6ZI2XaCkzUvmbAhbUoHA8Cg+pvR7g 3EYhuPQW9aGUbQD5ChDpzRzro3iGGf0ZD5vHYW3Mf/JDKevsbQPz/JLYgwodzHf14ued jiOimcRIc1LoLNUTSHPx9w1FQraXqG8a1BqV3hp1Z3PHarUCr/IvjxlZEtl8wd3XdxBr WYAB/ukRBbeyYaD51u8S/5xIZ6DmxR57DS3/LkbzdKRy1Zs8KUEuycDOzvWAlaAgHMLm U7vUg1d8ScY11hoVpYh6ZZVPi+pCztOukryBfiCynWO75naoWtznXhNJ325ngVr64Aov iO3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=VHkkHLPf31NpgIj6hiY5wrC76LIgFgDzISZWBv4Q/MA=; b=dIpTMSsIiBF0m93TM3VQMBsAhVjuslpsHl6as8qGNCs4W4L4yMxa8iab8nYfCqm51A e3wANkPdiljcogg47Dulsac8fQfsDkoBesa9L6xtJKnzoO5QwNtelfWag2/Ul97aNwZk pCoFWtDEOPA1cqLnorW5jPZ0451YXalN6n7VkYKhG6JLq4jF4nPfnt1sMd3b/hFEz1+g UZiKWanvIAxITmUSSVJ4X+ey9Tdydy7Sji0yyhmL9mbBXIZ1xtSgkEv7vMJbra7jxqlV 5mdVFlbEe2Wt+SPEWLWTdaj/3JoUCPZRTAj7htRlQnpZHSwtrS35ppZaRS9tX2Ff0WFv HYPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aKt+QjKh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:44 -0800 Message-Id: <20180122034217.19593-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 10/43] target/hppa: Adjust insn mask for mfctl, w X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While the E bit is only used for pa2.0 mfctl,w from sar, the otherwise reserved bit does not appear to be decoded. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 0408dbedf1..b201e5ace2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2151,7 +2151,7 @@ static const DisasInsn table_system[] = { { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, { 0x000014a0u, 0xffffffe0u, trans_mfia }, { 0x000004a0u, 0xffff1fe0u, trans_mfsp }, - { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, + { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, #ifndef CONFIG_USER_ONLY From patchwork Mon Jan 22 03:41:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125304 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp946752ljf; Sun, 21 Jan 2018 19:56:01 -0800 (PST) X-Google-Smtp-Source: AH8x227WP31iWnfqFG9afpvCs4ZKbxuhHaSs4ORem3MPCC7aoqS04+yS9Fpg97/YnQWRb4aKXm5P X-Received: by 10.37.25.136 with SMTP id 130mr6112756ybz.414.1516593361554; Sun, 21 Jan 2018 19:56:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593361; cv=none; d=google.com; s=arc-20160816; b=ZdzmSPh6jd4B5d+XmGV7D/RwzaF9YLcZEIdEb/H9zfABrsHMjTpeukaRfQf5M6HuRs Py2G+9UofgZlCq0XIOZr2o4yWKusheBz2+qfpc7rUogg4gNSPl3b3qI+PjuFqenP65mq 88e/nThNIGAqeej+EnuzX/vyC1hMbkHM/bvDgsxjFcaawUr/8Mi7tvltKtH4KcMvSyXE /qlVx9/vmn1e7EGmphvbDwZBlkSjPtjG/DN+Q7QNGs4Wr7F7KOZnAGPZ/YljfI1MgWlk BYJLsz4B+5syReGg70d4lZOHfbDfYvmm8RHUZfWey8SqjJOXbqVrkDpmeaGwj+wSqooX rLDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=4v9sEiBGAG4Ztqc7pZb7dChRVtEW7591nKjhbkJ+XWE=; b=cSZfutd+tv5kiM6rIIsMA1APVWyYm2b92/fiQwQ6ItV8ezKmqXEs7A5huRlYFtwKSB kl9NKPg166GUTECm+dmXYf/y/bB1hlzsl6KPHS/kpx8S3U0kIT8nzr1q/QS/+UZrlLeY 0IuWkh4SLrVmHWWR5jWOA3btN7gQ1XQ96+pf3lCUP4qR8oQQKDsVBMLqa8/pzYKmnxWD c6NHSuCYDX3qAPb2/thySgE9y3Zc0l/5P9jzMcnczwRsoluzwdA6pRI2XE38hG/TsuDs TF3gxDIElB2PHqPK2RBXCppF9h/h4/FL0qCeVJHbjS5P4uR0sBiNVfAn6Z/YQH8JkM/O 3J5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=d8mvsfRq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:45 -0800 Message-Id: <20180122034217.19593-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 11/43] target/hppa: Implement rfi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 24 ++++++++++++++++++++++++ target/hppa/translate.c | 30 ++++++++++++++++++++++++++++-- 4 files changed, 55 insertions(+), 2 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c92c564a7f..6ec3430ae3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -178,6 +178,7 @@ struct CPUHPPAState { target_ureg cr[32]; /* control registers */ target_ureg cr_back[2]; /* back of cr17/cr18 */ + target_ureg shadow[7]; /* shadow registers */ /* Those resources are used only in QEMU core */ CPU_COMMON diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 254a4da133..79d22ae486 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -78,5 +78,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) #ifndef CONFIG_USER_ONLY +DEF_HELPER_1(rfi, void, env) +DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) #endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 1c3e043cc0..3f5dcbbca0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -614,4 +614,28 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; } + +void HELPER(rfi)(CPUHPPAState *env) +{ + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (env->psw & (PSW_I | PSW_R | PSW_Q)) { + helper_excp(env, EXCP_ILL); + } + env->iaoq_f = env->cr[CR_IIAOQ]; + env->iaoq_b = env->cr_back[1]; + cpu_hppa_put_psw(env, env->cr[CR_IPSW]); +} + +void HELPER(rfi_r)(CPUHPPAState *env) +{ + env->gr[1] = env->shadow[0]; + env->gr[8] = env->shadow[1]; + env->gr[9] = env->shadow[2]; + env->gr[16] = env->shadow[3]; + env->gr[17] = env->shadow[4]; + env->gr[24] = env->shadow[5]; + env->gr[25] = env->shadow[6]; + helper_rfi(env); +} #endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b201e5ace2..89c22a4c3e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -651,6 +651,10 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) { TCGLabel *null_lab = ctx->null_lab; + /* For NEXT, NORETURN, STALE, we can easily continue (or exit). + For UPDATED, we cannot update on the nullified path. */ + assert(status != DISAS_IAQ_N_UPDATED); + if (likely(null_lab == NULL)) { /* The current insn wasn't conditional or handled the condition applied to it without a branch, so the (new) setting of @@ -672,8 +676,6 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) gen_set_label(null_lab); ctx->null_cond = cond_make_n(); } - - assert(status != DISAS_NORETURN && status != DISAS_IAQ_N_UPDATED); if (status == DISAS_NORETURN) { status = DISAS_NEXT; } @@ -2142,6 +2144,29 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, /* Exit the TB to recognize new interrupts. */ return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); } + +static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned comp = extract32(insn, 5, 4); + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + if (comp == 5) { + gen_helper_rfi_r(cpu_env); + } else { + gen_helper_rfi(cpu_env); + } + if (ctx->base.singlestep_enabled) { + gen_excp_1(EXCP_DEBUG); + } else { + tcg_gen_exit_tb(0); + } + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_NORETURN); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_system[] = { @@ -2158,6 +2183,7 @@ static const DisasInsn table_system[] = { { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, { 0x00001860u, 0xffe0ffffu, trans_mtsm }, + { 0x00000c00u, 0xfffffe1fu, trans_rfi }, #endif }; From patchwork Mon Jan 22 03:41:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125306 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp946937ljf; Sun, 21 Jan 2018 19:56:37 -0800 (PST) X-Google-Smtp-Source: AH8x226LUbBzx1qls2ixrO17Fs15hO+HGDr5ryDVsGeiqkla3VyNGTWRch6Tn0tlYUvYTpKYyJ0y X-Received: by 10.129.103.87 with SMTP id b84mr6342157ywc.470.1516593397006; Sun, 21 Jan 2018 19:56:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593397; cv=none; d=google.com; s=arc-20160816; b=G7C8Y+B6vIOL6714EWsKnbrPycekk3gT595xA7v1ma8u+tZRqxwDCkaPpUwkD3WRmT w9jEbUjVhz3Qasre0vI0byZrAAnSLR3cnoooPPwx2pPcrvuSVcaLrcOTeWBXENiQ/8OO GEk5AQnEi5Mf4FmSK9Yk+fnhIHX7ZI0TDWgK/LYdF0fwuAlmTlU4vgh4b3nlD9DQOCE4 FS4HzARGtXI0xfFGFZy8GHLKWuh8kNghKxxXbRkECNtN/q8qNIo3HZ2pS+04ejfi9WfY T/HyPd8MaO00P7DwddBtk4LOszImESPyuYAuAxsUA/s2ej2VCa983+Ja+ZyXqJ6LBlps e0DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=3MsEp4gLxHn4ce8bKU91X4N9Oqe/u0fNwuv/OlTqJKY=; b=o8tmWHoVr4NwHTKiF9JnC1Q9xfSriF+qW/WIQy4I/ZAZ23WF7r5hFQXAnL5506+NRd QDv/gwUvTsOm9FuGLNp7lYGz/6uPbaG0RqBb0XyQU3z0KDlhM47gbtKyZWusz5LERiaY hsO5eMpAb6XEbg0fe8E+lzcQdu8ABBjP40S/lM+WZRNzjEfmZsKDE6bwN4uYulprSuD/ I9v3hQKG6IjgSTEwK6hCKZ6UR/yl8BvZbg8UBIqDw9YQv6ilS1oP4TTEWPLDM6IIdP2z atocGXh00SMXLSCbSrMw8HgZdyaz3QRAHZSywoAPo6q3gb1vEELIWoYfVgUU0JZsiBzz Ff4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Zo+/DhfY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 12/43] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 2 + target/hppa/helper.c | 63 ----------------- target/hppa/int_helper.c | 176 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++- target/hppa/Makefile.objs | 1 + 5 files changed, 192 insertions(+), 66 deletions(-) create mode 100644 target/hppa/int_helper.c -- 2.14.3 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9962ab71ee..ca619578dd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -106,8 +106,10 @@ static void hppa_cpu_initfn(Object *obj) CPUHPPAState *env = &cpu->env; cs->env_ptr = env; + cs->exception_index = -1; cpu_hppa_loaded_fr0(env); set_snan_bit_is_one(true, &env->fp_status); + cpu_hppa_put_psw(env, PSW_W); } static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 48ac80cb2d..6e8758f82c 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -67,69 +67,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) env->psw_cb = cb; } -void hppa_cpu_do_interrupt(CPUState *cs) -{ - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; - int i = cs->exception_index; - - if (qemu_loglevel_mask(CPU_LOG_INT)) { - static const char * const names[] = { - [EXCP_HPMC] = "high priority machine check", - [EXCP_POWER_FAIL] = "power fail interrupt", - [EXCP_RC] = "recovery counter trap", - [EXCP_EXT_INTERRUPT] = "external interrupt", - [EXCP_LPMC] = "low priority machine check", - [EXCP_ITLB_MISS] = "instruction tlb miss fault", - [EXCP_IMP] = "instruction memory protection trap", - [EXCP_ILL] = "illegal instruction trap", - [EXCP_BREAK] = "break instruction trap", - [EXCP_PRIV_OPR] = "privileged operation trap", - [EXCP_PRIV_REG] = "privileged register trap", - [EXCP_OVERFLOW] = "overflow trap", - [EXCP_COND] = "conditional trap", - [EXCP_ASSIST] = "assist exception trap", - [EXCP_DTLB_MISS] = "data tlb miss fault", - [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss", - [EXCP_NA_DTLB_MISS] = "non-access data tlb miss", - [EXCP_DMP] = "data memory protection trap", - [EXCP_DMB] = "data memory break trap", - [EXCP_TLB_DIRTY] = "tlb dirty bit trap", - [EXCP_PAGE_REF] = "page reference trap", - [EXCP_ASSIST_EMU] = "assist emulation trap", - [EXCP_HPT] = "high-privilege transfer trap", - [EXCP_LPT] = "low-privilege transfer trap", - [EXCP_TB] = "taken branch trap", - [EXCP_DMAR] = "data memory access rights trap", - [EXCP_DMPI] = "data memory protection id trap", - [EXCP_UNALIGN] = "unaligned data reference trap", - [EXCP_PER_INTERRUPT] = "performance monitor interrupt", - [EXCP_SYSCALL] = "syscall", - [EXCP_SYSCALL_LWS] = "syscall-lws", - }; - static int count; - const char *name = NULL; - - if (i >= 0 && i < ARRAY_SIZE(names)) { - name = names[i]; - } - if (name) { - qemu_log("INT %6d: %s ia_f=" TARGET_FMT_lx "\n", - ++count, name, env->iaoq_f); - } else { - qemu_log("INT %6d: unknown %d ia_f=" TARGET_FMT_lx "\n", - ++count, i, env->iaoq_f); - } - } - cs->exception_index = -1; -} - -bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - abort(); - return false; -} - void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c new file mode 100644 index 0000000000..34413c30e1 --- /dev/null +++ b/target/hppa/int_helper.c @@ -0,0 +1,176 @@ +/* + * HPPA interrupt helper routines + * + * Copyright (c) 2017 Richard Henderson + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qom/cpu.h" + + +void hppa_cpu_do_interrupt(CPUState *cs) +{ + HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = &cpu->env; + int i = cs->exception_index; + target_ureg iaoq_f = env->iaoq_f; + target_ureg iaoq_b = env->iaoq_b; + +#ifndef CONFIG_USER_ONLY + target_ureg old_psw; + + /* As documented in pa2.0 -- interruption handling. */ + /* step 1 */ + env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); + + /* step 2 -- note PSW_W == 0 for !HPPA64. */ + cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0)); + + /* step 3 */ + env->cr[CR_IIAOQ] = iaoq_f; + env->cr_back[1] = iaoq_b; + + /* step 5 */ + /* ISR and IOR will be set elsewhere. */ + switch (i) { + case EXCP_ILL: + case EXCP_BREAK: + case EXCP_PRIV_REG: + case EXCP_PRIV_OPR: + /* IIR set via translate.c. */ + break; + + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_DMAR: + case EXCP_DMPI: + case EXCP_UNALIGN: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_TLB_DIRTY: + case EXCP_PAGE_REF: + case EXCP_ASSIST_EMU: + { + /* Avoid reading directly from the virtual address, lest we + raise another exception from some sort of TLB issue. */ + vaddr vaddr; + hwaddr paddr; + + paddr = vaddr = iaoq_f & -4; + env->cr[CR_IIR] = ldl_phys(cs->as, paddr); + } + break; + + default: + /* Other exceptions do not set IIR. */ + break; + } + + /* step 6 */ + if (old_psw & PSW_Q) { + env->shadow[0] = env->gr[1]; + env->shadow[1] = env->gr[8]; + env->shadow[2] = env->gr[9]; + env->shadow[3] = env->gr[16]; + env->shadow[4] = env->gr[17]; + env->shadow[5] = env->gr[24]; + env->shadow[6] = env->gr[25]; + } + + /* step 7 */ + env->iaoq_f = env->cr[CR_IVA] + 32 * i; + env->iaoq_b = env->iaoq_f + 4; +#endif + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + static const char * const names[] = { + [EXCP_HPMC] = "high priority machine check", + [EXCP_POWER_FAIL] = "power fail interrupt", + [EXCP_RC] = "recovery counter trap", + [EXCP_EXT_INTERRUPT] = "external interrupt", + [EXCP_LPMC] = "low priority machine check", + [EXCP_ITLB_MISS] = "instruction tlb miss fault", + [EXCP_IMP] = "instruction memory protection trap", + [EXCP_ILL] = "illegal instruction trap", + [EXCP_BREAK] = "break instruction trap", + [EXCP_PRIV_OPR] = "privileged operation trap", + [EXCP_PRIV_REG] = "privileged register trap", + [EXCP_OVERFLOW] = "overflow trap", + [EXCP_COND] = "conditional trap", + [EXCP_ASSIST] = "assist exception trap", + [EXCP_DTLB_MISS] = "data tlb miss fault", + [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss", + [EXCP_NA_DTLB_MISS] = "non-access data tlb miss", + [EXCP_DMP] = "data memory protection trap", + [EXCP_DMB] = "data memory break trap", + [EXCP_TLB_DIRTY] = "tlb dirty bit trap", + [EXCP_PAGE_REF] = "page reference trap", + [EXCP_ASSIST_EMU] = "assist emulation trap", + [EXCP_HPT] = "high-privilege transfer trap", + [EXCP_LPT] = "low-privilege transfer trap", + [EXCP_TB] = "taken branch trap", + [EXCP_DMAR] = "data memory access rights trap", + [EXCP_DMPI] = "data memory protection id trap", + [EXCP_UNALIGN] = "unaligned data reference trap", + [EXCP_PER_INTERRUPT] = "performance monitor interrupt", + [EXCP_SYSCALL] = "syscall", + [EXCP_SYSCALL_LWS] = "syscall-lws", + }; + static int count; + const char *name = NULL; + char unknown[16]; + + if (i >= 0 && i < ARRAY_SIZE(names)) { + name = names[i]; + } + if (!name) { + snprintf(unknown, sizeof(unknown), "unknown %d", i); + name = unknown; + } + qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx + " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", + ++count, name, + (target_ulong)iaoq_f, + (target_ulong)iaoq_b, + env->iaoq_f, + (target_ulong)env->cr[CR_IOR]); + } + cs->exception_index = -1; +} + +bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ +#ifndef CONFIG_USER_ONLY + HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = &cpu->env; + + /* If interrupts are requested and enabled, raise them. */ + if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { + cs->exception_index = EXCP_EXT_INTERRUPT; + hppa_cpu_do_interrupt(cs); + return true; + } +#endif + return false; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 89c22a4c3e..58837044a6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -278,6 +278,7 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; + uint32_t insn; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -712,17 +713,25 @@ static DisasJumpType gen_excp(DisasContext *ctx, int exception) return DISAS_NORETURN; } +static DisasJumpType gen_excp_iir(DisasContext *ctx, int exc) +{ + TCGv_reg tmp = tcg_const_reg(ctx->insn); + tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); + tcg_temp_free(tmp); + return gen_excp(ctx, exc); +} + static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_ILL)); } #define CHECK_MOST_PRIVILEGED(EXCP) \ do { \ if (ctx->privilege != 0) { \ nullify_over(ctx); \ - return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + return nullify_end(ctx, gen_excp_iir(ctx, EXCP)); \ } \ } while (0) @@ -1882,7 +1891,7 @@ static DisasJumpType trans_break(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_BREAK)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_BREAK)); } static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, @@ -4259,6 +4268,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->null_cond.c = TCG_COND_NEVER; ret = DISAS_NEXT; } else { + ctx->insn = insn; ret = translate_one(ctx, insn); assert(ctx->null_lab == NULL); } diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index d89285307b..dcd60a6839 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1,2 @@ obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o +obj-y += int_helper.o From patchwork Mon Jan 22 03:41:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125298 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp944704ljf; Sun, 21 Jan 2018 19:49:42 -0800 (PST) X-Google-Smtp-Source: AH8x224ST9VECrZ/JtimLYZoCeMk/OmksMEDiLFjfIR2zizAS4BLWcvNJ7k+kypgHvr8KrsjssAp X-Received: by 10.129.165.11 with SMTP id c11mr6094174ywh.311.1516592981969; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:47 -0800 Message-Id: <20180122034217.19593-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 13/43] target/hppa: Implement unaligned access trap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ca619578dd..6b2d22118d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -48,6 +48,21 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) info->print_insn = print_insn_hppa; } +static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = &cpu->env; + + cs->exception_index = EXCP_UNALIGN; + /* ??? Needs tweaking for hppa64. */ + env->cr[CR_IOR] = addr; + env->cr[CR_ISR] = addr >> 32; + + cpu_loop_exit_restore(cs, retaddr); +} + static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -139,7 +154,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) #else cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; #endif - + cc->do_unaligned_access = hppa_cpu_do_unaligned_access; cc->disas_set_info = hppa_cpu_disas_set_info; cc->tcg_initialize = hppa_translate_init; From patchwork Mon Jan 22 03:41:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125308 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp947110ljf; Sun, 21 Jan 2018 19:57:23 -0800 (PST) X-Google-Smtp-Source: AH8x225TibuJ+TcxNcsNXveHSwF4mpHA5WbTOw09T21ICbCb3Yp9G4EigJivVU9EF0TclpNaIwAF X-Received: by 10.37.185.201 with SMTP id y9mr6409933ybj.160.1516593443635; Sun, 21 Jan 2018 19:57:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593443; cv=none; d=google.com; s=arc-20160816; b=FIWNAp/C64SnPKJag8VGH/GUpbhLxrRIwVDUOtDeo3qVXt6ZrL3zB3nHvQm/+iQPp6 KE12Ws+sHjsssVjRYjm4Y/z5k94Af1kZscnfVYFidL+RVYRCzHdnIiBb6ipmPgIrNL8K hGTVgQyzRaTGNvfOjiNsj7tt1RqCf7KIuTM7/iVIJptceGEgZy2JNbDZgRmxvxgbMEUe Rr5Y6IpWBxlWO8iXD41TcGw9Kadp05m9GQPSNR3JJJD3xKQ0B6ybw/p4papNs86Hr9zH aFzSzD6m3H2Ihw7kI709KniQdz5hCw/8881hbaWli72GZTByn4jA2YdUvv/UjrYNYrz4 Cv7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Xl+u/KT3a7pecBfrUB6d+nQA8J7kVICjxAyGP2RtJ0k=; b=f3pI3TZp8CMFYGU6GUyfCpNaWA597OB3aC62WK1F3Jvh2az6jS8qV1n1VJKbQsGWPC lHQpI8YexmOwlP4+k9VKDOv2d2l+j2v6+2OZfzTgo+4HE41aNvRX7ncFbVoctQKGc6iu 6D6VO6vQ0VdkjkgzD96dyZoSk1+6MGfxeSf2dIZ4zOEB2qtZWs0N1O9iEv1EWyYcika1 m/1eE5Y13sWENx0K1QACIgIzceeRcto/0NGEBHuadJJvJF4idEOXlgx7q2c9LGOXkLrZ 1mWio07H5fflBsEmfIQuHVPn5ZSECUxjV9HBjHIYa49J1bbz4s4aJpTTBkZRaPkgqnkm GkEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HiTsZTdQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:48 -0800 Message-Id: <20180122034217.19593-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 14/43] target/hppa: Use space registers in data operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This changes the system virtual address width to 64-bit and incorporates the space registers into load/store operations. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 14 ++ target/hppa/translate.c | 334 +++++++++++++++++++++++++++--------------------- 2 files changed, 201 insertions(+), 147 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6ec3430ae3..94f9c8ca2b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,10 +23,24 @@ #include "qemu-common.h" #include "cpu-qom.h" +#ifdef TARGET_HPPA64 +#define TARGET_LONG_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define TARGET_REGISTER_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#elif defined(CONFIG_USER_ONLY) #define TARGET_LONG_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #define TARGET_REGISTER_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32 +#else +/* In order to form the GVA from space:offset, + we need a 64-bit virtual address space. */ +#define TARGET_LONG_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define TARGET_REGISTER_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#endif #define CPUArchState struct CPUHPPAState diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 58837044a6..0650c3e14e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -272,8 +272,9 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; - int ntemps; - TCGv_reg temps[8]; + int ntempr, ntempl; + TCGv_reg tempr[4]; + TCGv_tl templ[4]; DisasCond null_cond; TCGLabel *null_lab; @@ -454,11 +455,20 @@ static void cond_free(DisasCond *cond) static TCGv_reg get_temp(DisasContext *ctx) { - unsigned i = ctx->ntemps++; - g_assert(i < ARRAY_SIZE(ctx->temps)); - return ctx->temps[i] = tcg_temp_new(); + unsigned i = ctx->ntempr++; + g_assert(i < ARRAY_SIZE(ctx->tempr)); + return ctx->tempr[i] = tcg_temp_new(); } +#ifndef CONFIG_USER_ONLY +static TCGv_tl get_temp_tl(DisasContext *ctx) +{ + unsigned i = ctx->ntempl++; + g_assert(i < ARRAY_SIZE(ctx->templ)); + return ctx->templ[i] = tcg_temp_new_tl(); +} +#endif + static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { TCGv_reg t = get_temp(ctx); @@ -1313,6 +1323,70 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, return DISAS_NEXT; } +#ifndef CONFIG_USER_ONLY +/* Top 2 bits of the base register select sp[4-7]. */ +static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) +{ + TCGv_ptr ptr; + TCGv_reg tmp; + TCGv_i64 spc; + + if (sp != 0) { + return cpu_sr[sp]; + } + + ptr = tcg_temp_new_ptr(); + tmp = tcg_temp_new(); + spc = get_temp_tl(ctx); + + tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + tcg_gen_andi_reg(tmp, tmp, 030); + tcg_gen_trunc_reg_ptr(ptr, tmp); + tcg_temp_free(tmp); + + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); + tcg_temp_free_ptr(ptr); + + return spc; +} +#endif + +static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, + unsigned rb, unsigned rx, int scale, target_sreg disp, + unsigned sp, int modify, bool is_phys) +{ + TCGv_reg base = load_gpr(ctx, rb); + TCGv_reg ofs; + + /* Note that RX is mutually exclusive with DISP. */ + if (rx) { + ofs = get_temp(ctx); + tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); + tcg_gen_add_reg(ofs, ofs, base); + } else if (disp || modify) { + ofs = get_temp(ctx); + tcg_gen_addi_reg(ofs, base, disp); + } else { + ofs = base; + } + + *pofs = ofs; +#ifdef CONFIG_USER_ONLY + *pgva = (modify <= 0 ? ofs : base); +#else + TCGv_tl addr = get_temp_tl(ctx); + tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); + if (ctx->base.tb->flags & PSW_W) { + tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); + } + if (!is_phys) { + tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); + } + *pgva = addr; +#endif +} + /* Emit a memory load. The modify parameter should be * < 0 for pre-modify, * > 0 for post-modify, @@ -1320,118 +1394,74 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - if (modify == 0) { - tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop); - } else { - tcg_gen_qemu_ld_i32(dest, (modify < 0 ? addr : base), - ctx->mmu_idx, mop); - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - if (modify == 0) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); - } else { - tcg_gen_qemu_ld_i64(dest, (modify < 0 ? addr : base), - ctx->mmu_idx, mop); - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); - - if (modify != 0) { - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); - - if (modify != 0) { - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } #if TARGET_REGISTER_BITS == 64 @@ -1444,7 +1474,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { TCGv_reg dest; @@ -1457,7 +1487,7 @@ static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, /* Make sure if RT == RB, we see the result of the load. */ dest = get_temp(ctx); } - do_load_reg(ctx, dest, rb, rx, scale, disp, modify, mop); + do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); @@ -1465,14 +1495,14 @@ static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i32 tmp; nullify_over(ctx); tmp = tcg_temp_new_i32(); - do_load_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); + do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); save_frw_i32(rt, tmp); tcg_temp_free_i32(tmp); @@ -1485,14 +1515,14 @@ static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i64 tmp; nullify_over(ctx); tmp = tcg_temp_new_i64(); - do_load_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); + do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); save_frd(rt, tmp); tcg_temp_free_i64(tmp); @@ -1504,23 +1534,24 @@ static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_sreg disp, int modify, TCGMemOp mop) + target_sreg disp, unsigned sp, + int modify, TCGMemOp mop) { nullify_over(ctx); - do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); + do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i32 tmp; nullify_over(ctx); tmp = load_frw_i32(rt); - do_store_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); + do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); tcg_temp_free_i32(tmp); return nullify_end(ctx, DISAS_NEXT); @@ -1528,14 +1559,14 @@ static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i64 tmp; nullify_over(ctx); tmp = load_frd(rt); - do_store_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); + do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); tcg_temp_free_i64(tmp); return nullify_end(ctx, DISAS_NEXT); @@ -2217,18 +2248,21 @@ static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); + unsigned sp = extract32(insn, 14, 2); unsigned rb = extract32(insn, 21, 5); unsigned is_write = extract32(insn, 6, 1); - TCGv_reg dest; + TCGv_reg dest, ofs; + TCGv_tl addr; nullify_over(ctx); /* ??? Do something with priv level operand. */ dest = dest_gpr(ctx, rt); + form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); if (is_write) { - gen_helper_probe_w(dest, load_gpr(ctx, rb)); + gen_helper_probe_w(dest, addr); } else { - gen_helper_probe_r(dest, load_gpr(ctx, rb)); + gen_helper_probe_r(dest, addr); } save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); @@ -2617,12 +2651,13 @@ static DisasJumpType trans_ld_idx_i(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned sz = extract32(insn, 6, 2); unsigned a = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); int disp = low_sextract(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); int modify = (m ? (a ? -1 : 1) : 0); TCGMemOp mop = MO_TE | sz; - return do_load(ctx, rt, rb, 0, 0, disp, modify, mop); + return do_load(ctx, rt, rb, 0, 0, disp, sp, modify, mop); } static DisasJumpType trans_ld_idx_x(DisasContext *ctx, uint32_t insn, @@ -2632,11 +2667,12 @@ static DisasJumpType trans_ld_idx_x(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned sz = extract32(insn, 6, 2); unsigned u = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); TCGMemOp mop = MO_TE | sz; - return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, m, mop); + return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, sp, m, mop); } static DisasJumpType trans_st_idx_i(DisasContext *ctx, uint32_t insn, @@ -2646,12 +2682,13 @@ static DisasJumpType trans_st_idx_i(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned sz = extract32(insn, 6, 2); unsigned a = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rr = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); int modify = (m ? (a ? -1 : 1) : 0); TCGMemOp mop = MO_TE | sz; - return do_store(ctx, rr, rb, disp, modify, mop); + return do_store(ctx, rr, rb, disp, sp, modify, mop); } static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, @@ -2661,16 +2698,16 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned i = extract32(insn, 12, 1); unsigned au = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); TCGMemOp mop = MO_TEUL | MO_ALIGN_16; - TCGv_reg zero, addr, base, dest; + TCGv_reg zero, dest, ofs; + TCGv_tl addr; int modify, disp = 0, scale = 0; nullify_over(ctx); - /* ??? Share more code with do_load and do_load_{32,64}. */ - if (i) { modify = (m ? (au ? -1 : 1) : 0); disp = low_sextract(rx, 0, 5); @@ -2682,27 +2719,19 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, } } if (modify) { - /* Base register modification. Make sure if RT == RB, we see - the result of the load. */ + /* Base register modification. Make sure if RT == RB, + we see the result of the load. */ dest = get_temp(ctx); } else { dest = dest_gpr(ctx, rt); } - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); zero = tcg_const_reg(0); - tcg_gen_atomic_xchg_reg(dest, (modify <= 0 ? addr : base), - zero, ctx->mmu_idx, mop); + tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); if (modify) { - save_gpr(ctx, rb, addr); + save_gpr(ctx, rb, ofs); } save_gpr(ctx, rt, dest); @@ -2715,20 +2744,17 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, target_sreg disp = low_sextract(insn, 0, 5); unsigned m = extract32(insn, 5, 1); unsigned a = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rt = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); - TCGv_reg addr, val; + TCGv_reg ofs, val; + TCGv_tl addr; nullify_over(ctx); - addr = tcg_temp_new(); - if (m || disp == 0) { - tcg_gen_mov_reg(addr, load_gpr(ctx, rb)); - } else { - tcg_gen_addi_reg(addr, load_gpr(ctx, rb), disp); - } + form_gva(ctx, &addr, &ofs, rb, 0, 0, disp, sp, m, + ctx->mmu_idx == MMU_PHYS_IDX); val = load_gpr(ctx, rt); - if (a) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { gen_helper_stby_e_parallel(cpu_env, addr, val); @@ -2744,11 +2770,9 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, } if (m) { - tcg_gen_addi_reg(addr, addr, disp); - tcg_gen_andi_reg(addr, addr, ~3); - save_gpr(ctx, rb, addr); + tcg_gen_andi_reg(ofs, ofs, ~3); + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); return nullify_end(ctx, DISAS_NEXT); } @@ -2813,15 +2837,18 @@ static DisasJumpType trans_load(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16(insn); - return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); + return do_load(ctx, rt, rb, 0, 0, i, sp, + is_mod ? (i < 0 ? -1 : 1) : 0, mop); } static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); @@ -2829,11 +2856,11 @@ static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) case 0: case 1: /* FLDW without modification. */ - return do_floadw(ctx, ext2 * 32 + rt, rb, 0, 0, i, 0); + return do_floadw(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: /* LDW with modification. Note that the sign of I selects post-dec vs pre-inc. */ - return do_load(ctx, rt, rb, 0, 0, i, (i < 0 ? 1 : -1), MO_TEUL); + return do_load(ctx, rt, rb, 0, 0, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); } @@ -2844,11 +2871,12 @@ static DisasJumpType trans_fload_mod(DisasContext *ctx, uint32_t insn) target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); + unsigned sp = extract32(insn, 14, 2); unsigned t0 = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); /* FLDW with modification. */ - return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); + return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1)); } static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, @@ -2856,15 +2884,17 @@ static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16(insn); - return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); + return do_store(ctx, rt, rb, i, sp, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); @@ -2872,10 +2902,10 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) case 0: case 1: /* FSTW without modification. */ - return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, 0); + return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: /* LDW with modification. */ - return do_store(ctx, rt, rb, i, (i < 0 ? 1 : -1), MO_TEUL); + return do_store(ctx, rt, rb, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); } @@ -2886,11 +2916,12 @@ static DisasJumpType trans_fstore_mod(DisasContext *ctx, uint32_t insn) target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); + unsigned sp = extract32(insn, 14, 2); unsigned t0 = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); /* FSTW with modification. */ - return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); + return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1)); } static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) @@ -2902,6 +2933,7 @@ static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) /* unsigned cc = extract32(insn, 10, 2); */ unsigned i = extract32(insn, 12, 1); unsigned ua = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); unsigned rt = t1 * 32 + t0; @@ -2921,9 +2953,9 @@ static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) switch (ext3) { case 0: /* FLDW */ - return do_floadw(ctx, rt, rb, rx, scale, disp, modify); + return do_floadw(ctx, rt, rb, rx, scale, disp, sp, modify); case 4: /* FSTW */ - return do_fstorew(ctx, rt, rb, rx, scale, disp, modify); + return do_fstorew(ctx, rt, rb, rx, scale, disp, sp, modify); } return gen_illegal(ctx); } @@ -2936,6 +2968,7 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) /* unsigned cc = extract32(insn, 10, 2); */ unsigned i = extract32(insn, 12, 1); unsigned ua = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); int modify = (m ? (ua ? -1 : 1) : 0); @@ -2954,9 +2987,9 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) switch (ext4) { case 0: /* FLDD */ - return do_floadd(ctx, rt, rb, rx, scale, disp, modify); + return do_floadd(ctx, rt, rb, rx, scale, disp, sp, modify); case 8: /* FSTD */ - return do_fstored(ctx, rt, rb, rx, scale, disp, modify); + return do_fstored(ctx, rt, rb, rx, scale, disp, sp, modify); default: return gen_illegal(ctx); } @@ -4197,8 +4230,10 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; bound = MIN(max_insns, bound); - ctx->ntemps = 0; - memset(ctx->temps, 0, sizeof(ctx->temps)); + ctx->ntempr = 0; + ctx->ntempl = 0; + memset(ctx->tempr, 0, sizeof(ctx->tempr)); + memset(ctx->templ, 0, sizeof(ctx->templ)); return bound; } @@ -4275,11 +4310,16 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } /* Free any temporaries allocated. */ - for (i = 0, n = ctx->ntemps; i < n; ++i) { - tcg_temp_free(ctx->temps[i]); - ctx->temps[i] = NULL; + for (i = 0, n = ctx->ntempr; i < n; ++i) { + tcg_temp_free(ctx->tempr[i]); + ctx->tempr[i] = NULL; + } + for (i = 0, n = ctx->ntempl; i < n; ++i) { + tcg_temp_free_tl(ctx->templ[i]); + ctx->templ[i] = NULL; } - ctx->ntemps = 0; + ctx->ntempr = 0; + ctx->ntempl = 0; /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ @@ -4389,7 +4429,7 @@ void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb, target_ulong *data) { env->iaoq_f = data[0]; - if (data[1] != -1) { + if (data[1] != (target_ureg)-1) { env->iaoq_b = data[1]; } /* Since we were executing the instruction at IAOQ_F, and took some From patchwork Mon Jan 22 03:41:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125311 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp948778ljf; Sun, 21 Jan 2018 20:02:41 -0800 (PST) X-Google-Smtp-Source: AH8x225+zgPMzCMfIweoEwWxz2T8GAT7AwNwvI7evnldNbBuxit5aA1n6QSBLXDFzg8XnBodjc+C X-Received: by 10.129.228.76 with SMTP id t12mr6018273ywl.257.1516593761604; Sun, 21 Jan 2018 20:02:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593761; cv=none; d=google.com; s=arc-20160816; b=Ir0Qkm00mr1C8G4bcbYG8YBjH6Bl1R2hlBs8XvErI7SZeuDtcg1PwioM2jM4m+gJBx NtekB1yL4iq68dECWGD7lYmkjheA2pBnUI+RA0NiknglEdSo4dW/qmMnMxxyQ/q99EMN 0QuQzYmUGjpfRs8Ymuh/x1Tz9YVYnTdvpL2AxzrO9w7vgd0SzRJFqWDHXngSMvJOq8/E TF4WJ2hKYuWPnNkaSClHfkg0cPqp/rLNzSH6rR1Wtp7ufweDLDjE1tIoXf7UrEbSvU1J B7n1ktbKR3PAs5yijjJJkh97z/nkKPnbWVBpO5GRs+pB0RC//ERbO1jm07tDFI6ylcrr mKEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6DGOByGOx5XP7BAi95PSS2uJDFdBZDsbbkccAC9ToPA=; b=Dk4hqQKssbqHgDVehymPGjYLV7U172vKSH8RVeUMw/3RHz5TLCWgoPH+/IQsaeu2/0 n7zPF01lMAvCs4ARMb7tqSqxGMBKwObE5Mw49rFxINEFG5nXBEd8sNShQZymg2gOWuQZ fO4auj3sIozTULKNNy9i9Zxa5iG2aECpPUinvniR/U1dfcot4nCvFUENYlGArPiFMUBr Ps+PMoIuphY6Gj1cbU4CHktcGn8UHjxfd1XePJ9UAmPCP3HuxAFxhBHMW0IYHxE9f6jO uklIuZr6RxZM1NMSqbVEp3jTA7dz8emCRVkd/HcEVdrzP+MmvJzGlSlUk2XCbTMusiNq 843Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G2QCZ84h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:49 -0800 Message-Id: <20180122034217.19593-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 15/43] target/hppa: Avoid privilege level decrease during branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These instructions force the destination privilege level of the branch destination to be no higher than current. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 5 deletions(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 0650c3e14e..53974c994e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1851,6 +1851,40 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv_reg dest, return DISAS_NEXT; } +/* Implement + * if (IAOQ_Front{30..31} < GR[b]{30..31}) + * IAOQ_Next{30..31} ← GR[b]{30..31}; + * else + * IAOQ_Next{30..31} ← IAOQ_Front{30..31}; + * which keeps the privilege level from being increased. + */ +static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) +{ +#ifdef CONFIG_USER_ONLY + return offset; +#else + TCGv_reg dest; + switch (ctx->privilege) { + case 0: + /* Privilege 0 is maximum and is allowed to decrease. */ + return offset; + case 3: + /* Privilege 3 is minimum and is never allowed increase. */ + dest = get_temp(ctx); + tcg_gen_ori_reg(dest, offset, 3); + break; + default: + dest = tcg_temp_new(); + tcg_gen_andi_reg(dest, offset, -4); + tcg_gen_ori_reg(dest, dest, ctx->privilege); + tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset); + tcg_temp_free(dest); + break; + } + return dest; +#endif +} + #ifdef CONFIG_USER_ONLY /* On Linux, page zero is normally marked execute only + gateway. Therefore normal read or write is supposed to fail, but specific @@ -3430,6 +3464,7 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) unsigned n = extract32(insn, 1, 1); unsigned b = extract32(insn, 21, 5); target_sreg disp = assemble_17(insn); + TCGv_reg tmp; /* unsigned s = low_uextract(insn, 13, 3); */ /* ??? It seems like there should be a good way of using @@ -3438,16 +3473,19 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) manage along side branch delay slots. Therefore we handle entry into the gateway page via absolute address. */ +#ifdef CONFIG_USER_ONLY /* Since we don't implement spaces, just branch. Do notice the special case of "be disp(*,r0)" using a direct branch to disp, so that we can goto_tb to the TB containing the syscall. */ if (b == 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); - } else { - TCGv_reg tmp = get_temp(ctx); - tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); - return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } +#endif + + tmp = get_temp(ctx); + tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); + tmp = do_ibranch_priv(ctx, tmp); + return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, @@ -3479,6 +3517,7 @@ static DisasJumpType trans_blr(DisasContext *ctx, uint32_t insn, tcg_gen_shli_reg(tmp, load_gpr(ctx, rx), 3); tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); + /* The computation here never changes privilege level. */ return do_ibranch(ctx, tmp, link, n); } @@ -3497,6 +3536,7 @@ static DisasJumpType trans_bv(DisasContext *ctx, uint32_t insn, tcg_gen_shli_reg(dest, load_gpr(ctx, rx), 3); tcg_gen_add_reg(dest, dest, load_gpr(ctx, rb)); } + dest = do_ibranch_priv(ctx, dest); return do_ibranch(ctx, dest, 0, n); } @@ -3506,8 +3546,10 @@ static DisasJumpType trans_bve(DisasContext *ctx, uint32_t insn, unsigned n = extract32(insn, 1, 1); unsigned rb = extract32(insn, 21, 5); unsigned link = extract32(insn, 13, 1) ? 2 : 0; + TCGv_reg dest; - return do_ibranch(ctx, load_gpr(ctx, rb), link, n); + dest = do_ibranch_priv(ctx, load_gpr(ctx, rb)); + return do_ibranch(ctx, dest, link, n); } static const DisasInsn table_branch[] = { From patchwork Mon Jan 22 03:41:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125307 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp947070ljf; Sun, 21 Jan 2018 19:57:12 -0800 (PST) X-Google-Smtp-Source: AH8x225ediktyeJ8znurVnjJ5gMPgxUVswor4MgN5HiL3UgFqByrMDP6L+EwkjnqhvM6XfsuIDWL X-Received: by 10.37.234.4 with SMTP id p4mr2270479ybd.358.1516593432255; Sun, 21 Jan 2018 19:57:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593432; cv=none; d=google.com; s=arc-20160816; b=GdSbgxEBP49Q1qOfqi46/WxZPrs+BWxBeGY1uwMSxYXZlchqamn8T1QyFs8milQYAS JU01/pbGrMgCX0WXJDqq4xFtJeerAZlXEhjBdt2bWSKpd8kClFCwle6DSRoP3mZg59tg EJo5VBJlcB5rEih0H4nyauvEvg6mPkst1WCvM0ALjoKZMGsHyy1HxPpdL9JV9GJ2B+SJ jLeCkG7wFyYSywPrrbubymZJu9IY9owvmVbtB+zoO0JZzju1cyM2UGOxVjzzWz7C/dtS HaLlG90FhtP3wsLz0x2BUz3MBZuAqDh+JgW+fXHxbIHZFJtedME53XonerBH458xfbQp XYUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8eQnzj06xQhSLvMSt/uaqj9Ar31IWKr6Ibn8VxItBpM=; b=cXWF823gr6PEl8hZdRmCNSh0TI/QLD4986M1G2QHSJxKN2pN+TncLW7g+vPJ06iipI flwQglwWCjesUY83jscTgc6Ch73DynZkOGEFJ2pro85vRsHr7IkSQQk2tv68sBQr55Nt xlhhhJaYsGaHJAvrkdunLB5rfyOdaCV1ow3xuqhQT4og/Me3rxGmMYZzibr3mbfQ1Dc2 nQvDYckjUefHf3EOWh7oeANn7SYjIVQQg6Qv5ouv4blfSYy+TacvPFbrgu2eQy+nl2uM H5WW4sDn5Ty+x58hwb+3PN8bOSBUnkbnMO7rU7wDJgsvfv3NPmK7dO7shPcJbLvL/gsA ST/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U+5xW5pE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:50 -0800 Message-Id: <20180122034217.19593-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PULL 16/43] target/hppa: Implement IASQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Any one TB will have only one space value. If we change spaces, we change TBs. Thus BE and BEV must exit the TB immediately. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 53 ++++++++++++++++++++- target/hppa/cpu.c | 15 ++++++ target/hppa/helper.c | 3 +- target/hppa/int_helper.c | 16 +++++-- target/hppa/op_helper.c | 2 + target/hppa/translate.c | 117 ++++++++++++++++++++++++++++++++++++++--------- 6 files changed, 179 insertions(+), 27 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 94f9c8ca2b..d583ea43dd 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -186,6 +186,8 @@ struct CPUHPPAState { target_ureg iaoq_f; /* front */ target_ureg iaoq_b; /* back, aka next instruction */ + uint64_t iasq_f; + uint64_t iasq_b; uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; @@ -240,15 +242,62 @@ void hppa_translate_init(void); void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf); +static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, + target_ureg off) +{ +#ifdef CONFIG_USER_ONLY + return off; +#else + off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + return spc | off; +#endif +} + +static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, + target_ureg off) +{ + return hppa_form_gva_psw(env->psw, spc, off); +} + +/* Since PSW_CB will never need to be in tb->flags, reuse them. */ +#define TB_FLAG_PRIV_SHIFT 8 + static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { + uint32_t flags = env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu priviledge from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY *pc = env->iaoq_f; *cs_base = env->iaoq_b; +#else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ - *pflags = (env->psw & (PSW_W | PSW_C | PSW_D)) - | env->psw_n * PSW_N; + flags |= env->psw & (PSW_W | PSW_C | PSW_D); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc = (env->psw & PSW_C + ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) + : env->iaoq_f & -4); + *cs_base = env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a page. + Failure is indicated by a zero difference. */ + if (env->iasq_f == env->iasq_b) { + target_sreg diff = env->iaoq_b - env->iaoq_f; + if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { + *cs_base |= (uint32_t)diff; + } + } +#endif + + *pflags = flags; } target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6b2d22118d..237d2b8ab5 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -37,8 +37,23 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) { HPPACPU *cpu = HPPA_CPU(cs); +#ifdef CONFIG_USER_ONLY cpu->env.iaoq_f = tb->pc; cpu->env.iaoq_b = tb->cs_base; +#else + /* Recover the IAOQ values from the GVA + PRIV. */ + uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; + target_ulong cs_base = tb->cs_base; + target_ulong iasq_f = cs_base & ~0xffffffffull; + int32_t diff = cs_base; + + cpu->env.iasq_f = iasq_f; + cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; + if (diff) { + cpu->env.iaoq_b = cpu->env.iaoq_f + diff; + } +#endif + cpu->env.psw_n = (tb->flags & PSW_N) != 0; } diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 6e8758f82c..858ec205b6 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -78,7 +78,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int i; cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", - (target_ulong)env->iaoq_f, (target_ulong)env->iaoq_b); + hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), + hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 34413c30e1..297aa62c24 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -32,6 +32,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) int i = cs->exception_index; target_ureg iaoq_f = env->iaoq_f; target_ureg iaoq_b = env->iaoq_b; + uint64_t iasq_f = env->iasq_f; + uint64_t iasq_b = env->iasq_b; #ifndef CONFIG_USER_ONLY target_ureg old_psw; @@ -44,6 +46,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0)); /* step 3 */ + env->cr[CR_IIASQ] = iasq_f >> 32; + env->cr_back[0] = iasq_b >> 32; env->cr[CR_IIAOQ] = iaoq_f; env->cr_back[1] = iaoq_b; @@ -78,6 +82,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) hwaddr paddr; paddr = vaddr = iaoq_f & -4; + if (old_psw & PSW_C) { + vaddr = hppa_form_gva_psw(old_psw, iasq_f, iaoq_f & -4); + } env->cr[CR_IIR] = ldl_phys(cs->as, paddr); } break; @@ -101,6 +108,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 7 */ env->iaoq_f = env->cr[CR_IVA] + 32 * i; env->iaoq_b = env->iaoq_f + 4; + env->iasq_f = 0; + env->iasq_b = 0; #endif if (qemu_loglevel_mask(CPU_LOG_INT)) { @@ -151,10 +160,11 @@ void hppa_cpu_do_interrupt(CPUState *cs) qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", ++count, name, - (target_ulong)iaoq_f, - (target_ulong)iaoq_b, + hppa_form_gva(env, iasq_f, iaoq_f), + hppa_form_gva(env, iasq_b, iaoq_b), env->iaoq_f, - (target_ulong)env->cr[CR_IOR]); + hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32, + env->cr[CR_IOR])); } cs->exception_index = -1; } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 3f5dcbbca0..1963b2439b 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -622,6 +622,8 @@ void HELPER(rfi)(CPUHPPAState *env) if (env->psw & (PSW_I | PSW_R | PSW_Q)) { helper_excp(env, EXCP_ILL); } + env->iasq_f = (uint64_t)env->cr[CR_IIASQ] << 32; + env->iasq_b = (uint64_t)env->cr_back[0] << 32; env->iaoq_f = env->cr[CR_IIAOQ]; env->iaoq_b = env->cr_back[1]; cpu_hppa_put_psw(env, env->cr[CR_IPSW]); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 53974c994e..f0ee6be052 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -321,6 +321,8 @@ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; +static TCGv_i64 cpu_iasq_f; +static TCGv_i64 cpu_iasq_b; static TCGv_reg cpu_sar; static TCGv_reg cpu_psw_n; static TCGv_reg cpu_psw_v; @@ -376,6 +378,13 @@ void hppa_translate_init(void) const GlobalVar *v = &vars[i]; *v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name); } + + cpu_iasq_f = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, iasq_f), + "iasq_f"); + cpu_iasq_b = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, iasq_b), + "iasq_b"); } static DisasCond cond_make_f(void) @@ -1749,6 +1758,11 @@ static DisasJumpType do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); + if (ctx->iaoq_n == -1) { + /* The temporary iaoq_n_var died at the branch above. + Regenerate it here instead of saving it. */ + tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); + } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } @@ -1790,11 +1804,17 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv_reg dest, } next = get_temp(ctx); tcg_gen_mov_reg(next, dest); - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; if (is_n) { + if (use_nullify_skip(ctx)) { + tcg_gen_mov_reg(cpu_iaoq_f, next); + tcg_gen_addi_reg(cpu_iaoq_b, next, 4); + nullify_set(ctx, 0); + return DISAS_IAQ_N_UPDATED; + } ctx->null_cond.c = TCG_COND_ALWAYS; } + ctx->iaoq_n = -1; + ctx->iaoq_n_var = next; } else if (is_n && use_nullify_skip(ctx)) { /* The (conditional) branch, B, nullifies the next insn, N, and we're allowed to skip execution N (no single-step or @@ -3466,26 +3486,55 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) target_sreg disp = assemble_17(insn); TCGv_reg tmp; - /* unsigned s = low_uextract(insn, 13, 3); */ +#ifdef CONFIG_USER_ONLY /* ??? It seems like there should be a good way of using "be disp(sr2, r0)", the canonical gateway entry mechanism to our advantage. But that appears to be inconvenient to manage along side branch delay slots. Therefore we handle entry into the gateway page via absolute address. */ - -#ifdef CONFIG_USER_ONLY /* Since we don't implement spaces, just branch. Do notice the special case of "be disp(*,r0)" using a direct branch to disp, so that we can goto_tb to the TB containing the syscall. */ if (b == 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); } +#else + int sp = assemble_sr3(insn); + nullify_over(ctx); #endif tmp = get_temp(ctx); tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); tmp = do_ibranch_priv(ctx, tmp); + +#ifdef CONFIG_USER_ONLY return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); +#else + TCGv_i64 new_spc = tcg_temp_new_i64(); + + load_spr(ctx, new_spc, sp); + if (is_l) { + copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); + tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); + } + if (n && use_nullify_skip(ctx)) { + tcg_gen_mov_reg(cpu_iaoq_f, tmp); + tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_i64(cpu_iasq_f, new_spc); + tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + } else { + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + if (ctx->iaoq_b == -1) { + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + } + tcg_gen_mov_reg(cpu_iaoq_b, tmp); + tcg_gen_mov_i64(cpu_iasq_b, new_spc); + nullify_set(ctx, n); + } + tcg_temp_free_i64(new_spc); + tcg_gen_lookup_and_goto_ptr(); + return nullify_end(ctx, DISAS_NORETURN); +#endif } static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, @@ -3548,8 +3597,26 @@ static DisasJumpType trans_bve(DisasContext *ctx, uint32_t insn, unsigned link = extract32(insn, 13, 1) ? 2 : 0; TCGv_reg dest; +#ifdef CONFIG_USER_ONLY dest = do_ibranch_priv(ctx, load_gpr(ctx, rb)); return do_ibranch(ctx, dest, link, n); +#else + nullify_over(ctx); + dest = do_ibranch_priv(ctx, load_gpr(ctx, rb)); + + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + if (ctx->iaoq_b == -1) { + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + } + copy_iaoq_entry(cpu_iaoq_b, -1, dest); + tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); + if (link) { + copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); + } + nullify_set(ctx, n); + tcg_gen_lookup_and_goto_ptr(); + return nullify_end(ctx, DISAS_NORETURN); +#endif } static const DisasInsn table_branch[] = { @@ -4256,15 +4323,21 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_USER_IDX; ctx->mmu_idx = MMU_USER_IDX; + ctx->iaoq_f = ctx->base.pc_first; + ctx->iaoq_b = ctx->base.tb->cs_base; #else - ctx->privilege = ctx->base.pc_first & 3; + ctx->privilege = (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->base.tb->flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); -#endif - ctx->iaoq_f = ctx->base.pc_first; - ctx->iaoq_b = ctx->base.tb->cs_base; - ctx->base.pc_first &= -4; + /* Recover the IAOQ values from the GVA + PRIV. */ + uint64_t cs_base = ctx->base.tb->cs_base; + uint64_t iasq_f = cs_base & ~0xffffffffull; + int32_t diff = cs_base; + + ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); +#endif ctx->iaoq_n = -1; ctx->iaoq_n_var = NULL; @@ -4307,7 +4380,7 @@ static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next = (ctx->iaoq_f & -4) + 4; + ctx->base.pc_next += 4; return true; } @@ -4320,7 +4393,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Execute one insn. */ #ifdef CONFIG_USER_ONLY - if (ctx->iaoq_f < TARGET_PAGE_SIZE) { + if (ctx->base.pc_next < TARGET_PAGE_SIZE) { ret = do_page_zero(ctx); assert(ret != DISAS_NEXT); } else @@ -4328,7 +4401,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f & -4); + uint32_t insn = cpu_ldl_code(env, ctx->base.pc_next); /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ @@ -4366,18 +4439,21 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (ctx->null_cond.c == TCG_COND_NEVER - || ctx->null_cond.c == TCG_COND_ALWAYS) { + if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 + && use_goto_tb(ctx, ctx->iaoq_b) + && (ctx->null_cond.c == TCG_COND_NEVER + || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); ret = DISAS_NORETURN; } else { ret = DISAS_IAQ_N_STALE; - } + } } ctx->iaoq_f = ctx->iaoq_b; ctx->iaoq_b = ctx->iaoq_n; ctx->base.is_jmp = ret; + ctx->base.pc_next += 4; if (ret == DISAS_NORETURN || ret == DISAS_IAQ_N_UPDATED) { return; @@ -4385,6 +4461,9 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) if (ctx->iaoq_f == -1) { tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); +#ifndef CONFIG_USER_ONLY + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); +#endif nullify_save(ctx); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; } else if (ctx->iaoq_b == -1) { @@ -4419,15 +4498,11 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) default: g_assert_not_reached(); } - - /* We don't actually use this during normal translation, - but we should interact with the generic main loop. */ - ctx->base.pc_next = ctx->base.pc_first + 4 * ctx->base.num_insns; } static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { - target_ureg pc = dcbase->pc_first; + target_ulong pc = dcbase->pc_first; #ifdef CONFIG_USER_ONLY switch (pc) { From patchwork Mon Jan 22 03:41:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125303 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp946022ljf; Sun, 21 Jan 2018 19:53:59 -0800 (PST) X-Google-Smtp-Source: AH8x2244bKKgvip+7ytHSrlGt8Ds1grQrs7MXJ7gBtXXxZAOSJammSJI7v3+1ST5hZlgRuY2MRLl X-Received: by 10.37.30.84 with SMTP id e81mr2926473ybe.219.1516593239525; Sun, 21 Jan 2018 19:53:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593239; cv=none; d=google.com; s=arc-20160816; b=KJcwSnM4Ck2Lwet1tptLaYaGjMlp7sBUu1YuPysULRn+ij/Ks0RdgZ8SFQc11QmiYS pn3Sfdqu42hrcpMWC7zwiAcLHjttwhx0oE/XgNo91xrPJ2USDg4HTs8+BSF6uYPGf2rB hObhDqCMPq7jzt7csEjSEQ3GZ2tlA4mSxdiCVeuAPq7ZQ3wMfz3q6e3OM8vjTew3FaCA ExYptFLY1qlCFVKbCOuXIyfFdpxR3nNdcdiuD7sXTcQfEjMsAdRrV3L1ICi0lHje9Q+n 8gDE9LEV/WiNk9bpY7UBIFgt2dQjFxYHHWVBjAuf+pWt2vBLN/puYnS7u2PiZjhcbLNX BkGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=1NVSr064ONmjc3rvdqkvs7F6I+bFkP18U337rg7NEi0=; b=EgvgkX6K337xjN9XBDLwYKW5p+oxqnFDdmE7PQClN46AJp4lkqei3zUqK5/qaftnFk uTXF5Z5MCKsbORW2Eh2agcjTVPn8CjN3t4eBNzVY53ngZXHtYySLfW6LP/6BbJDUk/AR mSl89maO5jElpDIINLWY4fKRP2PzlP3sLxyCeINmYpZGB4KOV1YPDCkm4AxEkFpI7kJN Ja7eAyAp7BPV68TDtoMLB2/hXHWQ6vcA/QK0yrTr88zJtdqeu12pm73MbjUItt2JBxHp 16woZieoQBZzoSJZ8GWLXa5r0dcT+c8ljQ5TcDPRCyr+PfpS3NcCjJg+fVrR+AYWhCaQ OWsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Cf8zWXDu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:51 -0800 Message-Id: <20180122034217.19593-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 17/43] target/hppa: Implement tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 29 ++++++++- target/hppa/int_helper.c | 12 ++++ target/hppa/mem_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 184 insertions(+), 6 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d583ea43dd..c7a2fb5b20 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -165,6 +165,22 @@ typedef int64_t target_sreg; #define TREG_FMT_ld "%"PRId64 #endif +typedef struct { + uint64_t va_b; + uint64_t va_e; + target_ureg pa; + unsigned u : 1; + unsigned t : 1; + unsigned d : 1; + unsigned b : 1; + unsigned page_size : 4; + unsigned ar_type : 3; + unsigned ar_pl1 : 2; + unsigned ar_pl2 : 2; + unsigned entry_valid : 1; + unsigned access_id : 16; +} hppa_tlb_entry; + struct CPUHPPAState { target_ureg gr[32]; uint64_t fr[32]; @@ -198,6 +214,12 @@ struct CPUHPPAState { /* Those resources are used only in QEMU core */ CPU_COMMON + + /* ??? The number of entries isn't specified by the architecture. */ + /* ??? Implement a unified itlb/dtlb for the moment. */ + /* ??? We should use a more intelligent data structure. */ + hppa_tlb_entry tlb[256]; + uint32_t tlb_last; }; /** @@ -307,12 +329,17 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int); +#ifdef CONFIG_USER_ONLY +int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); +#else +int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, + MMUAccessType type, hwaddr *pphys, int *pprot); +#endif #endif /* HPPA_CPU_H */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 297aa62c24..e66ca26941 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -78,12 +78,24 @@ void hppa_cpu_do_interrupt(CPUState *cs) { /* Avoid reading directly from the virtual address, lest we raise another exception from some sort of TLB issue. */ + /* ??? An alternate fool-proof method would be to store the + instruction data into the unwind info. That's probably + a bit too much in the way of extra storage required. */ vaddr vaddr; hwaddr paddr; paddr = vaddr = iaoq_f & -4; if (old_psw & PSW_C) { + int prot, t; + vaddr = hppa_form_gva_psw(old_psw, iasq_f, iaoq_f & -4); + t = hppa_get_physical_address(env, vaddr, 0, MMU_INST_FETCH, + &paddr, &prot); + if (t >= 0) { + /* We can't re-load the instruction. */ + env->cr[CR_IIR] = 0; + break; + } } env->cr[CR_IIR] = ldl_phys(cs->as, paddr); } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 1afaf89539..4e92e35957 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -36,18 +36,157 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, return 1; } #else +static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) { + hppa_tlb_entry *ent = &env->tlb[i]; + if (ent->va_b <= addr && addr <= ent->va_e && ent->entry_valid) { + return ent; + } + } + return NULL; +} + +int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, + MMUAccessType type, hwaddr *pphys, int *pprot) +{ + hwaddr phys; + int prot, ret, r_prot, w_prot, x_prot, a_prot; + bool ifetch = type == MMU_INST_FETCH; + hppa_tlb_entry *ent; + + /* Virtual translation disabled. Direct map virtual to physical. */ + if (mmu_idx == MMU_PHYS_IDX) { + phys = addr; + prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + ret = -1; + goto egress; + } + + /* Find a valid tlb entry that matches the virtual address. */ + ent = hppa_find_tlb(env, addr); + if (ent == NULL) { + phys = 0; + prot = 0; + ret = (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); + goto egress; + } + + /* We now know the physical address. */ + phys = ent->pa + (addr & ~TARGET_PAGE_MASK); + + /* Map TLB access_rights field to QEMU protection. */ + r_prot = (mmu_idx <= ent->ar_pl1 ? PROT_READ : 0); + w_prot = (mmu_idx <= ent->ar_pl2 ? PROT_WRITE : 0); + x_prot = (ent->ar_pl2 <= mmu_idx && mmu_idx <= ent->ar_pl1 ? PROT_EXEC : 0); + switch (ent->ar_type) { + case 0: /* read-only: data page */ + prot = r_prot; + break; + case 1: /* read/write: dynamic data page */ + prot = r_prot | w_prot; + break; + case 2: /* read/execute: normal code page */ + prot = r_prot | x_prot; + break; + case 3: /* read/write/execute: dynamic code page */ + prot = r_prot | w_prot | x_prot; + break; + default: /* execute: promote to privilege level type & 3 */ + prot = x_prot; + } + + /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. */ + + /* Map MMUAccessType to QEMU protection. */ + if (ifetch) { + a_prot = PROT_EXEC; + } else if (type == MMU_DATA_STORE) { + a_prot = PROT_WRITE; + } else { + a_prot = PROT_READ; + } + + if (unlikely(!(prot & a_prot))) { + /* The access isn't allowed -- Inst/Data Memory Protection Fault. */ + ret = (ifetch ? EXCP_IMP : EXCP_DMP); + goto egress; + } + + /* In reverse priority order, check for conditions which raise faults. + As we go, remove PROT bits that cover the condition we want to check. + In this way, the resulting PROT will force a re-check of the + architectural TLB entry for the next access. */ + ret = -1; + if (unlikely(!ent->d)) { + if (type == MMU_DATA_STORE) { + /* The D bit is not set -- TLB Dirty Bit Fault. */ + ret = EXCP_TLB_DIRTY; + } + prot &= PROT_READ | PROT_EXEC; + } + if (unlikely(ent->b)) { + if (type == MMU_DATA_STORE) { + /* The B bit is set -- Data Memory Break Fault. */ + ret = EXCP_DMB; + } + prot &= PROT_READ | PROT_EXEC; + } + if (unlikely(ent->t)) { + if (!ifetch) { + /* The T bit is set -- Page Reference Fault. */ + ret = EXCP_PAGE_REF; + } + prot &= PROT_EXEC; + } + + egress: + *pphys = phys; + *pprot = prot; + return ret; +} + hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - /* Stub */ - return addr; + HPPACPU *cpu = HPPA_CPU(cs); + hwaddr phys; + int prot, excp; + + /* If the (data) mmu is disabled, bypass translation. */ + /* ??? We really ought to know if the code mmu is disabled too, + in order to get the correct debugging dumps. */ + if (!(cpu->env.psw & PSW_D)) { + return addr; + } + + excp = hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, + MMU_DATA_LOAD, &phys, &prot); + + /* Since we're translating for debugging, the only error that is a + hard error is no translation at all. Otherwise, while a real cpu + access might not have permission, the debugger does. */ + return excp == EXCP_DTLB_MISS ? -1 : phys; } void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, int mmu_idx, uintptr_t retaddr) { - /* Stub */ - int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - hwaddr phys = addr; + HPPACPU *cpu = HPPA_CPU(cs); + int prot, excp; + hwaddr phys; + + excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, + type, &phys, &prot); + if (unlikely(excp >= 0)) { + /* Failure. Raise the indicated exception. */ + cs->exception_index = excp; + /* ??? Needs tweaking for hppa64. */ + cpu->env.cr[CR_IOR] = addr; + cpu->env.cr[CR_ISR] = addr >> 32; + cpu_loop_exit_restore(cs, retaddr); + } /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, From patchwork Mon Jan 22 03:41:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125309 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp947278ljf; Sun, 21 Jan 2018 19:57:56 -0800 (PST) X-Google-Smtp-Source: AH8x224AQ6NB2D9hH202dK1k8GqlWhvpvj/sys3J7W3LHFwYgmpx9uU4QSDguORsv8cKX7bbaB1n X-Received: by 10.13.233.7 with SMTP id s7mr6158189ywe.208.1516593476352; Sun, 21 Jan 2018 19:57:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593476; cv=none; d=google.com; s=arc-20160816; b=MjWCXBf3ulZLcGrZ1YjHS+Hv1Z3SOV0wteNyEr2ae8M3j+JZFLLkK3VYfeZAoVJJxv tR/0hUiINI/Y7XNyCZ7nwDGgMDSxs6A/4hGiVPG5LDAokvwl/5O5UTm8fdRrSXMfy+7R pl3qLPbtTvaQ67B7ejzFjeHKcbbUgEjO1+hW8dxKsVtjM6o60pGb6DD25fLnDBLtBHM/ Lop2FU8m09SutUwmfYx7NFsGIMEk45ZT/4Vs9yyTZlI9IPBqKm1vMPQWcAaykVSc3P16 E/QXFnoed6IFRqKSfAhanSnZCNEMA1plkGgv4SJBj5VCe2AtrpoTEr0I6D6USl/2VC46 Y1rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Wc/CoNMqsyKqJodnheiaplEPKVpkUJ1XJf9Pg7DmoME=; b=0Ye9UCbv87P9Heas1geRjnMe548JRZ8mDOvTb8R0AvHPXfMOryd+iUfDMkSkMdDVjq oB4zHL3BqzrkQgRybkHGlniTf5kE8TILJQdWtKugF+pJSYwrr3YJfZHamzIysjysMuzI 0LBWH10gAuTgvWLc+gcPX95WK6UjRISkB6dadFU6PDFFEY266TuunAS7gKiv4O18hzmd rshjB7RIM/yRFgaYZU5xTtzPFdrUJ/DzTomtCh5Lw8CKdoF06kzWPkoyt1/MYcgrgw3J 14B6Qt5GJD/uDFHlLiHIzk9G+X8/TWEAeg59sxaajbG0Fa5Y31+4phZ2vm19qhh4fYfQ tIjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=byZZq1GB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 18/43] target/hppa: Implement external interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 2 ++ target/hppa/cpu.c | 6 +++++ target/hppa/int_helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++++++++++- 5 files changed, 83 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c7a2fb5b20..fc3e62c0af 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -340,6 +340,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); #else int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot); +extern const MemoryRegionOps hppa_io_eir_ops; #endif #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 79d22ae486..535f086ab4 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -80,5 +80,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) +DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 237d2b8ab5..7837d10381 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -57,6 +57,11 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.psw_n = (tb->flags & PSW_N) != 0; } +static bool hppa_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach = bfd_mach_hppa20; @@ -157,6 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) dc->realize = hppa_cpu_realizefn; cc->class_by_name = hppa_cpu_class_by_name; + cc->has_work = hppa_cpu_has_work; cc->do_interrupt = hppa_cpu_do_interrupt; cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt; cc->dump_state = hppa_cpu_dump_state; diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index e66ca26941..74ab34f306 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -24,6 +24,65 @@ #include "exec/helper-proto.h" #include "qom/cpu.h" +#ifndef CONFIG_USER_ONLY +static void eval_interrupt(HPPACPU *cpu) +{ + CPUState *cs = CPU(cpu); + if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus + * can write to this word to raise an external interrupt on the target CPU. + * This includes the system controler (DINO) for regular devices, or + * another CPU for SMP interprocessor interrupts. + */ +static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size) +{ + HPPACPU *cpu = opaque; + + /* ??? What does a read of this register over the GSC bus do? */ + return cpu->env.cr[CR_EIRR]; +} + +static void io_eir_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + HPPACPU *cpu = opaque; + int le_bit = ~data & (TARGET_REGISTER_BITS - 1); + + cpu->env.cr[CR_EIRR] |= (target_ureg)1 << le_bit; + eval_interrupt(cpu); +} + +const MemoryRegionOps hppa_io_eir_ops = { + .read = io_eir_read, + .write = io_eir_write, + .valid.min_access_size = 4, + .valid.max_access_size = 4, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + +void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIRR] &= ~val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} + +void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIEM] = val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} +#endif /* !CONFIG_USER_ONLY */ void hppa_cpu_do_interrupt(CPUState *cs) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f0ee6be052..cac21dbe2f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2113,12 +2113,25 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, /* All other control registers are privileged or read-only. */ CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + DisasJumpType ret = DISAS_NEXT; + nullify_over(ctx); switch (ctl) { case CR_IT: /* ??? modify interval timer offset */ break; + case CR_EIRR: + gen_helper_write_eirr(cpu_env, reg); + break; + case CR_EIEM: + gen_helper_write_eiem(cpu_env, reg); + ret = DISAS_IAQ_N_STALE_EXIT; + break; + case CR_IIASQ: case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ @@ -2135,7 +2148,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); break; } - return nullify_end(ctx, DISAS_NEXT); + return nullify_end(ctx, ret); +#endif } static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, From patchwork Mon Jan 22 03:41:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125315 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp949219ljf; Sun, 21 Jan 2018 20:04:08 -0800 (PST) X-Google-Smtp-Source: AH8x226YBoub0rEtBFYafwZqp6oexTmJcskXsKqtceIxuIID4cuRXZHCS+TzauqDI2fOG/fgz+Jw X-Received: by 10.129.108.2 with SMTP id h2mr6212988ywc.445.1516593848539; Sun, 21 Jan 2018 20:04:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593848; cv=none; d=google.com; s=arc-20160816; b=E7iVX4jb3W1stpOifXrs51jWv7spCJ1v6CJsAyri8Eq7+xb/2wrmgYG6WfH9tJKyGY 05U4GM9Xr4YETKHBm8iFEpNFzWxLkC6EeNRFuUMYLwPf1PmPWIAiFqxw7IyDOWuD6zIo tLC/FbwghDHu1p1Kiz80XFxIGOsKDEeBNmjC1dkgfCwyO8EsRInDfwiyw6j80X+RCak9 b1hRUNpf8jt7GSvRU2BSEltgXig0nAKmwCesaBa/I0Ypoq4Sm5OUHe2eGQIKSNKS7w3C RJ5y9tzcOpnNffYaRp2b62Edtj7/WeO3Kk0B/x9u2D2qDCZR/3221yeJwDzJLYiU6u3t jLnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YPEFO9LPohXVn9BoGQ5BmL2jQ6ehS0wU1b426MxvHpg=; b=E71w/UWeBH8Ayq0nXVpPF+Q6xCPBENC+pStTyYL7qkIZRlL0s+vPf7EvYDMbwCkabe 7lso0iU3p7pfmqb4ySlv65xZZq+3e7G1yQc7zrW4YfTCS4CFNPTgHy5Jip5Tm7n2ItSJ nBO/mCxQlUzxJ3OmywBFxq+4Bx8S4w3Wa2R3ZQpPyLh3CKb3PzgUzyEJ6x7lBP6hkeXe ZR8Ddfi9CQTmKFjtptQwbdnn3JMxGwaFpdUsntzzfgRuW+becNaxvR4NTXWIatZccYPn hvGIKgWY5qRs1sN/EGjw0cyAkU/DUWxCRhX6Pel59Uf/DnVla0DO+wld0Ovp+b1Fdg6Q Y/UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cfbJXKRz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:53 -0800 Message-Id: <20180122034217.19593-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 19/43] target/hppa: Implement the interval timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/helper.h | 3 +++ target/hppa/cpu.c | 8 ++++++++ target/hppa/int_helper.c | 6 ++++++ target/hppa/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++++++++++---- 6 files changed, 67 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fc3e62c0af..31a3702684 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -234,6 +234,7 @@ struct HPPACPU { /*< public >*/ CPUHPPAState env; + QEMUTimer *alarm_timer; }; static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) @@ -341,6 +342,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; +void hppa_cpu_alarm_timer(void *); #endif #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 535f086ab4..744b11cb66 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -77,9 +77,12 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) + #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7837d10381..86f5cb0bfe 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -97,6 +97,14 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); acc->parent_realize(dev, errp); + +#ifndef CONFIG_USER_ONLY + { + HPPACPU *cpu = HPPA_CPU(cs); + cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + hppa_cpu_alarm_timer, cpu); + } +#endif } /* Sort hppabetically by type name. */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 74ab34f306..ee72769544 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -67,6 +67,12 @@ const MemoryRegionOps hppa_io_eir_ops = { .impl.max_access_size = 4, }; +void hppa_cpu_alarm_timer(void *opaque) +{ + /* Raise interrupt 0. */ + io_eir_write(opaque, 0, 0, 4); +} + void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) { env->cr[CR_EIRR] &= ~val; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 1963b2439b..6d19cab6c9 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,8 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include "qemu/timer.h" + void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { @@ -602,7 +604,41 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c) return ret; } +target_ureg HELPER(read_interval_timer)(void) +{ +#ifdef CONFIG_USER_ONLY + /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. + Just pass through the host cpu clock ticks. */ + return cpu_get_host_ticks(); +#else + /* In system mode we have access to a decent high-resolution clock. + In order to make OS-level time accounting work with the cr16, + present it with a well-timed clock fixed at 250MHz. */ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2; +#endif +} + #ifndef CONFIG_USER_ONLY +void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) +{ + HPPACPU *cpu = hppa_env_get_cpu(env); + uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t timeout; + + /* Even in 64-bit mode, the comparator is always 32-bit. But the + value we expose to the guest is 1/4 of the speed of the clock, + so moosh in 34 bits. */ + timeout = deposit64(current, 0, 34, (uint64_t)val << 2); + + /* If the mooshing puts the clock in the past, advance to next round. */ + if (timeout < current + 1000) { + timeout += 1ULL << 34; + } + + cpu->env.cr[CR_IT] = timeout; + timer_mod(cpu->alarm_timer, timeout); +} + target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw = env->psw; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cac21dbe2f..cad661e39f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2027,6 +2027,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); unsigned ctl = extract32(insn, 21, 5); TCGv_reg tmp; + DisasJumpType ret; switch (ctl) { case CR_SAR: @@ -2045,9 +2046,17 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp = dest_gpr(ctx, rt); - tcg_gen_movi_reg(tmp, 0); /* FIXME */ + if (ctx->base.tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + gen_helper_read_interval_timer(tmp); + gen_io_end(); + ret = DISAS_IAQ_N_STALE; + } else { + gen_helper_read_interval_timer(tmp); + ret = DISAS_NEXT; + } save_gpr(ctx, rt, tmp); - break; + return nullify_end(ctx, ret); case 26: case 27: break; @@ -2121,9 +2130,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, nullify_over(ctx); switch (ctl) { case CR_IT: - /* ??? modify interval timer offset */ + gen_helper_write_interval_timer(cpu_env, reg); break; - case CR_EIRR: gen_helper_write_eirr(cpu_env, reg); break; From patchwork Mon Jan 22 03:41:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125305 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp946781ljf; Sun, 21 Jan 2018 19:56:08 -0800 (PST) X-Google-Smtp-Source: AH8x224VHcd2aUrDGMK/oQIpp8mwD1k/xOU8/81E/XVX6ngaA0467kA5inYme1PZ/T2KwfmXuV1/ X-Received: by 10.129.116.8 with SMTP id p8mr6249594ywc.386.1516593368420; Sun, 21 Jan 2018 19:56:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593368; cv=none; d=google.com; s=arc-20160816; b=0kPFPBgWUJ31jIb5ZbLX5xVLajsEu7Zy0KaaegNRgP5KPdLMRhuTUot53HfRZ9T1Ky UGPTm3G4Vz3bSdY56kXeENO8pNlPh1C5MBFn1EPE6woaS12gDpOt2e91uRTT3Wnfv5PC 6M4xUpRPXViqhGDR/uuDX5nx9itMYpFfSoSCXn4UECUHflLXxAnsYDItlTw9y4gyzxtW 37wYH/5DUeV3XfDpCc140GYuMFxjqwAS1d6fXEX14FwZ1IxVDwnYuPJdLWbgzFNC29ew 88ZPjF/iItgCEsHuf/8QylJHE+jvSCMdi6/b25lG18w6CQT++gTXwfItdidOJcvYfwOe n1GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Im+HEPUrh0H/MAxUF3GfHxxVzBKchEF20m9QHI/Imck=; b=XZaviJWF0aAAWvHmslUVKSpW4FRQtfO9U1kGjYvgilSV5NAhCO6phRYMl4++HHu23h 4e/r8he57f+P5/hNBYO1DCzqdAqq3H0CtJ+iN62/BTT/nZp/1y4srpQQsnxshQah3PO4 eOgxVsiS1ic3aO9xLDQ03g0HFrAH9MwwgfPZNEycjAl57tHY8z+laBQwte3P2PL6eeoR wCLqgr7XBACD1loLIAIkzj7B7OH89BUnV9IANCcuzx/Ekh4GIxDlALGg/SsrDF8KCmMd ejcob7kIjL3bbnk4QVBA96XrWgQrBrwh3yP6c9USTRVA5gPqxhXDAcxjnb/i6GUp5Eku rIug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EthKTJjr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:54 -0800 Message-Id: <20180122034217.19593-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 20/43] target/hppa: Log unimplemented instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cad661e39f..7334206b44 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4207,6 +4207,8 @@ static DisasJumpType translate_table_int(DisasContext *ctx, uint32_t insn, return table[i].trans(ctx, insn, &table[i]); } } + qemu_log_mask(LOG_UNIMP, "UNIMP insn %08x @ " TARGET_FMT_lx "\n", + insn, ctx->base.pc_next); return gen_illegal(ctx); } From patchwork Mon Jan 22 03:41:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125312 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp948989ljf; Sun, 21 Jan 2018 20:03:20 -0800 (PST) X-Google-Smtp-Source: AH8x226sChNTnMjBNMgY32dKtLbPuh8OTU3Fikyp+sJ3MAnD617N2f398Ef+vW+44ywnMEcnxJ3P X-Received: by 10.37.7.133 with SMTP id 127mr52409ybh.102.1516593800886; Sun, 21 Jan 2018 20:03:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593800; cv=none; d=google.com; s=arc-20160816; b=FcE6OmnjaXBteY7UpLai4N3nuNYwLifa643/GYzH3mm8N1vzy4XctVFPqf08Ln2+aF W1hknY+PvIav09TuNKT8RyINK9neajpRW+m/dbUjU4txG7OImqNZyNAEk5s+Oy2LTFdq tnMfPg2eqzgI9Ov0JyCVzRJDQNwJjtklpnhVm/K8e0buzEmd1q51bovMRL3ARlPi1wHz Ic7J8vR97FUojwEAyJhRx6HwLseS1q2blJf1qjUEYo78cfyta/AjYOniYTyYVGUIM640 ySiRLyNjJo/5sD9st7nU3EqMd7IKzRRfWTzkNxDRiL/58kvbdvzIr2K+JiqZ8bDoaAuC ZDIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/2rSKpbk9ETiNQxE5ni0XU0sffBx0JEdyXh/JE/AM6k=; b=eUijci7TyOORZl0CPoNf9eXmsVBNntNPwfys6e4V7sgfEuQgBhJNHvhagMTMCSwXj4 27f4CANadwim3oDZDyoXqD/4bBpvTwUB5q3CiKfydU3HiWJSdGhpEB8+xtCGrcPe0iE5 +uZerKoIzNQ7pqpZN9X1pRmjr75ULcLIxfoOCubrRIKdEfhvwyJHhKnLSE6ism2b7xup Iim19Sd+1EQzieUgEIY7dhqAEV/B4sd2N4uYXZ1MmzBpOksPG5R1kVWk2Vs/QuHQUxpI NDNhL7Bg+gePSgV/0vGZoaQrqcsS6QHKZV6IhoaAhcoW9cSvjSye6r7F+qf9oqlOpmmU Wt1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Tm5kjKYX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:55 -0800 Message-Id: <20180122034217.19593-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 21/43] target/hppa: Implement I*TLBA and I*TLBP insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/mem_helper.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++-- target/hppa/translate.c | 54 ++++++++++++++++++++++++++++++-- 3 files changed, 132 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 744b11cb66..d412093914 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -86,4 +86,6 @@ DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 4e92e35957..9d4bf132d6 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -42,13 +42,40 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) { hppa_tlb_entry *ent = &env->tlb[i]; - if (ent->va_b <= addr && addr <= ent->va_e && ent->entry_valid) { + if (ent->va_b <= addr && addr <= ent->va_e) { return ent; } } return NULL; } +static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) +{ + CPUState *cs = CPU(hppa_env_get_cpu(env)); + unsigned i, n = 1 << (2 * ent->page_size); + uint64_t addr = ent->va_b; + + for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) { + /* Do not flush MMU_PHYS_IDX. */ + tlb_flush_page_by_mmuidx(cs, addr, 0xf); + } + + memset(ent, 0, sizeof(*ent)); + ent->va_b = -1; +} + +static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env) +{ + hppa_tlb_entry *ent; + uint32_t i = env->tlb_last; + + env->tlb_last = (i == ARRAY_SIZE(env->tlb) - 1 ? 0 : i + 1); + ent = &env->tlb[i]; + + hppa_flush_tlb_ent(env, ent); + return ent; +} + int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot) { @@ -67,7 +94,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* Find a valid tlb entry that matches the virtual address. */ ent = hppa_find_tlb(env, addr); - if (ent == NULL) { + if (ent == NULL || !ent->entry_valid) { phys = 0; prot = 0; ret = (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); @@ -192,4 +219,53 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); } + +/* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ +void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +{ + hppa_tlb_entry *empty = NULL; + int i; + + /* Zap any old entries covering ADDR; notice empty entries on the way. */ + for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) { + hppa_tlb_entry *ent = &env->tlb[i]; + if (!ent->entry_valid) { + empty = ent; + } else if (ent->va_b <= addr && addr <= ent->va_e) { + hppa_flush_tlb_ent(env, ent); + empty = ent; + } + } + + /* If we didn't see an empty entry, evict one. */ + if (empty == NULL) { + empty = hppa_alloc_tlb_ent(env); + } + + /* Note that empty->entry_valid == 0 already. */ + empty->va_b = addr & TARGET_PAGE_MASK; + empty->va_e = empty->va_b + TARGET_PAGE_SIZE - 1; + empty->pa = extract32(reg, 5, 20) << TARGET_PAGE_BITS; +} + +/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ +void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +{ + hppa_tlb_entry *ent = hppa_find_tlb(env, addr); + + if (unlikely(ent == NULL || ent->entry_valid)) { + qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); + return; + } + + ent->access_id = extract32(reg, 1, 18); + ent->u = extract32(reg, 19, 1); + ent->ar_pl2 = extract32(reg, 20, 2); + ent->ar_pl1 = extract32(reg, 22, 2); + ent->ar_type = extract32(reg, 24, 3); + ent->b = extract32(reg, 27, 1); + ent->d = extract32(reg, 28, 1); + ent->t = extract32(reg, 29, 1); + ent->entry_valid = 1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7334206b44..af84f4d55f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1333,7 +1333,10 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, } #ifndef CONFIG_USER_ONLY -/* Top 2 bits of the base register select sp[4-7]. */ +/* The "normal" usage is SP >= 0, wherein SP == 0 selects the space + from the top 2 bits of the base register. There are a few system + instructions that have a 3-bit space specifier, for which SR0 is + not special. To handle this, pass ~SP. */ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) { TCGv_ptr ptr; @@ -1341,7 +1344,12 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) TCGv_i64 spc; if (sp != 0) { - return cpu_sr[sp]; + if (sp < 0) { + sp = ~sp; + } + spc = get_temp_tl(ctx); + load_spr(ctx, spc, sp); + return spc; } ptr = tcg_temp_new_ptr(); @@ -2344,6 +2352,42 @@ static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } +#ifndef CONFIG_USER_ONLY +static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned sp; + unsigned rr = extract32(insn, 16, 5); + unsigned rb = extract32(insn, 21, 5); + unsigned is_data = insn & 0x1000; + unsigned is_addr = insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs, reg; + + if (is_data) { + sp = extract32(insn, 14, 2); + } else { + sp = ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); + reg = load_gpr(ctx, rr); + if (is_addr) { + gen_helper_itlba(cpu_env, addr, reg); + } else { + gen_helper_itlbp(cpu_env, addr, reg); + } + + /* Exit TB for ITLB change if mmu is enabled. This *should* not be + the case, since the OS TLB fill handler runs with mmu disabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_mem_mgmt[] = { { 0x04003280u, 0xfc003fffu, trans_nop }, /* fdc, disp */ { 0x04001280u, 0xfc003fffu, trans_nop }, /* fdc, index */ @@ -2360,6 +2404,12 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04002720u, 0xfc003fffu, trans_base_idx_mod }, /* pdc, base mod */ { 0x04001180u, 0xfc003fa0u, trans_probe }, /* probe */ { 0x04003180u, 0xfc003fa0u, trans_probe }, /* probei */ +#ifndef CONFIG_USER_ONLY + { 0x04000000u, 0xfc001fffu, trans_ixtlbx }, /* iitlbp */ + { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ + { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ + { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ +#endif }; static DisasJumpType trans_add(DisasContext *ctx, uint32_t insn, From patchwork Mon Jan 22 03:41:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125310 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp948045ljf; Sun, 21 Jan 2018 20:00:33 -0800 (PST) X-Google-Smtp-Source: AH8x227omVb5bDaPvgbYlh3ryJjguOa30FQrG8loIBfkNZ9aaiaPTibt6NGWk6G75MilfFcjIppr X-Received: by 10.129.88.70 with SMTP id m67mr6003651ywb.352.1516593632901; Sun, 21 Jan 2018 20:00:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593632; cv=none; d=google.com; s=arc-20160816; b=WdbmR0JU7BcJTN+oOn/2lLw/k3frRKenLiWhW33JmPv7vn1gDTmxFHMYm05JHG7NfL CJ9pyzNaO8Z0hION6N/RaI0/pgLEli+g838XZbRZhV04fRTTdVPw/79s5PP0GVWEuYtN NfU3mGcYDOMMxYgCtwIElWBKP7iJgi3oubspRUQZhApuKXZ8eZ3obD882zWaJLc6glaY jc114HTATdLO0BsoI+hO2+qVKDbuBptxX8HZvi1whxCCDPdIbTH/AF5snFM2PIWXTVfZ fGAEkaqeTXxQD8F4BJ7auNmHSrcalPpBl8z+Wsw8Y9B6gN3Mh6VYhHnP3+WQl7mROISx JeOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YqGaWrSkk8n2CzVQlDNC4wooKg9lp5QRQVhVZ9nZ7po=; b=P8pRjl+X5TZsQ+/SAcXgZGVsaHnyGL6zjTs5dOnZjb/3WTDyWDO5jgU5vbX5yPxx2+ HmkWogdysl6mQvV658qvBGxEPW5KLMqJs3Owcd0GGNZldoVwOoK156w4B/KZEnoGPxu7 c/2t9IkbXBvJ63AnPRoxr5EB0LwFBQXlB8MC3BunM8EU0OT+bK9ewnhZfetBPJSwgSHa SnRAXcnVB1ZWtGVUKTdoatmnyNEGu5+IaI4I64vOO5hqIkBqURRFFTJhSAJRhDTTq9eb 7Frwr8SHIk/EXSY2qYIwW/fzuuKaMUgWcB3Z7VkJn5gioBLMscPN1rYzfV58ZQnC7uSu mWow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G+nYNg+z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:56 -0800 Message-Id: <20180122034217.19593-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 22/43] target/hppa: Implement P*TLB and P*TLBE insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/mem_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index d412093914..f059ddf3b9 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -88,4 +88,6 @@ DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9d4bf132d6..b5e2e35908 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -268,4 +268,41 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) ent->t = extract32(reg, 29, 1); ent->entry_valid = 1; } + +/* Purge (Insn/Data) TLB. This is explicitly page-based, and is + synchronous across all processors. */ +static void ptlb_work(CPUState *cpu, run_on_cpu_data data) +{ + CPUHPPAState *env = cpu->env_ptr; + target_ulong addr = (target_ulong) data.target_ptr; + hppa_tlb_entry *ent = hppa_find_tlb(env, addr); + + if (ent && ent->entry_valid) { + hppa_flush_tlb_ent(env, ent); + } +} + +void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) +{ + CPUState *src = CPU(hppa_env_get_cpu(env)); + CPUState *cpu; + run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr); + + CPU_FOREACH(cpu) { + if (cpu != src) { + async_run_on_cpu(cpu, ptlb_work, data); + } + } + async_safe_run_on_cpu(src, ptlb_work, data); +} + +/* Purge (Insn/Data) TLB entry. This affects an implementation-defined + number of pages/entries (we choose all), and is local to the cpu. */ +void HELPER(ptlbe)(CPUHPPAState *env) +{ + CPUState *src = CPU(hppa_env_get_cpu(env)); + + memset(env->tlb, 0, sizeof(env->tlb)); + tlb_flush_by_mmuidx(src, 0xf); +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index af84f4d55f..44e566837d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2386,6 +2386,42 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned m = extract32(insn, 5, 1); + unsigned sp; + unsigned rx = extract32(insn, 16, 5); + unsigned rb = extract32(insn, 21, 5); + unsigned is_data = insn & 0x1000; + unsigned is_local = insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs; + + if (is_data) { + sp = extract32(insn, 14, 2); + } else { + sp = ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, rx, 0, 0, sp, m, false); + if (m) { + save_gpr(ctx, rb, ofs); + } + if (is_local) { + gen_helper_ptlbe(cpu_env); + } else { + gen_helper_ptlb(cpu_env, addr); + } + + /* Exit TB for TLB change if mmu is enabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2409,6 +2445,10 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ + { 0x04000200u, 0xfc001fdfu, trans_pxtlbx }, /* pitlb */ + { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ + { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ + { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ #endif }; From patchwork Mon Jan 22 03:41:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125313 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp949012ljf; Sun, 21 Jan 2018 20:03:24 -0800 (PST) X-Google-Smtp-Source: AH8x227Lx9ouZEjusARMnZmfsRIGePH7WjmZn9oU5o/CF+emltkPxoITrCKORakxThfZvp1nbZ60 X-Received: by 10.13.202.146 with SMTP id m140mr6255764ywd.511.1516593804070; Sun, 21 Jan 2018 20:03:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593804; cv=none; d=google.com; s=arc-20160816; b=BqIbYkrmCAZ78QQ6C8bfdRpddSbWBnbX6338MKXCmyD7bhgQfm70PoP2H3p36+aB0l jjNWregEO6i2k3xg8GYVoxGdL4k8grVCjbbgHpb6mB5GOIPdBgd8PyxIF/I7X9u5gk6O lOh6WJCE4ShQuddfWwbv0ZRTmik06rAreTL0pVkXmyUrVUT53AIOyAm+ysRsAB8YlzeW psnfp7HGuYtNXYMQMUDf93tcPo8strkntE1Nhr0FMTxq2VtpnF6Er0mHXdqSTJXikJvR rihRmQVfLk4G8SkdX4kpT/8uYPHyW84PGXIedYa2D1z9SSr+Cg1Zcsl18O3LSfqQTM4v yTRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ObFkD+wBC9Qrb8OO4s/Ca03ZxlKBQ1krhtGC5xL3Wpk=; b=0nOWWL6lbkrG9195uDun6tanINntznn7F95XdHkGjSI5iST/YLNUPxkpbcJ2zrZYOj DVonTrMgGvqEaWwz+QbP3ACI+YpIzZ+zaABVSIiRR10i8awoWRGXLHVedJVluHFyrJiM dXPk7pvU1Z4XdmhYrMSSKALaOleWfWWYX5UxX+/DJoUlf3mcgqsfjB9E+LElpBmnInPZ 7Io7qfO85JclP9gaqM9nWDQEvcDYTJLEQ1dvzftEEEylGETO4LNVat0oEueTz+rF/ZcO xG7ne9P1Tw4ykYTaFBUa6yHpHAEWnjP0yEK+YybI54aCm3G52Yz1UtPanaqsKN1FVQNz H5rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=f1WhqNaA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:57 -0800 Message-Id: <20180122034217.19593-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 23/43] target/hppa: Implement LDWA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 44e566837d..5b49cc5332 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2943,12 +2943,50 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } +#ifndef CONFIG_USER_ONLY +static DisasJumpType trans_ldwa_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx = ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx = MMU_PHYS_IDX; + ret = trans_ld_idx_i(ctx, insn, di); + ctx->mmu_idx = hold_mmu_idx; + return ret; +} + +static DisasJumpType trans_ldwa_idx_x(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx = ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx = MMU_PHYS_IDX; + ret = trans_ld_idx_x(ctx, insn, di); + ctx->mmu_idx = hold_mmu_idx; + return ret; +} +#endif + static const DisasInsn table_index_mem[] = { { 0x0c001000u, 0xfc001300, trans_ld_idx_i }, /* LD[BHWD], im */ { 0x0c000000u, 0xfc001300, trans_ld_idx_x }, /* LD[BHWD], rx */ { 0x0c001200u, 0xfc001300, trans_st_idx_i }, /* ST[BHWD] */ { 0x0c0001c0u, 0xfc0003c0, trans_ldcw }, { 0x0c001300u, 0xfc0013c0, trans_stby }, +#ifndef CONFIG_USER_ONLY + { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ + { 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */ +#endif }; static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) From patchwork Mon Jan 22 03:41:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125316 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp949409ljf; Sun, 21 Jan 2018 20:04:43 -0800 (PST) X-Google-Smtp-Source: AH8x224OcWCOma54fR473ARFC2qKIXh9/dv/7juqBMd82KTaUpPuJGPwQDpj8NcarWJDCSDVGiCs X-Received: by 10.37.184.20 with SMTP id v20mr6085197ybj.139.1516593883832; Sun, 21 Jan 2018 20:04:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593883; cv=none; d=google.com; s=arc-20160816; b=Be2kjZHbMMj9IU2K9o/kaZJ+vvUI0H5bFUFbm1Fc021SrrgQC4gHrV9j87xar3BMit PFNFD8qVTbEHAqlDptpoSYuA++AnEe5DAfdxSEUyzrVBv/uEaLlEB3DyCm4RzuYlDObQ o9VumBIGiiRE1T2dwvKo13B7lMCFD8CrEGfbW/wf92CBL9CfIf4DAmd8ylHPuILE0Qkk Qh7Rl+c7Y9ZrI6TM73G+gff/3cp8St6WRuL7Lwv8zt9lJmIvoAKEUiOsRVgdISi5D0RJ Hp0aGdcGcnEeFamvGbyEMOHbHfNh+5TuVcasoEDwLb7ZwAz3zBfSKa4palg4K+z6zrAl T4mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xE/Zv2DUrJBEt+P7UQ3XeDRFqVWiz2CLnQgNWEowR+U=; b=LR1Xu53ExYznR9jjzh0PSq/X3qqL9p+Sp9tkVbcqYyrwPAOKU1Gh7I4j7WTe+ZpRRS i5yPR9s5PHlV2vY+3ZCzRepYD5p4Oc8Ft0OQjYyleq8vzYJ1RCoRAKQFYhKSdoUqKpN5 Z4/FlDDkohKw+UUk6xICLdPLYwGBM3FIN3b/bKpDHSP8xe3UaBWONFRtpCeJkMRPmGRV 5lmWJWuAjt4NcL2Rrraqh1Zc099fa5iDXueIrK079/RjMcvG9cwp6blHHBHmuOeaMok/ BaXYz5k7WXT+s4MdtmB6IBMP1yZaMDsnDhl6Y+k6pJC1IvIgACNzr/abl8pMItp/dhjI XRmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VeeBgLjI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:58 -0800 Message-Id: <20180122034217.19593-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 24/43] target/hppa: Implement LPA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 1 + target/hppa/mem_helper.c | 13 +++++++++++++ target/hppa/op_helper.c | 10 +++++----- target/hppa/translate.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 50 insertions(+), 5 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 31a3702684..a6e4091b6a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -344,5 +344,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; void hppa_cpu_alarm_timer(void *); #endif +void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index f059ddf3b9..1e733b7926 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -90,4 +90,5 @@ DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b5e2e35908..9d93894019 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -305,4 +305,17 @@ void HELPER(ptlbe)(CPUHPPAState *env) memset(env->tlb, 0, sizeof(env->tlb)); tlb_flush_by_mmuidx(src, 0xf); } + +target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) +{ + hwaddr phys; + int prot, excp; + + excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, + MMU_DATA_LOAD, &phys, &prot); + if (excp == EXCP_DTLB_MISS) { + hppa_dynamic_excp(env, EXCP_NA_DTLB_MISS, GETPC()); + } + return phys; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 6d19cab6c9..d270f94e31 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -34,7 +34,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) cpu_loop_exit(cs); } -static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) +void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra) { HPPACPU *cpu = hppa_env_get_cpu(env); CPUState *cs = CPU(cpu); @@ -46,14 +46,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) { if (unlikely((target_sreg)cond < 0)) { - dynexcp(env, EXCP_OVERFLOW, GETPC()); + hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); } } void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) { if (unlikely(cond)) { - dynexcp(env, EXCP_COND, GETPC()); + hppa_dynamic_excp(env, EXCP_COND, GETPC()); } } @@ -237,7 +237,7 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) env->fr[0] = (uint64_t)shadow << 32; if (hard_exp & shadow) { - dynexcp(env, EXCP_ASSIST, ra); + hppa_dynamic_excp(env, EXCP_ASSIST, ra); } } @@ -645,7 +645,7 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) /* ??? On second reading this condition simply seems to be undefined rather than a diagnosed trap. */ if (nsm & ~psw & PSW_Q) { - dynexcp(env, EXCP_ILL, GETPC()); + hppa_dynamic_excp(env, EXCP_ILL, GETPC()); } env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5b49cc5332..bbef2f0d7f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2422,6 +2422,35 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_lpa(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + unsigned m = extract32(insn, 5, 1); + unsigned sp = extract32(insn, 14, 2); + unsigned rx = extract32(insn, 16, 5); + unsigned rb = extract32(insn, 21, 5); + TCGv_tl vaddr; + TCGv_reg ofs, paddr; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &vaddr, &ofs, rb, rx, 0, 0, sp, m, false); + + paddr = tcg_temp_new(); + gen_helper_lpa(paddr, cpu_env, vaddr); + + /* Note that physical address result overrides base modification. */ + if (m) { + save_gpr(ctx, rb, ofs); + } + save_gpr(ctx, rt, paddr); + tcg_temp_free(paddr); + + return nullify_end(ctx, DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2449,6 +2478,7 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ + { 0x04001340u, 0xfc003fc0u, trans_lpa }, #endif }; From patchwork Mon Jan 22 03:41:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125317 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp950032ljf; Sun, 21 Jan 2018 20:06:41 -0800 (PST) X-Google-Smtp-Source: AH8x225MmVZLLXJ0IO6tzijlKYYBxR/XSfNSOL4MKh6YqaGrYrlwUAwZkRzhlBzanwalvTT+rEHh X-Received: by 10.129.116.67 with SMTP id p64mr6103139ywc.110.1516594001237; Sun, 21 Jan 2018 20:06:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594001; cv=none; d=google.com; s=arc-20160816; b=oamzYzULRZcZR2QhHGy0UoxydQhHK4BcF52PNfKRoGVYaG89KfvaWnUBgziHVjedS5 Qa5TiB0fLFMCoN5JvDhxnTw+JzRXkax4dPbZ/Z1STsNrfQ8HMTWUD+uxXbYmGswvZI9E O9InQw4DzvBw9NAJUL64HBbOjliAhpfOKdp6vBCp480QunB/S3Mc8dkKJb0zjg2ReTO1 xnuBQsjxcK6r9IsvNftGTqdPhhZ4YpK2JiCQ/bNzFRC/MyNo09YkvgmH/61TZ4CkB/oy 5z2wK1svxJPXJ3duMF6RIUhfFelvDyw6jvB8ctIkzDqMxucaT7aWWmn7s4cNkbe7wsGM Rj3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+LBPh6yn6UG1tncxst9Z9jkRXDXaqBy3i48OJuMm2Uw=; b=x5Kgad2/1/g3+GriR1JuXpAvUUbns9VCu017sAbzTFQjcdIHuEn/euKihLQ7BcXfAc 1wvB3tHCsDKOnyue6k/pVFrGA2Uyp8mYQv0E/ba7gmfLCOMSVObqu8lDUTspIhA+AeNq QH5Lac+P2rLXnSw9JqNlHytR/DLBIMfcMIlJjBSPlkeoa6vUUPfVJ5+gFsIHhrajQyHJ eOuxccapXS+1Kueoot105h4uOjCfLp2o6S+TenbkiL3qNxhc0RUkb67inV0kriMaXdEV MSPCniu4CMbcJ3xlLFgJ3DA8vPIHTfRcnd2jsmRHQCfPb9FC7fJVhmrH45wdhxiQi1wH pdOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NO27F4Wl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:59 -0800 Message-Id: <20180122034217.19593-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 25/43] target/hppa: Implement LCI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index bbef2f0d7f..b207ae192a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2451,6 +2451,25 @@ static DisasJumpType trans_lpa(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } + +static DisasJumpType trans_lci(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + TCGv_reg ci; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* The Coherence Index is an implementation-defined function of the + physical address. Two addresses with the same CI have a coherent + view of the cache. Our implementation is to return 0 for all, + since the entire address space is coherent. */ + ci = tcg_const_reg(0); + save_gpr(ctx, rt, ci); + tcg_temp_free(ci); + + return DISAS_NEXT; +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2479,6 +2498,7 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ { 0x04001340u, 0xfc003fc0u, trans_lpa }, + { 0x04001300u, 0xfc003fe0u, trans_lci }, #endif }; From patchwork Mon Jan 22 03:42:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125319 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp950742ljf; Sun, 21 Jan 2018 20:09:04 -0800 (PST) X-Google-Smtp-Source: AH8x227nQnjESFBrBjqEwmIIwvPXzmTdCQ8x/uz9UFRAptxFatg0+vDgLs/pU+q/7y55a+Sz9y9I X-Received: by 10.37.218.21 with SMTP id n21mr6213404ybf.178.1516594144430; Sun, 21 Jan 2018 20:09:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594144; cv=none; d=google.com; s=arc-20160816; b=bWSzXjkloYqsd580rsjixNtcK63sKKn/UmCOGQyoVPRDutp7ien3Rg+QpkbcVkibHu gkNAd8gnqaqWYnNCGGSrBcPNcgnZ1oK9SmY4+0YTYNPo6wUmzRztZltoR5lOpMaJSgFf W6hYHukCnEdM2pXEcAy/4pUCRwOmTFIthrhTsHBdbZN/VWDkzX8DEj2TsdUyHMGPU1FH vZJeEIYzg8gJIPHzyJuL+0a2g0zqZ/OSIJL+drp5lvDxXEy7cZznkKvQHaLF9Rnq+oUm HxPGCuSM37r+7ArvhvmYrkj5gsdiVdzPYUBXmLs5WvcVhiNULj/UNaiQHr1pPMc3L+X6 sc+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=nHF+URsKehLoWhZ0MUasCPlUHzVGJYEB06DVzIVQXSo=; b=nSxXaCBw5y57uNzXQDR0Btbl1uk43RnB8hE83RshhItqaHuWsNpAUiB2rEO6vKlsUT E5mpTch5YC6vudD7FUfGwgKUHmvfyaWFG57P74p0UX+RiLvEQs0DEVLesJVsfoRWIUy+ d+iHH2ww6Kgas22DSVId3BoGcNeEhhdp68XrC1iG6Bv/911mXiw/fyznJpcOgRezdjLF Z8U7naOJ9UuXiQovsP69FPJhJvCpHRi9BkiPrx+b66NJsFsoQrqwCu2I2Ya+UP0ox/U3 Uq2C7Ds3+X1dBH7sWaYIz5SYhq9Bc0m1xg5gDefglUkex5azGrraLTkz5QpKBg75hAHT 9qSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TNCOGDG7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:00 -0800 Message-Id: <20180122034217.19593-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 26/43] target/hppa: Implement SYNCDMA insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b207ae192a..a311a464bf 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2301,7 +2301,8 @@ static const DisasInsn table_system[] = { { 0x000014a0u, 0xffffffe0u, trans_mfia }, { 0x000004a0u, 0xffff1fe0u, trans_mfsp }, { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl }, - { 0x00000400u, 0xffffffffu, trans_sync }, + { 0x00000400u, 0xffffffffu, trans_sync }, /* sync */ + { 0x00100400u, 0xffffffffu, trans_sync }, /* syncdma */ { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, #ifndef CONFIG_USER_ONLY { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, From patchwork Mon Jan 22 03:42:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125314 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp949208ljf; Sun, 21 Jan 2018 20:04:06 -0800 (PST) X-Google-Smtp-Source: AH8x227ghc2SfOzgp+gUsyYhocHdSSF4HwMleKBpJAnX2fvZ5ZIjZG7zNNISFo4oW6RuX6uhf5O6 X-Received: by 10.37.181.130 with SMTP id q2mr6029521ybj.429.1516593846550; Sun, 21 Jan 2018 20:04:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516593846; cv=none; d=google.com; s=arc-20160816; b=vM9zvssHMDtOYzFxaE8Y+L0GlJfaMC6JaqV6Z069BhdXfZq1JkvK0UNXZsxpZhm7d+ I5sOKfMcT6DTbW+0tcpV9QQUpGRR+4Hj3wOkL8915Ze8Y4E/Mycdb0A5OrBrr1KyOjH8 darfctHsZ+CiXeyvMK5lry1Rrq1lD9vV8U+1lgKe4YOCToxZBEVlBuPMoNRkLPUfk2zX SYHd14J+LfjQ73Nnuw4brQPO7gAR/PYdG0erwPmK1fsOvPlVC6l/riNqrnRSux2JOWID zRd/vmDx+3ZN9vgYTdb7mjF0veyNE8O0ayzUboGx4SRi77X3pc0PE5rGE7rbS3/N/w9k XlWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=MaG9Rwopn83QHEKkMTmfjC0sA1jP9/xTUxqjxCfG5XM=; b=Nzz+BiYWnFCEvBmwZeNs7OElkJwLxbNkAHyZdiNfikIelSUVoM+SQ58i62J7laaCBq +5vILU2I1XbFaQenHs95QLZXyl/LxuYe2SpToMQS8gGD8McrMJM/T40ii1HDWwLz/08q 5eF/aq7Q8+N5wyrdInyxULWVxMghNuUxYWg32GvVBRq/2iqiGmJEOhIkpYVU4sHrq20S VRfwTiFuJNavEq91KCHivtq9vRk1fqYTQI06VKvs78k4ZbN6ThhlyCG+n9ulrLBeApP1 dVhn1QO7S3ddiFEKvQwddNIA7y8mhytSUePXJ7zFHsPxKaFc3V/0ni+3JaHaOB2x0S3a 2ObQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fruBa7Mm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:01 -0800 Message-Id: <20180122034217.19593-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 27/43] target/hppa: Implement halt and reset instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 13 +++++++++++++ target/hppa/translate.c | 25 ++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 1e733b7926..31320740da 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -80,6 +80,8 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) #ifndef CONFIG_USER_ONLY +DEF_HELPER_1(shutdown, noreturn, env) +DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index d270f94e31..c2eeced0e9 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include "sysemu/sysemu.h" #include "qemu/timer.h" @@ -639,6 +640,18 @@ void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) timer_mod(cpu->alarm_timer, timeout); } +void HELPER(shutdown)(CPUHPPAState *env) +{ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + helper_excp(env, EXCP_HLT); +} + +void HELPER(reset)(CPUHPPAState *env) +{ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + helper_excp(env, EXCP_HLT); +} + target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw = env->psw; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a311a464bf..de96765664 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2291,6 +2291,18 @@ static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn, /* Exit the TB to recognize new interrupts. */ return nullify_end(ctx, DISAS_NORETURN); } + +static DisasJumpType gen_hlt(DisasContext *ctx, int reset) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + if (reset) { + gen_helper_reset(cpu_env); + } else { + gen_helper_shutdown(cpu_env); + } + return nullify_end(ctx, DISAS_NORETURN); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_system[] = { @@ -4508,7 +4520,18 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) case 0x15: /* unassigned */ case 0x1D: /* unassigned */ case 0x37: /* unassigned */ - case 0x3F: /* unassigned */ + break; + case 0x3F: +#ifndef CONFIG_USER_ONLY + /* Unassigned, but use as system-halt. */ + if (insn == 0xfffdead0) { + return gen_hlt(ctx, 0); /* halt system */ + } + if (insn == 0xfffdead1) { + return gen_hlt(ctx, 1); /* reset system */ + } +#endif + break; default: break; } From patchwork Mon Jan 22 03:42:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125318 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp950237ljf; Sun, 21 Jan 2018 20:07:23 -0800 (PST) X-Google-Smtp-Source: AH8x226NOplLazj1a2ydfMCbNq1WHYjDGpachY4CsbSP5wzD9Ff+SocOmzucDG33S1Ko0IcBGZlM X-Received: by 10.129.148.193 with SMTP id l184mr6060181ywg.452.1516594043795; Sun, 21 Jan 2018 20:07:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594043; cv=none; d=google.com; s=arc-20160816; b=OE6nn/rJPcgdOw/K2MXTv3vivaz5nLToEDYYA1lTWNYnymH3Tp3kD53QItlLSwhioe 7Zn/MzJOM83JdtkISKFAnMrraeihr4jA8AeGtaVGDlAIQhPCf8zHVHdKK+7R2LcK0Fek xH57JVRPmX1hydBOJhIK0UybYMtU3W8o224RtOsv5Nv9ynw9LRN0S1vfwb4cWgMU40Wv 6kTD156hS34RZ37OlMfUU3RaWavDgk+z91bPDxo0gX1hqjJE124AcRkxSh7YpS54cklG MEmgq/KTp1GCRjLfr/p2FL84iwb7xIeBNbcrORiqpSCsoJ1xDtT5FCkQNfC9CJtkrvsb e+wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=jQDvwAZOAXYljqzsdO87DYsQ7XKjm2rpXdoxkaoGBP0=; b=KJg/bS0OFsrEji5t+3XDk2FG1RzvGm+hlMhQI1MW3ZaGcyUTg23ExOSYGwoF/zgtIV CNHfKYatfTTeUIVG2ZEpIjJQ2syKsllCJbujzklStoH6AxNbUQF5/+9ZBM6r343E+wrb HauxAUcRJxCXSYLkK4Txj8UL/HOKEOLpIrkrjaei5hqoDKvXd/dVLhlgom2B2TkBqqaS cmZyY+uBRhIyDJ2EG71GS40tdn9FmYLxwTtoGYLlcw+Fm8UqTaMJZI1CUdB1zcH2xCsp 3eV/v4JjThCUNZpvP568KiKdqjglqFo9MxOxPYf7XeJWK4l/Jku8j0VUDL757BJ4rJAa CLLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GHDkE4DH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:02 -0800 Message-Id: <20180122034217.19593-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 28/43] target/hppa: Optimize for flat addressing space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 11 ++++++++++- target/hppa/translate.c | 29 ++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a6e4091b6a..57e0bd6f0e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -282,7 +282,11 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } -/* Since PSW_CB will never need to be in tb->flags, reuse them. */ +/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. + * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the + * same value. + */ +#define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, @@ -318,6 +322,11 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, *cs_base |= (uint32_t)diff; } } + if ((env->sr[4] == env->sr[5]) + & (env->sr[4] == env->sr[6]) + & (env->sr[4] == env->sr[7])) { + flags |= TB_FLAG_SR_SAME; + } #endif *pflags = flags; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index de96765664..e4a140b9a6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -280,6 +280,7 @@ typedef struct DisasContext { TCGLabel *null_lab; uint32_t insn; + uint32_t tb_flags; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -319,6 +320,7 @@ typedef struct DisasInsn { /* global register indexes */ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; +static TCGv_i64 cpu_srH; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_i64 cpu_iasq_f; @@ -356,8 +358,8 @@ void hppa_translate_init(void) "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; /* SR[4-7] are not global registers so that we can index them. */ - static const char sr_names[4][4] = { - "sr0", "sr1", "sr2", "sr3" + static const char sr_names[5][4] = { + "sr0", "sr1", "sr2", "sr3", "srH" }; int i; @@ -373,6 +375,9 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, sr[i]), sr_names[i]); } + cpu_srH = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[4]), + sr_names[4]); for (i = 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v = &vars[i]; @@ -600,6 +605,8 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) #else if (reg < 4) { tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { + tcg_gen_mov_i64(dest, cpu_srH); } else { tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); } @@ -1351,6 +1358,9 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) load_spr(ctx, spc, sp); return spc; } + if (ctx->tb_flags & TB_FLAG_SR_SAME) { + return cpu_srH; + } ptr = tcg_temp_new_ptr(); tmp = tcg_temp_new(); @@ -1394,7 +1404,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, #else TCGv_tl addr = get_temp_tl(ctx); tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); - if (ctx->base.tb->flags & PSW_W) { + if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); } if (!is_phys) { @@ -2101,6 +2111,7 @@ static DisasJumpType trans_mtsp(DisasContext *ctx, uint32_t insn, if (rs >= 4) { tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + ctx->tb_flags &= ~TB_FLAG_SR_SAME; } else { tcg_gen_mov_i64(cpu_sr[rs], t64); } @@ -2396,7 +2407,7 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, /* Exit TB for ITLB change if mmu is enabled. This *should* not be the case, since the OS TLB fill handler runs with mmu disabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } @@ -2432,7 +2443,7 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, } /* Exit TB for TLB change if mmu is enabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } @@ -4545,6 +4556,7 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, int bound; ctx->cs = cs; + ctx->tb_flags = ctx->base.tb->flags; #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_USER_IDX; @@ -4552,9 +4564,8 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, ctx->iaoq_f = ctx->base.pc_first; ctx->iaoq_b = ctx->base.tb->cs_base; #else - ctx->privilege = (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - ctx->mmu_idx = (ctx->base.tb->flags & PSW_D - ? ctx->privilege : MMU_PHYS_IDX); + ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; + ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); /* Recover the IAOQ values from the GVA + PRIV. */ uint64_t cs_base = ctx->base.tb->cs_base; @@ -4586,7 +4597,7 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ ctx->null_cond = cond_make_f(); ctx->psw_n_nonzero = false; - if (ctx->base.tb->flags & PSW_N) { + if (ctx->tb_flags & PSW_N) { ctx->null_cond.c = TCG_COND_ALWAYS; ctx->psw_n_nonzero = true; } From patchwork Mon Jan 22 03:42:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125325 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp951300ljf; Sun, 21 Jan 2018 20:10:56 -0800 (PST) X-Google-Smtp-Source: AH8x226+yBZ7y7PsW7SKRpA2mUVv/IOTIrIeLj/aD3evWEIJOTI8hk8xS6NF0EFqO1PoS3YzjlNz X-Received: by 10.37.218.21 with SMTP id n21mr6217343ybf.178.1516594256074; Sun, 21 Jan 2018 20:10:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594256; cv=none; d=google.com; s=arc-20160816; b=qV6++0Aqu2/i4oYhPca+QC22BeLnwk1au7jh0DNq9Cx+9rTsDAyITZlgFnWkU9I5l+ uf73rFPAmCDNF/j6qpJpM7W3mO5Nv20z6WTasMvcThqtpq2NYJHkMzYhFpC6XfWHn2Nh swGsxNMqot+w+sll07z51ddQIT8sxn4YUZTxNcKIjvZjTa0DxLmQ4rmmCItUhCSqf+N0 yyqDKSG6RyrJvr73c0KP7SzEOfzY651v50O87O4OAm4VpUbXBBqjt1XbNKJhE+nOGFXZ C45WvKs6f2HxmCgEgneQAUfE7nqCa6vRIdkvG++JqdHAhT7YtoecOeap+qzqDPZeiWab rA+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mOdt0qcyMnQWoblkB3DI4JREleHkAHQJdcCTlXCiOnM=; b=WcX6lHrvRjK0jK3P6YnSIEYzf/CxWWhzIvl9omvsHkMVqQN4C3+58/wC+mlVU+NrZh Us8uuGIxn4dY2f9mjM9/3JOhDZC3B8yMqVCldwjvJLOkakT7M/CMsV6jvWvIDtsSTVBS uAcjjEk4aPR5bfhJ+oop3IUZ5jzwv+aa2JLaFwwGbxkqaxh/f5t+gaLoRGTdluHzGkYN Y9Ewh0KLZIUKGFJ2z6p9gZdqLe/MwPDoRpHQtHtI9zsYikqnejnOAIiXvP6R7kTvqDcC mWrXdvRLKCz77BEvkedME+t0lStFG1flryEyHUi++X6EvbZ7tShyGzyYJ2C8ybdD3vyY TQTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LsnHSkeU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 29/43] target/hppa: Add system registers to gdbstub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/gdbstub.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) -- 2.14.3 diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index fc27aec073..e2e9c4d77f 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -41,15 +41,93 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) case 33: val = env->iaoq_f; break; + case 34: + val = env->iasq_f >> 32; + break; case 35: val = env->iaoq_b; break; + case 36: + val = env->iasq_b >> 32; + break; + case 37: + val = env->cr[CR_EIEM]; + break; + case 38: + val = env->cr[CR_IIR]; + break; + case 39: + val = env->cr[CR_ISR]; + break; + case 40: + val = env->cr[CR_IOR]; + break; + case 41: + val = env->cr[CR_IPSW]; + break; + case 43: + val = env->sr[4] >> 32; + break; + case 44: + val = env->sr[0] >> 32; + break; + case 45: + val = env->sr[1] >> 32; + break; + case 46: + val = env->sr[2] >> 32; + break; + case 47: + val = env->sr[3] >> 32; + break; + case 48: + val = env->sr[5] >> 32; + break; + case 49: + val = env->sr[6] >> 32; + break; + case 50: + val = env->sr[7] >> 32; + break; + case 51: + val = env->cr[CR_RC]; + break; + case 52: + val = env->cr[8]; + break; + case 53: + val = env->cr[9]; + break; + case 54: + val = env->cr[CR_SCRCCR]; + break; + case 55: + val = env->cr[12]; + break; + case 56: + val = env->cr[13]; + break; + case 57: + val = env->cr[24]; + break; + case 58: + val = env->cr[25]; + break; case 59: val = env->cr[26]; break; case 60: val = env->cr[27]; break; + case 61: + val = env->cr[28]; + break; + case 62: + val = env->cr[29]; + break; + case 63: + val = env->cr[30]; + break; case 64 ... 127: val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32); break; @@ -94,15 +172,93 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) case 33: env->iaoq_f = val; break; + case 34: + env->iasq_f = (uint64_t)val << 32; + break; case 35: env->iaoq_b = val; break; + case 36: + env->iasq_b = (uint64_t)val << 32; + break; + case 37: + env->cr[CR_EIEM] = val; + break; + case 38: + env->cr[CR_IIR] = val; + break; + case 39: + env->cr[CR_ISR] = val; + break; + case 40: + env->cr[CR_IOR] = val; + break; + case 41: + env->cr[CR_IPSW] = val; + break; + case 43: + env->sr[4] = (uint64_t)val << 32; + break; + case 44: + env->sr[0] = (uint64_t)val << 32; + break; + case 45: + env->sr[1] = (uint64_t)val << 32; + break; + case 46: + env->sr[2] = (uint64_t)val << 32; + break; + case 47: + env->sr[3] = (uint64_t)val << 32; + break; + case 48: + env->sr[5] = (uint64_t)val << 32; + break; + case 49: + env->sr[6] = (uint64_t)val << 32; + break; + case 50: + env->sr[7] = (uint64_t)val << 32; + break; + case 51: + env->cr[CR_RC] = val; + break; + case 52: + env->cr[8] = val; + break; + case 53: + env->cr[9] = val; + break; + case 54: + env->cr[CR_SCRCCR] = val; + break; + case 55: + env->cr[12] = val; + break; + case 56: + env->cr[13] = val; + break; + case 57: + env->cr[24] = val; + break; + case 58: + env->cr[25] = val; + break; case 59: env->cr[26] = val; break; case 60: env->cr[27] = val; break; + case 61: + env->cr[28] = val; + break; + case 62: + env->cr[29] = val; + break; + case 63: + env->cr[30] = val; + break; case 64: env->fr[0] = deposit64(env->fr[0], 32, 32, val); cpu_hppa_loaded_fr0(env); From patchwork Mon Jan 22 03:42:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125321 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp950931ljf; Sun, 21 Jan 2018 20:09:41 -0800 (PST) X-Google-Smtp-Source: AH8x2274EEI37SJnE5mnzmgxRt56nvK6N6SgNVjLdCPzhpYqZX7f4JQUuvcfeqifkQUpkM7rbNgk X-Received: by 10.13.194.66 with SMTP id e63mr6023545ywd.65.1516594181231; Sun, 21 Jan 2018 20:09:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594181; cv=none; d=google.com; s=arc-20160816; b=lKE4pNoN/qTobuvCbFOrOc3o59z8MTN3WRe6mqLQ5FjtE5Vaf27f6nZvhPx94W2Dlp uKk4OvjJo47J3Gm3Ze4Re+Xs6+wcMV1Iz1j/IsLKSFPpSbv/xXu4grZahEjnuJ77bZtV AodR9SLZ8zGHfVo+cavf/JIOw2RsHHuLeucgpMf8Vo4MN47h5iDTIJvF6HpNzD+rfEeL XGin9tof0mdg6rjfvgA364Q1JA1Oudx7ZFuTGAkb/b3Py3OWTE2MAxgpjlnRl3LeEjav GpFI2noF5M1hBdvJmlWr9NfmkoLYkgcvu9dVTVVjtdIldQmyfCBHbANK3iUD7PH62mA9 ZSWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=2SmQ+J2Z4CJceLw6P7MR9FARqmH1HZAqBHDwpxzF8Bk=; b=W7IxLDddbCIRSstCLX9BQNQu/Jt/d3xIthOpJo9ya8opkVGlm4fTOHQCKbxbbktmEu 80uPRxfcw/rriC/hksk3BJgme6oZ7scdwDvBrNZWD3pUn/Amg1llxdBO+OVZm7vU3qqO cxhIbrSIkNdVV24YaT70/DCkW1H9TEPUSVbjmc88qC6KxqL20DMj1bByjLWwTlhzFJTj sDW4y5XyhREOr66wYPvnhhIjEI5ci3IyMukqCgTCuFc3lwAoDcJKzutpqNVi8RzLTUhZ v2YSFU/PVqh9AtszY+EmBlqe0kjLgf6H/1I7WG5pfz62Z0NiG8owvwYer4aYhU9rnSTP A3WQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eRB1W31p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:04 -0800 Message-Id: <20180122034217.19593-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 30/43] target/hppa: Add migration for the cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/cpu.c | 1 + target/hppa/machine.c | 181 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/Makefile.objs | 1 + 4 files changed, 184 insertions(+) create mode 100644 target/hppa/machine.c -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 57e0bd6f0e..8a87b8a9b3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -351,6 +351,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; +extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 86f5cb0bfe..0e2d12603e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -182,6 +182,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; #else cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; + dc->vmsd = &vmstate_hppa_cpu; #endif cc->do_unaligned_access = hppa_cpu_do_unaligned_access; cc->disas_set_info = hppa_cpu_disas_set_info; diff --git a/target/hppa/machine.c b/target/hppa/machine.c new file mode 100644 index 0000000000..31312b561c --- /dev/null +++ b/target/hppa/machine.c @@ -0,0 +1,181 @@ +/* + * HPPA interrupt helper routines + * + * Copyright (c) 2017 Richard Henderson + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "migration/cpu.h" + +#if TARGET_REGISTER_BITS == 64 +#define qemu_put_betr qemu_put_be64 +#define qemu_get_betr qemu_get_be64 +#define VMSTATE_UINTTL_V(_f, _s, _v) \ + VMSTATE_UINT64_V(_f, _s, _v) +#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) +#else +#define qemu_put_betr qemu_put_be32 +#define qemu_get_betr qemu_get_be32 +#define VMSTATE_UINTTR_V(_f, _s, _v) \ + VMSTATE_UINT32_V(_f, _s, _v) +#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) +#endif + +#define VMSTATE_UINTTR(_f, _s) \ + VMSTATE_UINTTR_V(_f, _s, 0) +#define VMSTATE_UINTTR_ARRAY(_f, _s, _n) \ + VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, 0) + + +static int get_psw(QEMUFile *f, void *opaque, size_t size, VMStateField *field) +{ + CPUHPPAState *env = opaque; + cpu_hppa_put_psw(env, qemu_get_betr(f)); + return 0; +} + +static int put_psw(QEMUFile *f, void *opaque, size_t size, + VMStateField *field, QJSON *vmdesc) +{ + CPUHPPAState *env = opaque; + qemu_put_betr(f, cpu_hppa_get_psw(env)); + return 0; +} + +static const VMStateInfo vmstate_psw = { + .name = "psw", + .get = get_psw, + .put = put_psw, +}; + +/* FIXME: Use the PA2.0 format, which is a superset of the PA1.1 format. */ +static int get_tlb(QEMUFile *f, void *opaque, size_t size, VMStateField *field) +{ + hppa_tlb_entry *ent = opaque; + uint32_t val; + + memset(ent, 0, sizeof(*ent)); + + ent->va_b = qemu_get_be64(f); + ent->pa = qemu_get_betr(f); + val = qemu_get_be32(f); + + ent->entry_valid = extract32(val, 0, 1); + ent->access_id = extract32(val, 1, 18); + ent->u = extract32(val, 19, 1); + ent->ar_pl2 = extract32(val, 20, 2); + ent->ar_pl1 = extract32(val, 22, 2); + ent->ar_type = extract32(val, 24, 3); + ent->b = extract32(val, 27, 1); + ent->d = extract32(val, 28, 1); + ent->t = extract32(val, 29, 1); + + ent->va_e = ent->va_b + TARGET_PAGE_SIZE - 1; + return 0; +} + +static int put_tlb(QEMUFile *f, void *opaque, size_t size, + VMStateField *field, QJSON *vmdesc) +{ + hppa_tlb_entry *ent = opaque; + uint32_t val = 0; + + if (ent->entry_valid) { + val = 1; + val = deposit32(val, 1, 18, ent->access_id); + val = deposit32(val, 19, 1, ent->u); + val = deposit32(val, 20, 2, ent->ar_pl2); + val = deposit32(val, 22, 2, ent->ar_pl1); + val = deposit32(val, 24, 3, ent->ar_type); + val = deposit32(val, 27, 1, ent->b); + val = deposit32(val, 28, 1, ent->d); + val = deposit32(val, 29, 1, ent->t); + } + + qemu_put_be64(f, ent->va_b); + qemu_put_betr(f, ent->pa); + qemu_put_be32(f, val); + return 0; +} + +static const VMStateInfo vmstate_tlb = { + .name = "tlb entry", + .get = get_tlb, + .put = put_tlb, +}; + +static VMStateField vmstate_env_fields[] = { + VMSTATE_UINTTR_ARRAY(gr, CPUHPPAState, 32), + VMSTATE_UINT64_ARRAY(fr, CPUHPPAState, 32), + VMSTATE_UINT64_ARRAY(sr, CPUHPPAState, 8), + VMSTATE_UINTTR_ARRAY(cr, CPUHPPAState, 32), + VMSTATE_UINTTR_ARRAY(cr_back, CPUHPPAState, 2), + VMSTATE_UINTTR_ARRAY(shadow, CPUHPPAState, 7), + + /* Save the architecture value of the psw, not the internally + expanded version. Since this architecture value does not + exist in memory to be stored, this requires a but of hoop + jumping. We want OFFSET=0 so that we effectively pass ENV + to the helper functions, and we need to fill in the name by + hand since there's no field of that name. */ + { + .name = "psw", + .version_id = 0, + .size = sizeof(uint64_t), + .info = &vmstate_psw, + .flags = VMS_SINGLE, + .offset = 0 + }, + + VMSTATE_UINTTR(iaoq_f, CPUHPPAState), + VMSTATE_UINTTR(iaoq_b, CPUHPPAState), + VMSTATE_UINT64(iasq_f, CPUHPPAState), + VMSTATE_UINT64(iasq_b, CPUHPPAState), + + VMSTATE_UINT32(fr0_shadow, CPUHPPAState), + + VMSTATE_ARRAY(tlb, CPUHPPAState, ARRAY_SIZE(((CPUHPPAState*)0)->tlb), 0, + vmstate_tlb, hppa_tlb_entry), + VMSTATE_UINT32(tlb_last, CPUHPPAState), + + VMSTATE_END_OF_LIST() +}; + +static const VMStateDescription vmstate_env = { + .name = "env", + .version_id = 1, + .minimum_version_id = 1, + .fields = vmstate_env_fields, +}; + +static VMStateField vmstate_cpu_fields[] = { + VMSTATE_CPU(), + VMSTATE_STRUCT(env, HPPACPU, 1, vmstate_env, CPUHPPAState), + VMSTATE_END_OF_LIST() +}; + +const VMStateDescription vmstate_hppa_cpu = { + .name = "cpu", + .version_id = 1, + .minimum_version_id = 1, + .fields = vmstate_cpu_fields, +}; diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index dcd60a6839..3359da5341 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1,2 +1,3 @@ obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o obj-y += int_helper.o +obj-$(CONFIG_SOFTMMU) += machine.o From patchwork Mon Jan 22 03:42:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125324 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp951177ljf; Sun, 21 Jan 2018 20:10:26 -0800 (PST) X-Google-Smtp-Source: AH8x225vh2pJMfgXjCH6yY6X55nF6IXpHvoQqJI88XW49y1w/+c8b+9pisNBRvG8w8wFsRtlg17Z X-Received: by 10.129.161.202 with SMTP id y193mr6466157ywg.228.1516594226795; Sun, 21 Jan 2018 20:10:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594226; cv=none; d=google.com; s=arc-20160816; b=cJdZCrCHDz8wgz/DuGsyRn7gvhbGkW/yy5i2JtQt+xSdFITUJPSswIW5y7etowU8JR sXLFGJ++r9QKrrZCEPP1jhYv44UjZh7N2aBQ/hQI66mjGbQtYQfMWqLANlLgiaW3w913 /g6d8fIG69FX3jWsbmoHmNQtasneroFZW8K2LZN7CTfidzffAo1scYhaKijXZfQQzO3l NHVZSAnw857x96TqgdPW371h+9MQP5lPbvBkA2KnqXICcGWp3hqgySTAh31ytGvH19Vr ylM1pVeDwLIVCM+AJ9aWqLr7W0/sICLVssuldeogGUNRgyevwh83lphUsGGYFs7rQhLO uTsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=gCQ4YatksYou5Apg3tk5GECCViHRlF1RM7HQ34t2B0I=; b=pv0ChTmC86C5quGWyJiyCagj11zwXFF2+jWYg4oNCjL/ootvWtqae7GZoPS5tcbHL6 0+oOMy93R2CHOKq5IEvNzNZUdOB0vdNFTNtl03L8k/g6vef9n2bMLkye9dB2wYjtrp2I W84BX1QjdshDKPXU85P8jXMOrLCtGl//FHQzDuQPbo/kb7SBI0uk1tRpcxPuKMHaUdDX yT9ZA3A5iWsvHm3OXAd3Q2+P1JgLVDMFIiIN7CtuQ+meE1iE9wkaDN9+u93jGxaIyOoi Vs+XjUd2rJmTIpySBTdE3uQuOkN/jUweTkN0olEeMkR/x8uP+jsKdT2vMqzG7QjY1Ygo nLdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MjYCW8Nk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:05 -0800 Message-Id: <20180122034217.19593-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 31/43] target/hppa: Implement B,GATE insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/mem_helper.c | 8 ++++++++ target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8a87b8a9b3..79763b254c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -353,6 +353,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9d93894019..e2f94faab5 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -123,6 +123,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, break; default: /* execute: promote to privilege level type & 3 */ prot = x_prot; + break; } /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. */ @@ -318,4 +319,11 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) } return phys; } + +/* Return the ar_type of the TLB at VADDR, or -1. */ +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) +{ + hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); + return ent ? ent->ar_type : -1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e4a140b9a6..c064c9d17b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3771,6 +3771,53 @@ static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } +static DisasJumpType trans_b_gate(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned n = extract32(insn, 1, 1); + unsigned link = extract32(insn, 21, 5); + target_sreg disp = assemble_17(insn); + target_ureg dest = iaoq_dest(ctx, disp); + + /* Make sure the caller hasn't done something weird with the queue. + * ??? This is not quite the same as the PSW[B] bit, which would be + * expensive to track. Real hardware will trap for + * b gateway + * b gateway+4 (in delay slot of first branch) + * However, checking for a non-sequential instruction queue *will* + * diagnose the security hole + * b gateway + * b evil + * in which instructions at evil would run with increased privs. + */ + if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { + return gen_illegal(ctx); + } + +#ifndef CONFIG_USER_ONLY + if (ctx->tb_flags & PSW_C) { + CPUHPPAState *env = ctx->cs->env_ptr; + int type = hppa_artype_for_page(env, ctx->base.pc_next); + /* If we could not find a TLB entry, then we need to generate an + ITLB miss exception so the kernel will provide it. + The resulting TLB fill operation will invalidate this TB and + we will re-translate, at which point we *will* be able to find + the TLB entry and determine if this is in fact a gateway page. */ + if (type < 0) { + return gen_excp(ctx, EXCP_ITLB_MISS); + } + /* No change for non-gateway pages or for priv decrease. */ + if (type >= 4 && type - 4 < ctx->privilege) { + dest = deposit32(dest, 0, 2, type - 4); + } + } else { + dest &= -4; /* priv = 0 */ + } +#endif + + return do_dbranch(ctx, dest, link, n); +} + static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -3849,6 +3896,7 @@ static const DisasInsn table_branch[] = { { 0xe8004000u, 0xfc00fffdu, trans_blr }, { 0xe800c000u, 0xfc00fffdu, trans_bv }, { 0xe800d000u, 0xfc00dffcu, trans_bve }, + { 0xe8002000u, 0xfc00e000u, trans_b_gate }, }; static DisasJumpType trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, From patchwork Mon Jan 22 03:42:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125327 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp952368ljf; Sun, 21 Jan 2018 20:14:50 -0800 (PST) X-Google-Smtp-Source: AH8x226zdB0i+CwpXNf+2g9YT948sPUuGW+x5chZtS/pSmhcqRinNLAOQcUki2a/W2srn73QtbLi X-Received: by 10.129.239.14 with SMTP id o14mr6292007ywm.193.1516594489976; Sun, 21 Jan 2018 20:14:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594489; cv=none; d=google.com; s=arc-20160816; b=JoeYYoKai2Fnzeu00PlfMPmkIhebVgUXHBr35XQYFJx1OuKZs4zl0CNNriXi23a3bz 7JIrrlhGBITAnY2QtmsGm2xy9sRtS5TI2wdbNREreDT6jc7+p8Nll7x4W4Ptwi1hP8qR p+QOWE1CFSa1l6GN53I/IegAqNy90sWw1JtYYVwqOsxf2B4lrgpa4hIbrWRSKZM5Opef roiCR/E6gyq9wGGl6TaL21NSRTHcq3PUZAv4A5N9RDu+vmw1vKIOk1ZvQ7wviShSOWPf 9CRuzFeFkr7K5KIiaVanVxGYbI7qmPYLJy5P3BTGuGQI4MHzwIKwVt+Se2/P8qKEDmTa xWUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=DiACuF9fSwjx/ljspLFoCBRlabayy+kU1qcoqcfzFP4=; b=dxAXJf9VCVhnRsSV27iiTuRWvBR7Gr87MYixJylllcuFDqbQ047GgXanvsZ3BP5la0 hUonEsYY/KoTI3Sv2+5lfSH1dj65X6dJsKQuzziLIliaLtL/0pRNSg5nfgmINj3jJQLe yn3FPf5UMqI8Qq+1vhw/0sRMgY1x2Gzkj1KbxHJXDb19dG0g7bOIPHqoDZDw27fPC/EW YP4s72SpL3NdpSP1howHc0+9vnsd/2hw8jvO0c9iM9r/5oN6Sl78pz2z5pXB4q3DLLRB Rv7wnXHqBTs3S5OBkaUh9qN8nKLpd3ZwhqchB137SK9O5eKw/+l/XfWGYkwgkscbmhFn l49Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QNEKRa0N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:06 -0800 Message-Id: <20180122034217.19593-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 32/43] target/hppa: Only use EXCP_DTLB_MISS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index e2f94faab5..a0a385cb54 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -97,7 +97,9 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, if (ent == NULL || !ent->entry_valid) { phys = 0; prot = 0; - ret = (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); + /* ??? Unconditionally report data tlb miss, + even if this is an instruction fetch. */ + ret = EXCP_DTLB_MISS; goto egress; } From patchwork Mon Jan 22 03:42:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125320 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp950903ljf; Sun, 21 Jan 2018 20:09:36 -0800 (PST) X-Google-Smtp-Source: AH8x225NNLKyDLbtadR5OhP90nOL00fY9oV06d5taY4r4DJPJMFqmmEZCf9asPaY9MO9U7/7d+41 X-Received: by 10.37.49.134 with SMTP id x128mr6436931ybx.388.1516594176693; Sun, 21 Jan 2018 20:09:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594176; cv=none; d=google.com; s=arc-20160816; b=cocwGZdbg70yKlcPWeLHDTvrb+ugDTARgO8NH9zbYbPoWYqu0MJegezeFcq6yZp2tt ZrFhM+gKcsnm43SsnnY2cx5mudsk1BN/BixmnMToE0SETSYQ7WzUT84yoWfV9xVsEa7B tMBSBqZa9jmR54Fk3zSgURkXP3gdE/sqdIRcVw8ZPM8LlPkqH4Ia5f4NQM46Zy0qcOXu pvmwThLSOMRhkbbxwB2Psi7QpFwiB6+8mCbO2h21b8SPlrmiRcKlHxiXzYqnjFgjx8UU eHWqk0bIEmOxZ1Swoahfmdx3D4Av6MRWkOOW/JpQHX1q/so5ZQdP1eHqPMKl+JQWbLCx cnuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Vti81VcYGKqh4UY2jYTWy88W87kMYI3hQYWy+iTEQXk=; b=OGcT1bS2i+0Cjgs5mLAbvXjOEbYpfg06v8ZQ9weIPMJWj63N0JNC5VpEOmzAodZbiD tXtlsChAo9DpudeGEktiOjniLRT6cnfbxXCZEfeWLnzbPuSyicr5GxJcipMTa8QcaTu3 9QQW/emStIRrkMdv26F56lbj6xvEbapM+wCwOeE3ib2ZZFwx8EvOjuQDXL9cYhTQZsCo RS3/7WBSCHkHWsGmYp9UC98/61bbb+ErixGng8CkWIBTyRuLUkUsdTk6sVeSSrbfwHXu MG874qsv+bt+vOIfF0CAeEgSpyhCKumD74VQiwt576MAOlXyuVmRPeFKC4tGEUjBHA0b Eu2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OSZdIz5P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id u7si1746434ybf.332.2018.01.21.20.09.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 21 Jan 2018 20:09:36 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OSZdIz5P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41802 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edTQO-0000aG-1p for patch@linaro.org; Sun, 21 Jan 2018 23:09:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edT0p-0005w1-Lp for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:43:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edT0m-0006l1-JW for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:43:11 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:35400) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edT0m-0006ik-Cv for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:43:08 -0500 Received: by mail-pf0-x244.google.com with SMTP id t12so6084819pfg.2 for ; Sun, 21 Jan 2018 19:43:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vti81VcYGKqh4UY2jYTWy88W87kMYI3hQYWy+iTEQXk=; b=OSZdIz5PMSYe88TwizTE/y0mteNGFRKRVshlmAqVz11NUf2CEHPh6RcWSVC6FKroGC AaozhtwJoRTSbRRYc6FiLvcYNoy3F3ohlWmQHkezpYV41FakscCmjemqAtz4RV60agvL dcBen36OXkXRPcc6baasYmfj314cmqO/RohvQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vti81VcYGKqh4UY2jYTWy88W87kMYI3hQYWy+iTEQXk=; b=S/PrCR4a9WaycAxwXeR4BKfv0h+XnYMZuQxtxKxGKwHJSAJRC/kTcL94jPyOxegtoE 2/w+/PK+7xTk9ZPfXY9PFLx52HaaijiENvAh/hMvuFU94dpBHhODTH/4G5/xcf295jsu RYJqZ2n6TR6QRIsIb8gZZobIZM/QQ9Uq8MHU2CToUpBqWjmEYvsUr6suWcTpQtnNdeap qfy5WNIvW+sxhfvsHtKHj4kxGEq2dfAxf+2P8S3BWjNgNOqtotVs0++KvitNV/57olur raZspa5+1m73UaJI6su+tRvUZG94394zsuA3WkSvNrdfVLBEUf7a7u5Rpk+9JASRjgPS E45w== X-Gm-Message-State: AKwxytdtj+FENn+aVm+eTj8O4Q0uwsv1QbwpLdlFc+k2GWUWvgyfF8Pw 1KGKnNygPXEE5/W2fRHniOg7STxVhno= X-Received: by 10.99.171.78 with SMTP id k14mr6014540pgp.287.1516592587075; Sun, 21 Jan 2018 19:43:07 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:07 -0800 Message-Id: <20180122034217.19593-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 33/43] qom: Add MMU_DEBUG_LOAD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Andreas_F=C3=A4rber?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This lets us tell bottom levels of virtual memory translation routines that the access is from within QEMU itself and bypass certain tests. Cc: Andreas Färber Signed-off-by: Richard Henderson --- include/qom/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 93bd546879..6367acca97 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -64,7 +64,8 @@ typedef uint64_t vaddr; typedef enum MMUAccessType { MMU_DATA_LOAD = 0, MMU_DATA_STORE = 1, - MMU_INST_FETCH = 2 + MMU_INST_FETCH = 2, + MMU_DEBUG_LOAD = 3 } MMUAccessType; typedef struct CPUWatchpoint CPUWatchpoint; From patchwork Mon Jan 22 03:42:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125329 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp953267ljf; Sun, 21 Jan 2018 20:18:13 -0800 (PST) X-Google-Smtp-Source: AH8x2249Mo8bJZz5g592cjsR3IWBvhnWBvQKELNK+pkUqOMvvJzeZLZ85MwlkYBL3N52URRyf6Fd X-Received: by 10.129.172.14 with SMTP id k14mr6215023ywh.20.1516594693369; Sun, 21 Jan 2018 20:18:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594693; cv=none; d=google.com; s=arc-20160816; b=vSc66nmUeDvDW2aWbee++nt6BKM+HnKxo3t7mQ/zY+Uvt27XPBfHY3QwLvY8H/AQkA 2ZcG2jW6GWebzFVJ7iCrBG8nZw4jt2DPq+6yvvJaGNkXAY+VjFeF6fF1qTXsveawvg13 OL5JSA8S8MTh2T+62R1Lj8gYz1p1dEm1vWu5pJMP6U6WKRUQ1Ci5+D5NcyMBA3d36/BK jlSnSAIIYibvCPjtw3vwafmoRSog2S0zM1aTse7B9JIouM3uT0CJNJiFtup6TA/mQSNC KxB4/T7yDYt+Zc1uluR6hdz0RxiTgmNUkZDx0DGSXuOpZWoI4QQ9z7UxCWh96+r/RzLJ 9zVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=OsW7WXWA3vPnPbVumLykTyx4Yq9vIWzD5fZT2ziin/U=; b=VKK/HFG5pWajiYNjRKX/s10Cs6GWPg4gECdbJTbhefNAcSW6kynKR+S/AHHDCKqWyW HIOqctSV9J/5iR8HvZHkkZmaqixLXtTLB9nO0Kdr3mzjSiJdRcwD17vFJVrvJRLcupRm IJThRYGLspZqBSN7sa6czi0nHVpVi7LA+tmNfWaZVlKCQ82pF8gRijHkRcV/hjOA1E1b i5hCDbgHvGl+kt7iWfvAj5qVss6ZJfMLL2UO/PaStDC0kh6UugQQWsKZ3EE8CRXQDxvR 2290zgZn/hsyLnAWs2Nv3z7Qs01cL/8tMIQpozbZVp+TI7YJiNqwC9VSEFE+43U0IcA+ OUrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RaLo1UKS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:08 -0800 Message-Id: <20180122034217.19593-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 34/43] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Bypass any tlb protection checks, as this is not a "real" access to memory per the architecture. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 19 ++++++++++++++----- 2 files changed, 15 insertions(+), 6 deletions(-) -- 2.14.3 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index ee72769544..e831944b8d 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -154,7 +154,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) int prot, t; vaddr = hppa_form_gva_psw(old_psw, iasq_f, iaoq_f & -4); - t = hppa_get_physical_address(env, vaddr, 0, MMU_INST_FETCH, + t = hppa_get_physical_address(env, vaddr, 0, MMU_DEBUG_LOAD, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a0a385cb54..4bdc4d77e5 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -131,12 +131,21 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. */ /* Map MMUAccessType to QEMU protection. */ - if (ifetch) { - a_prot = PROT_EXEC; - } else if (type == MMU_DATA_STORE) { - a_prot = PROT_WRITE; - } else { + switch (type) { + case MMU_DATA_LOAD: a_prot = PROT_READ; + break; + case MMU_DATA_STORE: + a_prot = PROT_WRITE; + break; + case MMU_INST_FETCH: + a_prot = PROT_EXEC; + break; + case MMU_DEBUG_LOAD: + ret = -1; + goto egress; + default: + g_assert_not_reached(); } if (unlikely(!(prot & a_prot))) { From patchwork Mon Jan 22 03:42:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125322 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp951088ljf; Sun, 21 Jan 2018 20:10:12 -0800 (PST) X-Google-Smtp-Source: AH8x227CTOB9+qq/AgEu6D/oXJKooxXXWvynakzVZ0HwK+tdlEXN9UVXzgEnoPe0JfC1OeBRerIY X-Received: by 10.37.220.204 with SMTP id y195mr6324592ybe.435.1516594212349; Sun, 21 Jan 2018 20:10:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594212; cv=none; d=google.com; s=arc-20160816; b=clld1NE3MJi3yiJTAi1BRZ/JSvlQzfrgLu9Ul9dgO7fSC64ELSl1RB25btu8TLODJL YrXWKcRQjlrsNlwIMvZDdUsLSkPqLpbQ8zCped+Z+Ngta4mTvSOs1Zjkx3JMTv/+d3rm Jn2mFtygR47bG/eALQ2UGgfd9B6kwBnYC5vgNBjNq4SeSU5mYcvYRYq8avJCZvb/VAYK KSrhm3eoQHTt3EKFLPLOF55Pa/z39Vq7nsYxgeCVDewQyLttg3+GiqF/IN+YfEQh5ebB nelCjcC+ScpphntclAZBkQVnFPRO6k60MTNcw2fQzsTUNRgWfcCSFy7Bo0euR1WXX42M Kubg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uM9VQnVeD/8UYYaqpWmvqQvdYHZqsf/NPRdAvweorjg=; b=W3oxr+N/K0uX9QSlRcuXGWm4ufJOCZyaMnybYdvZPfnCxDXcq5GXLddXh7Oy7IghDk wKpBxx0vCunDZN6EPmOpUzkd48YLVPVfjNidrNOVl9oIs6u1swejUBCVnx2t3nTPGvpx 1FDKIQ3LjRcn+KMAkytsN+IE5D0NAOvpUUdn7GigJQTFb6Kzuy5SJvBhtYqOSm0a23/z RsIVb/gJQfPHq1OLlk1X3P6CuMImGooKKxJZO78+1C9LoXknCUv5h3MvPewJhYWnm91s Ckv0obObgZCdTPxAW3Dlar/GHobkFEU1iiMKrR+GWf8oRo/4Q4iGFymCxH5/06uHLlPG l8xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g48PFGCv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:09 -0800 Message-Id: <20180122034217.19593-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 35/43] target/hppa: Increase number of temp regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c064c9d17b..6cf4e37062 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -273,7 +273,7 @@ typedef struct DisasContext { TCGv_reg iaoq_n_var; int ntempr, ntempl; - TCGv_reg tempr[4]; + TCGv_reg tempr[8]; TCGv_tl templ[4]; DisasCond null_cond; From patchwork Mon Jan 22 03:42:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125326 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp952109ljf; Sun, 21 Jan 2018 20:13:57 -0800 (PST) X-Google-Smtp-Source: AH8x2257a+Du7/0bJBA2WkjmYOseD4CLdvqsJFIA33bUnN2zGGhzYYjyC1Sxxqw1boKpHC6AvIqg X-Received: by 10.129.25.214 with SMTP id 205mr6133585ywz.340.1516594436957; Sun, 21 Jan 2018 20:13:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594436; cv=none; d=google.com; s=arc-20160816; b=ddxFMTsQUxoSac229nXj7Ei0WhXkYaLE9gagnUpCOw/6YnA2uNxu0OFK4ur/Iagh7e 0P8HT4xhZRX19ik9JK1xg3KlH0EVszNtQrVQq5o20eUx29Eriy4Zqok9KkfbwzrisuGk bFe33nlPyaS5YWWqvNLb6u6Yo8yL+t8Ncqiu+ahzn4FTNRa+tqGBxgkPS10osmhrSEWZ L4nhLXu4fdPmTrVWPN++R0XE8qIHiq6ZW6PfU0KND4vjGcUufPQky4vDJ510gmiLJXTS gy2LsyJdwSW/tHS3M3QV5BN7nMdeMRSiiG4apPXRsPfuOv45ve/udZo0ExCbwg+qsgXC tA1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wR+xk8vf2Y3F0KFMq9XKNE7FWHXsOvffWVx1kV0b0yo=; b=tD+qx2djdDTxInyeLrexWD1IYMZsdVg1VpGY5CSA/uNzqu+PFWWAIyEX5mAYFb5fZM 789BKc7WWt8aW7wQvHwgsnsg0gRwA08xuiSsREO1Zez46X6GzvmFcPP9PVzoz3rW/I5Y SVdqdZFDZp8mKQANBHfACMD2G71VbpKA5IhRhjkhGWewqNt2verKsoyqvnjg1yfzz8mQ esE3MItwv60QK9EFeXhnjhqohU5fKdgCi6NxelBH8E2bGMBYZ0dNwzQSA/Ak2LFCa/9d cwbjydQfWbUff6wQ886CGZPNbmUM1DmwGvCVHCTpTgq93gSaCLGIAiGlks0kC1c8cnzt uhfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C3LcgGPv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:10 -0800 Message-Id: <20180122034217.19593-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 36/43] target/hppa: Fix comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Signed-off-by: Helge Deller Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6cf4e37062..965641f380 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3182,7 +3182,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) /* FSTW without modification. */ return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: - /* LDW with modification. */ + /* STW with modification. */ return do_store(ctx, rt, rb, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); From patchwork Mon Jan 22 03:42:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125332 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp953955ljf; Sun, 21 Jan 2018 20:20:35 -0800 (PST) X-Google-Smtp-Source: AH8x226eWKX5hbBsOfqRG3BOA/9intwR8tPw7aH+hJA/fGdKP27Z3RK0FFW5RElR2JsITb0wpSw/ X-Received: by 10.37.202.137 with SMTP id a131mr6306604ybg.198.1516594835703; Sun, 21 Jan 2018 20:20:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594835; cv=none; d=google.com; s=arc-20160816; b=kW92CxNIguMawQNoJZdlO6nicBAJlW4L1/EZjodiQLQ7lBEAd96x2FGXDw0JNV3Wn5 KD5g+raaTh5JFH31iAtUmz6dNYpQv880hsAmvEK0FRqlbHvHK0PpY79Hj/ieyqS/YSos jpnU4kRyxQgCGN9TQE2cTNSVDJErmQ+D2JF0l3QvOj4F2XyQfy0KQ8HW4wcL0Jqxk7Jr TsNvP5e4BEjNGW+1ZEqCl6pHXpfzs/RHTpJgbwF9VKITMBb1fomiiHzQXU086/+/JkeQ vU9w8Q4rM33vGqpZaUPBnZwW/ovyCs8CgWGi0I1RHFx2ec2ldD3ZhYg1ZWM4t8EgglkR ZIFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=SKNm+ebBE43/fKC6IkH85JW/TPVSxjUx6/2Ko5bVkkk=; b=XrOVZLJMUjeJ3SqHLyWMJ+7BpbqWokeMZFs1khyCTsUloXzrXLkG4ERosvYHTh44nQ c8O7DHdq0KmNAGWbFAxEbyjDhkeErzorNSS6GN/JiL79zr5TAmoHgp9KZC1nxRLC3jfu u/nz9tkrmiHq7pqET1sNubJc0iHRVq8Mmfxu0mO0gG8SnTfyX8V9WJWtl8ZJZem9F92E YHO1WiQEyhsHftoFp1J1i/DmYHW5T90QdIYfyJAnS0L6R9S7a46xWbip2jCJ46JJfdqV neDia+PJaK3FcJxkrlTUpRsiHiPY2MTLfOFUM0yrmMUcYH/EqonT+fNVWMLo2Oq6IT7l n40Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=N88vU21e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:11 -0800 Message-Id: <20180122034217.19593-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 37/43] target/hppa: Implement LDSID for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Signed-off-by: Helge Deller Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 965641f380..76ed7e1ad4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2200,8 +2200,20 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); TCGv_reg dest = dest_gpr(ctx, rt); - /* Since we don't implement space registers, this returns zero. */ +#ifdef CONFIG_USER_ONLY + /* We don't implement space registers in user mode. */ tcg_gen_movi_reg(dest, 0); +#else + unsigned rb = extract32(insn, 21, 5); + unsigned sp = extract32(insn, 14, 2); + TCGv_i64 t0 = tcg_temp_new_i64(); + + tcg_gen_mov_i64(t0, space_select(ctx, sp, load_gpr(ctx, rb))); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_reg(dest, t0); + + tcg_temp_free_i64(t0); +#endif save_gpr(ctx, rt, dest); cond_free(&ctx->null_cond); From patchwork Mon Jan 22 03:42:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125330 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp953300ljf; Sun, 21 Jan 2018 20:18:20 -0800 (PST) X-Google-Smtp-Source: AH8x226n8NAMIPMBgngNy5n0JqnkspygDjkvtoQ32dn/Uhr2I8lFq5izozsWELBRawcIdTw8VG7k X-Received: by 10.37.187.72 with SMTP id b8mr6170338ybk.89.1516594700545; Sun, 21 Jan 2018 20:18:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594700; cv=none; d=google.com; s=arc-20160816; b=L7cwGNjthPvvGMIFIrDEOoV4OzGzFkd0yOfuR8SrpGp5d/cnmYX+0akgi9N15L4Ejq iG64Z/+UZw7pDOVY6ToAO0ctu10nZcYGWdfkO4js0+Y/tirbSuew1rY+0y6FyxVBRQcK bO2Xj4yjiK9yvQ4e+I/Z9PKyy+Nxm2+kSCYNkKH5a6VUt5VVCWYpyNoyZs2xBufvQvmA 5r1ycR2pAw1Sp5kBVrtP7tJweE/3sVJQaNx460gfd7ArMmKyqqljrAkUmnqWMDAuycVS Yw/UIinTXlm6d4VFy02ZoWeVbc1pFzFBNBKUS/OJYnmIMTyFZaUlYHC3mPBhKaaIf7pR nZiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=NFK44SG8TiV+12Xa+isXZfQRMWHIoxl2sIziVt78rTA=; b=k04T7trF6UMgNrJjQcuWj5SbT9fs+bXG/uK0EQEp9pb/dR0nZnFQtCDrgwSD6GY4Yr Jhc6fjuad0Bw8zQO5FXwEwA3RnuY2xrFQI3XXGL55wtmhAgfnhx5RtOyupY/8A56gFM+ TSCASZgb1darnhu4CuwNnVpLS9nZ7FWV+nrwFGuwG4sJ+Y6WvFJzdIYlDwy9ZVaptbu7 u2+Cl9/7U49kXHzD6t9yHoyfZ00oKh6Np102gMyOcgUUidr9UuQzcVrbj52LO9iIIgq7 kozub8/Z9S/1+ktJRvqrILvLrf+dZmXyZtX8IK0/q8ltyryTm/3kPEJUT5nPGA5gRWyT /Xdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ncl9C9+W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:12 -0800 Message-Id: <20180122034217.19593-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 38/43] target/hppa: Implement a pause instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 76ed7e1ad4..8884754f05 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2815,9 +2815,45 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } +#ifndef CONFIG_USER_ONLY +/* These are QEMU extensions and are nops in the real architecture: + * + * or %r10,%r10,%r10 -- idle loop; wait for interrupt + * or %r31,%r31,%r31 -- death loop; offline cpu + * currently implemented as idle. + */ +static DisasJumpType trans_pause(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + TCGv_i32 tmp; + + /* No need to check for supervisor, as userland can only pause + until the next timer interrupt. */ + nullify_over(ctx); + + /* Advance the instruction queue. */ + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + nullify_set(ctx, 0); + + /* Tell the qemu main loop to halt until this cpu has work. */ + tmp = tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + gen_excp_1(EXCP_HALTED); + + return nullify_end(ctx, DISAS_NORETURN); +} +#endif + static const DisasInsn table_arith_log[] = { { 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */ { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */ +#ifndef CONFIG_USER_ONLY + { 0x094a024au, 0xffffffffu, trans_pause }, /* or r10,r10,r10 */ + { 0x0bff025fu, 0xffffffffu, trans_pause }, /* or r31,r31,r31 */ +#endif { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_reg }, { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_reg }, { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_reg }, From patchwork Mon Jan 22 03:42:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125323 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp951151ljf; Sun, 21 Jan 2018 20:10:21 -0800 (PST) X-Google-Smtp-Source: AH8x224SoCernUD1h1Rfm4XPge8Fm7gH0p42alVYO8u8iIfxcsWyEFw6cL8BRzm6kYqm9tVmh+8P X-Received: by 10.129.83.3 with SMTP id h3mr6179425ywb.268.1516594221733; Sun, 21 Jan 2018 20:10:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594221; cv=none; d=google.com; s=arc-20160816; b=D6P9CIC/s5tu44NEpLdJQe6A4j6S9dUJCq7WhC7usOPTa+F5fb7xjp4L/D8+MZ1Omw gSnr7e5ShEktDddr0UzQfZRWhFj9oFzeUpXKQ9uDTjTf4LiGr3bZ2Bz0sf0uiaUPmmI6 /f6EHz4bzcP1SQxMTzM19KIbjk63gF/5ag8WYVtHkj8jeUOs8woo1D4K1vyWKAxETbFT 64y/FzkBpezOvFjVQUGtsG1K5v10wWQK5NFqJYY0kFJDeQaYU6pThz/3BmnjIcmpqIcF Q98sI+W8yxvjl4rsZQRVBEgG3PK3SyG5ATuQAA+apZLl2JEF520aUlZqXkMumRLjj6Y4 yKew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=I7hJmiQ1Q9yqUQ481WVu4Y1jv4Ki0Jen8UGkxnlcN08=; b=hlgiPGB7+zovw/WINNkTezO5Z8+z4Isl2nb29bN6go7oTNAA+NiCo64XSOj2Jf9lBC 8kuutmsc/N4Ur1M6WLclYP2fTUS7tkDkzoW0ql5AVJdArCvAZUaYmr/UIcxcqLY4cBN5 tfMiYkkOr7mTlWzuZd9+BebGkWAV47FC279XsgU7Z0+SOEWrwbLJyvmmAUt/Kv2KNWEY mY804hPtEmiu75VVdgxErDwMGX4gFHwHfh7omTSsgXZnX9xkxxJdqP17hGPBqCNhEp+1 Hj5yc+0rkrRiwvsTcJqJygBf60hUvoUNQsvojMDBIkQ+Z04pT/ZwLEDufLUZ6QvMY9Vv /wZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I2WAboz0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:13 -0800 Message-Id: <20180122034217.19593-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 39/43] target/hppa: Implement STWA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8884754f05..74f78ab4e0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3097,6 +3097,22 @@ static DisasJumpType trans_ldwa_idx_x(DisasContext *ctx, uint32_t insn, ctx->mmu_idx = hold_mmu_idx; return ret; } + +static DisasJumpType trans_stwa_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx = ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx = MMU_PHYS_IDX; + ret = trans_st_idx_i(ctx, insn, di); + ctx->mmu_idx = hold_mmu_idx; + return ret; +} #endif static const DisasInsn table_index_mem[] = { @@ -3106,8 +3122,9 @@ static const DisasInsn table_index_mem[] = { { 0x0c0001c0u, 0xfc0003c0, trans_ldcw }, { 0x0c001300u, 0xfc0013c0, trans_stby }, #ifndef CONFIG_USER_ONLY - { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ { 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */ + { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ + { 0x0c001380u, 0xfc00d3c0, trans_stwa_idx_i }, /* STWA, im */ #endif }; From patchwork Mon Jan 22 03:42:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125331 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp953398ljf; Sun, 21 Jan 2018 20:18:47 -0800 (PST) X-Google-Smtp-Source: AH8x225udR9+miFUWgJpfvxqO3M/UM+4nqE61+KcyZzpzmUa9kwwuzYJjzBivdUfoBK+Yi68gHJ9 X-Received: by 10.13.201.197 with SMTP id l188mr6289554ywd.132.1516594726957; Sun, 21 Jan 2018 20:18:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594726; cv=none; d=google.com; s=arc-20160816; b=ACGsnPI67floQb8bqrFpgauFJO9++VBJQHXD0GvyCWQyJefUv0pacPSjYPeh734ZsO 1kNnnZWH+tdAea0rvkpVLbblhxnogSxKUB2Jg4RiDQVGWEGGWIvWwoFjI2Fdox1Tq6uK V8jA4aRsYs5QnGzvUGxu0E4096ELq+pMd4pWwZmKl9FntHgqcWzM4mJiEk0htVrQwVHt DDnzl3dYhmDl1IRZgsg1B8WHBXzVDrhA/EEb2rQLFZNNHaQ0ZdyTotIbxcB1E28EhTOe yh5K6Yw7sW0fp6H5NwRkf2eDbeVeCp3Y62pnIiciGyedphwMaelCBf6ZCMVj3xc2NlsD Q+7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=d7S8Ce5lJfY62ku+UN5mHsL1FCYRy5z73FBQrD8A3sc=; b=JiR5oMhCY+nRi/C2jqa5QiBhmBJkg3cL+dCu1subssDOD/ryP9GxHr0gmQL1rbuTXi U69pvRMnbeWlCRKSO27IckN7smOZtR9zefbTYTAitIcfKQpu+aPLMJOWVv+FKX1rkX1Y 3i/nZ6rGUOs1uJ2/aHpwPNWtEUgcU5uRmI5lCPt2iJGi0CjWSge1vAr550QGyYP7Tm1G ON6pJcBgL11qpoqpAS/o+r26vbwP7Uj0BWAuXn3nHzwwFYgzQwFNZEfsEj0eLbJTIAGW 7JARxIq4il0JG5/1HZ4+Hhm8jrVcR+vyV/2UdUlIAF8/yZiME0Zo5AAVphuE9h2kL4UR cKLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=W2yoWHiO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:14 -0800 Message-Id: <20180122034217.19593-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 40/43] target/hppa: Enable MTTCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 6 ++++++ configure | 1 + 2 files changed, 7 insertions(+) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 79763b254c..3df3ebd19d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif +/* PA-RISC 1.x processors have a strong memory model. */ +/* ??? While we do not yet implement PA-RISC 2.0, those processors have + a weak memory model, but with TLB bits that force ordering on a per-page + basis. It's probably easier to fall back to a strong memory model. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #define CPUArchState struct CPUHPPAState #include "exec/cpu-defs.h" diff --git a/configure b/configure index 6d8c996c62..420d50a47d 100755 --- a/configure +++ b/configure @@ -6522,6 +6522,7 @@ case "$target_name" in cris) ;; hppa) + mttcg="yes" ;; lm32) ;; From patchwork Mon Jan 22 03:42:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125328 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp952517ljf; Sun, 21 Jan 2018 20:15:26 -0800 (PST) X-Google-Smtp-Source: AH8x226OFaKv1YVyke65KxeNNxBZb3uuIKRAGhlZ2wU0vtro6rG9OzFKwTuuCiDOtwrBa9q9FkgE X-Received: by 10.129.87.65 with SMTP id l62mr6309635ywb.380.1516594526463; Sun, 21 Jan 2018 20:15:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594526; cv=none; d=google.com; s=arc-20160816; b=HZg1jxmN+jnf1Qfxb0vnreiWnbPoqemIuB0x+xiyCG60IEBCYX5cV3r5H0GyTx3bbg XbUO1eTn+TPD0VYYzYXnVmGq3f3mtJYJTi5ZhJi9ShQjGl4FfbzOjn/UDmdyQVq7L+Fx eN5jxfq1kmjYw0NaPd140xSlpXUydlZF4LNqHI2gZzj/NYGJvJGPbuPnsh9p+Rm7Qczv FfbQTSZPZ7F8Yj9EqrjbhNkvOQIiBcfr+djMZOUCdIrAzRBiezofk7pHeV4NYlVQg94s +46weVzZz0dG9F0x/olCaS8GpzPrdgIzNvQzxOLGXMxggT1fLSgkmRTUqX9E2RlvyNiV oZlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=DbjwEiczyexg7GdZVK9cxx7OlQ/GenRutXrNZ4ZEASU=; b=pMAYiuiQGO1RT93M0+sk7Hlv6Pcsu/yBKiFA4NibqAWhovp19qjbnLsS1wdqNH1HiA /hJcC34mvEUUkRY5DKqAtVBNye9Y4TfRtJuJg+ahGdFG+42dhBJILXL3oeti+xQ8lgiT h1/GiXyXBbRvowN9NYNpWetH4N0rR0BGAjRTxWr4Gx/Vb8ZIKkdksS5h/pN2y1i84i9e 4cWVRgM1M0QDwGdX9iQPsxggWBIeMIv62RMe78ACwKcBQR6YUfCLOJVmPXtNCJMR1taD oDfWZK7Zf8pabB7nAzuD4pecR3wfRCQkp0Ts8ZdssHmu9bao79x/1prEbpLGlxQO0eSK UtIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gjoJpCyz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:15 -0800 Message-Id: <20180122034217.19593-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::232 Subject: [Qemu-devel] [PULL 41/43] hw/hppa: Implement DINO system board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Now that we have the prerequisites in target/hppa/, implement the hardware for a PA7100LC. This also enables build for hppa-softmmu. Signed-off-by: Helge Deller [rth: Since it is all new code, squashed all branch development withing hw/hppa/ to a single patch.] Signed-off-by: Richard Henderson --- Makefile.objs | 1 + hw/hppa/hppa_hardware.h | 65 +++++ hw/hppa/hppa_sys.h | 24 ++ hw/hppa/dino.c | 519 +++++++++++++++++++++++++++++++++++++++ hw/hppa/machine.c | 247 ++++++++++++++++++- hw/hppa/pci.c | 90 +++++++ default-configs/hppa-softmmu.mak | 14 ++ hw/hppa/Makefile.objs | 2 +- hw/hppa/trace-events | 4 + 9 files changed, 963 insertions(+), 3 deletions(-) create mode 100644 hw/hppa/hppa_hardware.h create mode 100644 hw/hppa/hppa_sys.h create mode 100644 hw/hppa/dino.c create mode 100644 hw/hppa/pci.c create mode 100644 default-configs/hppa-softmmu.mak create mode 100644 hw/hppa/trace-events -- 2.14.3 diff --git a/Makefile.objs b/Makefile.objs index 669d8d684d..c52925133a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -155,6 +155,7 @@ trace-events-subdirs += hw/vfio trace-events-subdirs += hw/acpi trace-events-subdirs += hw/arm trace-events-subdirs += hw/alpha +trace-events-subdirs += hw/hppa trace-events-subdirs += hw/xen trace-events-subdirs += hw/ide trace-events-subdirs += ui diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h new file mode 100644 index 0000000000..4ebb8a7883 --- /dev/null +++ b/hw/hppa/hppa_hardware.h @@ -0,0 +1,65 @@ +/* HPPA cores and system support chips. */ + +#define FIRMWARE_START 0xf0000000 +#define FIRMWARE_END 0xf0800000 + +#define DEVICE_HPA_LEN 0x00100000 + +#define GSC_HPA 0xffc00000 +#define DINO_HPA 0xfff80000 +#define DINO_UART_HPA 0xfff83000 +#define DINO_UART_BASE 0xfff83800 +#define DINO_SCSI_HPA 0xfff8c000 +#define LASI_HPA 0xffd00000 +#define LASI_UART_HPA 0xffd05000 +#define LASI_SCSI_HPA 0xffd06000 +#define LASI_LAN_HPA 0xffd07000 +#define LASI_LPT_HPA 0xffd02000 +#define LASI_AUDIO_HPA 0xffd04000 +#define LASI_PS2KBD_HPA 0xffd08000 +#define LASI_PS2MOU_HPA 0xffd08100 +#define LASI_GFX_HPA 0xf8000000 +#define CPU_HPA 0xfff10000 +#define MEMORY_HPA 0xfffbf000 + +#define PCI_HPA DINO_HPA /* PCI bus */ +#define IDE_HPA 0xf9000000 /* Boot disc controller */ + +/* offsets to DINO HPA: */ +#define DINO_PCI_ADDR 0x064 +#define DINO_CONFIG_DATA 0x068 +#define DINO_IO_DATA 0x06c + +#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) +#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) + +#define PORT_SERIAL1 (DINO_UART_HPA + 0x800) +#define PORT_SERIAL2 (LASI_UART_HPA + 0x800) + +#define HPPA_MAX_CPUS 32 /* max. number of SMP CPUs */ +#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ + + +#if 0 +[ 2.160168] 1. Phantom PseudoBC GSC+ Port at 0xffc00000 [8] { 7, 0x0, 0x504, 0x00000 } +[ 2.260162] 2. Dino PCI Bridge at 0xfff80000 [8/0] { 13, 0x3, 0x680, 0x0000a } +[ 2.350158] 3. Merlin+ 132 Dino RS-232 at 0xfff83000 [8/0/63] { 10, 0x0, 0x022, 0x0008c } +[ 2.450160] 4. Merlin 160 Core FW-SCSI at 0xfff8c000 [8/12] { 4, 0x0, 0x03d, 0x00089 } +[ 2.550161] 5. Merlin 160 Core BA at 0xffd00000 [8/16] { 11, 0x0, 0x03d, 0x00081 }, additional addresses: 0xffd0c000 0xffc00000 +[ 2.700165] 6. Merlin 160 Core RS-232 at 0xffd05000 [8/16/4] { 10, 0x0, 0x03d, 0x0008c } +[ 2.800160] 7. Merlin 160 Core SCSI at 0xffd06000 [8/16/5] { 10, 0x0, 0x03d, 0x00082 } +[ 2.900162] 8. Merlin 160 Core LAN (802.3) at 0xffd07000 [8/16/6] { 10, 0x0, 0x03d, 0x0008a } +[ 3.010187] 9. Merlin 160 Core Centronics at 0xffd02000 [8/16/0] { 10, 0x0, 0x03d, 0x00074 }, additional addresses: 0xffd01000 0xffd03000 +[ 3.170204] 10. Merlin 160 Core Audio at 0xffd04000 [8/16/1] { 10, 0x4, 0x03d, 0x0007b } +[ 3.270157] 11. Merlin 160 Core PS/2 Port at 0xffd08000 [8/16/7] { 10, 0x0, 0x03d, 0x00084 } +[ 3.370151] 12. Merlin 160 Core PS/2 Port at 0xffd08100 [8/16/8] { 10, 0x0, 0x03d, 0x00084 } +[ 3.480148] 13. Coral SGC Graphics at 0xfa000000 [8/4] { 10, 0x0, 0x004, 0x00077 } +[ 3.570145] 14. Coral SGC Graphics at 0xf4000000 [8/8] { 10, 0x0, 0x004, 0x00077 } +[ 3.670146] 15. Gecko GSC Core Graphics at 0xf8000000 [8/24] { 10, 0x0, 0x016, 0x00085 }, additional addresses: 0xf0011000 +[ 3.810147] 16. Merlin L2 160 (9000/778/B160L) at 0xfffbe000 [62] { 0, 0x0, 0x502, 0x00004 } +[ 3.920139] 17. Memory at 0xfffbf000 [63] { 1, 0x0, 0x067, 0x00009 } +[ 4.000142] 18. Merlin+ 132 Dino PS/2 Port at 0xfff81000 [1] { 10, 0x0, 0x022, 0x00096 } +[ 4.231309] CPU(s): 1 out of 1 PA7300LC (PCX-L2) at 160.000000 MHz online + +./hppa-softmmu/qemu-system-hppa -kernel bios.bin -nographic -serial mon:stdio +#endif diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h new file mode 100644 index 0000000000..a182d1f34e --- /dev/null +++ b/hw/hppa/hppa_sys.h @@ -0,0 +1,24 @@ +/* HPPA cores and system support chips. */ + +#ifndef HW_HPPA_SYS_H +#define HW_HPPA_SYS_H + +#include "target/hppa/cpu-qom.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_host.h" +#include "hw/ide.h" +#include "hw/i386/pc.h" +#include "hw/irq.h" + +#include "hw/hppa/hppa_hardware.h" + +PCIBus *dino_init(MemoryRegion *, qemu_irq *, qemu_irq *); + +#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" + +/* hppa_pci.c. */ +extern const MemoryRegionOps hppa_pci_ignore_ops; +extern const MemoryRegionOps hppa_pci_conf1_ops; +extern const MemoryRegionOps hppa_pci_iack_ops; + +#endif diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c new file mode 100644 index 0000000000..ad16c055c0 --- /dev/null +++ b/hw/hppa/dino.c @@ -0,0 +1,519 @@ +/* + * HP-PARISC Dino PCI chipset emulation. + * + * (C) 2017 by Helge Deller + * + * This work is licensed under the GNU GPL license version 2 or later. + * + * Documentation available at: + * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf + * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/devices.h" +#include "sysemu/sysemu.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hppa_sys.h" +#include "exec/address-spaces.h" + + +#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" + +#define DINO_IAR0 0x004 +#define DINO_IODC 0x008 +#define DINO_IRR0 0x00C /* RO */ +#define DINO_IAR1 0x010 +#define DINO_IRR1 0x014 /* RO */ +#define DINO_IMR 0x018 +#define DINO_IPR 0x01C +#define DINO_TOC_ADDR 0x020 +#define DINO_ICR 0x024 +#define DINO_ILR 0x028 /* RO */ +#define DINO_IO_COMMAND 0x030 /* WO */ +#define DINO_IO_STATUS 0x034 /* RO */ +#define DINO_IO_CONTROL 0x038 +#define DINO_IO_GSC_ERR_RESP 0x040 /* RO */ +#define DINO_IO_ERR_INFO 0x044 /* RO */ +#define DINO_IO_PCI_ERR_RESP 0x048 /* RO */ +#define DINO_IO_FBB_EN 0x05c +#define DINO_IO_ADDR_EN 0x060 +#define DINO_PCI_CONFIG_ADDR 0x064 +#define DINO_PCI_CONFIG_DATA 0x068 +#define DINO_PCI_IO_DATA 0x06c +#define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */ +#define DINO_GSC2X_CONFIG 0x7b4 /* RO */ +#define DINO_GMASK 0x800 +#define DINO_PAMR 0x804 +#define DINO_PAPR 0x808 +#define DINO_DAMODE 0x80c +#define DINO_PCICMD 0x810 +#define DINO_PCISTS 0x814 /* R/WC */ +#define DINO_MLTIM 0x81c +#define DINO_BRDG_FEAT 0x820 +#define DINO_PCIROR 0x824 +#define DINO_PCIWOR 0x828 +#define DINO_TLTIM 0x830 + +#define DINO_IRQS 11 /* bits 0-10 are architected */ +#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ +#define DINO_LOCAL_IRQS (DINO_IRQS+1) + +#define DINO_MASK_IRQ(x) (1<<(x)) + +#define PCIINTA 0x001 +#define PCIINTB 0x002 +#define PCIINTC 0x004 +#define PCIINTD 0x008 +#define PCIINTE 0x010 +#define PCIINTF 0x020 +#define GSCEXTINT 0x040 +/* #define xxx 0x080 - bit 7 is "default" */ +/* #define xxx 0x100 - bit 8 not used */ +/* #define xxx 0x200 - bit 9 not used */ +#define RS232INT 0x400 + +#define DINO_MEM_CHUNK_SIZE (8*1024*1024) // 8MB + +#define DINO_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE) + +typedef struct DinoState { + PCIHostState parent_obj; + + /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, + so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */ + + uint32_t iar0; + uint32_t iar1; + uint32_t imr; + uint32_t ipr; + uint32_t icr; + uint32_t ilr; + uint32_t io_addr_en; + uint32_t io_control; + + MemoryRegion this_mem; + MemoryRegion pci_mem; + MemoryRegion pci_mem_alias[32]; + + AddressSpace bm_as; + MemoryRegion bm; + MemoryRegion bm_ram_alias; + MemoryRegion bm_pci_alias; + + MemoryRegion cpu0_eir_mem; +} DinoState; + +/* + * Dino can forward memory accesses from the CPU in the range between + * 0xf0800000 and 0xff000000 to the PCI bus. + */ +static void gsc_to_pci_forwarding(DinoState *s) +{ + uint32_t io_addr_en, tmp; + int enabled, i; + + tmp = extract32(s->io_control, 7, 2); + enabled = (tmp == 0x01); + io_addr_en = s->io_addr_en; + + memory_region_transaction_begin(); + for (i = 1; i < 31; i++) { + MemoryRegion *mem = &s->pci_mem_alias[i]; + if (enabled && (io_addr_en & (1U << i))) { + if (!memory_region_is_mapped(mem)) { + uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; + memory_region_add_subregion(get_system_memory(), addr, mem); + } + } else if (memory_region_is_mapped(mem)) { + memory_region_del_subregion(get_system_memory(), mem); + } + } + memory_region_transaction_commit(); +} + +static bool dino_chip_mem_valid(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + switch (addr) { + case DINO_IAR0: + case DINO_IAR1: + case DINO_IRR0: + case DINO_IRR1: + case DINO_IMR: + case DINO_IPR: + case DINO_ICR: + case DINO_ILR: + case DINO_IO_CONTROL: + case DINO_IO_ADDR_EN: + case DINO_PCI_IO_DATA: + return true; + case DINO_PCI_IO_DATA+2: + return size <= 2; + case DINO_PCI_IO_DATA+1: + case DINO_PCI_IO_DATA+3: + return size == 1; + } + return false; +} + +static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + DinoState *s = opaque; + MemTxResult ret = MEMTX_OK; + AddressSpace *io; + uint16_t ioaddr; + uint32_t val; + + switch (addr) { + case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA+3: + /* Read from PCI IO space. */ + io = &address_space_io; + ioaddr = s->parent_obj.config_reg; + switch (size) { + case 1: + val = address_space_ldub(io, ioaddr, attrs, &ret); + break; + case 2: + val = address_space_lduw_be(io, ioaddr, attrs, &ret); + break; + case 4: + val = address_space_ldl_be(io, ioaddr, attrs, &ret); + break; + default: + g_assert_not_reached(); + } + break; + + case DINO_IO_ADDR_EN: + val = s->io_addr_en; + break; + case DINO_IO_CONTROL: + val = s->io_control; + break; + + case DINO_IAR0: + val = s->iar0; + break; + case DINO_IAR1: + val = s->iar1; + break; + case DINO_IMR: + val = s->imr; + break; + case DINO_ICR: + val = s->icr; + break; + case DINO_IPR: + val = s->ipr; + /* Any read to IPR clears the register. */ + s->ipr = 0; + break; + case DINO_ILR: + val = s->ilr; + break; + case DINO_IRR0: + val = s->ilr & s->imr & ~s->icr; + break; + case DINO_IRR1: + val = s->ilr & s->imr & s->icr; + break; + + default: + /* Controlled by dino_chip_mem_valid above. */ + g_assert_not_reached(); + } + + *data = val; + return ret; +} + +static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + DinoState *s = opaque; + AddressSpace *io; + MemTxResult ret; + uint16_t ioaddr; + + switch (addr) { + case DINO_IO_DATA ... DINO_PCI_IO_DATA+3: + /* Write into PCI IO space. */ + io = &address_space_io; + ioaddr = s->parent_obj.config_reg; + switch (size) { + case 1: + address_space_stb(io, ioaddr, val, attrs, &ret); + break; + case 2: + address_space_stw_be(io, ioaddr, val, attrs, &ret); + break; + case 4: + address_space_stl_be(io, ioaddr, val, attrs, &ret); + break; + default: + g_assert_not_reached(); + } + return ret; + + case DINO_IO_ADDR_EN: + /* Never allow first (=firmware) and last (=Dino) areas. */ + s->io_addr_en = val & 0x7ffffffe; + gsc_to_pci_forwarding(s); + break; + case DINO_IO_CONTROL: + s->io_control = val; + gsc_to_pci_forwarding(s); + break; + + case DINO_IAR0: + s->iar0 = val; + break; + case DINO_IAR1: + s->iar1 = val; + break; + case DINO_IMR: + s->imr = val; + break; + case DINO_ICR: + s->icr = val; + break; + case DINO_IPR: + /* Any write to IPR clears the register. */ + s->ipr = 0; + break; + + case DINO_ILR: + case DINO_IRR0: + case DINO_IRR1: + /* These registers are read-only. */ + break; + + default: + /* Controlled by dino_chip_mem_valid above. */ + g_assert_not_reached(); + } + return MEMTX_OK; +} + +static const MemoryRegionOps dino_chip_ops = { + .read_with_attrs = dino_chip_read_with_attrs, + .write_with_attrs = dino_chip_write_with_attrs, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + .accepts = dino_chip_mem_valid, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static const VMStateDescription vmstate_dino = { + .name = "Dino", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(iar0, DinoState), + VMSTATE_UINT32(iar1, DinoState), + VMSTATE_UINT32(imr, DinoState), + VMSTATE_UINT32(ipr, DinoState), + VMSTATE_UINT32(icr, DinoState), + VMSTATE_UINT32(ilr, DinoState), + VMSTATE_UINT32(io_addr_en, DinoState), + VMSTATE_UINT32(io_control, DinoState), + VMSTATE_END_OF_LIST() + } +}; + + +/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */ + +static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len) +{ + PCIHostState *s = opaque; + return pci_data_read(s->bus, s->config_reg | (addr & 3), len); +} + +static void dino_config_data_write(void *opaque, hwaddr addr, + uint64_t val, unsigned len) +{ + PCIHostState *s = opaque; + pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); +} + +static const MemoryRegionOps dino_config_data_ops = { + .read = dino_config_data_read, + .write = dino_config_data_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, + int devfn) +{ + DinoState *s = opaque; + + return &s->bm_as; +} + +/* + * Dino interrupts are connected as shown on Page 78, Table 23 + * (Little-endian bit numbers) + * 0 PCI INTA + * 1 PCI INTB + * 2 PCI INTC + * 3 PCI INTD + * 4 PCI INTE + * 5 PCI INTF + * 6 GSC External Interrupt + * 7 Bus Error for "less than fatal" mode + * 8 PS2 + * 9 Unused + * 10 RS232 + */ + +static void dino_set_irq(void *opaque, int irq, int level) +{ + DinoState *s = opaque; + uint32_t bit = 1u << irq; + uint32_t old_ilr = s->ilr; + + if (level) { + uint32_t ena = bit & ~old_ilr; + s->ipr |= ena; + s->ilr = old_ilr | bit; + if (ena & s->imr) { + uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0); + stl_be_phys(&address_space_memory, iar & -32, iar & 31); + } + } else { + s->ilr = old_ilr & ~bit; + } +} + +static int dino_pci_map_irq(PCIDevice *d, int irq_num) +{ + int slot = d->devfn >> 3; + int local_irq; + + assert(irq_num >= 0 && irq_num <= 3); + + local_irq = slot & 0x03; + + return local_irq; +} + +static void dino_set_timer_irq(void *opaque, int irq, int level) +{ + /* ??? Not connected. */ +} + +static void dino_set_serial_irq(void *opaque, int irq, int level) +{ + dino_set_irq(opaque, 10, level); +} + +PCIBus *dino_init(MemoryRegion *addr_space, + qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq) +{ + DeviceState *dev; + DinoState *s; + PCIBus *b; + int i; + + dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE); + s = DINO_PCI_HOST_BRIDGE(dev); + + /* Dino PCI access from main memory. */ + memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops, + s, "dino", 4096); + memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem); + + /* Dino PCI config. */ + memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj), + &pci_host_conf_be_ops, dev, "pci-conf-idx", 4); + memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj), + &dino_config_data_ops, dev, "pci-conf-data", 4); + memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, + &s->parent_obj.conf_mem); + memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA, + &s->parent_obj.data_mem); + + /* Dino PCI bus memory. */ + memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32); + + b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s, + &s->pci_mem, get_system_io(), + PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS); + s->parent_obj.bus = b; + qdev_init_nofail(dev); + + /* Set up windows into PCI bus memory. */ + for (i = 1; i < 31; i++) { + uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; + char *name = g_strdup_printf("PCI Outbound Window %d", i); + memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s), + name, &s->pci_mem, addr, + DINO_MEM_CHUNK_SIZE); + } + + /* Set up PCI view of memory: Bus master address space. */ + memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32); + memory_region_init_alias(&s->bm_ram_alias, OBJECT(s), + "bm-system", addr_space, 0, + 0xf0000000 + DINO_MEM_CHUNK_SIZE); + memory_region_init_alias(&s->bm_pci_alias, OBJECT(s), + "bm-pci", &s->pci_mem, + 0xf0000000 + DINO_MEM_CHUNK_SIZE, + 31 * DINO_MEM_CHUNK_SIZE); + memory_region_add_subregion(&s->bm, 0, + &s->bm_ram_alias); + memory_region_add_subregion(&s->bm, + 0xf0000000 + DINO_MEM_CHUNK_SIZE, + &s->bm_pci_alias); + address_space_init(&s->bm_as, &s->bm, "pci-bm"); + pci_setup_iommu(b, dino_pcihost_set_iommu, s); + + *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0); + *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0); + + return b; +} + +static int dino_pcihost_init(SysBusDevice *dev) +{ + return 0; +} + +static void dino_pcihost_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + k->init = dino_pcihost_init; + dc->vmsd = &vmstate_dino; +} + +static const TypeInfo dino_pcihost_info = { + .name = TYPE_DINO_PCI_HOST_BRIDGE, + .parent = TYPE_PCI_HOST_BRIDGE, + .instance_size = sizeof(DinoState), + .class_init = dino_pcihost_class_init, +}; + +static void dino_register_types(void) +{ + type_register_static(&dino_pcihost_info); +} + +type_init(dino_register_types) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 4625e591ea..9b6dc8607c 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -1,5 +1,5 @@ /* - * QEMU HPPA hardware system emulator. + * QEMU HP-PARISC (HPPA) hardware system emulator. * Copyright 2017 Helge Deller * */ @@ -17,20 +17,263 @@ #include "hw/ide.h" #include "hw/timer/i8254.h" #include "hw/char/serial.h" +#include "hw/hppa/hppa_sys.h" #include "qemu/cutils.h" #include "qapi/error.h" +#define MAX_IDE_BUS 2 + +static ISABus *hppa_isa_bus(void) +{ + ISABus *isa_bus; + qemu_irq *isa_irqs; + MemoryRegion *isa_region; + + isa_region = g_new(MemoryRegion, 1); + memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops, + NULL, "isa-io", 0x800); + memory_region_add_subregion(get_system_memory(), IDE_HPA, + isa_region); + + isa_bus = isa_bus_new(NULL, get_system_memory(), isa_region, + &error_abort); + isa_irqs = i8259_init(isa_bus, + /* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */ + NULL); + isa_bus_irqs(isa_bus, isa_irqs); + + return isa_bus; +} + +static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr) +{ + addr &= (0x10000000 - 1); + return addr; +} + +static HPPACPU *cpu[HPPA_MAX_CPUS]; +static uint64_t firmware_entry; static void machine_hppa_init(MachineState *machine) { + const char *kernel_filename = machine->kernel_filename; + const char *kernel_cmdline = machine->kernel_cmdline; + const char *initrd_filename = machine->initrd_filename; + PCIBus *pci_bus; + ISABus *isa_bus; + qemu_irq rtc_irq, serial_irq; + char *firmware_filename; + uint64_t firmware_low, firmware_high; + long size; + uint64_t kernel_entry = 0, kernel_low, kernel_high; + MemoryRegion *addr_space = get_system_memory(); + MemoryRegion *rom_region; + MemoryRegion *ram_region; + MemoryRegion *cpu_region; + long i; + + ram_size = machine->ram_size; + + /* Create CPUs. */ + for (i = 0; i < smp_cpus; i++) { + cpu[i] = HPPA_CPU(cpu_create(machine->cpu_type)); + + cpu_region = g_new(MemoryRegion, 1); + memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops, + cpu[i], g_strdup_printf("cpu%ld-io-eir",i), 4); + memory_region_add_subregion(addr_space, CPU_HPA + i*0x1000, cpu_region); + } + + /* Limit main memory. */ + if (ram_size > FIRMWARE_START) { + machine->ram_size = ram_size = FIRMWARE_START; + } + + /* Main memory region. */ + ram_region = g_new(MemoryRegion, 1); + memory_region_allocate_system_memory(ram_region, OBJECT(machine), + "ram", ram_size); + memory_region_add_subregion(addr_space, 0, ram_region); + + /* Init Dino (PCI host bus chip). */ + pci_bus = dino_init(addr_space, &rtc_irq, &serial_irq); + assert(pci_bus); + + /* Create ISA bus. */ + isa_bus = hppa_isa_bus(); + assert(isa_bus); + + /* Realtime clock, used by firmware for PDC_TOD call. */ + mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + /* Serial code setup. */ + if (serial_hds[0]) { + uint32_t addr = DINO_UART_HPA + 0x800; + serial_mm_init(addr_space, addr, 0, serial_irq, + 115200, serial_hds[0], DEVICE_BIG_ENDIAN); + fprintf(stderr, "Serial port created at 0x%x\n", addr); + } + + /* SCSI disk setup. */ + lsi53c895a_create(pci_bus); + + /* Network setup. e1000 is good enough, failing Tulip support. */ + for (i = 0; i < nb_nics; i++) { + pci_nic_init_nofail(&nd_table[i], pci_bus, "e1000", NULL); + } + + /* Load firmware. Given that this is not "real" firmware, + but one explicitly written for the emulation, we might as + well load it directly from an ELF image. */ + firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, + bios_name ? bios_name : + "hppa-firmware.img"); + if (firmware_filename == NULL) { + error_report("no firmware provided"); + exit(1); + } + + size = load_elf(firmware_filename, NULL, + NULL, &firmware_entry, &firmware_low, &firmware_high, + true, EM_PARISC, 0, 0); + + /* Unfortunately, load_elf sign-extends reading elf32. */ + firmware_entry = (target_ureg)firmware_entry; + firmware_low = (target_ureg)firmware_low; + firmware_high = (target_ureg)firmware_high; + + if (size < 0) { + error_report("could not load firmware '%s'", firmware_filename); + exit(1); + } + fprintf(stderr, "Firmware loaded at 0x%08lx-0x%08lx, entry at 0x%08lx.\n", + firmware_low, firmware_high, firmware_entry); + if (firmware_low < ram_size || firmware_high >= FIRMWARE_END) { + error_report("Firmware overlaps with memory or IO space"); + exit(1); + } + g_free(firmware_filename); + + rom_region = g_new(MemoryRegion, 1); + memory_region_allocate_system_memory(rom_region, OBJECT(machine), + "firmware", + (FIRMWARE_END - FIRMWARE_START)); + memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region); + + /* Load kernel */ + if (kernel_filename) { + fprintf(stderr, "LOADING kernel '%s'\n", kernel_filename); + size = load_elf(kernel_filename, &cpu_hppa_to_phys, + NULL, &kernel_entry, &kernel_low, &kernel_high, + true, EM_PARISC, 0, 0); + + /* Unfortunately, load_elf sign-extends reading elf32. */ + kernel_entry = (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry); + kernel_low = (target_ureg)kernel_low; + kernel_high = (target_ureg)kernel_high; + + if (size < 0) { + error_report("could not load kernel '%s'", kernel_filename); + exit(1); + } + + fprintf(stderr, "Kernel loaded at 0x%08lx-0x%08lx, entry at 0x%08lx, " + "size %ld kB.\n", + kernel_low, kernel_high, kernel_entry, size / 1024); + + if (kernel_cmdline) { + cpu[0]->env.gr[24] = 0x4000; + pstrcpy_targphys("cmdline", cpu[0]->env.gr[24], + TARGET_PAGE_SIZE, kernel_cmdline); + } + + if (initrd_filename) { + ram_addr_t initrd_base; + long initrd_size; + + initrd_size = get_image_size(initrd_filename); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + initrd_filename); + exit(1); + } + + /* Load the initrd image high in memory. + Mirror the algorithm used by palo: + (1) Due to sign-extension problems and PDC, + put the initrd no higher than 1G. + (2) Reserve 64k for stack. */ + initrd_base = MIN(ram_size, 1024 * 1024 * 1024); + initrd_base = initrd_base - 64 * 1024; + initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK; + + if (initrd_base < kernel_high) { + error_report("kernel and initial ram disk too large!"); + exit(1); + } + + load_image_targphys(initrd_filename, initrd_base, initrd_size); + cpu[0]->env.gr[23] = initrd_base; + cpu[0]->env.gr[22] = initrd_base + initrd_size; + } + } + + if (!kernel_entry) { + /* When booting via firmware, tell firmware if we want interactive + * mode (kernel_entry=1), and to boot from CD (gr[24]='d') + * or hard disc * (gr[24]='c'). + */ + kernel_entry = boot_menu ? 1 : 0; + cpu[0]->env.gr[24] = machine->boot_order[0]; + } + + /* We jump to the firmware entry routine and pass the + * various parameters in registers. After firmware initialization, + * firmware will start the Linux kernel with ramdisk and cmdline. + */ + cpu[0]->env.gr[26] = ram_size; + cpu[0]->env.gr[25] = kernel_entry; + + /* tell firmware how many SMP CPUs to present in inventory table */ + cpu[0]->env.gr[21] = smp_cpus; } +static void hppa_machine_reset(void) +{ + int i; + + qemu_devices_reset(); + + /* Start all CPUs at the firmware entry point. + * Monarch CPU will initialize firmware, secondary CPUs + * will enter a small idle look and wait for rendevouz. */ + for (i = 0; i < smp_cpus; i++) { + cpu_set_pc(CPU(cpu[i]), firmware_entry); + cpu[i]->env.gr[5] = CPU_HPA + i*0x1000; + } + + /* already initialized by machine_hppa_init()? */ + if (cpu[0]->env.gr[26] == ram_size) { + return; + } + + cpu[0]->env.gr[26] = ram_size; + cpu[0]->env.gr[25] = 0; /* no firmware boot menu */ + cpu[0]->env.gr[24] = 'c'; + /* gr22/gr23 unused, no initrd while reboot. */ + cpu[0]->env.gr[21] = smp_cpus; +} + + static void machine_hppa_machine_init(MachineClass *mc) { mc->desc = "HPPA generic machine"; + mc->default_cpu_type = TYPE_HPPA_CPU; mc->init = machine_hppa_init; + mc->reset = hppa_machine_reset; mc->block_default_type = IF_SCSI; - mc->max_cpus = 1; + mc->max_cpus = HPPA_MAX_CPUS; + mc->default_cpus = 1; mc->is_default = 1; mc->default_ram_size = 2048UL*1024*1024; // 2GB mc->default_boot_order = "cd"; diff --git a/hw/hppa/pci.c b/hw/hppa/pci.c new file mode 100644 index 0000000000..766420254e --- /dev/null +++ b/hw/hppa/pci.c @@ -0,0 +1,90 @@ +/* + * QEMU HP-PARISC PCI support functions. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hppa_sys.h" +#include "qemu/log.h" +#include "sysemu/sysemu.h" +#include "trace.h" + + +/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ + +static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0; +} + +static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) +{ +} + +const MemoryRegionOps hppa_pci_ignore_ops = { + .read = ignore_read, + .write = ignore_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 8, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 8, + }, +}; + + +/* PCI config space reads/writes, to byte-word addressable memory. */ +static uint64_t bw_conf1_read(void *opaque, hwaddr addr, + unsigned size) +{ + PCIBus *b = opaque; + return pci_data_read(b, addr, size); +} + +static void bw_conf1_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PCIBus *b = opaque; + pci_data_write(b, addr, val, size); +} + +const MemoryRegionOps hppa_pci_conf1_ops = { + .read = bw_conf1_read, + .write = bw_conf1_write, + .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +/* PCI/EISA Interrupt Acknowledge Cycle. */ + +static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) +{ + return pic_read_irq(isa_pic); +} + +static void special_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + trace_hppa_pci_iack_write(); +} + +const MemoryRegionOps hppa_pci_iack_ops = { + .read = iack_read, + .write = special_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; diff --git a/default-configs/hppa-softmmu.mak b/default-configs/hppa-softmmu.mak new file mode 100644 index 0000000000..013e5f046f --- /dev/null +++ b/default-configs/hppa-softmmu.mak @@ -0,0 +1,14 @@ +include pci.mak +include usb.mak +CONFIG_SERIAL=y +CONFIG_SERIAL_ISA=y +CONFIG_ISA_BUS=y +CONFIG_I8259=y +CONFIG_VIRTIO_PCI=$(CONFIG_PCI) +CONFIG_VIRTIO=y +CONFIG_E1000_PCI=y +CONFIG_IDE_ISA=y +CONFIG_IDE_CMD646=y +# CONFIG_IDE_MMIO=y +CONFIG_VIRTIO_VGA=y +CONFIG_MC146818RTC=y diff --git a/hw/hppa/Makefile.objs b/hw/hppa/Makefile.objs index 46b2ae18de..bef241ed25 100644 --- a/hw/hppa/Makefile.objs +++ b/hw/hppa/Makefile.objs @@ -1 +1 @@ -obj-y += machine.o +obj-y += machine.o pci.o dino.o diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events new file mode 100644 index 0000000000..14c67937e1 --- /dev/null +++ b/hw/hppa/trace-events @@ -0,0 +1,4 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/hppa/pci.c +hppa_pci_iack_write(void) "" From patchwork Mon Jan 22 03:42:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125334 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp954744ljf; Sun, 21 Jan 2018 20:23:08 -0800 (PST) X-Google-Smtp-Source: AH8x2243LE4AN8kgEfxGYI7g6gjYYq3HLNGJkqZVoqWGpWqgVJulUfywSqcvrgZiOF4ENvAAn4Ml X-Received: by 10.129.115.86 with SMTP id o83mr6202793ywc.0.1516594988286; Sun, 21 Jan 2018 20:23:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594988; cv=none; d=google.com; s=arc-20160816; b=hqM1isjquMaOeH5Yiq96vf7n6lNhp7ChoMCQuBxiNsYbIU88LzHB8mwLRQ7YCwi3QX uFOCyVLrBJFalbTVMGinv6ZtfbeJgKc2HyAGuKJLJbyVEH/Hfe4h1gB7EDmsS8sqw/kV KhK87SkDRABZqTP3GMqADTli8F+5UtPPACKXTHz4nNAh9R4qCm+Su/L2deky/5tKz3dR ZvLseh1toCmkUbelb6xFKmrdFjEzSoC1doh3ufhKyOIfe7s7mn6OJ3qzv4xRhtzx45tN Gy6JmMMwK1M5VFURxsfHpgFxvARBh3/9FsNpyfspEQni0loj96ZziPb7RbitcMTR5dge NJgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=3qlGn/Cev9ZRnJ42AuM8l715MDL3FQWxgHiylJ1qML4=; b=H8bjQT1VpKr3pIEd865zOH/46J4FSSevKml8P6qKW3yqj5arZjFx0Kh55psD0A6uI4 9m8gjkYwvvxkiLbw5bGLplX/ZT09jSioLqZ93Q5zBL4UsHgwYCc6dfBKFXi01+OEhJbk MG/7ng2drLzhogAxWKROmOTL8CqVtAJfpI0n4DDZsKJAyB2swa4Y1XCjF2hn/ztNqAax ljtjKeOmq8sd36KrX8uisg31uLbKK9SKhE+XA2uT/RmjYmZOmcINe2/WIsQPHIIu0ctx ZNBqTxnbYbquugVpzL9tOArEh9YHunva+DXo9i4dBxx4FWOe+eT3qWpiMrfOSmXj+kRA Sj8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CFvlNq+v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:16 -0800 Message-Id: <20180122034217.19593-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL 42/43] pc-bios: Add hppa-firmware.img and git submodule X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- Makefile | 3 ++- .gitmodules | 3 +++ pc-bios/hppa-firmware.img | Bin 0 -> 461352 bytes roms/seabios-hppa | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) create mode 100755 pc-bios/hppa-firmware.img create mode 160000 roms/seabios-hppa -- 2.14.3 diff --git a/Makefile b/Makefile index d835bb92e7..5ffb7ed57f 100644 --- a/Makefile +++ b/Makefile @@ -649,7 +649,8 @@ s390-ccw.img s390-netboot.img \ spapr-rtas.bin slof.bin skiboot.lid \ palcode-clipper \ u-boot.e500 \ -qemu_vga.ndrv +qemu_vga.ndrv \ +hppa-firmware.img else BLOBS= endif diff --git a/.gitmodules b/.gitmodules index 1500579638..7a8282df46 100644 --- a/.gitmodules +++ b/.gitmodules @@ -40,3 +40,6 @@ [submodule "capstone"] path = capstone url = git://git.qemu.org/capstone.git +[submodule "roms/seabios-hppa"] + path = roms/seabios-hppa + url = git://github.com/hdeller/seabios-hppa.git diff --git a/pc-bios/hppa-firmware.img b/pc-bios/hppa-firmware.img new file mode 100755 index 0000000000000000000000000000000000000000..ae833437a73cb0955491b95f03cd42132d8d2e9c GIT binary patch literal 461352 zcmeFae|VJTo$vq5R zPuLD5K=>tKpanP7w3l>o&$_2QN>_XETdbm}wG9M_bhV{FwA1?SwRl>u#{GhPU+;Tn zFk0Q+v)})|*U5F|x}Uk9`{(EW+@Ig~{d{fKjk8^DSB{nab6bTxy3SixH)+%=$m_Q( zx0k1g<+5t6N-L!I{3j`6>ECkwgU@ou#`9Fbf1LmS@Lwt%{&UK*{@1+e*W5a1e&b&? z&6_tpGH+&MWcHn3x%;n|eq}|ZcK(W`Gv?epKXUs$U+EZctz5Ha)#|B#^;dV?xn|{k zw|#cmJ$L`r%H=EWx@*N({%ZA#rMKOA&+2Pdu3EL!id}QvHpIA4cZesm4 z%kH}8zU8;w_m$OaKD*|x?_9q8t`(pC@`^QPq``<~E#iM4|F7{sh5!5ce~SO%h}-ff zBDIB=qE$@#%1F|-+;Kb4y*Lu_yP{R@qpoLz@u(|y$@R-%+;WY&lR3TXnd_cwd4dVo zxnR5|?swI-IQ>mIRwR`;YEgeiWr&9{70ix2tg`Jcjn9siU0pTvKZGIubRW$t*keJk^q9;552RK)Zf z&*o>-|MOmJ_F?v{>Y zu`P8Qt>Ycf$96}OwAmfL)bU(we_faLT3u_zOODT zpW#2ke<}a=d8^<8|L6Jt4KN)&SRd>hSR1?m94^|q?v{bIWt}{~nR!4YEHm-ODa5W;myy-)@$5_O@Y3`d4b-p-u{T-P`JO?QeIu3QFRg{iK*@uN*uN-WaPhY0hN2~w{C;?N)6v*zweR0sY*FuV^{sWd=Q%5B=3nk^jFwvQx<2~vazfj>`pY$! zldHqSTi3)FDIff5Rhex5rbHwtSZ!U?KBW2TS^eJp9C*ok7bc6{(U5D{yWbsBUqg?C z&6*FkRGinEv)(f!iJg~*T0C}it##bn>TXH32j7h@vjzqpu6SSV*$+77>9r`^n_UaH zWgqcA?39}n`0h-$zp1&=x7J{>;M@FgK~V4C{%z%Xy|XLbEpMmFLYZ=w_ka`n^c@JG zlx?cBd0l?WjK9RXiv085UPFUs z2nIW6#9r0AOr3M8vpE?%K%H}XuireMH}$LXhwW+3v&eo)WIuz)ue4OfS)10z1=fT! zYrH|yYtQU)0?r!ug2wq)^vr6H?ev=G$)xjn|CuvSdTi3qI#0S6Y>q?@IlWFP^uXTQ z+yD24)qxW5Ef-ub*|4U6tN&{O)-3j0;h=w=dH$)MC*Mc;y~()QAGZZU-d-o<^z~>j zSXu||g{^CTcv$5$58(6%l@)H){oG~2lg4)(ja9*y%HT^y(K2U3s=ag}ys4=9^;pqR zG8CrYcbk9IV0aQV%cXXpXRT^~u&?5q?D5cG8ISE>8Yty=oBtl>bA)tRy3I3t zyg{eWy}-YMx_1OhhWdbMpSxAgyVy&KK^ zs=ePa_+Cu8R?5$$Y-6gua!0nF>QJ{$zrFprmEL4t$n5V=n8E>G*2 z=i6AE?|sspKk#~R*wKc)X_KwUN6_PZ{Ub|XAK-N@7x1N$lp}#r;mfY&!zu4 z^f@=xUU8r5W&8BZ&dv8+nV09?=q~Yo$6e}MU7UZikG49CZ8M%pc>^c=XtT4}iB8rt z?RFOXPIj6y*2zxZtts}C=RVnK-sNt1B3a9tySF|ODfS-^>~)?ruz}WE)`mNHHyXZj zhk=vh^km+RhDaT8w+igq|g7oUb+8oC%=>gw@LEA}U*SwBfkbCJ3}&p5{M`~MRCHf_NV2Ip4{ z4^FK(&z^}7mXY2TNz`nxthaw#{9V!H!6V@=c+C5(aV`6_WT@V*;@$mvS9hfFeey=L zKhF!Vg-`GyXRy9vc=M7-tzGJ#PoI&l)<}SSAO8X64Nj}L04#C`>na{Owb+h*{b8$N za7x7wou}Pp(6@!X$q7Ee>g%0WgR3(bciwf%&ip7~xgH3{hh_wmO7XoHO*| z)62vka(0O?3g(TiR`PP*ey2=%%cfdMvlk_I!F$Dn2OEKDd-&kM0~Nyq50s~(`_p_p z&2z)|WqGcthpaj{t714>UXWxDZ=wEf>gEkzQ8A3HsQt+VITH$gi4%#wnQ~Gyawv<~!CCU``|C!GdS9 z@c4^%*&mw2NO>mJUeK0q*M2qnfHeRvELMBW{h(wd&0TOcyoarc0Ka1y1Y+cZFB` z8(V9O#XB44*9Nlui@ee-|7x6FJI1@o=vS>neRj8Zlau3nAW-hRKh5JryS)#)TVA{n ze<81Ej5yJ@_2uQRgq57-y8Mj6>0I-RS!-YeW?W*@F~${3gS--_)16AsqoLeI;r zr06_!hr(k4nldya^jp=9Bnqn}qktdhph3SsK1L>X~tdL!+{I3SJE(n@76l8=2kxjaI9nrU`Ss_+^XhwxJCH^j~+V zw{HTnLYjYRZW+DA;2OG2t&uB`Cq&2KZR1pSWoN#bo7q3$o9boP=9Q_D`_%?(--zyW zXmc_$A)4z{181B1AK+WK;FuY!;YF22(Pgnq+Y>Qk8@N253{Jk%5;1y5W^DaN51!_P zyph~8?=*Kve0Am2{QfKr0QM2uIExOl(eU96Ef>t8(TAZWjm*vL!SwoscNo1`{V|`- zGpgs+Y#Ha;JTsHd&ZJG5bZ#cSF_V5ilg`Vew`S4>ne+>pbWtW8+&hNG6SE(nXncWhPB#(tVlqP$oT^NngvPsdSoSWzxuqzTzXE7mavcHR5^Ki0A$h z&jTZ#zx%;+-fJVCkB)dgG~#*Ri0Au9Jg*$_JYsBl!4L9t&yRQ>F^1d`W60e#qD*qc zb7I8vyb;e6Mmz^Tc+MGy7L_2MP5@sbn{JOpNZo~V(c^a|9qbi;Wc5nmnwHbc3VLKS zOtpLSqUGaqkpcT8ziR)b!p;Z(cRM%`W8lM(H^ z#o}eqqsw+sUm{SRmSdbz(ARw5y6kVyAEMo{OTMp(-+NA*GU4z&9qe7vFVU32+%(-A ztWiIn9rSaEbRlx?-}C(UcBhrLy+Rx9K6i`irNW-;vvg2xWoZ-qpEhjhSV5AyNq9bd z#D0@G!w>Ao$=_fj)9M|+4-YF8^04D#13>=<)B+TfLWKuo{>MR?6F3!7%v$f_&3_2 z>K62|YiV0LcAJp{pGQ}GE;iom8|1*|R+nAZ8@sgW%a1&cE-l;VL6rw5j7DJ>Twh z7WjLMu~k~`ZF^(S)YV(LiG($eIo={#n}vhMC|av_)uwEM-WKO!{SUR+-8EMvi|gvI zvC!)d0k^a0Qph)B>qpY_k@ae-Evv5HUq$(*56X`@n=LQ>WM@3GC|Z^4j$dz`i%+wD zHS`QNA>?4$e)#}If-d@2k#$fjBN(RIeFwn7+*Es^i~N?&-4WRk z(!BB`dnwiKe;QdK7y0^McXr4AN#)cQZHyLw)jS85Rh%C{Khs?8E1lNDUi64>Ij+Jk z*?g^1>;SSeU(d6CTe9JKuN!HbvPxz1^X@_S4Tq1>*RbZ0;lGEZS48ujYNK0#@62g; zM%LR8zfVMSXftT#vJM~iw}i)@P5WC$O+<%ju~#@H&;z%>v)JnCioN<5<%J{Y1;FSp zZ0v<)R%yo0e$2n7*vMturuNTcZ_KA1@%|lJd+hC_v2$JWf4|rQ|9|0MV~sKIp@DU+ z*zB>>*F|HOva%gE=GVYMW3xx^ShkYiD(_vC8?4)JO;9MQ-#;K5nn0`e@EwD((bBur4)2jmEALzO zdaTN~GSGKJpEWH*D=yoUq%$@zwrVMNrRo5a!!tXrh~}YjX}@dSO{-n@hWnEd*183I zFLHM1Skqcpu&L9P<{2aQ^gYLsw}b8`?1mo7-+<0sL>sfgnKJNxeDiY+`@x&4uBrVK zpl!3F4`90)>t6i!TcdvLoXgGge#go8{+&}0Mfb5cJ7xAJryN=uw;y%DD|BAkMemhP zEZylc-MjfX`me3ARqT*V$y_$7{^d2v*f|-K(b*Zp#KD>9ZOof-)srtf$-Ux5m-TqT zq&++*tH%$lt$4o~Rl;6~ILq8QtXD$& zP;`JdnAKuq%1rGxQkR@nUCuo}O!xg_o*{N16N8{3*<5OqLhW&z5G% z1X^EoL_I4Hd&5mxUMO3*Z1S=vWbE?uq5T2b#iQZav!boh%3!_&f6ds&Tan|R?RunY zLt`(t>($sJ_E>Radzb&B*P1Dte&g4z*~X8t$C}`L)%^v%=iRj`Z~Pp+mwg`dsXrM% z2)6&&&68ip2EU0hZAjbC@rzxyvln)MU_VzIvwN-D4eKJeHPe6dUR+MSR-7$r`=2aM zvX(vYxIG>FttRDlPzL_iQ+Qo*l06`O?LPGdY>Z50_Wg^oJEH~G0&xCb@O^Eh|ELu` zX#FF&hOHs#2G6z_J8icsp*2MgnH{akmCk5suVb5TXJ+t_c zmIKFp3mIr1^d5g@f%xuX?6B~Mf|c^`X#FX_9v$F+({E_4m%h(_F+9QB?auWrx8`dM zvYQX}jta_Nl*KQDuP?f+!B3&XmRUaFRyJafRsmNJa0O1|-W<%qcAfmi*Px*@#COv2 zg|Ufwm}?Pp)jp{*ZNC_EvA^Wc6s%WjzopvqeizLHPWi6)S%=2%MC`BCPVzhLZM4O{ z%zI4bx;DpVsa~eede&1ut^=y0@ea0DTojLItj2fB8t;}bP;`^NLbOvRThEK3_y%AR zIQ2h+fdS^etvj*``!06g%A2%a(rpEcZ5xwK1FI`8Mmw#5c;rKg3Br>``rNB}r1vR5 znv?eZnmzduSwZ89hVm^lF2ZbwpmSSi$-k z+Kb%1C_9$HAbHSV)(u-&S6yf6OU$oJxP#~(NvMCR|&cv9g!W4qb&0Dg#!?*Z8_m}(E~A8HT9h8jI8+o!Vp zZcl{+caF5*WNaa=P1ofgGBh}CgWV!ui{$vB{Z0U$UaI=SH*W|y7}}b*UbGcIDZ0s+ z>F6ToyNN_p8R4MHr_1?_9p&=x42|wEYoCeZ$k6@fh4AmElIMhzjjgWgv<=u5`M?J3 zxniZ3NHh=G z!`>W;-Jtf-K~4M!cz30KYyO|UErQ?0y(_E#A)6Zc3mJNj^jzr1CGh#-RQqTnyODPl zdkme>_cWh;lw+4HikwtL^vyP=u(GQE5Ix4z#Pyg|PIDC|@1qqfkNFI~?%t$Kok zsrOdMR=vR^p)fGGh<~Y)G2cD-OxWmq;6lSa&_4Ex{9rRh6FQ(@mucRTiqTrXfwZ5} z*fa;yK1%mMA3n(C#re>Zi`d?C2Yc~Tu9hz|Vj&~Scj@Q1gKRh~xCkEn_A$@#AHc(f z9lylHqmUP5%(FFa;JZ8eqHL+oVt7-F@j)0Lu(OnM<>Zey`OFjje81`q&GOi)YyZsM zf=)N%?cX|`>A4&KX<$(P+I7Wa7+3M&5#v8)AAB%e4ZrJnvEd!~y%n{s(vBAz-b0R+oah{by;HYe(_-U4TrM)R$?z~EkBCE0VWXkNz& z`1b&IhvTtZ&<_>^t2;-XOOJVTi5fv&3}wUhpo;kQeQC)tJWS&Z%R=zk~A@1BP| zO$=3F^vNUP;mL<%-#U4?V)&u{UB&F@7JRblxSws(udHfkwbM(yN-MUIZ_&mM#qZc& z_dK58P&?apKo?5gv-}$ZA^h*dT{|KhCT~Qx->UlVA9%MmshthpE&82XylqST9DeNI zckQ`i7wP$Jd#ZkguJPWfL}(m5aVKRCowyJR`?~|7uB}y1(N?Z^>prz{EB&>0^;V}y zUr6hJ?!Vu*so@%}d1^^uh434>`VGx9-CxeNU0c>$>W@0-w)Ivy>dW`-K#BT;$M$dS ztm;?4(2iW-X!yfmeR+!Z+9anyL)N606h3bD&WJL+uY`90E$>@-f4AO``V~HG{1@b3 zB=3#%ctX!;JY9RLdo*9~9s`#jrNW_SG;YT84r8fg44ct0d%Djhq`S6wtX$hZmsgNl z;y1MUGCsGLnZBq$O6`t-T_1SeBpe*v9162Wz{G#O8F!g=o@b+-h})ncFieGXiGcU~H#> z+rANS*hk*ugJbbeeE{1&%Isv`3!+8Dr1g2%z(1A~m$dM~{@5=jPh`B;xBbBm z0Gn{-VY>)fg1y$vUTbC_H?xPE*}u)~-DdV|Gy9cTlR3ni+=4#682w-=wBb%@!@bak zwMJ$>nbser9}r7i)$tlJLT6(WiRY@Xdo5Nk-ooBq9G&Wh4v*cz``zM)X}XfO@6}vA z&ZYWw^-ij04t|67@WQ&5d|UbYt@6CXc9uT{_*6>A5DgX$qHW2AXH|~(>{+0=8@bxs$|A@RTUY%OvJuSZ9)Mw3G*=fy-_gae*tF1+aeSwmA zpS4JIi2Mn@{y;117iNrYiB4;Z<|?_C{oJ5| z*uh$4>wiL;q0CKHhn9u>EDcLO8ZxvCKbGP&rjh!KY>rY5~~6R&Bi|WGQ6j%;2gg{ z4{Rm^k2%0&F7T;`k4#5ix`DYj0h>ASlv}*z`T5R!1$n>*p9C;^4t|t_JoPH@{4sp( zzLlcM|D*en$hDN&lBG|yy&GP(A06mbt)+n>V`1+Uv3JVYJ5}tR@$8+6%&VR`O=s`S zVej0+-jQ6s)a;#~#$3Kgpx0L$*yEcJ=<`hp9B>ZgS2~>qq2vW@fK}E6`+~8%mU}9D zG!_T^epPy1@{h?{dzrJa=Z}#^r@QQ`Ev3nM_Fc{><#|p!r{{j(ifnzp%F;V$Q?BEz z$n&71-vA$LQaR77&a3t)_sw%U3trpSwPcd^!KnT~->5@@16>=xIagcZTXI8T7idn(mT^_gubZ#l#PF3 zZFjTw^x>18de-sR`{f@?>%Jdz9-!%Ym))I=JtLT)=iVY609s)DIGKI50i6urh8<`B z8r_$E7dM@81(;Jy)^3ImWs>^Y)gQ5Zk76(Caun+$|4yEd`0wl(!C}dZTfp5}(48q7 zuVnx9nBD8a^Tt>D`s3-o-P@sG#;#shkBx@1;2ZpH^a0t*3pYaRx{LQ==Li&TD(*?k zhWSsK{nKSdnyxE2#2z|?{#oq5H?YUvbHDJerDMG{p>B^=OTOKKJq(+A4`<7g*}g9K zBmIqjl6&G0%v}>Z+w**iftoK__N6MQ{ zTNCDD$J_ek4?m?m@O3)){-!?>=oKt9M&|v+rfCJ=rQfr?)+*VM6=S~$xnMD{$%U^O zyS~;&b)+lt{s!oNE&JY+k-dww&cIQ&=Bm_^@I~60DS9sa$iVSWW?xgMu0DSkd-nrd zQMe@UW^6^#psO~u#F`|!j?cyBH}u_F2%T7*xZUMfOlksMQ{z@#D$kB$Qb|orDrrzL zsiftKNhJ+QZzGLJXCtka&PIAg&DI82b6Yen#ud!cbY`ZolXfnavc0|Ok#!g*~A^zRf#WIlYP5ni}nV652a(zk>?ip z_GDto``oR*uM?xb$K8sq{&L~Aj4gZ12wV1!v@N@EXJCxt#tYXI5B_!RWLql5+b`;z6!*`}>9mUAuC%)f8Q0#p%;VR*4tx;p{;;bUid7 z+4KF#%Z+!nkNM^$^E+hX)bp_2_X(GUE9n@XyjyCf|L{`HjM)DJUBF+HH*s)( z#js>V{LeYaiAUuF6-~w-u*m6ZQUhXXGe0<^0r=plN6426zr-$jc?~>2%vxLsxII+|13`VeB`UpXT=Q zGAMl!yRf&er2yL~u}+jzUGnZG?ZERV?eWXkGZWbDYzk(U|!3uf%~Mjp(Zd%$Kq z^YT1yxAF##q~|g4L}m_mWaeOYJR)97jJp*bi;vMQeDUN7R?um4-e6{DzTs)e@V4PG z(};uo$QcB|SNNgvVJDJ(|JIHZ4O`GnXLbxU?2ZPo75%hfKf3Xvj-NDq3)|7Wj#nEV z!*+CI$IA`R!h7aoLwl)eJT|299t%6#iD+%!xsD$d@V6|BJ&WJ#*<|PVa(`2x)IXPV zI?&jx&(MEk`n(V^&7CCBYuZ96TkiF zQ@{1tYQwwP~o&^&Y-i# z>Gj`L>_4%GxvVL+PwZhXYl@u{dzj0bV&921Cf_=-hWw7=eDd5U)|hv>@imNdwKa9* zIuF(3M_6r5lWp+i8OF#OoH+xGC%G4&{4@PehEHnTL+Q1ojfQ{vP64std3hTDg9%Rk z9u3Sqv9DZy$SJ8M`J>JL3bJ>~tVC)_j@k1AubKB#*>9&uykE|HW1srCv1wdcn5kdW z-))g8C-#+{H};z)ImXsC@EX61Wb4YwQ``UHww70aS8XxQrqmMm4%IbnjZ#}~V}HZG zwg_7)ze9%q82Tf-n&qxl`JL9fo3xgKU&kQ);8bjjSx?}IJh>YkdcS-(r)J>u2iA7G zdxl`Ebr!s})`BWlLtm_9xm6Ov<0eM$^)LG!hY617G88B6M>`piDkG&iu9(&eSt|VZVEE;cU)7P9r6L z13t0EevjA^{1mjc-^d6po*ry_zmu*GEejD7kc+%Hmoy(-xozi$s+9NyYZn@tX4cG{ z&7{p%)-2mkD{EG!{<{1`yhayeFv+dumS_NPCaISdR@bi(n*tl^^rHh&TkLo#< z;nR9Yz4IUYeq6-~y$6TPyv_K4gXXVsF`k?(47@e?{vVC>*uQpicA@H{6IXBlc0}ta zpPI$*i26t^8M9Pl&gx$pH@xu!-BB{5#?)PLeh3^K=q3)U&plJWX-D>gy=v!^#&qhe z#|D?nIe)Vl+%{)Q8E3xyo!+b5v*95@aJr1x8k>Flj{TM++MX^)zHBP0uh^T^lF<`Y z??dmwk<9yGYDwukde6Mi5A4Igd?<21b6d3i+YL9FG18vu^3M2qGxZ{>^B40TS8>+B zI#Wk};SZH(&VN~_r8 z46XwR-;YgIwq#p%!GQyeb+N`T-??OP&SlSSoNwKQZC&lkXHyIRNsqD2x=`R@6Y zX^5}2ZqLw%#gtpAHPjv^|4XW)z5Di?<9c{^6)~z$;WM3;rU9U5(AJLSGrViqpgx5(e|&VX}ivK zXV0LaL(Eq@(k0@(w2N<6ZK)mQ6&}$!FK}*zpVPFNIb+70s z@e{+w_>phC`=Ax~r{yHo;rAjle&RG#H+yEye#!}|K6=U=?Y(Ti>ad=A^w5ALwSwg?6vG1#udM(Ik0XM1Q)f-v*BxkP2;r7^Vjoa z!2ulJKiG#KiI^DSGrs+e2A9H>$JD-XFdDSc_dJqmEPS(7(IVIT_-Dr>!(WU4cOo); z2%GtI`2C!y54rwj^k|2&FJVvjkRFfSS$Djy2tRfUcBFfw1;iv3xNl;QtOqYmY<$N_ zY;ixqPX7u%-xu&LwUup@?^-$t^Dw$Ia>?kr7SC(ggNvkB;A>cE(klxR@ZP?z9q~Z( zv$3L{E8>fkKk0G&6pBSKGEM0p&fEn5#xK6>=ql0cxm&&$+Y$Y(+frHNi^cd&5^3Ga zxrIBqR0jX}WN7->r{Vi8FTLLXl=y$f#@mGL;2mtN^Hipp@#9OY!k0E4U)n@`Y4!L6 zrsEHogFoOF>|OZT@t*+;^r(BGb!*`Z>%qUvXCdl-UT5rG$XqR{wy_&0y#oFvu*pAH ztXK?t)a%3*Zo}@{fvvmA+WTOCBtB_8{=}PVlTYH47YsZ{7A1X;V@oEEpYhwweXjq} zKxowI;(Y_pRY=}5XHrMK0Iyl%`6X@Uu6W&w4E7mWFkooa63_R@yJG3<)@RWd&aXIa z)ykiW&X6+i+r}PSdfNI7?>17> zXN>=lwf7Px^6885I=b6^~^y8D;f1K%;RXy(jb6>ac-R@I&3 zT#9q3dW`>T%sG&Rb362zj zBW2)76*w{;9GM7?)Pp0_!I3%O$SvT=VsKssop)3fhfASfFHwuoWhFfl8v zY1h8$2x-QSk+Zh0#am0ceAQ#D*h;+XGwnoEZN+~u&p{J^Igc_?-cMJa?Cj_Uhc!Ry z=WNKSlJAwg;0e8dr4Js2y^OegWT9M-@-{ybnLF5pEPT7e{WulF$<@h#Y=icov27Nc zz1Qx(MRp(B45{4K&iL=uF7RyOcTTF^U4;E`SZy0zZ+E>T`r!LD^OJqfjM4L+86z~0 z@xGged&RrL4?U;h=UNZ^&f~K_Px zgFpJzRPnTvd(hXg(@Lk4KJ4A=UKqU)yW~8I9={yDz1ux=^Mjktd9QGCt8e=(=cjWL z{?176?-RQ3>DFoIty>1pTMGj`2h*vZ^?%C+-J4ZqaYxh^>-Z!)e2KfWUW@icT-$n} z8_-{0l5@M3YoFw+RGTMlFMF7^Yx5if2D5mV0H!nfeGnK57K*Pmv2&@mf{W%I{&KaM zYO}NP6bn`6l;(Csaw@uFpSxA_l%3g2{Nl+@;)wsq9LeAG<&CwRzt5}Qz})ua1^vB| zJ-<(CZu3|2zaTxA`SB0W?bd%NoJO2r+qkZ*)@1pxGb7qS&d6W-~d_SW8 zIy1g-=qBOYCzP3#E>kW#`|)L#xE{}x8U2Z6+U$4JWy)Sv8M80K6>XA>wEwelt7&~E za{iO`nXvJV2+q(BXgj|dac(bqWRoz{D}+eK%Q z(lNOj$H+Rgc@_OWqcIp55wD%8ueg_y`rc*zjdb45;-^jU4xe3VoD@?f%=P9_Cqvy!Rr_4K}7bA0J z=PNm&y<(0jo9;vL4&YMpn`&2exA$}J4L)$uth$y_5n@Jn9z9Ka9C}@=u{WT{sUPaI)??o@>-6#MbM_5=Cf$C7_NqV9zKNyJw13sdw4b1U z{lC%vN@8C|_J4VwWpHi^?@j-i-_wY??-a_UbNGhp~}xO^7)+M_*gWU#aNq<+@$wB9wp*6=;v9Y;QY^@g(zPt)E4 z)`b09@k?`;9XfS}zPSvI7;)}S^y!8v))i{!2KW_isGni!fY63&>uS*fbi3oC zQN77JJr~dHwIbVkV}FM~u@;`xhn%atE6Dqr$y*iZo!MvAvaWqWam`d=*NI{%Zs6- ztK@T&yqvr}BA;xlo4XyGdhI5s)7<}fFdEEHisotF#7qG@@4~tk|Gf0sH2VLT7%T%j z&KVD0h3w0F-EB4WU&_if4ruFs=x!r0zlHhv#XD1NrRE+h&Lfpus4#$orFF+9UM zec^*KcqXKlI5+)A#=x3M-WQzC5@Q6<8)s;q@WzbsC1@yqXXt+;^0){4hxE)c#$3f% z$2YfH^BQLn|CtPIQrxR_nOFK|lp~LX;Pc<)EF5WUDK=+|bb9odGknH#{q zfWIzO-Bl>`r+6|BQ%gSYKvqto!~Z!+)N#~lQRfoFfMen*43 z7C0rFfzcn8hkR2cU6Zy0&5Q&5s%p;aR*VPQGZ8$i2hXODq}$MoU?%p(j9D~*Jw1_e z%hyn^F*i5j6Pk&v+E(~Gb4LHk0Cyd_-rvxfoF`cY*`rM~*83>&v|R||f?!q6k3Uo3k*X5dAfei8Qo5VspT&HD=W*ZAH((@xOf+{eHm z(@%o6yasx(;PP5xugbt+DQk*;kt_Olr|4gr4~{wk+*V2EvL)b}#5D`VVl?kTvE zchh;6Uq)x4i&&$H$lUdUIpuFrdB%Pd*+)D8=aB|Fi3Q8-mw)Gc1ocPH`MC2DjAenrwdZ4Ni7gw}T!G7a!8Fz8 zotS|~eKeG70l%eDq)*b(j3bxzY}R;4=X56`t4IxOZ|Kdrfc@)y%_f~GF8yzu`JHNH z8}8O-j%gbu{V~V&S-ijFXzbphSlNF;Udv;@-^=_CXX%0A-RO6mfvBu&DV%cY;_nA| z|7Xqp(+Lde)2s=K%|p)W0Y4hydy(cZS`(TV5zmZ{!S7nN!83lg%DuF4zvLeH#5YXa zErsXdN&App^nRhrX$=hR&&1%F`$wkQQ`FDS_DD+cP&IQtOKe-{UG%}Gre*dNrNIE^LHI*>E{zyaGmul#S_TqmA%IW-eluv!f2x0UV9}gEFa~1J#=Wa?bRBtQZ+dJM(p8BA z)Ho{+@_ZiJY3^O==q;!PjwiBk6wUp2a0s7n;9232#dWUC`$Mvb`T&oT-0!v${8`*_ zlK80;#7_+nKlRgw_uz*v_@D>-dJ+7y4BlAn5o-_r2)O$Ey>TtE=~OyR>em&lcAqd?=3@zHYe=fisKi&Nl2$pX&`w zT=uhu-HrTjn;H8l^LHCqEEzk8ah{WpMg15*5BsjB-#>ljw7h|p*XO;aeOS|9_>OtE z)>=jWQSy(cTEpDggd9K&Aj0rREfX^mof92#a$KKmO*y)feXRYFEm}3_uZyw-cypjqm>a?_B@JruVR4^|r9WqU00%7&LcXnmgNxhGDQ50lS$or zz(M%nL1&}A(K!}>(rStyvF0kSM|N6dkOiC%waB~C_-(PzQs(p6Y+LawOIMkd=`#?0 zJ$A7-nN+;VjP4(EPu_FH>nyWp(8nC{dG@^rS+!;RkE>TQ*PEij2`=R;4_^iTqzNwk zm~Qzk)8$JZ(>rYb@^>_+^NLR>Z)3cAl{wG544F=4O#3BsJlov9D0lf&{)SBXdq=!C z{mZ_|`?P%0Mw~D8728N$<5^;APBg!PPq#nU=FaN^PeFQ~(3OXE?vV8A?dQXw#|ay zsN;d&RJdZDaA^8-#3n5xHmQWzq(sC`3XiY68(F0hx$d^XofVHneX(D%_CB3c^zLvw zyXQ`@fgAkN+%*BL1M4*}QxDis-kgCHzYu(ZlNUO8y(f`t6KmBJ?_|waXV%=myEqG@;+nG;j*Fof~ zJWF>6+|ApY(4@syr298lSfsW52av%GUh^Cjyv$m+jhaI{x9)r-vWmQ0cJ+Ts{IG?1Un^RS zJphs<|C#2(+8<=@z~1*u)!qC^OupV*RaRwEZPrqJinF>{bntn$cc-B_<=%fZK03$r zsXOA^TvaNMeMYgE^O^@6PH;XcPWr6wL!r-d(Rao7>^f(DJB+cFebVMkOP_6Urm5|m z+nhGFopbA`&5=IQG|3mlResSfcH@t9CPHtASsQb%{QGSMm+YdvkoP;t?Hdb1_EGMm z@6S`*dQtaps?R$I+{LW31?-#TPa$?=?ufV^y?ON+v?m;51$K0DV zMKqQ7x;JTBBeD0{^1_i(y^+2T&)2@Ct|ez>^taH6x2B#(kHv0VHp=Y1HqTnE8EZd5 z>wxZLXehsByPloK1&{7;yLHzSpVD_t+~nV4zm6`LG&oVt8Wjsyu-8>;&3pSOhm4xR z8E0qmbMId&RZ=O2(U1JwsO10&`$9GwN zsXWT&ENvxuBM3CH8$(1n^PLBSM{Q-q9ps8u$q&YQ7Tl{oI^Jmb9(fBpPSX$akkKiw z%SR^4M<#;DK})jumX?XE@{CMW?oFSMa?}Pi{V{m?_u%P|{nInxX$X4p573Kk1?HPV zXC4W7K9k!oOl< zZuuyX6Oey%`?XHQkKU`bGwZS>v{=ttLuj{^Uh{%P@<=>kWSu3UGQE$kg;p#HxiZhj zM`Z58T2gTqn+-mm@DA10f8;T6h#0Qu!CZqw@bvfKgAWk9bAR-zoK;beJ0E$$=I)SO z;(a=|uZ@_#Oy86OV{z)3=E7KxzwZS}EnkMJ6fi2Ls7UE;I*0EL1Wr#Q7PYN5c zzLDpvWsmgsAg|l*)*Z>J#HmicHSph@W2b&m7T6K59@cN23rzIYUahl%lR~AzL~m^^ zdJo?d<2z%}(Rg32ZRCLcwa#TZps&^^o?v3&e?xr8Tf~{}ul1XFPvijE8s7d*UP3hK zL*;WH#o_D6y8q0F6GzUR|1;oer_S6{#`f2WfJ z9Ju48*u<%lmZw^|bM6J=Al4Q82cJma6*Xx)_s>1SSz6r_^#o^WxgRQXk5u*!seJO> zI+IMA>pPq2`=3Yj{lJmrswwU5$zN2Xke?kedm+rRZ66Q+*mA zZL9B@v^*w0@B3l;dsF%*3NQ`en;e!b#Ix+|=1ggN-h2n+LvtK`Iz7jVze?K=(|#m) z!nfc9k9A~xj&+0ZDeP(B>w;J6BgQtVyFW9wj(OPUO&k&W+ahB(Jd0nXRQua^AM}2F z^PsVJmrY*7x8r(=zbPd)8oagf%^5t)_*X95QC}dYK{onhW-n{c$`)Bx7!2&&Y(<8( ze{06emK8pLT_goBYh;aD2RBw+WS{)4ku#xz(QdqN`S7{rxn(sTl^=IaU9g}QJ!%Ty zu**@tXeIRNi|O~3f8c$@yfbH8*#nFL+es0&lQLrmd?Dtl{@rI?DnI$p1s3JGhp&=Y zemD0k1jcSU*YKvdo3?3JWxlcBZSnqkwF`}YTy3Xeog;t8CCyDXY|ZbLa`YPPt#v=U zz9>Dv$~TDpokAJiWhNVd8K>^orM)<|w;kU7xn-$V_d(TZ{?RnWnqMAk-OsN#bg}N| z|DnE!NBYFR@V8eSPWR<{_22Fb9Lo46{sNDlM`q#P9`?NMJMY(B2+jOX+qrVSl4>ie zW_y%c;E#^;G2BARbA7QLE(F}>T@r3P5%z@4h7qz!JNPO zz)qhN!KZjyc6wrFdbEzyk#SP3qZXQWHsQnjAnzK{Pu&ZdYV{qAmgigO+_khrJcZH8t0gz7 z5Bicnc7C*=pojNYUG4+D-1i;J_)c|yxa20AST*&PYV}^kUV47}*4PhKhI$Q|cBhRP z`;5%k}-9L0C;7U=Ub$c%)Pk}S4htd^az;k$<%L%cKB{jr86UlgX}~5lOFZb)w?&9+DBBUe(w)rkq9l9sUVH^r z_zK1&*Glu$d<8`J$om8!jdO^usoh%o*;& z7TQ*SoZ%ii;;{=`10k)uY$SzC0;Nq?spc%jsCeKi=Tze_`XjEDYp-+|`;;MZaY6;Gypzr81BVk1+nne$`vGXQsd z3geLhC*o76$EPqIpTZpQo=Mlzr zgu83M7L0S2xrDnCFP&UnYE3?)@0wOzGT*-IWqjD;AN*nLpzNL5arvIq_h`qx$o|I= zE*+YCE%MxRp(EEqBPI`R#_o8B71bGabeR&xw1{RHI=kH5t)a8H1`mim@dyW8D}!;# z>jOzEcW9H&M}{xa))d9L4E(mDOSa4HM}#WG-;nePl*jL%-}I`;lklE?)iOI`EUQa(A?wA zS+jEK@n?PjT}Q6d{&jv}zH`z=nKjZMbVn(8T!Kwh=W@9#x}Vf?9$fjiE2Iw!2ZhVf zfyW=*5J~8)Tw#BpRCt@k*^_;xmdYWkW^wcwb+A8|D>i2_<%Q>=kCcBuQ~u(E>tfmR z>#}{SKlQ8rz{e1MuQIe=xCzY@{Xe zjk4w6*SIp}FMg=}Gp77`%HOT?e~M=Z_G3j8wVte3EASqB=FhCj=L30KKhY1Zk!Xf! zht{X*x}1G{HzLIP8M~|KhV!O-mUK4py0?Gr>lVEEzRn_WEO*n&$VvR7hE_bd+{EQ7 zM#9)rQmy62#+eESb*6T)c&qT9eN)YIRQL|BMNT1anT2euJIL$)AlrhGYjg&t)jJ*= zf$;s9zJDNm7p@EEMa%d-8JxW~JvQ%+`ra>jQ-s^bUdVksoZa8g`!5RD88dP#=db94 zGwYQam%b<36m{LdDLGj&K#RH0zY-j_hYomylkzM-=SwPqRf+U*qr-9!ZT6eD+B4Yb z+XQ3o_74Haa=}V8!QlB{n=|A=>Fos!EhJ+tRy{l&ndMnz6Q=O zH1O6pA%5+7RPYw89p=C3_L}4N9>M*}r=qu8)ti>r=)O693up0A9`_W=HqknE2k@I& z_ae3nFZ?zi*}$Z-IXM70rJx*;BJ5XyT zo&R<2X>hFx#=ilrKeK^vkwV|O&#^rFUDCZCZ$5crX8y`@tmmILf_n^P}7~1V3Ot3$SPQvH#q} zGS6`CtLEWG^s12*5|NQH}^5qOBerWEqPir7#*TavY>2i=u_Zg=_Iw?b9?N+tE|?L zJ-kkKC)Ly0Sn5u%<6bi4xB#;1T>5Qd9c|JUWRs#yTSb&R5dAIRk~_ye^n63))G_Ys z#@hs}2fh$-kEN%(-K=BfdgA_ydr`ICFB@9s?g_46;Qp%F1Jk$5frSf1UFi!6nmQ zrT0;%9C%i$Pwi{9ufEJ)W?zvvl{%f7y)q43o3SUUZSrq4JOSSK(J?#Em@`NFy;1G| z(#-xZH2dG!@QztY=$3T;E$P@U?sV2YSFM3}r5iW#ZRt(;L8Wtjda03d(dBYi@lEzy zi3R8dcb55=TBXiXXN>$&{vT=o8$P z@4U3(iK;2pd>fI}d~XMzW8Cx?v@>zU_zmiFlEhQxai>)eF&c->oQX%!c=%@e>xKIQ zu2W07^WtIBD$ay0bx-FGR_+gikJj+~%|H%mBeK$BU<+;*UW2R`*Kg6n=5+kmZhceP z!f`Lmap8;;r?K1R4bi)4{6wc1VS7W~I z(AB$P3VTR(aw*fMGCVI*%J1tbt5~{L(wY3OH1A6$rFwd+jz&wWE$$louKMTuiWYHx z;gzJ(&=p@!c1GqYM!SY@H`n!*tWS1U?P5OCjWc%Wz*6p%3LqQQGAH9N0)B^(jV20y z%40uHC$@ef|Mhjm=20Km_}=CB^vwHue&cuHtZuqIHU-~dephjK*7)iz*sJkjP2OX# z^e?kU^S!0e$-`m%>fzySd(D01XNgNcrteFoZR3UYj49dFXXetrl2ouk#{Ed#Ow7a@ zA&(wl%;z$Citc`#FI@%vT)=qTMjvSkbYsuXCH{ZjsZM0PKI>M=rMe?3-eoNi4!~#i z`~~sb-f7TM=pl4zx`|tBvub(1g_y*}7a6W|Z=`dDgA)a*>WWIkn@(Qwo@YH`h@(OfXdk8t{{NSGQ6nD|+UZh-NRR)i2Y!E6XCiejB-4-1oczU^5c!<(HJko5mJNMXKZ~!cHRnmP-%X=U zeJ`!e$osSrUyJ>lu}RKVzvf#IN6grL)V<2gz53ZmU+jAXGEvX+&gPOtFd2(kM8y( zk8?||#Om75NQY`8>-~Z&rmpa?-!p z-_;#wRWI@U6ZF{~y#3^O-05xVfimrFeDq@^PF!_AUD0Ea-!r z$=w;{e>wkm@xO*~%ICB(e6@|??f$3heC)p>7hDr*_X z;=w5uf2%wDk!4I=7x#jOxPxPVsx9|D%I-$5o1*zKmx#ulYRw-XUCy`sI;}6I&#zg_ zb$%_e#=0FkfX-BTjOUf4hbdP}dXRXRncP3>r~V@DXdE6alTV`9F@8sE^*oP5zx`Y2 z@oThuE&sDwZ^yT`*iIm4lZHqqC)QdMNavDr?k4AH#<$;$4LpVytTW>am+QMHv*86k zU@5(-L~wm@<@F0`Gk5Z0)~Gf2TPjPrxgW$kRgPxA<{G%R<}THH{H{+?<_2P#TC;Xw z;hyf%!fwuaQU9+0^nF^D?t0wyn9a_H2#P)M**U-(7mslWexKdw8~ zkJ==D)~-o%R_hL@L^#iR0oj;rc-!^N@vGtw*q}FR9NKT)=c*=Xzj;2zod%uY7Bcz& zOWwPOM_Hcx{_jjC$z&#n$q90pkVyhIc&Nb+hF}iEK^bKED^?T|f<}Q7wYFGc6})hD zLIMOt0RwVaVHv5k*j-n#Rz)vpleQ|>)lxI$wp=*-a6t9+71s&W(GLY zo4jc(WbEFw-!!a4@CGkNzILH`o1qM7Xtw;vUzPi4uywNt->^`MCeYcneR52jHTihpDVN ze%X2(M*h=E^Hy&p#JzaqmHZdk(31uTe2@DJK6g!L;Ju#_Hw>HW;HS%_0S&bk8J_(SYkCw zXOd(W{K0YX;8_zjo@yJsK*&F4hJa1K7EEAF8|mu`FE&8-Dkh|WjtJ4ml;!-V9k|xz|;eJn~Tr( zf%7)xie6ywjX7!JOESC_W#bP>%YKOvoR(Iqb7$Su*obp;aqKI>xl_A3v#!Aa2{!o{xh>OcN7 z%zF#+Ru`2|=dJpJ|L+Gkb0%}X4HcDqU-idZ3s2IA^J-i7s){1-8+{e1!1CCle_(sN( z!B>kHCHhM`vwyfF>Ae}Ay{uR~Snz`Sok(Niqzh8>A^1w1nK!+=^3JOH0-j!ZdzDRA z$*SIhtg7ViO3*8ikinZ>I)}F#-n+6gG+(MeKD(4RFW$KHc7^R`WG5=l{x6XK2>wR6U&FJFp>aVDVmY69yUecVz=3*OtoucuI&o0@-*f73+qsJhAxA!wA z?-IMd-~sIq|4IWxegt>HUhf4X+q+8n6L3vYt-R3G3j{bqI>^EF2AJM67G?i~lX9~|WFahy8``jP3w z>=7U8os;_S&FTxR;2gMLW3?`}U{*NW)rS3{%=IzoHQBC+^nAr<58r3>Ahj~anlDFp z(z@7J&pYvtDV}fUrT94cJql;8Zf7jNPyUARZY#~`Mw&f*6k|4nbgPw~Fy(oev|sLt zjhV6GLg@R9rCTzlaVu?n#zFC8r(L}k{S|Y6(RhFSo)UN(8j%%rO{_gW9(@@(74ol( zjp{c3*1!w$?_V~mopL7XJdS+Bf^ImTdw9T_$5}Dyjq&-Uc^I9n)7uwVq4sw4`|m9M z6FBl}Xg=9fj^1=Tc<6`({r1q|0_&|$BB4WzOV6A4xVENu6erpxIQbp)eHOZDH(U6 zYQuk+?VcH}OE)^JdSVO3Ys`8d{t;!Tt&NS;TeW-2&`m4EO9UTLTzA*X`;ez-bqArB zEY}_X@t&$ZqQ_4AS>18)(F5RI2f2S8N001j^vHgQ9@&r4Bl{WehA!R>Gr)OrS@*@P z`wG_mXx9B0)_tA*ZaCg$k9lUDJ?53?>@m-J!yfa>LG1&Lxz2Bm^^_Ci3w6Jio($0? z2%Ah;+2_I{gpK}OSaiyXo8}C~?)fQqneR_Ke$%tl-n;4f_-y3aS%dA|SBLicR)AwX z4zGVv`(sx1(Qg+8x?ch}&bGDP*(I8VO;o-m4jNl)Ay zVE%24A9wWp+rzJ0+2GFOG{?Y-7Z9g`k zV%#yi;eT6CJ2x{(tvMo12)z44mCbiGVUzJ6ke@aesn76*PFGt^|NjbKStyoM z!PyZE_om0gT`8x`8t_1?6Hb3m@S@6k>%0ByO*-kyxjWtTh4^uHeQBnC>;^Tc4s7CH zr}~o0!FFcwA(g|r_*7}AZ$!8^EzWuJ0{n8P%z0Am8Ziz03S8?WbJjZJF{#ZWMi@SS7XBKnH8O2!xJkfg$b2D0e-r=1&{W_;YUC^?-uD(}i zm6PBcMl(^_L}n*YyX8oUritcTfw0nMFw zm@^;9GkPyI7W`xF@NJ22a9*1gdb_u&OmrA0kLX#}++Q`mJolZ(eVQxf&HOs~zDm9a zO}?yo->^dKVvX}B!TZm-vIspJ0dt=zAMudnn%8wVUN>of<9~U=-B_l%T6?N7i?smF z#x);2VoH3rZ8wBDKB+O$d}xo>{&OzxDaZgHXu2J^5n_z*XAGz6ZU_&~1m;2ZdYYMo zdl~nK8E@I;=^zg>qSpD2FNI3Xo#I5(Nri>eq)!UH8(PD&v!B%)XV-5=c2j=wicnP> zI0b96^rXV!k+<>Hsg2yrtU}~;1GGW3?~2-=UoV=sb%} z@v5IUpBmtzY&yl^5iSypoOa^+dmY|pufx}D?Cb&$N5JQo20pTzw3$=CWYxg)Fd*I= z)?xvF*}u)sTm*dv{$bMOsZZ3Ci@vQGcgV;SZ58X`cNt&}dNj7ve)dK2hfm;)pUN43 zJ7;_|u=QTx`Tf&a7o71)a{br4G&UKdmgvlxdhlx58Xvx5!7rOe0TTx~`=ZmB(`nMb zz`pkHLUv?TdNAW=PikVW;k$p3G`aNQTt>Yw1Nij@YbY02a}FH{n{^&zyKWzD0RIcP zdAQqg3vi#n9ftcDE^-hf9>V2~bHp6nYzH1$Mi!?&?HucBY3H^`fIG!p?!_+cA;pC& z($42huzFXmtSItN@a3;s8EHeGiN##Gp({L!PU`+D)-P+`*2y&6`3C1Wi=Z1gb9@tv{j2cIBcQeC`%y1KOw;pNRGZ87b6CNZAoy=s5c zy}+0mwYCjO>FE&OAbY&h!y>*hH?Tx-WHqoXkR8k0^^XtV^O0Qi@=O3;%|Lg^1mZ$} z8OM1*eZ*A|r?<1Z1w&1vko9tF-o*bIpPibu;Jv0XlF1-G*Tz9yad_P(a7T+WXG_AV zO_!#y{?I*PXd~#GyN!O|zJKpe_c3p|@CfyS_jY#o{!~1wld>MIcZj!rbC1=S{j0zX@nb+=4vEL;(4t_ucucTCb?4*V zO)tX}=XtWP>1OV|vg0Q^*LNjo2Z9GbhF_QQO*gR6=6T@02y8azDZGybbBCl`}1+So!9@-B>{zM$SFaa9nBlj`DrF_Cy2tmhE5g%f?aESr@-2=Y<6) z8prJKeRfc=gL3j}k2i1@GkyIPz(U=X*&F(8{iw24AsoqcN;r7tHgH%y+Y?oKJU-2 zJx{EusBU`*{%hy{R(q_mQ|ErTtm%^QO5y(GF|;}IZ(zM{tr|`KyWQ8-*0~K&0Bhm$ zU1~#!yOeZXwU+6Anr6eu2KXqE&tqJ<4-H^f;{bLw4o+hpu&Z$zy!k`yYJ7~XjL%pn zE*my9bUYDj0!G1Wbx)Rk@9YiLXzVG|=|k>uosFym$(FThel#cXmhv;T?=)_5=H^!L zr-0^1^Po8bw}OVP`N(`?!LKwQKY2lPKJ0PMI=00Z$ofHGmguCS^XZ-ijc%N=@8pb~ zX;W+9G_tYnz>fyi&HdnxtmgtV#ABf~3D4`CSNHKg7fcT(jiYF7Gwt!$`@ega#?s7Z zo%>Y0rR-D9|GHSkZjCv8m}~kgIqeqSBedRr)i|H>e?0d@qj;;d-n@J-z`YUt>S4Yg zQNNuvr@qop-#)E7%C%H3G{pa@^Lx@z!$*cE1ioOxKGs>zy=V{NzjtK1cSNCG!nd>@ zev@iwpSp)NpMAeyp&8#1vIc? z%38=BtBo;R=)kvI&hSMy=? zQER%^FJb709JXC`*zaxPDI6hwF7VG91INPoA)`ZvKHjf2LqC@y=Q}Q3pRyjA^^9vC zD8Cf0$O-W_nTs9@>GZE)zmI0$j{!%m14o?zZXi6>w(X8hY1;JggB|F4Y4zW`pa=Nh zQhG)-K%MFB_1>t>%aYy>@5;^KYVEb1O`nC}{|PTkH?-IAw^F3fG-&qOJucmAt?;t6 zc=%h~nM9k>JxXWsJ+2o_ToC@8xt!hKNpEkf_x!8mE5n|#@o-uQdVHu0nbOx4SCP@^ zs$d;da0d~6u42sym(q^)rnHS6ow8-@t^Rk%KImVFjr%Bhc87yw;48G{Sl!_dQsV6Wh2g9wSH&+IU2B()9B1w`|Ce^SYyX+Ia`YWCk4ENHb+28D zyn<-4xa<8rCeK#{=eWn8R(;^6F6avtjP=*ims6uK=w$34FLI);aZb6L zR4#kW$e~IXC;NO*Zw$!q)Ttl5b4B#dW%5h+d24!w!E@#WCMX^l`;f|Fe)R@Nd_f`k zhcVZ~pu=mA^7fVenJJ4mFZ6}ER2KQ>i+@~x(!vW9*s3(V$>|=b_)+Y6@z)w2UGr|! zT5wYMukKptELe!`i+;^tILmEe@4+Qo>Sq156chpjH_U}c1Kgx_>hZKT`4_y|sI>qd z1mDKbq07o<-LD%z1m2%q(BFvenh5s^%j$loX^wxDFMaK)hF9%z8c`l)t~ytSigbqA zVWm%)v73{2Gwp3T5NtZ8aQdV+z}t{}8+EsEA05ZMNav<-6~@Q&Ecl!?R_}7N{U0+w zF|}Fki?`(MWR7NWuT8YOUEzuLLW}(vSpIu#pFhSq^&vF-N+SpGBdH*kD27sxmP zi)@+kdkSBc4Aa`(O(zw`xNcV-12=hR0Jn+KhK20^3gGWwyftt?e-@Z3o4oB;V5jxp z=>xQ>RPLgN4!~LcS7`QvpU|lcf7jk5{;s|77OjB43maj`bLsmo$#s#g?eGPY?moi@ zc7eE6);!4&%ibQ}UzH34>1G{1VbWnA2Y#^=#I3Yi55GyemFD|y!>`?I+s27>Sr2Gz zq^~pHl5<9L#T@q=*bTfD?AE=JH?tcxK7&U0tu@`TJ^K~M_UsJD_H3JDd-guZ_Ut_A zqb2VwTTimpV(Un@TCp`7=M6SYT>C-23+i1O*iP8j+7fTm^R2tu7Fb{9Y`B~A;{j|# z94GzPb?zx`ZJnovGur5~zH%0ni5Jw+8pFlDkda*!e)|SG98!Iitm)@NtJxExRs9^C z^`9D>IqUBQcfB9n_hInfrQp2qufQ7x-!-`G*7$7C0liJcTQa0iy#*Ve*kynhuxI2B z@$qB#^9_TW%r3tUy#$6f&X~I6v$Gy!eNIKc!qm4;pvMn>K0DnA?pK~ujI-N5KhpHh zn9!dCzeXc;$kZCnn%7KQheK}#epHRL?|0~VhquDtA-w@f`9=`d9Nv~1W3S#$dg<6^ zpJgtl4YyA@(Re$sOYi$7?5lfO)874if4r-z0~@qgb7qvd(2WmY4Hn-*L(jBcAdVPHK)`YV}2%dFMIhiehkkx z{GguCkhNd3f7wk-G)FpP!z0uBITy_xpR=-h?C7-h;cL=%Q@7i|T=VY5TjG0-W2ATC z?0+4xM`yw6?LXdQ&wFk$e4pc(hnjFO)99C&SDywCD`gjFLfYR2%!J@rdYj9`A9-Thfrj@wlBdw=$20wh^vR8v&hRSZ(h(m+S)pw?+t-aNoWPIuv|t z26k1G|2kmHRoZizLEeHA`JoSLT~`HSjDPSk;bPni#|Y-bv*i_D*B*j?GTSZwoJSQN zpN%aQa8pBH$sb`!pE~WmlY2lgJPf0Iym!fd$BmC(*>(+NU&6oeEhG>`UMMRDVe2?Wy`6 zv>nc3tsUAjvv!Y%HfCvkt=D>0czc6)ocbA`T|S@iJ^On@{fg5VfU`#QR!Cd4zC@R} zE4#~vYfrU>xQh(`|oq1-0_4^J3cEBGk)(w(NgEoGZ*@638~U~F4`&ThM3@bt8#_DSxwD^?+0HTE5TcHW)v^VOi6D0lK(E^qW*mlZwX zGV4|I`QW<^x#8*@?j8-r>#R_KGog6>DaqE9{s=tFDI@nC%4lEkRzvZ$6Ai{*S^M6c zIN!xt!93*BEjR7>qiNSxE3LgBn9%R?&KsF?A>L91%@DmUTh*^3^%Gur!Q|Xg@Uw|G z-_S3`Zvox0>H5(n3wm;sIBKZ{E zohQ@x*LkxGu3LUno5mn>c_8@s%GtL9t8>A@&{+)KuPtxa4>v&f!=?TZ<2nE>F92`L z#LOQc+xb+WKy5^?bkWLru@Jb@7oVJ0cPR58C3hI}#jWDk*@x$`S1)}Ob%!>Wo+r(< zd{2;VD88@edn#@47`G#Hi*1`UbDMED z82(tnn>hi_8s9=}HZ3;ms5K>deLLft3f&{M23~ceR}wvN<5_p216ZqK-#(*#Zjb-) zC*YGSa`pyv6!A1^UOcA>kFJe{0?-|zHV))*>^#B8HYbPiPj~X=cRP8Oif50v-vi`n z$p~sMxNpV(e4<{HZcdKUZP7Z>xf~stzRR44UD!oqErv6YE%8~~!XNktyH}61bO+c_ zQsWMn`1gcP#lVx&CRAAc2(hM%uWD-e16Lbzv;U~ONPIT>EV&1*TV5;taB^fBI&fRD z)5{v>`+ecK{#NkXN3GvVeji?XegDqz)FZ2wF&;g*r;CCb*Unwf7&+zG%6o3J+nt?3 zyH9m35A{V~qRm~%zCA))gH6ZREUOL4ue-pl%dF~K7h5$q!mkGG@MdERE@x9-H|uOm z_~rCn(Y@)r9w1(E50Dny9Nq0dPT!?524;O2-sX?LT^}h4Z}!Jom%!sfXs)hP8m|h{ zM8A-}>zeyQ2FGB$ZmVFv3=Z%CZK+OKKX$DrHg>dU{n%SQ+~1pycVD>C=7DSpc4*%j z7~c}SpKp)ZKOW1|J`#Hc)v7D?wW?YDmd?${m(oK19#62XJ}soWqgAQryW0LvI?o(< zkOBUYxhFo!b57$0KZfX!_Zr?)@MCC@4?}}o3JtOY8sutdkQ?-N4-N8JXpqlO1D|$i zkisX~f5SG(Zl2*ID{_ULv*M5Oaz8ZC^tjz_>~QGLQG`vF(cnRkg0r>^&*lEq*FN7> z#J={nFSFsAqrYPz{y?-oeXzYMeK20`+sT<9V||PNV+?&U@A+CEz!alvL_AaupcUu-y88K$;4P! z>8;UuXDV6MRW%X&0Ls6ea;lNhE;zc;*pD|h){)7)6FF_dY&moMygLI!u?=tJ0vBR; z{%P4BM@I0Qq(cX($&YPzY%2^`e%T)74ZlD%Vae4>u0yi3qM>4QA>SW#w@RJ{8Nwpu zXpJll_7{|Q26`Y0dDEEj;L)b7%A+!n|J}em&llZ;d%Tg=Pwww!8TVz#C`dlH2U!ZW z`98@2U3rJ4ZX?exx~=S*k#6Rbr$PbFmnS;*Y(J)PK~~qzn3T&dxa@~(ETnr$w!@`g z06pKu^gCa6!8Jy_70DL-J@i+$W6Pw66ky9;f|q` zi@1@3tCEc}bBT=q<+*IVJeMU2xhTfASaV6aSDCp)ep@n9z@&s-v5RVlGcI=|#zpg@ zamnJ{EUP`R-S=+VFyE``g$Z4zzP+|y)HQn>-qQH2Il28+xxW33jP&kA^*N895Y3V}n7nRc9g`(8sa@Z=qpr~RsWyO;e` z^u%W93G;#3ukhbvXbX~=EU{kad#uhn!E)T0?X_vU56?xPuLrx|vfWspwmWA_UbjGOjY~bAF00Rx6*b;m!vs&&obdx=oN5(q_dBE2E1MAW5JzfKDnqmRd)^D z#|ZlfdG0%vMrS!V!C-uL*-~@A{viDvwyh>k9h<(N_P6>r`Mg;k&O&%iMGt}JP5c

GA==TG@%LxVZvTQXLI`}bAdIzsm( zXj~chgKNdj81(u)#O)?*0`Pwvdbfi9HNJuchZ`D(dP>htIowd;>)C~!f`$t20#nsS z;jdHPYiNL%aJRqJ?9=<=EnY)2VJ(Rlc(Q%YrL3oaZ|HuYK0VpiXm~62R-v&ZkG+P< z%hz@FRR+M*C#avbD|j0T@}`bnQ_&p8j`#LSMkd~p{+aZg)~yF?Yardg4R6H*;M6VY8^%8Bi(|{u{Y2%&xWT1)CmOrd7w2p~BHg)}tMYsq zqm;MlAmwLQ+z)NsKzYfR2cBKPJ`0e~@E^6s zpuvNaQu(uE07=3we{2t+ln(KH=;S)L=nPYH? zg6lNLlYY@q$~#-J@R;zbrqjGnN)DgBl>ZU&V~D#+afIKb{eyflch!+^2oJ4V^LBh1 zatpP+SN&wovXR^Ea`U0lY3+=B%-|n-BbI%qmei>#kMP@^@>Re5&Rx%AWY2j!P+J{) z%Wl?m3Od));*5zGUdoR|j|UDl;P>I~#0~HUjm=Eqa*3{s8bA@O;9I9147>X9OdnUC{r_)1k#T!G{<%`wRbXx?x(Nr?4f~Rq2H`_%A)N>CzihvTAwgsmwTbIFLCce%q>*)sMn2WVyQ{fpKmc;c9`ue&U88%G|X;=SlLY+|>R z?tlk?^DEda+$Fl*syVjL+qiij`avE;=hJp{>Fg{0bK7=n{N&A6WbzhkGPc^HQSP>@ zo~w#RH(J%m^`ylu_l|WtMoHh){{z4KLiTQJ)t1nSjE3t8dZF&Kb=Kd2SJ3wPY$aHjL+=V@IC(-r=3z3dL)DSSRNG$2&Op_{<1* z5?jB!WOip~bx2QC=8C+@$R$Tt+}He0=977UgU;|v*y_`ohzvbl5}&-$iXML4+cj^K zwKiPniaph~K7hNvZH2Y6ZIkuX;1O&_P4jlOJ#B4c-7WXc9~bkltX`q9;T-5C&GNRD zRu}w&fwm{DfABqNWMpog*K2L$%+NU>YU{DKv~9H3080wV(~T|BK69V#wfex%jSeK? z!cVk?V)p*Cmd_7*;MFUde}BFwps`?Fwrf19R)YgMV*{_m6ScjbKCL6IMbf+zPGhX{ ztsUfVM@IAv`P5%#-tZ%6m%uvg z2yoAhm%Ex0ylvts2& zQ}ofw{JB-k8fY1+D?iU0(i!_+S^h)vcaeW(ytyPRv;$n2GJw<3@Xi{4Ma54qb^rXC zZ(&b77H`fkGw0HU{_5}=U^(}*cyr#TDu?r5^q$FvXF6zPou07Isu35J*Yp9tb?*ta z$yK?wucCx{dkinf5PB-|Ee~zjCLXP1oaL=)yme&lVa^@9T)M+#M=smtYE2tu?qa}K z?+M)_-9K92zk3AqRNwmk8feg)P=bd`C`(pz~6Ya9Y`!BZ(UPOZ@L2jgc_Ga3B zYk$?$q&m9#z7VSF&bidJqxzi2mvcT#;iM~wTe-A+@z*Bbj%)iX z|JM6^=}C=Sz8kup8{@6|ezuEthN4UCw&@Jzj@%1RqoHf@w)L#ppIC)fU0p}3y||aw zzT5Z(mASU>3vq?3Z_x|9b;YuC(UEJ`t8|C?7Ihn4T(krIbG(NI(ff45hUKvnu|D|J zr8nWrNj(@ppnyH7M+Z|dGr`AzYe*m8KT_j#ke z&Fn!_e%_BLi~R*&b)uIm)ySoc zTVf|}SR$VK?i2O3s+)4QM3>rm$p?S6`@E5tXmzdNJo~Hm&=_|&^RmVsf9t8W&yAve zO_$V$p)JKHGneFTxkfsuDm*oBT!<{p92eSJ`62p5|B$sCJpG*3vsn|Z);`wo7VZwL zR}bUQy#_inIx#rg%ICCGp7Qbi1bNqY?a=$OXSZw!tL1#)@3QywW+?ug zH^RXbXu2a_#_wToXzoH92l^k^nq>~ehrL1bYR0A|XzoJn<2~vd_`{>&AUHa0Y!CT& zh3ohi@%CMh97~*}V-se_MhrjU%2BP zVP3ky@1*y_yer3>Gw#&52!A*D{e;X~fN*@msMi@f|q1$Pq5TG?;(ntf*0l;Iy> zzR_#ud&IZ#=tlIKby$VI4qs68J>*vmy;n3o^duQNuV{7XOEPrV<%h5HidSIGx0_Zd zzvfbWHUAMWQ@Ac?q2>iTNG0vx0-Yd(vD^lJRjB^d_B8!z<=38hh_e15o12+iSPSie zjp6*1Kd%Xcx~xA2|Kw`fRH_=e8m`jBtY>+<+M$ai#TtL$i%UKo6&e4f9~x0SXvGj_d$ zkCa}ZZFdaSm+m;a*W2aaw_-xR%UH)y5(Es>%pdc>fs@87vuD%@2j5t z$Lk|S-j{qU1T&HIeI8i1gu8&oZwq60QDb=HBXuqVkC1be&QZpqK)aV{Yn!ZFD{I^tH&3&k@$|9YW6n;llP2^l{ zT@&HM2TeFU*N69cCx(mt4^T!?IN$qZ=Swlp6)UZ0?^Ew-FZT3p`Z2EO=rV6bCF9JP z72dcpqYv8SFld`cvY!jx)A`fBJiP-#v;07QjgRhWqzz&}qc^)ZG>Q9Yi}x{43jE!D zdPkD~*mlOS*eW=Cs?^xnWSv;?=CYH#-x@wg(nd`?p>-ssU8^wCdPuv%qy^tO`+o48 zNy~RqT0}@pS}$p@GikYBkk*W`?iyFpmYh&p(nwEVcDyWYUGi3v>jy{%X zbICHN>;P#O`(HA+7G;;7GHIdXB$YkVNt;L7GPOf%r+e?_XK=-5*=(_mabi!vjo?xR&oaPy3buXqmHjVXC2?e z|F@i13vvHDXG1mcVoNyRZTX9R1>?^pmT@xW25!{ zKJAHkd0+0Gr}E41(FlHrU?F-Z%cXxZ=Y4cd zCfVA`!TyTg%8Z`y-x=MLGgijJCk2zE--af0D%4F`h2F8g0pzjrk;VGUH?R7nH?KzX z<|V$dnw;*y%lu!-`P9fvoy_@Hcqiyf=0^5-uij8{3bn^Mn+)F6_1v1_2A3$$KdCXG zKb!5d$=w}q$+}K+5HHW)sW{H!iMZLyuQ}#>y5NS&ZI6jwl|2Vn^I*!*Ix+Yt@Em@9 z)`0J%&N$lVI#$7%wZ_(i>90Wdd=u_$M=)yC@9ZQ<-7UveF)x?Z~WRN8DC=` zo%_YjDxbT?z0f%_;POCTZ>M3vaFHz||hM!aWroojsN3%-(A8 zHPEgl@c+ct#jc8JP3XNpT#q3v?wNCA)-Rry=?`Bm5;-(V@jf=jU#6wTbp|XfbwDdt6^d*Zvm5?mM)&**|g{?Xx)RelEMIneEWU+rekh6)k*5_{*BZ zBO}6FSThBzmm+8oo{SV<3V4mZf6%Fa6rE12A1v0oX9@RN85`N1^HiWP2f8@40pMKP zZtZh$Gj2h^_CnDa)4CNV{0$sjac<`0@pv=#3^X6?8I8@_w)&6S>)q=$ujuXfu8pTQ(zt)5p3^+Fk8&-EH>VjrHrhLfFZcpl6NBfA7xCT~A#G~t z``}c+W#8(dV9bFoe|nk(PHfZ`#U9zytl2M+_y{X9=&bNXHVs?MXzu^ z=cutI#anXm(Cf%C@-_@D`lA1JU&&BQc_-=WHRfuk!39p`2j%a+*q6uqe$fB8d4C(v zUEjRt>z&#jUr(9rRH6gI;_qe+6m{SKlOL+B;4Cj|pRD=DO^daT^p4g2KW=K^+!lOt zw-aaZTwnw?405qyP>h^%1#-%xp%smRR#XQLJONtKRA@!FLyu{m223&Z7-TGJx!*}| zA~4RKxd~Zk>@dWeN4zGQ_t6F3H_>Z&&NttekABlM=w#@I%rox=dV}W;&4;|xNWHJC z{m}l6-4*c(5MCW`E`P`gznb#%psUT&yBq1QResWZF)6RHapL5?fi`^Vci?e! z3szUfply5tZqWmN+_NRtegR(XHtx#x{w44Lil_K*%)WeqyI2)>BMN6tDc-@ndRAU=s~cn`&Q27Tj>?5->4YBn&& z=CKJuZ*jX-cgASnhVV%5lA~idrS+qv(9be?>nw`|RKy#piL|yc5qkct^?koHgvLJa-FWp3K2O z;nBtLCmq6lnfY1_Pt#%N9C(TEqk(+iOUz+gU=w>ahD^HL?(Btup21B<|LOYL9xDK^ zUtqAe_`J?5lMzXpXR&*zV+fgCv$$9w=26nFZ*DyNacGE28+*U1@f|Q48SYG7!c+=6evB9eZBMC zqj%!Zq_49yHk$v8KlCzW-So(QuDTS(aLg!S3!ToJ+ogpI~7k&%I@e6*i6<%tQ#h3mav z(fbH`y!*sUBe|0HdT1xh(u;K0)SrDck-2U;d&+Y`_3K-Cf$cNTo(|4aSoAfUt_Uyx zBEk(#(#CO$9_BndAN|ZiUwDzXvp#0OEZ*{%v7|Esw}&n_ONy%+u< zYd7*KyTfm$^^f(Y?H@ZjYe^Is*1hbz=KPM&E;<6uOLQ~o%H5*3N#VjnMa7F$K5<2) zc|v8`br&r*G{RlbUzV?kJ7Kp$Guj`0G~J56N;!K1TY!~Yft^qP4mkpExf_0kqVGY! z7%jT`s#xWI%{BH5T7Z?4+Q+AWGYmV;ItvNcK+YnlxU3+0Wa@=?411oq8jY9Y+L5m% zpUqp_QkbhTQrzTaDcD~G#~h#1H}?+cyZ3lsnA^%3gUvhB&Xxk+-@VL9$clc!y}s*I zMf@7@NHZUWZYwNYV-dIp=e*w6#m}ery~j6I#B{bJXZWG;ytQqW1_u|+P`OiIO<8~I zg-kDHw`=Ucy+6#d0$bE3WNSXjyebfsZuQJ+d*4d8dgj%(etqdy&%8E}BHilXSCUb+ zb#%9Q4zO;gfJ+pB@4)kz;Zu z?`q|xcWV80FZ#)s6{kKk-)h^!@G$ya$a{CMgX`XF<$Jjs3Xj*_PlRNN zY4rZk2F+pks;;JW${U5B7h2~LwGSP;fEUeo&5>xY-cK7}gC8x(ni&u;(5mGzy(dTy z8gj_qlNy_FNx({^owC)cKYKcJqwE_mINA7yS)cGRAW!)s`Vs~x?;y6MsmD8CWgO_; zom$n!_ZMM(QfXJHPwyMLRn%-mmhIQQ3Q z>QWsUJ&(T?oTs(a;8EIR-2Gpq?lfRcF7PM)*apK#o$KG=zFl_Aknfi4b-LO|+GfcE z8{V~M-vq)W4=OqW=eKMOnl!n5i}tV!9HN8oN_`(1U)l-Z`X%uNNv49hso4H2=dSy( z#yj53`VG3jLVYdLaensHaM2I0(tS>2th-$DJx*mvM-BO3Bm7+Wg0UfDc%W4u^^PR2 z!`}+M1iLqb=SwcV`BuO8Sdq8lSb6X_v=!Qj(TkF8w>4dT$m8snO=tA(vxW67q_oEw`^^&i12{`!_@C3O?&ZjW=<|6RWa9-NrBJ`k#z-hyI-oZuSpjCO9 zPqvNC!tdiw85ex5rH;0ZF3Eys!XG1;+s}74?$1Qmh&Q`rm%f>}ZJfv4`LmudJT<-6 ze)-wk{cXLjVbCUjk6RS!b(H`kJ|oSW_$A9{wZ&X{ZL3@b;KkFuJw9+}cvd-s)~#XNEU>MBk*24$5wc+y{6aq zfmcDdiL7=7I;wX3GSY2rl&x;{hwrClr#t)w=Jt2s9QEKHaU1v0Jw5Zk*)&by_9gDn zt?(!o>n^=26gn@P40wZ%9PxUWsGYJAt~NUD`}y4c|6Ut&&;`|afV3|qweg2e8`Egti)yne zzqP1X?ThqUzkr_%9LIVeSYqD&;1Amp*=B7MPNsDx7)1WTMS~xd5BR6JOX9Oej0F}p9Gj9+1TNByzYxFlpieh; znO6EHd%wfFf)^~all{94{d({~K~s`G$b-mK9Y?0>G&-F=M4swn!V8v-^yA7r(IWrE*a$0;ge5a*;b)WbVS6NyZ;hd<;qk2#ug{A#W}Z_EB`p*VrC8OC9UTDMB@(+?kzu$ z9+VpB!&cUKGw)a$s=e_@b)Qw=clzV zy7!Lzp7tyF1LInBr^Xfh>7i(~rzR`g;>oGP;N{>A&!hiKa%LN94`auTb3I{8a^fbd z@?dL$m2ttA0oNHWJ{54lyL_*>d++PDDxX}~v|Vx*=%RYwUb}hEj{PTeMbam=3HL>{ zNAQ$!G&(Wp?~8i3X1)JV`roAc?cg2M^LuwbWzVQR(zro7r-1VoZ_3!>FtB*%eaP{E zlU%2|wAQuG|8k9cW08%P*&p1qjqH`#BgprhJ>`u;qr3x~ocY`bo`B|HXk_v7VP#rx zE5G*lg>oz3!iM=#Us3i@=;{B~FL?Ps&!4kCi32BN{M#Lu?@!_mTnBG#x}P;HJ*y9g zmcvunRpSR{FCCf$@8K*=rHV$p*ByL(MbpVDcnr;4%qll}N#_2%X{vNMqg(IZYq+OQ zu1d+|OoG?HX`1j7zQGT8SDID)7-3_yADnwBvZ;&_cU5z5orQfe(kI2Q#|B2K(X*J~ z{}Zo65)Yu-|Batpv7xH+^J^D{gbTJ{5B@gJcBGe2gG0~*J~+^h>tyn1s3FkjO!e4MY_x1@So4^>1(t6 z4QXc0YEApcZ)6*f5cP# z_Jo+vOIf-LC@$`bSh5w>UEFk1VTm&FzwDoLrB3{t{I927t`q-5%*zBbkCcc1PU5#G z<-d;jjzqlDk|xXltX+ofZ#<(sacjgMyNer-@O|=1{>B$bGmw+B174M&rHi5J?D#MO%IODBQSlJ&BkN0+U7dO14u~8d{AHcuUJ3eiI z_}3kOa{Y>*Z9G@<=;@w5ERgyR*CarZfHt9v8YO)PMOe z_upHh{@=9IuCw%YjSt^So2Y-lF0ZuP%NS9<(kJ&{{!vbT^?!hG>Mu3*C;1co@8~Wb z|GEB;SN#KVt3>_pu*)h*)SvKot6V3Z@=F#v{ipu%qr7JPN=*IEcQxr74SF{&IOveB6oekW2bR{RzKGulcp-y2#Xz|IO~=+B0_8 zaLvE`pPT<$XZ(k2{`KubAI)yHU+V*Z2mWr{367uohnxD7{E7PC^fHdbSL3Qb174TL zZ@5=&kiWb5#^m`|`NR(!)SgtlUEeTMf0EzS@A#>In5jR>Z|YC-?^k>2PnXxMjbWz# zEB?ZBiTa4A{=!849psZgQGddps9*jL;y>5_!l>$@{zSZ~U+r;*5zaUY+^2?uGKj{l&%4g4)$3?vAx5wK~uk~#FN=Lj`AMw9`#NytH~mlYM=$3mAMw?nOW&?|(oc{ZxAKzvFaLhhC&lNR z@<>16HR~xaPQC%-H|@_$)bI2s?@D?*en06aD7{mkm-6LT{j@JPE*Ov$U+u&zJ@I+b z&-o*c-^rh+@$YcTqy4!`ul6Zk{`P;z-$6L#2QK&D@$V;}@;mXlQT!^uL*b8URel}r4a_FfOvX#e8>pu6~bXaDDD|I2@Q|2uwX&*y0WlVAHkXLr*6r~aI7 z!jslRj;a63`p7ZuP4e$odfGprc9GwUo5(*QZe^d-`ghXHuk-^~{C`m%@i`IVH69ai z<&RNbM^gGF3ODt+G+rvt|MGhi@W+NnS*l<7fdikiRKLlOOZqI+f5kig?xgq* z;!XdZc=@Bmt9?o@e{y;9_b26_5VtZ-|DE*mEB(L~zg-^fXKp+$;=8@{Hz{80FKInw z?ozzdU+PnNrvKW{@_U{BchGZ=@b1|Jn4Oj{wMrOKcN14$7_ClyPWa{R1W@b`~yz;s?YQve%*T|A5MM7?@B6fA@wBusxOK^QJ?$~$3H+l)SqGculgOo(sv~J_v4?CA6I-*c`+~Jgx~3pSLp|w@@Vhn^4?TA_`RBcXTI^L zoAFQb@24KK|D5zu{E7WFK>BWlUrFyZ{;T}zM0%Bjzh8c}7Z-op<@tB~ zrv5AO>8Ac9e?;Y|K3tU_BVVHb1C$q4IZpj5zgzK1=`HegB$cQ3x|00K^RN7-JjE*? z{s`qM{{+V$lbhsMdGZf<$D8!3ZvcNHe`5U&cxe|rjfwsz{QI5sjz2Y;C{N*}H~mq4 zj}xqQ{1?AQ1w{NzuGdg-Ur9{D4V->E-k5B>?vw}aoM zL>&00_A9-m^jG5D)k^QQ$3^_*_L5%yg-(2j+_>eA60Z6O@DCuL*!{Wq81ZI3DxCCt z@T>d|T&3Ty@Fah~{Iti}-#TpQ+m>MkUuIn$sduQ^v?NiE#&;#p5%{`U-2Jk z9H4L2=zKdoKEum>{Im%xFTa$yXA_2gNt+J9_p^#mic=qw{r7s=(@F6Y@OLEnN2@OU zZpz9a@8z`0$Nl`nEAfp7=*Q)F;$Bog?7WQ|)Q3d5PTq%;;%_JK<#_Ve5ohkvd>4~< zAdy$J68&Y`5rJbRKBQjnY}5^a?w+jW;>!QyStYO4b>kjyw6j3wrKq!e>Cs-SGCS zJNl7z9eBKWWr+AWynDNc`s&UN?b~{;_7ePBedEs$?b~*q@4!&sP0NP%{rxh&y?p=6|K#e_IsU{E21S>{{gXfiV9@_l%=^EbHid*h3+$ zcx`h|*yDHT)#7u=`!}DxRAk=KjqVBjhfZdEa`sftGSRVePMWkc#~+(H99noQV?CVt z*vc4gdwfQ$Mq}aou@C<8ExaRS5Vra$-a9TT%>QFgfy!68hkjOi?(C)E6I7y1AoH{mB$Cl;qVx;kiZjf`)L<>mV) zeE)=R4?4_#v z*kfw?dWLa@-~8;Q!h22ny;ef6$7BFbjrEw^LzF2O?}mB|FMb8 z(Oqh5iu>_RRpzZoyiJfK^*D0GnKUa^>boRolzTv(yT@>r8C)G_AJQRazng&n=9c|l_CSkgYAj^ue+{+_cBUeUa`|G50U9riw8 zPX4_;u;#NJ?b4U>xI1R{is041H||eAZNreKH(HUSFSEXZA%}j-IQ_<6*F!OD_#wth zZPwaVyU$+AdG=T@Yg_#&b5Am1r_wW(_wrZ)H(1*R#7|D{kIFEx>1V*D&dY0irf*+j zZM(j?d|$@{@PA!YnD1ip_+`Jy9{t?-r3HPPkc$#E;k{ z*+}P1&^a*U8~ZsEip_cOEPm;~c%Ctv1dqmQcr;{daqHWE*s;q#A3FPpYt{S>0l$WN zfnWPr@4&C2Uf|b0);sWPs2BLPkM$1x;`=9jdw3uHjeonRZ2z3ltiffa=Qd7eZs!$6 zHUi6ZrWx23v4$zkkDkiIODyX!=amrpZt~a zHs`BvpLi=X9`L{HDP(;#vv*nd{t4K)Ij3)h+3?8y1L*_5T+WqsZ_fPAr~7JrCwQYm zc9!n|Zh?1McZ~hos&LnRMG?)@P@jcu1I_`)5*X=!&HM70@_l(s`Mx}+eA{EX!jrnTuX4-A?^zMwXX;=2`~DK~j;0@CY+8Ar zwa=pepbZATrO<}U@Xh*x1K%d`R{DQA-_P}JyxEFq9=(e_g$Wop__yp^jrlO`S+CJY zknr1cS>E>-b9rSB%v>(t*H`IX>?@2djspgsS$z0cY;SI z!2rP}2M(CNsC>bqLout|7zRFb(wq_7I)-&V zb>qvFPnh&r`d{%3OPsMjcx7^aZs2e7`D*$B56R3m$ND4}e&?DKp=#HBaE0wE)5`Og zc?vUvsl!d!k3D6+e@z{>@e}YD_K0Bf(We<_((Bwf)Ncja&7oeZkWrcw(=yl!tYOh|k5$jn>_%l6RFid2X14)a0>Ie&0^_ork`g@yE_NebtAV z3-6=8lGvlHyGOw%=a_ZZ;(y%}H0w)zG?(04524#jbsgOYPHER=d0$3%L()1(u4nna z*M4KxE^C^#ou@VJU2I^=oyfrLOvJ?&KmAzpdgm;duQ-1JWBO^TWclxcCni4>6wx?jze3gAe9?@PFBM&4nkg7@j=Y${7v39|OFv;|!RZ6Ai3DjvC-hUVkI%}Nd_~Bv zE7Y#KR^1YkUO{Y|W4n*>fVZm{-mVH@_Gn=C7+`iCFna%eSvjZGwzup1HCFIPjksC;g)ixT^ys%B zm*S!92hRSv{0w0aMqaYMCjK$$w&(ln;vtiKG5ky4I0~O^=jPD3xrZAcvgaujBEK8` zf}yAW5R!gf_lo-smv0X`SH1jw{4-be zg}OGLLp_htOo_FXa%2hc%@Zr9M{Mq)rY`!xYzh5J7V(h0z zmQ@!W)f_CVE^*`rTO*HDBcE^c1M@uszTi8u(Mx?49%0VN=IpN`;{whgelBpGbK>!Z z4=XKuQJ!=|Nas~cWKs3C$B;iEf5_->UR3=>;hWS`nUGK9J4pw4wb22N%yT~S(58Oz zn=S9HcrWr;HTuKJx6js-O_^SFIm|KTQbuHHwNL!ZlK)h_;sGRH{m3NmRi-c7rF)+? ze97h~BTu#ueln#!`{&|9oxlF=zLV&DKzJR(AM*2ZJd-k9s&IQb=iq!6JydT*2j@CV4*pnOgs>&lw z`VHLd_2sys$6LpJL1iL;G9B59ZSk1}pK-^|hWAYT)90x>hAt^=^cFRkx?8-jX;0w? zp93D1mmd+#V9(^E+vQKl<~K=y_{z3g^h;Q2wFesSXT2NSYVld#0p;C)V%8ajWp)Qv zA=@XrPP~XA3-VsW2HMaWpIJ0jINjVg8#WJ~7y+MUgRx->Z}$Z7vV!=`+y=t7qjwe_ z-SUsL=ilxH2hw=AAPb1>zBhP7EAa0=pY52w4XphCPP3nWzta$t5 zGqV>X_v=}E9zClcTFhPEX#;DUM;IQyw|nndpz?-d_aH}aG0%C=qVpfPQhpt6yV%v= zR8F~)1(AF$ys3>B3I7vwZuGSxt0sMwjNOPMrd?jv#doc?$oH)KYyh#A3XQ95vqF>|S6}!;9$j{P^sj3*V{i^C7R(FyMO( z`WHIv_&!iO)c9-Co_cTyo44HAaX(Xef;Y&yRAB2krS=!tza47Kpsj7i?MJO2zBAaTM*k)2z}QGa4?wH- zz`EF&`5CEh?iQhO?WhQ?~!d}<*Ahp#F;st3eI3R#K?b2CN)_$HQt)?25Z>x04k4c zqlVK*ejPj|H?)JaJM%lhWr{<{FoCyJfWu_OXQg}^?viaH+A=E(854Lr(Vx)O)@JYv zBNI9+Wh{CJr6+Lt;8(Q|Jc~6h*ijcx^f`Z*t<%xB!0@Qw3V(cr@_rPb#rp~A7_Sv- zx8zdWvC9E(>7DYgnIDq9N94Dfu#f*Ae&VzgS1umz4kVIx2P6QK_?zO3gY_J?k1L7HzHoM!-+)Z-EEw zKk<4n;|(AAy3oA=GgrkC13N#z7L;yi4tl38mzi6~zawtBZ!r1Lvue9(JLEd?oy@s2 z$8Hl2K31r4hc02(9BbiI+n?^U^LwtA>mTnC?>ucuhvIwX=Pj8Pdlk55mtQ{M_|qK! z4#%JE_&Xi{2**F~|6}i6;G;OMeBqv{VHkuA0)&yR$MlRO5TNPq83C5@j79>1(MUoH z!XN>*o->ld=wWH}0PDfa*x7Yr?6ngou`zyRuanq`cQ+5)v9ogQ5S&%K+-t`nG4Zk+ zg7a{)$|kl+!lLhgs=B9VKzMWW^S9sq-7hWmbe*bGr%s(Zb?Tg|k$T^?rEaSK+RYgy z82itlKSvzdv$H>ylxM{|v}R`$9<~44&5rAJ+~T=`+1a3R?bjP5``oqm9jFhv;d}U{ zwre?E?92d{^6$Ka#x){edV21&oQ50z)Qg~#0y^LW`>LP=K5Uf#TB#!-+LX={9ga&p zn)%o_(erg)bYAzIyw*YIr`Hm%;QjZ2|J8)&0G`8Pl8N3Q{vB^>RG>z8)^Le6ppikV90~>hVx|nAGe%r$2GIWSSIJ+Px*wOC?ioP`>S)GokeZltJ9yaUc2Jl*@%i;C}IV9%)>Jm95mSyX5NWmQaDd__G zfd8kI(?w}x2G*9ZZ>+7^-ng->qKfheUcafVuCAhvr)w*!`LnvFd;=ly^0M`tHt6Y1 zwPhl&rglrsdQo0cQ;w8KZ>=fk<#k)j)>WYr)!)3WrmAdf1%VtcD=%-{R#sI}uEQ0Z z>$Yyu(}JqNTUS-HzOr#^)jESVQbezMgW$2Qp>FGj>c;A_T7h3%w_UnvbLHlm?VGVW zh`g$b&6P&FVspjTin6UW@wV1iG*)ab-%zjP)@`le^eZ-R-BNMmO~fvTx0G+;Prbd0 z%^PbtT)Sb*#+ohFWt-P;;PB>cjddH=Z>^}=EMy6(f&VRKn{V7uXV9uD+uR7*5K;P^RF$s<1YmpFmdzEL zZ*ghIM&$NcPluFM#F9LP$yU!=-%Dk zGt@2j^$f&1yW2Vaii-LowHBYNz+-1@tsIWF_671a->^&{g!7T2)pAws`YV=m9=p)v zw(wvlB-qjx3FP$LucSRjstFxXzKun4D23mUh+B&;Q=Sei8 z!EQdx79 z=Vl*pCMnCw}fMTdq~=yu%l%5NR9h> zg)L#~BFX^G*f(z8m6R1%zIeNVKtP5*aur-ExAb+kwTHQZkx>GSazo_ZJ>4Ec?BCNL z3wI^e)y++BUr!4$%PSgmyTe0gvq z+ASM47Ww36ECG~Uvr2|EBGJxPGPhz*eZc%nw05yQy_mtYau{4>3l)y02soLFLu1{ z23nf0SY7Z|7mjgbKt#e~DaRP=N`z)1;SbaUUxFU!GOAE(E|bu@n{Hgo=l4LLa0}Yh z{QiRF+%cflM>Hr&DuB{Xtu<0CN%{SfRG2?30kaejX$8hwZR>*>1E`W!;MtP8qEy43 zKTOEDxc%evjeL(3Y0E%&H%S5g;@VZvxoVXb8RkCCWo5S(t)_y@@{RSryM@M5A0tje zs@zsBe$jS9J>;cGU0t0$#1nmP8t5Pwi0o`@1pAnH(zwa_Fu=p|U}qnU6!&&u8oAjL zYTG97BurF+5pRXsVTqU4H+OS0Nv?uWH|`7~Lk=r`kx|d;2L$d3t*L!tJo2qyuCxD6gfhzsp0W3V9V+DWh`5jpcGp?-q`!&q%&l@}Y_Q zd~KEM3Wb2-SYrM54J+h+CD2$`URQnP`q5}xwN63P)@nWlK1KPqa&uF;mKin zXLGDMzs)1uOSx=oS#1RXay7v-ncz#ysdQ6wUz?|#q)?DQAm_JsuGhgD2ya)8LoMxK}zG`kQ!0Kcn?mW+UKZzK?k!T*Nc6t0bM8^FJCnft;# zsF15SlvmtTEpM*bN{db1hRs_+Z+mm6@O`)|!d+}=mT*cik=i;3x)eo`rT*6b&c;r1 z8OeF-3qyOl!xXsC+$+~KuVq7(jL@)RYmHo2yJ3CB#)|bkN`p+2{Hu-8p5ER)pqY}K zPXdxjK)fiqOb9++C+-)m?-_`;@oCR}M()3@FGpM_7qnv5ak~VeCAE)I(E`a*_vix4 z^81%zE$L|+XpIS=FFYs`WOEQ6pvzr7gXDgRSi#T*&?qMhjNuo*Py!mGgn5uWN%$Bd zYd0x55rzj8>*?zc2tS$(GDJqaCDTP-w7-)te9*l7Ho$zT>>#=EMSw5#>&?Y3^>?*&_VlZf&TzDi8v<0)^K>lCc)hJ~u}>qKTbjGpk*!=S0#-6! z!mmOk&sP}%?Ie6!&wyVC1*t(#R>4y+@pra%^@!z%^UfReM0=XC@K8I|J%hBg_jWb5 zH23pe2vo(0ksP?FNC`YcnDsdLhUgHl@rr!VIIxz6R}$7u)a&Z+Yt)y4M%`9%dU~J5 z!_(Z|+R?*#;A10Xq?d6nx%_p%UeZ>nnpgE{-c^#+SYBPxh&I>v^zz7{u9|PRgkcr; zU_%5dpoeC?wCd&e5`$t4G0*tA+u1{d$(;lg8fD~5ceW4okw6e_^!G+PW3(<}Bd5KY zhVT-{Wu|(~{c#@?Yglizc~6S86}C_JpFl{CVb6f?B9I~P?}>5;xVpKuqq93K-*i(& zIhyfdyv^HV03VPrP>d(~6(2)Vcj$b7e>0z3$@#m(dmx|WJTcy7gBW`rLGsZS%YDBw z-U{qjibS%d5E2j5cjM6_c6PeBB`};lLY27X!I-SY>b|KCMoi6zC)*}t7p1#D+RVdD z*s>~KNF`LL8#{BSjC&D%&0UB;bWb~Rqsqh^=>A|#^qcGjdP2RDW!k_?k@E4K$ChYw zH$pNogoQG(E~V(oxK^%ib12BW@N40j6qNZ5-iL_*KQo`*)pHN|A?rtZ$J-e?#DPFn<2pKmP7 zk%4aPU(i-0)?nAx7i530MKHlqK`x_mFeY!>S-I#(1x%XqHRpR4uf8a%;^5yb18 zA8X|;8_LS%EnC+&Hf$){LW>_ZZ<0*i*o{l%FSf%IR3kbd*VNMXvz(7);tnX}Ff+k~F`*HxsQJ^XC5|Q4yJVYN zE}-~2rf*&>zm(<&^yxC4if`;+CZR+sG|)7_eBK*lv=;l_m#F9m&mo~OoG#75D<}`O zb)C@`;g$B3(u4Me5Sh=o9WPNq!j?SkOKn@XK`yVTtF1_IB#a%mLimwUz8%ogj35R} zOMk2l2A%gWUJ=`z*t#VvY(y1>`rh-Uc+p5pBW;9$ZDS|8O|D*tc$-{DS}^$HBLrB{ zhBE>gHVS_xWJEH{(MIo{zRvcJm<)&MIuAaI0p+q;I9wr~mGP&Bj#%X}Cy7et_>e5lNMsK>Hgixm^D2;xUsuImj$ zl@cy2taR=YztEF7x?Z*(o>EvQXBWMVGiWAJH=diAm?1kci}QxM`Te9Lboo|mG%F~H zwfE9%qrReIV?N>1|K*uSx-r_Go-ec@XNI{Rq*9t@x~ zMIu@0hdvY{^)|;kIDw7Z>(Naet zD64ApD%Y>UQd+D~xCP|O@Sc_)3KWyDYwLVmY0Cy;J=7SPsH)EHfnj+!cCoPaGSt!8 z+940Y2j&4ro7}QTzBSx6Kmj!5k+M#&Bo0n^{Hbf*T3O%xr>zT|+wpn5nIB`+mU*~U z3t0mgP;6Mi^t6Nl7i+>V(A%TtDfy?&-PJ`YDHv@+54VAf znn*<2*bHY5V@lJR#x_2q5ir(u48+=Sj!F63o4KD)ey~&)jmkC1#kfn@wu;b`uJ%?K zx`G?m!(gmYe2SN5=o+urw+dTp-LP9x>;)9uxcMe|oenOSeTok|eqM#%7-{TBAJ!Z7ljo2;P(x88rV21n+by&GB&tG4&d1J+mAU#7_9li-MQ$9H(Gv?P29eoFrZ%1LV zZH!`UXdk38p@8rb^RU@s)I+jSw?K_O6zmW7LIT}wjf1x$O_3rk;f*Z=5l#d9kB!)s zBykV)^7BBkW7*h>4X0SRk%y=}pTfyT-l#ZOMaaSPMNLVfY14=ZDuNR|Y68XjoYh(@R!Hl}sDdR}Lb$l`eDSW8$xtfXMO1Dk|s4H{;qag4y@e$Khh z2u*I9AT|140EMx!I9r0*%kt1!Qb?mqM1%T_bgYqYeP9=1M8Z;nc+!jG(}U4bk1csPCNIVnRwT5HBUrBO8K z@9oAhQFn}nlrE>_mv%~fqz9z0N#B=#XIW_RT52ramXBLLZ#iK(XPsruwXU-^TgRcH2SQqqYg#zu5kBR@ST=W;M(jp7qK9 zZhMfDGIy>d*=5{?4&FWbuw&23exJjJuMg5!!6o|xxZiQ$U$p4(lqAhAH{scv0C%8J zFP|L+d_;#)W%dM$${kjt+yQ(C;p>+J_>O%E@FBnx3GmB+&m_QS@fVu-Zk%z=!Cyqo z8F5$)`g8UHK54c$=XJpEB;bSpl!W>zsGpM1UJBZqtC{$7R{>6Fe=gcj%|bb$q#-TS zZQ`fq0Zx!-D&(2^m4xzV@SnN&nebJIV0eoi_Q83lhd-!6v}R%<)|CIN%cr_>+KtmH@v4_<{*9 z1ltR@n(|&)5BNco|AogSX;HndPiQ+m19yR`U+IN_t4w<7wSb>C>7{=K|7Jrr`CAP6 zF0MD}FWv?Cc@ux}gd|;^fPXdcuYS@jzxrvwQ)d0Ee6Bx&&r4bzR#?mf%%o0fS(Ec%we;BCY3*~*T*CC z2}#OIH|3E9d1f`4?Ps+CPLM|yXF4o(VkoMzF z;6Dfa=OpM`&d*>L_nGvahX6l;`ugPreL2q@Z@B>QCbL|w0(>W6Jxjg|@aqZiDM@lY zX!7ei2KaT8Ul+>V9S*xOe{u`()~_~G-*P(upD^W^m94%b43EY0`SUIli!v1;pG2mli$LxNRsCP$81g? zeepafN#4gDcr`7UNkjSx+-LOm@$iCwpJDF+`()hs-wy_VzEZ#=3GhBiD#G7s@^WMs zrQ$D#@LoQHKHefJt*LihWx#7Nerqn6`f(lDfH{n>KgFnDoX}n|+Pi+2*`Mp1B*|ak zNHOU73jsfF%FF)*zI8Ed@)H;V{GiS+9)V+$RMKSXOGz8PUHQC8e_cAh1yQWa2lCqB z$1aQCEZ+ovHeJx^qi+=w?oyLJebcnkm>(#wJcMsONjkkFl2ilKk7PLJ8T@aRCFv%- z*UNx!$^!hdIi5G20DQruzYXneGvtHpZQy6yGiLv{J&%8%|Deh5j$?pN>-E9Ujx&<9 z^N2}*C-h}khAIDDXn)s(2{7vKdS0(DAw3~Uw-lQE-lE}D=00F*Ns z?Zu}hX;O2fa(*?WS4q;V_>Y?$M*FWqpI#j?<^AeDz{kKGe(8SoaojH_z$XCzECGH; zlK#2C?C%eUCF#w(O#V-QMUwtC%bXv-1pMz+`gqBb^lmEdJX1dJ763kLj`zDilce|3 zN2Oq@T9^Lfc4kHqC=k@o>6d~sQ1;LEf=QkDbh zlaj@iX2Py?!09HwD+6#=0xScT6W~0+c?qy4S#o2WK%8He+Fd z<`4)QCuK}eKV6DgCtX^%zn zZQa3H<#$*PTW@E;uq?1imaEU}V;yG!C6`@Ok~=yjE#EaIrRGgZj!okJ@~J84^OWQ| zX1T1!Uo!q8fxk%L|3?z|iwXGuaImK*Bx(9Q-I_H08$ACwMci2MBbAlPl%`9TB)AKb zWW8cOoL%WEpqW?VxKf(#KLMv!MqB%dj1||=eLuK}g^ZXY2A-qag1-yihd;@6q#cti z7D}HHX)9y0wcf__nT^sS-^OeblSKY38>L0Qoy`JOkw4o;X_0@G-BK!@n9u3V zp3l=6Je_8zb_LD?o)$O@d0OBsvJ(#iC!MDS&SIVxI9J<=AAz%krv*+1PYaxD?8KYE zxt6B|P9{$aoGhEY)b_OCKif`efuF6~^Mdp1eBc6|l^g7PJNU!I7igY>W zN2E9Kc13!ljbtU-y^+%w`I~IEeXL33SJ){n_zCf};HQ$O1wU0hE$R+{K9dB_AWsXN zA)XdE!<5GV#ULHn!_xw1FHZ}c+bBIDa7K7q;EeLLz!|g8I>rtOoN=BOIQw{7;Ow{0 z8n#_4a1QXaz&Xg%0_Tw3e#F4Jou>uPVV)K^ci3m|vpp^7+{x1d=VLrAaQ@1kBH8h` z&D5{I=4pX*7f%bEkAr{fNrCeTo)$QF^R&P@LNtp7&OJOWaPH-4j)S=*6-d|E=A=C% zO;1^(<(64A>6&V+a#O@3Z9>)zIVOM`z}RLwh8wt+y&BA zjQFuR9LG40;3tphIHoM^zr&4Jcra=!8K?a$aN1AAapnWZa*M?=Ptf6QwV!% z05@Kh!f|Xmju;CQ2Ydr(0pXmnkZ#1stNrXxP}YHaE5}*Lakx#J0Y}hTq|aH=ug-EN zp=vGhjDEMvxYMPNnzl5VPUJkwIi2y=)`Pn<`=+EO(j-Z0`1p38w7vf)(*nd7l4i~4 zX^WN7`Kx12%G}he=FKmY=1Yw=wFkED`$wl#CXgTe#N7p@pM3T)!ne$q=HU;2lYT7m zI&({;Qc>p@cl}F&^tMg3$JUN!-IT*Q;~$!B>Pc(RM!flcr$y&on=k4w zTD-(+v(GkpXD07ved7I5sy~NG)|q&78oZ&Lx0*IDVZ6<;NJZbcY>p-ME#0V(m{rtY zL4U4=KU~BI9*Zftn64mx76*g$!5>JXy;-wnL4b4T&Yd@J-hu@S($mu+%B-v`e90p( zFR!4W0N;f1`FzF2#T-AFCIy{RP?b;_ziLo&2BkC*N-Rjoow>m23@&p9RcG)zXD~>= z*9Dzw(77y_T#%4EbAiVb^m>A8Ji)b|V32;-20d$n9&a$YAR%|=0)+IlrL1{U)?z6u zi+&g51*lolYy|p=1qrz`7tEWNwP0S>;(1va^Rlw&HzRA_;;eZKvXToDa%V0`PtUqK zJu4$U>)Q0JEc(4RD?KAC{pzgbf`r_e3$R6Rg9jj`rAldO^qY!}`!vZ0Uof#CA$R5i z%&-(k8ny}NInuBgra9)NIa1Rc_y?*<1qrz`7tEcTmO3}>s<~jUTY2h8{X_vz0tELZ+B>X}PmYG%A6hM~p4MUfebGf+BgL3f;z}zXNdzLBe?t-Xh6Whq9DF& zrS(po5%72`{EgPu_P5VXh>VPkH~nw>-_-H~REet}{#es=Pw4!mk@{XFh6MfvXut?*`~?B~Bi}*~C%$FK>wJ_7Ba!HN zQGPMf(lOl8)DqF0H}Z%%KIl#gG2QJ%xK!JO~s(A4lS8a*e< zr<(W`Z;vbqh7*@g|J-{Q-+I;T50^E8dVhKUh=k6cUjD{gBdOe*=H=8!y*-pS6{p(c z^{3zbbP~TrnqNA7&I+lQK7%>@=9|-o{oq9zq=kZClmi!+-v8;B4%6Vh_>!=Vl3z?0 zP1DOISg_vWthl}Mi|Lb^%FAgq1>G4wK~d9mwi1hnQ%BB>BVE2IA0+h2kyLKNK|eZ3^mX|{HH*1G_5RuI(mYHD zTrl&f41A#gI=(;)3C{JzKN8$P7`@U-pCR|Z1zW#kHl5L;Ln)Srw1dZe(?Ix z0Hc3tns$MPWKEXd8jei)CF~t#(vZi;U%;dQaeOL-0>ojVKV$Y(V@geuJ=N#aJan~} z1jMzI8$O!MxI}#_BbU2 z#MOx00ZA7fN6<7Fp{5C=e>{)Y&pPRmr{PW|X$U;k6cbk*=6r#ELhmUV=TGOGB*`xw*4G*%S0Z&vyqpH0 zW5n_G{A7G*MjT(~?>eJD{CS-gjJHIIpq5U5zH`dFgn?<;R1dgb$s5 zJZI{XYyKsdj%aWyo`a`PojP?|U#}>(IyDIs1j9}jd^1c&x(K3++<&?R1O(VLbA3YY z7|5OC)`g?+#TOQKLa#7*T69$h$6&&F1gFEgd4`$b7lFsAxnB!72kvYMkreicGRLsk zkBL%zGCSbkjv38mX-#C_o3tz)!?3T%jT)FN;#bem!wW+vboV)K#9$%O;Zy^jmq`}& z(krq5ut;O3yNyO*B=IXQZV&ae`7jpqcut0qn$O+4ccM|h=+7wOG}3ok&)n z5pfw5KJaNo|3aKb?5_(qIq**k`(bbsf_}ub$ss?AMGv_C#lwAK#SHeT%nbGMEowc| zALbnEN}@|fMEORLFJk=mx6e%w>SX~w;`@Z~zT{$w;Vj2vajK?A_C{bIkL#&u#;D#1 z>El$mm;?lUpnAeFOV~X~4&^TiRa!fGu#6sIu{zL$L6{(t4HR#V`jwVIh?p2mFs0jOgH!T)Z#Hu`Y z7F?q`Mb3I3jJR1}c16@<=%*eti}6D}ibyYsmxaurN5v#2(FeO8DOcSE0&V=GIuhCmXyhgxFR7{!(r4k^bl2C@>;Dg4;HXi44h%n8v zPP47LRFp|EMfs zY*9}iF<6n~$AvKvwm>h^TY%E?jR0;%5tNHw2=K^Lt#jA#t2%XjzdWwr;Ri463 zpFE{CoyPWEi6jXq^6F6$rgB}Sop!xea)@dMs2>!a{t1!k`3&=lN11x;@t$}ZY$rg; zm{*8KdA;OFG#-cQEnF0|ISZhvwkuH7!tz%;Fn+A+K8m_ zDGa0m(KnL#WkiA^5ImI>2VNEh{#PL&#eF#R9ixa3Cn#eS>d_Ie5#$w*6jR1Xn#h1T zM5F;url&6Jlg>xP z;bM+-Vd8u$!H8V28V*YrCZTQM7`rv}OV5#1+VZC;#=M)r(**G+NoXFwq@ctn+QCvu z?hS&EiDC4Aa`FP4kqbQFxPak=+_1&MqYT6t7wJ&1<)V1vsEo>Ajg-)WifV9$h<$BX zq6mWcLF@p}_nbsg1H}w_ygw;Lohc$9B-njT{ay5jnh(fS142yGDh7auxqg^=P5_LWmNBP6tFb-ep%TJraGKf@2N&OwsBy#J|^5WpEa zq>7&7xx^RzE()0NJWn0r^hiz;IUyrNkkiWnjKe0P&lOKf(?&E6FQ-I(T*L<+=sy(l zjf>o4h5)#)jC}BeL4H7MyC7w0+8GV@4Bh580mzD*8U0j5^fDuLSmJ)~82->p^mFVb zzr7?9L^jD~Ogf`K(H9Ow9ut@u#lVY0~V(#V>kvRLEuSzqu(#lCL$)ZaNmc~ z=dpqBG6Vol_NLlPynSmESxf+t|2p+ z0qpZs8JD1&!JRK^!f;Y__auWH1;V3zUQQp#rF^0%oFT)RGTbP`fihet;WQByqO%4s zX?`DdsWkx`&XI77czZ+~SCF@BI6+ z_7U&_*YEW*9Up%Q@WIz5^k+|5Hl4)%I_}fB&*GlKePPN{VZ-g9zdf3=JYJ0Z3EX#H ziTX4YV#@N^Gr%dpP2c98@uK#D2YQcz-eVs?ZvuFag5G1G_t=%`K}x^_y+=XsQKDy^ zJ~<%~--*}s$y(q&0(y^v-lHEtuZi$L?-9^@;>L2(0c^*=-Z zK<}8&Uz#+1QjD`vYx-m<@E!)eW1x5J1L*A|JkWa>^d9~I{`Ld!DCj*5dJkWb-XFjK z@Idb<=pDTxz29-Xhd}Qr=pDTxJ*WZbJp_6Wf!;$z&oX66!z1~kzhj%SJP3LZf!;$` zq(^`220YMv5cD3rB7f88(}4Hc6I0fba^TUl{LA$h3H(I@|CdR?D(?$P(kDN>UUBE; zisnbM_d4;{Pjf!x_NK|*n(>PNZLeO6zqBpIpVjV@KCFxPce>2{vcep3G%pet4WQ}TtpuV|lX{g5P?J_HY?)c%k}>(7VS{uKwD+R@wRDM+8UPwV7| z*uG5=zxUj|BYPH zKK`#O2np5@{)w{r^)xReI);H|NKMh|1|#N z)D^Dj^Al7Om%mjO@~6!9I1)ly~cb#5^ja%gm$yBb$~EIveQ^v#D%KD(Dq?gqN7d=`9lVi9h-ural;3 zhCAKh15CuPybT*Gq*eh=#dE2izjn&{MhnX-{5=hb%CUZIS#|92Lw zMIS)t|F)tj>D`}U9V4;Y^}bm&yyDg?fd7uXhqwn-V6*&j-c`^gXcJc?OMhRhDqcH* zR~+Egq)Hv>7yf^Sbqb&CyOJf3&2yY}iECM&>dMVi^IfhySFS79>vrXyW`Pm%n1&bw~<3=i9%~Sd1(~Nx8MFm#;gA!_S1!pjCCI)d1BHllwvwikv zjwP32D=Io9@lUm5NKfef6S)z}#Y?IPk8U%mqDbxN=?bfTu?}^pr*F54ml3Fa1Kpn1 zzMlSmHQL$2b2@r^n>~10(!j9FUs>9f*m(^~dNH8X}FiEhB+`#yY#geMmC#<_S?s@5>Nxg#?Uwj8>ZI6&^a& z+DR{ehy!Q|gajwZ1SRyFNB}@c1R&BPlH&a+iRsQB0k!nt1*E{#%Q~9znir(ew*D?t zopm(S7i&cc5-s$)K_t=NUhpeYU3hC)4cI|Rz;OUDopVYWyVgUx+nK=kg! z<&T8^5+2S_VsE)vg~;e_GKM($JDcfU(t@D`g1iFW>EWSwZX}hO8Le&LSTGzBFZ<=~ z?rx#}p%-mkx@gcHyxl`&()(%X^_u-10*>oL2dxFYT{^*7Yr8(|AT-e5;u-ER)U36i za4?+x9GS+oy;;{H=tzHz_{ET+yLcxpM1>WIUhdm3q!wxJ>y7CWY{6Sz^lZE_ayJkV zNVT*zi-ajpAwE8;7!+NYc$b`BmtOxPhzmX9TG9*Q(mOa&fERbrt7QdM@xB+4CgtJO znyGg@rH=uPNg~Xp&NJdV#39Z$m$spmqVeutEKI5s>`6i#NQB~KJv`fJ#KWt^A>L9P>gd!b3N_T# zuTND12AYX~@M+90K8wQry$R~th1ah48+cv4v4o=DwpR2GA^vc<8wqGod;$W53XmG| z#9#}JA96n08`jNTOP4;GV|e#2fAb7pxW?rHofXLa9nD@{sDtKoF~r3gkM8Zln|$fz z)u;jnT6_A!G&N8SP#4}?)yYAwJSNCXtN07$*O65e#k~oNrmI1tcvG+-PTk}+Neew~ z{cSKi;bEF@TrI_9LavA2m}C_7Q$`ow9F>%TInmK;YTFTPt3$CMxl1%d6v^w)#{A zt=>*uSDSlvb4EG5$9T6BtpJ%UU#ct+FJu zD4wxZWAiS_urc=hm{P#-0{H;*_|tRTd0Af9f^{xu;1xB%FRhUMlf|E2<+9n>U8AAJ zu3*uka<)flXUpnc-a_X0Tkr?3R-0vIC0poMHK$5|U9n%EKU8d+#SV@ui##r;-_`DN zx|}w9IXFEpS!{OpSK~6$?@2P!2gl_Cja?&KT*&&Nq#)~mjLQwS+1|x0>Sv2(7FCEY zTO|8dvQC*TIij+U%IZK7wQXf73i}~b7U@lIZqpMVRV!@{_79`VBJJTSUy05d)!@|Z zrIfV$BX%$AmThy`t%?`kT6#&fErm5J?DJOHHkW;3!~*bLCbNT9CEb^G%n{68`~{6S zA=`a;vTXWr+(4fJ`tY!iTaPq2-8rS-b-63mA2<(Is`nOZIrskDmdcLreG-DsaaRRg zF1KpCiaj>!x2Ux(yWF;U?0Jivo9*7^D|F>$?Nptv{ka&-+)ig+mdmrtHlNiii<&mx zVoPIR7?aaWed$dhx9VE~Df&xtG~lZxPSs;uz}@9EG#dC zp=pw7WGWjfJuJ;nN!ir^5({h#S-u}aO*??ppxoYo;`MBgyxCjg3EW^?#LE4HkGbxz zbXL-ky4c>(cAI4d+i79T4xri(EV2tsxYT7EtF%J2bNd*l-rlY{1Ed2fq*3ldcYrr$ zWvV|Je_tFQJOTTh#m{0gOI1{cm;Mb@Hn6$%kRMy%X9E^CS7rmUlcmywKKtcTpz;bb zi&<>x?EO(c&;u@KnLDQ>0P!qlKV^OkyXraH)$CJavdiQ01s17`pa5O|Kxv?8x%URI zZ3%mKG_=IqQDn==wJpiDWjJk1T(%6qiZEb-igEl3Q__X6|6hEvok}8xm{*s7x}gdm zA5j+F;!@oh>0e@Eq_J`tNxw+3s}%s6g6vwE{hQ?XW%)Ig%~9BJsH%!RJsxuB_}ysA zqb^{Xet$0MgIeWOowjS({&9aLCJ{@=RFZSqLWT82cCb}SgQ}9a2J2l=TnqjgkWY20 zm748ZcFLysvhuR>p+zV5%E)+Tmfut2(l9so-xhK`yr9H&aDgq8-DCB;R5tu1OF3)H zV$X~!AAxz0mw_&3<#4?k477s}n2$k#78jf2hrMySAnl)GVEM|Q0XxG?8_E%~2P8>ss(evm$$^x^uF&B@O1IRWIqw#!JrzeiS=!W_7eGd+u1u|i6=+3b^} zezuz|V9|2O`bpT#+320@0`SFg1;Fhh@9uLH#&jVU{F+?vzvf%-9Y!RBJ$0jrFySC9{H16xg_H$vtLNcQ|u`uzAuGf zEPp$uutu4=@Tq7j=ucriN@G9aLVUARTG%dBTJ0Y| zr3+&*tjlYwvx5-ix;J(&-X+P_E& zTPS0dWBD@MsedlTtos{PV?RRSqmXNg;>;r(u~;st#;o#{d9^ic>2qvHh!sAkvO35y z27CXNaX*&DFJf32`@Ti43;_Cj4!vrT3HS;Y9mc+gSv?6>+7xy}h*c`pn#a4ERVZww z!mf@$V?H-7Z)a~yA+1jot^h38n@nkkJ(?3@dm{l= ztyEz!zPDF#c>>N#XS>Sg!jvd{C5iZ4&b$@(sVjZ1%zWlP!sc3NUEzxin~McUVRN2i zLqJ9v`3fsk)DBj6w!L*#`wligQ4uZXGnYAk7)9Z3$(%C*jA22KQScVVyRrq9f6&B+)=-6!b4d|GY zeP>jL<(SQ$v10v;Xuirya&@dMMr!XWVYkRkR!Y(^LwfxIbeNlFnBx@8S-&?>3Fht_ z^`rP5t6bUM4)C7Q0|0+zm0d0lkzM``+Pa1v8Kv|T(kbjI7I8qHY*C2yo>-UJ-u{hm zwAZmYa#kJ$P=IAXRr5L9N8@b&bdTczY98fQ?<}kyEFPh-Pw~E4^-srstR?U4fleMF zBWr^jpbA%oycg))UU?}-d>L!; zvm8ZW41tKn{v?sIQ{PxSeei{Z#+iBOBTOHh8U7)bnK<4hd28dy9FKQ&6Xo#~7sH>K zax8LaENsoUY;)%f=D_*~Dl03iz7fE0C0|HbB&0g-XNQL!Fe#9V%BE*4He$odCWc7A zt;DPqt}!VFoB)T+{(VSsvClXnwmf#nutRQeHaN7Qhr8JtnT0}Zjl#<7z3h6K-B^z) z`7kQ|&JtM!*)%F5oghA8)WNas|Fe%i@n~ylAa`kngf`MT8Py-AkPZ!OyuXfH17?i`Pxd_ zxvtLf=C~_em86tJVh5g9w$+b$^r9`2m&NU%%&mg)NqowAS)}T|tkSH!TyR+`SP0qI zV0FD-A-?y@Y^$7)5y;e`TgYZvFjd*NV6MMD{vQFAkN!qXK|Vc$RL&XUAP>zdYXTL# zR~+Jnu8$yOC@FzYQoL}j4!M=;NJ&%12b`c&d>>{Nt)EL}rdN|xD_#5kURO4A*$92z%J#4+aJr4&Ji0(#bO5wz`5OuHC{0K^ikiKA1;P!q`g2(*Tai!)4m&dy~0HLabK@kvR)QL+K(eFB* zppO8Xuh^E7GX)ZGr+AvWDbgPsQ!>3BP{C_YSMSlht79Q6O-I5A;E-Tu)g2inik;m=3?V%^%985D(L@!Ktd- zwLl;rYxvh@!K)!NNxBGKnMlX(P0Yw?%flC>o_e`fr>>RfUM?cg;N%sg>|>t%OaFAqf2yG&)^j z->REqwa3 zUT?q`Wgi<4vELKbJ1vU0C?A28pS@>Mo?4cfzayZj+U6>@=qTytI^2~-d=l70_IrHU znwsPGA~YA~M9t51tz1US?kcwX2nB`zDJks;>4TN7qAbd((C%arpqrv{TUN6`jgjkY7^{q}8e_FVxuyA(C6 z_Z$ND8_ZAXGK3z}BYtEYWDdD*Nb>>zuG^H7N{~Knk-ZI&#`i|+0g=;^!cN%z)GxZv zBVc%CNC`9```cE9eZsD=-`u7+U4`uT%pYK{?^PPgGK;9U)$IORGW#VA&i%7ODtx#3 zAr^CBqK?K&T~4+-L_Y36!?XW82=*b+dUXt8tdG4ZJ;&}F^OJkJf6o!LvwyZ6xCL$B z#-86(ud;o!z4iR;vt~EDxz=*=)X8)%^%>WO973BP+=YWwuSm)K=gfE7;~zD%mN? z&%TCL0`V{VN6h&b`BN@oLBH2qMI0f-XSoX7p|EFx_X7zEgCS0pzob2-whyV*nCyNP zb6s|58Y^=gg`)@MqzwR6E_64j9hK~AIMR0_xPf)R6N^OyD3=6(@GN`4`W&3)<@8g- z-jG61Z7y_c!Ak6PHQer8-)is)E&IFCdfLkQp*6&|D>aqsp_z1M=K^}RZm9QD94zj^mdw}J~RznfWiYgDPEL>ld8Ke{l zeZ~quFvRxM2UK1z%HV?cYX``9T4r6Hl0G&8I9s%|lOFgoWV#98svI+LGB&RAT zSfL^O{5_`GGWOTZ-|htT?ug7GxeCBFfabagO>QyxJ%9GzG`6jzFy>;_4M%_Sy)d z^yd)3z9Ah6x^mpk?LfL0Dj%Ut^bz3KFkZ{pXV_6{^GhQK0Nl^~;lo*Zn-TBcH|~Fh z{jX6+>{%F>dpmci!7r{rd{fU}9(@DaRhbL0KLn#2tZ;2|!`Z}-lU4bdS7EiG3iu_5 zO18VUyDD7HZR{$)%kl7#>QcR7b~|js^r(W=v<0FbQ(S>v`?aF|UW7=Ffm-O^Dl+9y zVJqPu#}toiJ9`Jweg(E7l&Zp#8!*#jGrF^%00)wqCQ`q20R820*(3YVwB$qt~s|CIb|;J3mPD9KUXHz1N;9)jh4VU}`p zCYF;Y_sGyOr|Tyk_J&>F`S4`521Kl_2;%MD*|7Ak;i^&m2=$3*(b-9lINL|JH>FkRaX@(6qE;>wNMlHP(W*^2*`r17ykJ2_)-4+ zpAv^xVRKh`*z46?TVNKKu7Gk4BQmGUO)7L#g!bpXw7~ynG!%gGc$fR6b+ixTA^so- zq}~9+-S9J26ROJXCW5{R}PBNEca;Z zA?{y~IB;kY%q)dj@XS*Y)kA6rwk}NV8u%6#9mH4ww3pE{5{;}ci^L> zuuoe3>f^h!y(_&dvAqlL?a)~4plfNn3jeXo4|qvT)!+iOVcE@AG$`u{>>e6EXfgSg zFJisAmYp1lcv~^w$`G2sXAH6L&f@W2kbMSo`X^Ajhxk+B&(C3P{wCmWA^&bXMJR|* zLOzGJVY|$h^PPuI>=&zEr;7a-A9q#*YVbCd{bEe1^r>3@3eD}#46==6=!*RlGU+)bEX=n9LYEj$8cGqKz5B}AQd*Cti&2TH*;zwK+@_iHP zGEX7b3f@9r$mhg1V9koWmC)*HC+zMV>{V4_-c#>XcrQ4ya51|3ac7jGZJT~~e@`~J0|`~c3T3W>F?l1p3|mqR1|Riq-hU|?6) zD(qvkxksr|XNYAg>MoUS6Kji?{5f{x(fzCl3|{>t7H>b>kB!cK2(tEBvAVGfqcUO^ zq=wkzQz^~#OEDE*>p7a` zvtKfWcpRcfO3S5`6_97ev;BeQOj0sW#xi`4ub^bC@h6*+e_( zX6i7b%s;?upTmqaxoPrIxED&;S5$>Vlh2R)2L^V!Xv_Y96#;X~3Xqz0j>DLqJ|~+Oq6rMc!9UBe5#z6dBKl}u`Lg9mCBA)tRiA7T+~Qy^CXScl zx6~N+kq*$#5$z`hd^h-Vb~mV1Hib3IHkB<^klIP9d`j(-UG6MQI>5Oy4v*2hpTdrG zDflMG?bdqC-&I2}eJXn&3wSzCI2CL>42EzlpO@vcY3v8s)yQO@A5nN(uGE6gLseDy z>cMJP4ko0{i!XHeOB;MEB!Y9qNt-Hs?U4#;$VER|B3M!@543w)bwY#(`Ym z_8pqHdR18R=M@v{N7IZ)HCmQ+{VHOlNZ)N7!D+LhTy`I4L_g>L4BaPb+q<9A}}@4i^+e zX|Va&3nQe=-(||{!21;#BUOw+{cuX@bY;VV$Yy7F_M_|odta&t=TD9*Ir!QI{I0ov z+RH1?#JU9^0YwjuhXOmG1MpUD*sD`K$ouTLqGEi0W%W1YHfo@HgX;!&VQxujr59fT z3I(ubLtiO)bX>{KbGcXMe&ZVmXug!YIos#X$wP#e>%u&ES&}!CWA9?$9E()%sOqSK z0=*7rY_Ggp!>KwpIiO3QfXT-izt3Vga_LSe(T}kM1qQx~?;o@}PJp8cOXvpIjoA7} z2Rzub@zXaAdK8?6zj|9}ClH>q(GvcpQU4H5s~)0FCw$`s(R?l<92(7^V?T8^dl}0V zz9E6IWifjZr*FCJ)9~GRaSX-ZflXY@?jJ=w_4=5<3g3FUMs~xFS+X#-!cnIrq$E=)u$m*kKCD1h09qA2b3?Lw4-mM{d}99_V{g1-%fb@TDAE> z=y{sz%EcE5xJ0^Sl1rC70uv|)p1Pgru-C1Qg_QU%`@-lE9;jRZHq?5rsUM)w%iFZ9)bb^-QN30?4uCdh$PN0SB_mnk;Gg&&Mv#{r^g226d z`7s1P$*5#sWpb1P9-BR4-^Kn1hX3R!0@EV6XE+{+umjke+pC;ng?_fZK2U`2b@G!I z{=u@2u=Wseab(Lacn{VzZi}(t&7t*;S}uBw?;*Z`{fQDfOMvIKigV-*v5y>K|1{zk zn*lh#RoGMD;8SA<3W7yNLA8p+iJbs;;x-xHAijgdzKZj7wDB(p7-{>P_4(QS1MJoV zSa`>C*{y)!v0#VL&(jAg(U{5}#S9K7dPj{E)x;TNr4N?5*=er ze&#yB8vV?DfZgI}xkuQ|ewKHD?eeqy10?|%MwQd?ATeve2~8CEkiW&TdzxX zT#Y#m<)U77uz9hf9Gv;*^3Jbee>---R?ObL?MZiGRn9SWC%zZp>Y#lq`U*rkeG~2< zu#?pQoQGkWbFtCp_W<}I-0WQP8j$`G_9l$ye3y>R&8UlUz4RCE}0^N)+Tfhg}A;ZyRZQ@&MfH5C^M`(6n!zvJP z7d3#nIkA9-SdOKTU0PLwB^(FC7?fQqc4v3N^fmC%M|D*PN>*;t2C6FCu@r;1|A6_x zRw4GY3JLtq7`9?)5AOxbS*L5MYbZPS8|o{su(lJJtUsKE{ct)0&&&EzZoth>57)CN zX4m5x!PXRee72*W{c<>TBU_+scCKQFXUo;>QGAUnw}ickEpyCnY<+uNZW;i5U5p(c zKB9K`)*qz3^r~|??(M4fyNUpvv>%-vgPG0sHZ&lr{?1T68vmAq4yL|2M0ZcJJK|FHMwVNqS#`tUhb1ymtIp`eHe#iWSL0-|6Q3Kml- zs6~OwToh1fF%^YqjB}#FIVRCKWKeOAi5czgBxbN<#!k|mq?68M=6N(p$8-{Z@4F8W zyYKz(^ZUNr|J>)hJbHN7p4QrHuf6to4$#Gg-Xz?IJ1K71;6jYRupI+W6`sNgz^!sp z@(j!|q6^qPR28|&JM(f=)Q_!PJKKm`N0@~qTZ{{k?IPx`ff%Wa7b47qfE&=9e(K%c z*gF9A_A<)V@BMpR)j0;9e(JyZEvsnu762*)781fJ<6MBSLaQ)Km`)(Kb+u$iPR9f$ z8ketztN#JX{W0j>l8Sq`N!V+O4#!e5e0t2-$XG;k^bX)%H6(gTmE?va4Cg-mAFxmF zul^%uaKyaD_6x_kNR1CT7wPT_3Gv)VQ5@Ag{lp|U!n<~g|*Y)R&--#aTr@- zaq0srFnJ7CUsP8j;>WADBWMgKJ6|Do5|*ncZ{0997Ms^xn&}zTl@!Z`OUxv!#a_nY z!6f=&9BPolE%8a1{uoTD<7}xB;nCw_seK&a8B=y-N6x_>@S~_4x0rd@^Pg@pPg1|h zE$07vgLx9hX3fa)V79y|1%jn;j`s*8_Eukq8LrrB4px7m#^tmo^xOK=?JuW#y;+wGk;JNWfS7Q}- zT$408d2(uUSt)qmcU2M=S133fyN-rtgq*>SOCn7H14mfY4A?@PdTAxMBrscmZ46K1 zVcwYT7>>Z>iZMrV7&P(W>e1rB4yVQ%`F1XGCtxs|o;q%F3<|=iKO40xOG0>Nj!MI( z9wnMO!m2(a%P_Ot*@^`W1aDNIR>{e5=vX?z&(|bjMe=*O_@B}|sD4Z(WAgYYl8jQH zg)<(ZeiGhw6pBm&#uXjlM`Xif5NFT}M(_#_=J2|1IJr@nHZm0$V9}?@G+D@GSgpP! z$?8B^h4+DFjgJzzQN7<=hQ(eG3#i-RQ3Y1Fa2ES}RZjG{#ouZSGS zMGjyk$2rVyFu7GSqze|2LF$iuWtB{(8A?cqdYevGhYd)QsRSC-`&0wTrYIpXYLgOx z*Fu#qkL3Qx7d?}blf=JfXLn*IU(IZ`+mr3>ZB5Q*ywHkQeVj{{I5X3)c%N0q9m%^@ zGS>?H|4%>v6cB~@sDBFir?mes2w2#E%0{nN@6pKr!b^~- z*?+%s*egL{ko~{>nebcP9{TsyP5L23{i&CXY7A86x5i?{#DB&R{P%uXg0NsT%i(`x z1^#|Uz0*e)viqDe&)D&_sgf{8Khy)rMhIU=K?G0{;ZVU!3` z3IO%5WgsXLHvz$GppoTU|9z^HE=lUO{xW$`l7VLo&Wiv4{9_TS`2X@4Y@)xiiRAnL z??#0G?1lb@C5?$4_2Nzb!58=c%h&#|c-?;>eR6}d+x?#v{oA(!{$nOd8L#mCry&dU zpcDfMDB1sW;(rSJ%MH z@<;}vjW1y%nWqh}&^Ic$+0l)+c!9m}x;MT=poF&IMRUB&sRTRQ+-->%d+|X6zAh?W z8t&lxq$6uE<4q0aJXxG8?_X(1N&9dz zE|x_^MdQUqRi>=|i2K4xAE;xv@~&AGy()TERCuf^YGh(^%fwhqq_{_L|H{hbh2Qb^ zKQ^Y1$*L3?ce*O^GEj{1!~kkVUf6gWifB+%zf3Lm<`@sFH)*8dpvtoYXaV3l~8t;7e zII$mqmwU1E^GEE5y}WYm^Z}!r77?vpr2Q6`q`TE)E5)iBD*nVcqN4@XD>6ZUzzN&5r#`)IuIxeD<; ztbQ*~X1bJ(Pn$`xUT#7?;CYo6Wyse+gfXqz_->@sr`2Zj+mJu%mb6O(^+~!G=K$33 zb0X#swAuKwm>f(gUi0gzUm|4(1D=*p%!wPa#{yFnIT&R{;QLbDBTWKRTfwW81}=z2i(NTXLN8#!JwveYiy>GWFa%5P&!K{t)^bUKTFvxOl=O|R(J2v0y%LI>@~eVX zk`k|qN8nbK2(&T5)^-KUz=wMktOCA$fr8bNzbIH$=;s(LxsTO-k&ka!EcB&n(Ye8v zniFhYD-2S`1(U7k4h55K$0G_BY?<+_pJT9OvQ-uGfzK6brlU8h z-qtmANJI)-ZGwUYTZF1ZP~`X|5h&P>U#VcS&D^43vQ7O)!GbL_X8Jh>OBQU;lI`1M zI}WinT|=)#q_Dm2dIbx%jNhVbSfa$+Bwa(x03_2*KZv9@GQFl-Pk z$%lrm@*zr8^KgSGVO>^FqyXAuVBHH*$imcfpP`Y z6J+`fnZkHAxjH){ffT0w^As$YGJdJf4yKF;Q#+UnNTw@3Rxp|NrYcx4Wwsmr9E0VO zsm8!ZE}0qt?$gzSDUianW2=G%Q^tR;Lzfj{U|J8ROll+3J&!7wOmFlkSTIEjFJC{$ zV7Y?njbwTsyXw03`01mOqFvYMmZpcGv|dT)031W8LI+mGYxulfi>ErokIyZ7JTV2ovXVe;io6b*%(~x@O$Ru!AkP)rybp{cgCyh!&0na&S98y|sixHB7 zCBpq1jG`coZb?JEWMo07{a8@k7QJ!2Bzc!3Q9_|{0yD5HCzKiKl||;*eMWd1$)-Vg zx33XCMzVS7oL!xgaT2jN!ZqQ>1Y#c@J{Be!6N$CD4rjY$Od{4HP1#Z0Lq?gtzz{Tr z*blgGhcT6D@S#8{^_$A2GNOBgw-TSPJ(>9DnQkj2<5uVli1GwIfGGhr~xnFnc zWXV_txR%O_deCaj#8)RzqBv-M3UUc$HH8?nh^gse!;Mpc`=~6(1IB5@TAjP2TQX)7 zv%=apj5)xkDb@j#aXN4>y-P^D(a7cw)h%``lZ+;YM4AOFYv! zlWE2SN2`r_6fF+eyWW@&{9ppG&m!Y2q&b}qqw;U1@A3rl6~a8y6E((7bHp5@H&1$9|)Wm_lnGGPV&@=o`N@ zwi8q60FSYQ*p~uj-r{d`;}2&{(KR-pk-Mol3N)GS(O$-l6oMH} zpD|v?a8`5LXU0B;dnp}%6T zp8+8sH{JlESAG!0lw-!5kSa`m7(~rx<8Bf2>!3OLhQS4*Z#}>O9U8+oVZh!{hsw&4 z#sdgC4Q}X02a#1&diet5A!63SkYMa5W)rrqGae>p6Pg2zM}S55y3yZw6u6i5S^v24 z7%_c||7hcJ;(@Mqg4iDeid!LWr8>M4=7{$=S}GhuLJJcV#)xvH2@csm@*k|2j2L(iB8ex0M_g`Wf3<4 zkABhwrzqDp1Mh#!M5kzL2flH-NjSw0;8}k%(Gl9Zfmg?y;0Ps~2RPMc5{|G3__{Am zxeV_Gp8TsxIKpMXqh_1v2yM%Oi&Z8#LdkX&usO&?M|g4tu&v1iN9c2MHE`k0rUInt zT@T#cYAPhY7Wmc=Ok!}^2t4~8Q!&G@1D?`mDq)$MfVb9}EX13E8?Q0VCf)*keY{DG zHCus?dYeiaz74o+nW>C;JMhgNrn$sBfcsuC%_F`ZIJmqfdyK zZ`wi0qkuaun&_EqT!M65Hti&y1U&s`(+#MR82b9onr=egr_vFgS7f>w_%-&3z9&rk zfIq1plH@5NiD8I-P0)U%eV%1fLH{QCB|$${12%?ehMspL*QptrhyaBA z6)8u1MIZ#ZM9PPOJ&}f79}Eo3bPbJ7Qmz&viz*&oovWkx^wC>~=lZfpjyXBgav_3# z8U1hH^SS;^uLmCfwu0#;Ef;gaQ0ff=K3R{WS7!dMh(ej+FrzE%Gg3YZa*Wn5>> zrE3*~2n2~Grhc6-=fce@bF?;BF5ImCdp*^lzY#-#{vv$8eim!e zVJZnoGkJ7eehLB;kmmH6{8YgVc;3tTX~gVu-QVX=hI=h$6ZfsmPe-_zwMNg$=K#>h zrrD{@=Kx^iKy~6z`Ec}-Z5;3cQ$G3ja?q-KJs*yKRI!2D47>+|>>Ha$<~giF;5`s$ z&kKfGsPKrtAbHK^S?FO(W1aBKVr%!(vN})B8b!=bqWxqRnp~Njwb^H}&Bf$w`1)CB zEM+Ee-Q-zlE~P=I|83S-Vp`&ybF-kdp6Rr{)Q@M0u{(n0@0^9PyJxn6s#+V9hXG^6 zTa<9bOi1YeOq>}Kj;uz?n$2cPD3&CtADbzmm?p0DHABL%i<~C*?Jx@o1AvR8&6H4Z zkM1^8!aj1J`=Xf=o~9zZ+s%~FW&oaZ&I}2|?~0@(Gv3TA0N)lN$@>VH?48Fki?(vh zYk3^9dLf_h{SgJ|ctKNc<5LQCv=RcLDpOa5?#}7trFww72HN0+gUk zd;7Z!*zd%=>ZZ;DFu_!pGU*FY{q*IWC9dcyK>e+^P@5fX1)~0(<@A1BAXQhGww)+o{l#pi@7e;^-xkigl~m=GLgswdZRC0c^gWkXfq-%b1U184g36WczKg_l zNO9mXB?VyWsk|-}MJHG_atQ7W&2tZg?(A0}1efZN{~k!~eO65~3_6HhW#{s`8O#Fi z$lHiiRBFZeyq&PHp8&_+nD;0``vKK|$$Jb|a0xJAeBR@n=mQ>mAnzO!*Z>VL=e@+V zU>4L2r!;mP`2_0`CE4>XGK6q}0-^7vOEhYzE4UQeYICWft>9M3hhLe{P;etmLp*}& zgsThAq*8*du+iH$s`HtQJFq9U2(XP+qap(V_==M>=}kYiyct2~4OkJqt(LbiT8hLM z-zBw-u{QX;CeqQ?I7ny(i=aBKHXk|){t_aM`bWO#di0rNp38@%dTbQ?Yx5!cC?7v= zCFHY0r(t!$&v7)ge-e@pViYHpSG}GO6NIk>_HpIoIU zF8E75i&$vU=EIGR+JNZz`uuoCvxtnI{7J-gMLDtg3B(#*M}4D|pGfRYYnuOE{$dbp zjJo_Gc-2e!OWVRp#7Y>FfF8im44q>UL^WA`@Qy!BKB#qlJ#CwB)l&5G2dAv`ZV=n@GGKEv(fL(Z!dx$3yBqL zE)HfP87SBLY%=wuOA9K3rG~6T!mvk+3{;#XlwQQ;k(eWO@5h&@U`4c+Rgpzv4Cllm zGqWfLY5MfoC@O+sggk)2f>lMd3*q&mXBH(AYoJB9RFp)_LYmGOB@>J7ug*_a7fnFs z?{rO0B#J|;SlB{2TZ>?W!@tT^GQ$Xme^rO@l_!c)n0z&-h9N7_E!2?C`z&jde1oAV z9U&HlNyeZcckeFB6oMce0!|qe1OjFWK@=WSnN?9!A7GVGlbVy`(r;y{Cka)E!~#JBBO5td0~KFnpfr)VbATY=XeEXo6Z zuo8H~{Y7vlq28?F{HuyE>V=NFjWuM0jrmYWGIogmLC_-y=}>P$4;!LK3EDJ7j~8?; zRdjW2VNoGUzZHzalZ%Q5JA`9)Q89zrA?$5MCBXd&N|RWCPo(JVu12Y7Ht^|mT}NA& zR5XXG%R+iIRVi@}@HS^r866udTa{ik7vcT+qGN?*&~=Vci)R&|ArC;Hy6+6dz+(%M z;rhU0cwS{lKh#@{9;g`1r_U6l?^m!0{s8K3m-#kr=H@Hef-=u%4 zN-q(8Gf-#mLUJ+R7@@N_Hb^DlHTF5ttQc;jv2TiIiy#kc{E`xI3`;`+8)Hh?H$@jK zo>~IySA<%7yo7yIOd67`5ken~wFoaR0XLmz2Za|EJ7N|#Ngv0Q1OKoLdC1xp^h8vK3$Vl$7S4ujIx*H* z;4Q;0`VJcRIJFSai(0x~tG7V?<7j+fC|u(JL!o}orw@E(f%<(OR4Ii){VWWbZ*9?9 z(7@xkbJDlc0$(kB@s=R6|E5r^bx1q@a7|AyeFEmQ-e9HT=UYX~e7s z7)~ap-m>1dqyzVHcW!x+g>Fx5p6(rE5pGYbt9RQa3*DX=HEhpW==Q`Ynp9_j+mrhI z$vFSn7z$^Vn12KrgBd*7Q0?-W)eGT$&s*TZ!XKgO zZ-2^S27W;gAKN2Y3V<&d1{*K@5m9Tgp+S=me?ib zhgDp#R6@MFsEwLN%K~Pgy2oy^EM%c7Sb4_Im# z&H>vr+fvJL4%n$0OC50_@VLX4dZZBx^O94R28NH)b#=HTi=E+PBsB(=VHOu;yF@=4 zaT$GD>W7;dNzc-U2RbnNXW-FYMdf;8YbKr6!3pR2NZ+M03F}woaw4TT$!F!c7 zpsvUQC?qlj53#X;?#|?qNl;eaXW}n)^|JQIe?`El7gI#v69K;g-inlz80@dQK70)=18}rQ%X@m z<>42k$R&<85W;n74A?2XJ4Hp`rL<8L+Ahi_^c2iCN{dZV!J9>yQEq^FEJr}4%CCao z$UlyiF;d`?2i5cvnyWk`vJ{GsPC`@EY%WF1DNgi+rxZ=6c#7!mQZyZkK^lW!DVt7g zC!~H{il$Tg&%E=cVg%JwWzJym5WDC(L4(}>O&p<}(uP-OJf!O&Wv2rmgf zJUU;DmB*ijA`Y&bORMe|)qWBIok!+UpGv?v1k9U!MZhBnSkp829;8ro_b>t$48J1a zAt*CUHJ5j429i8TQG3DmT_M6{2~DI5nFqy1{~5Uhz6dHFVt9rD3+Df2DD%D0MfXp7 zP8MQv@i6$MQESSiygQ9r6CNw2C5>9cG)Bz~X;52C0QA*VlScMjhws~$1_8wKet2yf zJ9a;8PXCX{7E$@T{54j{6tf#;PMu^$TgH3{*uLM2ri?A2pT2Il-ikR&%sUX|I*S## z5e|Ig8&=32xD6{vyHm141Nvojou|)OVYJFfwS0yZHpr7YXeMSiyJyU9l$raPpB45L zYo^4@SQ>KS2?NtPIwUJ=E9|TAYAb6iHdwl*TUlE%H2NB?v=K2^YJbK`8^Kv3nS3so ze2$dMz6!IVnPVT;;V&~uR(PuMnPg>u$BLOnYzbY@r0=bqS%_uL5sMYBWc)F%jqp-4 zW)>6TIN>|kX~o1&>gQ$?WDr|j+-!nuqC1VDmS(DBtgy22nYwn!k9op`#pKnn+nNa6 zNnX%z5(NB^O4@jrHJQpIuPt9&Qz!#@L7r4%@^U(@X~g7ZHCQJTbDiQ`YfUFM2zM9D z{bm0co%I-HM|A35>v2Sjv2@jU))T~>ag=;*y#rWGYhtdlo?+gv<>Q4C9`UhgN@BG#JATil*SYdsLnC!itw?0fv_WdWVXNd>c-wE~^tMpb(f+j3R zwA*2w3b={vTi&uxBWBSt7Hc*!6~1+&6`pRw?S4XO6Ow2pv2$st{Y=7!&%|S344JSL zRx#oBe+}IM#=A4M))k2S8im$fuwG5M$avBn)|JFm^`iOKRlq{k*-Ndfi78O|wbnJn z-n7&SM^IW(=LqW-%o2|y7Fyhj*g-9BBW7uFsn#9LMJ-M*vR=<{mKML>x|5iiTR6db z12Hw1^O^NVVrnk?N$X9(qMxjqW8Fo}d5rNI>uzG&Us06xW~S#n#`Lju4>A3-DcZW1 zn09GBVBJR?NLwHAx{viS$aNVJ5c+XO3^e^YVhTO;_tqzfDKsqUJTaSo@m%YZz(O6( z9I+?$223JWSnZ=FataO_+;daF`sVthGzt5Rt7+H$muqKUcZ%SC%p6FY{Lqqi!( zc*oo2VZh4Woc2HGm&0LAd<}`htIK1Uh?4GGTn>MwIMF4&ga{# z91}#hjQDH$L}GT!ElbPeiPv$|%bSSV zMAd&TZziUU9e0$s5Qpd*JWW!$lf_fUZI{biiBksUh+iY*5^JNQ<+N|#E_Zyg1k2+z)1XroL*HN2+ zIE0M1oXD}Eu_k?hMB&vowAEnyW492P490$BOC+XlArM^jqz_o7m|-@!Xr<6`J8UV$ zZ1cPrn{d(8XJV!eE_#f`0DRHcUtpN|0eyrER9j%u?6A zWw4bX;tV1VmfI{M0$69X%_e5G7aDAHhzCk7C1$k?Pua?dsn>1S*ya+`q*m;*%_F7? zY!=&mVzJ+1DmU2bpbA-M@9vdsu-{1^unKh^O?514$LZ z#B`&30xIAjrCz#G)t@WSp%mY5aaM>PCERG`27M)RB&|cD9o3c0AS6nRs$>Qs(T<`@ zW)KoJ6jZVcDiXDY=quqDlO9nr3%AIooOV;CaEq)?&$&wB7O9KbMU}!Wit1byxV_Sh zRn5zY=-W|QFv!{9S6Mj7xhbi#XpnQpxXNO|8R;kOs)W5NMmKF@r7&0;-CEyDVWc!V z{a-4Dk+R?IYOfSVY5+DyR|+GI0UkN8QW$9*aNe*=VWbJbos%l9ET4UI=`EEu;&k9q z$(0qvS->k_sH`N;0Uo`rashEJuxfYZLgIX2eOzS~aUpS9Wi_z{IO)gA8sakG_|GeA zsRrwyO(%aKtj(Vr(Sg6yOADZaWR9Ipg$tm8_@_}82GxuD1#Oa)LiQ?Y0c=`nxMXR8 zFly?)IE=r{Y9aB|Bti_Jjh(HWQIK}nM21f5C*LgvYbSUP9cjpy-TS_ zqZaL7D8tvLbOPIK3*~2+72tL2NS4nQKajO33K-)8XKTrqVQbg^vWL{`ilnO z+LkKH&>y4g#%1IxOeRwAj8jTp2YIxss$eKWp6)jd)o9@~osg#*%2VW76&-3cfOJz%gPZ-nfaDMq}4G z7P~cRQmPapah)_0J5fQn7nv*tN{Q$Y39xlFUVQPwjMzugN;crXtLVv6x|AVJld`28X}V;TOj52i125|2N%>NRRC!^FWPWGXg?SeW zE)-puf1&ik+zYcWlw2sgP$b< zv^DP_a#A3RLtA16c%kMqCKqjW8*ISTrmd0dd9%QPNzcI=xk2!Y?3HR{4!kxwa@inM zAqhm58<~9Q_HufkXjn0(-eStCMSG{8hwS0W+(S_gUGI=BS-0{5;wNY4~G12VAT67r26>ZsE3(1uMC~`@yn0~YKCpv05&WMfeify%UL(1;z z&HCCnVy;RS*=u2}2BWyXY{?#8n*;_9M06+BCbLlXhLSC{Da3S?n>N>`5|cqpW^Eb^ z^27TKbtood2hVou;u*$#bI#S#x^SA&UEeI#!3Z!3<%Y_d4Rwj+qYbMAlZ;D98@{-X zJVd@_f2ku6(d>s)>jV!D(__D`o6K;v&`e!Acl$Kre5fvim7tePd$ul+CG>S!WlchS&48@E9qGM(_{4!?*E4=HbGYwaF zjXUa$%qp(mL0T!ZMYL`p%RlvSoe3c$wd%SV_I#Wz`Btf}h-IjhYGYtSwOPjE$LdOu?NDQ&TY zu`T|m#CYKawo?c7zKO7bEVsC+od^>cRm{S?x)Rai%Es)`5sA6PI$B;9T0Lu>FbysJ zO8xLeG*y;cl$eQtwywncm|6s+gGHg2U+B#k8)l-|J>Q4!VI)~--w54HOf9s^q5Fv0 z8T3a&_Y>1XWA6>Ug_w03{&wiC#N4|$7#n&UG50R|%0mwjbML}?P3S>lcH+vU&_l%B zPrl~o(0*cC`o8+m!^FdQ!qFe84VCL4U8{k2XF}-_p-vFBEuq3CV$G0+sYk!R6aEvvi-VY%!fpc75J)X*0cjw7^ ze_~2{`b<3xm~$wUI~5g}`nK4bwma)F4Ve1U2uNeE$1FhHuiR_QiiarEjK~?D9G@)A zR&1!or$DS_G~4d|@xqzWY-5+j3rCY83@Lsxiot3WqLog{YCzjh+aL;RK-K=gfOZHfZX`MEaL zjv!$@;BIF^4SLiB&qHzJN(bIrvU>F+Tk^_1N@qC z)?%*$v{K0v8nW#0$vN|Myi8%ACdvZ;jWKrNlWF~pC+zUaiuKEP+Ub*p^~-;-qak4Z zqUG$l#I*ilPP=FbTEFfqyJ!en|Js@Me56r^um|n4h&gmLoww8fiV3)_)lUE0I|AW* z+;;lkKE42#y-e(WsJgT4?GX0}qQjHz9fLk`LYuvl!HRL&yO@nOapN(&o5j&5#xApW z1KZLRaXrM7#T+vGAT&{XHmecCbIuQ<=tc~ygXY$VfpyT_8Yc}F9lNZN1M7gfH6{|L z(&en%(U^jv;-u(f-=XAjVIhqf*yy|qCA)nZF%&8uCT>Dw7BO|)GQAPapy+tvlt$4G z^e~C7jiMcBWciLp(GJvc=7>ho4%Bht?TzRhiic_KZe*JX9fv&Km_7uQ@JOx228RsuF$Nphat^r~ zaSkc6!7e%E8ivb}uJ%R{wT$pVs<8PExehV0%5H^&P}r)Muw5`VD)+y<=<+ssr8qdl zGj5M;>_9P%kmw~TvIU=0bI467GrPSs28X;D#JU8;%vWh9*D;g24AkaV9P)ZW@rYz$vqQc{P?ewpesIXwf=WVRQADB0Zz0Zmzh%MjvQ!$meiqel!2zS}n<-M=W;8nEW8UN=^FsqYn8=LCapG4{dVDPbu-#4$kuJH$ljA;c78iesZhx|4bsR5z7-63CK4ExF2?GE`J66_~O9(2g>l3+i% zew9Ohj|BTk;CBxB0}|{f*S+YFKV)fPAm-#ap{^J5Y*AX@qz@+TzXK%^XX z$e)s6Pd|a0e@-F=glCvT{(=pf4#EIFUos{O#Dr@d@>e8sn9Ssmzb26jVkKnzhD1Jy zJJ2fMk|+cb7U+;KlCXdX4RFZckthREu+t&`K*9<_j~?}RGOYx$=6;9#BV($VXSGAV zM4}GFsLc-fClZYyB2n#skZ1vs`Kv?znZyzh+f)wu7ZM#H9P=FVuOzzJCTnWS94ffz z{CGqy9qmx5CAwe`^<54X%oYwvagqG~1wM>{nA2w*DsK{MSi#I+9sJS;T%1PIfIgY! zP-z7{QbT&X-J#M6TI=H-$xBiWl`k`EBO7s+?NALPp)=t7mM969C^>vVz`b#TEIEdu zjMR@ED$XDiGtwS{%nGPZfLz4>Av!FU%AeOa;@ap*CTKiklF+l$yY=7 zHGgS>zYl*QTFi_`aNIxqHHlBhjTFS^;kbVq$19$ZVuR!G$EbP2C)>v~Vb@_Mf={g+ z(+op>h0{v^hA}NLri+_7J*&Mp414_2tX+tx+1$)V5liOIlg(@pu^`F3*o^k@Imzk5 zoO8`+j#;}n-HQ3N8Bb;3v15HR8>2T=8p&)(qWC{?xjx|8kY)s%%M>PP1!aQU_k43O zGbyW^=266)Z>;n*k0$0kb^G1TA;es{(}P7OvAZHaZ7U; zF(=AJJDbN5bFO##Of!@u*@A!%KZrlK2F&aDsE~naMo}AE-Y_&nuLYdtK^th60YP^( z$1(#ZqL|z^k0<6NX<1G41ZEbKq>kn|hEwR&kDDhFbLn-Ru{j>Nj}-`gp?MP1Q_xx8 zHnYKnp!R2*6PccZR=?Yv#Bg5giCf&9%szA)j=pNygl>}Zj|xjuLnyd>=SeXfG`9^ z#QVUPDff>KUqCZ-j`5KZAoVB0-s^m163j0jegh%)hkazYw1JRUk$&b09~qrX>d(;n z$Y_efrJ3v;J~C2EeZY}F`p9SsxfVD)*@r7S+%be$Q)h+w$Y|8Uvj!TLkIY8x=O#;G z5xquNuaC?I>h}XtYxa@RLP6zv5L<_fQ8Hj-kOVHKvp#YLW?v5rDPKa#sh6}q9Ha{` zAu&o;u?_p_Eg*~vX|a%F4=a2T)~!QF@;*CKnlf{iP4ZDqVK(Z^$d!2S2_ID!GmDU3 zgp`&0sHP5ubR%TPOIL<;z{I1@`>2Jb2#H=m?^Kn@K~A)K(f7k?08TdgfB`t!=%Vw^ z=yamdiQTkta8(qm3~3-QY0K0l}M7UK}U zV7n6?6K|#gSDT&m7PbiB_;;N&Eb(TZYJ`*C!WN0}q$Fn|aTKuYq*Hi^XyB8lo%9gm zgB_+U{P7UrScI#-aneQDsMU}QPPz!&1mL)5oHQ>Rz1{X7oU|_6MBrNC-3x10}u z<%C@+Z#l0Ia?*apx;H7yIgOa>-lUmMjHFU;I&klLCk9Wcmj}?Q;Z7s4EekmRYp02L zDzK~HnM*tk_~dct4B~8HQ>t?&u{h5A)R{*-9pNFbIrE9R;S+bxIg8i?y!|VunK&2t zmiwIr#4~^^#yAUs`#A8ya*Ajg=0VG`DDQtiG(?vQOPWA88GI?V78(1qoNZD_D`o_i zle!M66&13ai8s{f>@0VqLmjzU(^?GtDLP2$iq;aG0!##4f27p{m`)?V{_eo_tq^WD z8)#fkYaQTj%2czewI29rKJX3mS{s1RtRDrxJ+{>j{3Ot+v zk0s-a9^kj1P$T%=LMUEGNp1;hJ%Hr1b#184K_zvYTWUR|q;BkTO0AFq$#rcmsr4|S zpRNn=2%(-T*3PJiYdwxq=;<^QT2By4Q`#eZ#PCO2?*TD8;71T>?R)XG>wlaI zn`^xfg)OYmB4YN3tq)ML3Ihn2_W%(ysN7O-p)4%E;Uj5NrK6RARYL)ZLcJ>S6t6|i zehtZ{3tAju%|-_KP`Pw%pk)wW={$ zD|HVFbwcFxVLJN*t?FpR?S=8FtU@6p0eJ=0CNU8L% z*&i;(5WyB}=;)9ZV~AjrA$nZCW-&(SGJ1(ouPshSgxFg5-oH47SVs7M$710LISL%T zuvmCPwdfONI1rV(A4Qjt5|;R&m?ji(u%G+4)+&zn8?ld~#+mxvOOO{n3cbErNj)2> z_aH^>7ff9zF?HQY?)KJ=7jJ5$RQj29Nc0|Z&a5+|lPi)PddWO&P_mA6vmY@f!<*NF z2j|!+EoP`hIxP+sd!Ohw!y(M4qs8mrvk@VNU%bvOFm;7jzKI8>o(ksF6R(9M9Oo&( z8$}wQ2kDoV8F?iDCuN!E z5+?%h*<^<2ka{^>XV}c}9LnHus?BU=8V(Kz6V2ts8NjIr%{F2V6iGA96~t431D`b0 zkBI9f3mz~pAm)IuA<(>#I2U;8T=OF0eBika<|^VsVCNsr)x;KHv%y?LTn1e4G}Ev5 zS%Eh{ZLR~hRRUXs%{(-W5;q_`<&wFTxDj~RB=ch8Cg8nk<|V+k7U1$R zW*0FhP#HnyHsV&`(Pz!=#OyRVOUxa_G|42Jxs%uhJnM0D7jYY~D$(pFZU=5UZ|(-} z>tKHwl^tVV3S&Bk2pH2cMzG_-m;}}U!xnrf zy#5*UPS_H@;{+ENREN?}2^T23^5lt{f^i6X8wpRJDF{a<;jQp>ga~4KE6t(;129h0 zp|w4~gcQWUELI@mn5iI^#j&~UeFdCKh*QBs<^p(EW$o2!E8wJ3EJtrmFTjjO(PrGG zf_P$TGjC48Bx;a8q3h)W47~mkoSrY=Q;^6sti{d+1xdugz#INi0I#NeCS~DW1u4X% zDcs&+V++zD97jtCmoX^Z(nSTCOhomS*A+}5_5wasQo!|ya#20KU@9>ehGk_17>JZZ zsZ6f|I9cVz)m{4wFauM*y|PX&z$A>fnh@Qj6+YO7>6a}NvMo2z2j8)RKG^SB`e5B= zp14(R)8Kh+AWz(yF7U*yEJ%E5uK4E=mj#)*=dp5=i*8P=7v`LEl@ik*SH0;fV-nUP zHq}KpCyb!o$3-_MjKE&wf}6ALq7lSD>7tv%F$bquw*9>BKjq6X7yO9rb;O7NlpK)n9?jArggzdRKy@NgmhhznSMcJMxpJ*6f$Y1tAp4Z z_?q1=_=SoXWwRS@wqo*-)h`XyxZn^f8j%k9d#)%KoW)Dh8bctR{f! z)1to)H7)w9 zBHfmITsIK=Nm<=aN$c8$atF`INc)wi742np zw@Vt=ZHRkEsm}psVTXq09VDjZd5v-%Vv-@{SAIRD{A-W+y8eO%W2Cru<9cZ@|KYi= zmx09_#Yg75ULh7&TcdyWb-jiR^OOvKyCTEugBjvJbG^Nr8ohie4e#G@HRCA4cqtzc+9+Jl zEQIAOiWthaV5Q2%(-<+PkoBv`CRpG3i;KrFiwcImtG38Cl&#=faDz!KS~@R< z60w(1M&)}h9;GN1HH5i%l(Oj3P`{|s4rN>X7lVt30aX>qHg2&?r60_OGE{*i$Qs>D zH3CGhHnO9sUUI2MlAzt7Vq7VW`4BhWg3?iL)jrtp>WuUlq!3f2&9?Ljn4K!j$dLqN=)54FYrx5GKhJHhODkTy-X%Av7KGB)J3}a9e;OfBis3JXb$y4?Hx9YPMildhq2S3=H!iT#eCHq^Je3}4A?3x?P2L_P$cY8!>nsnO_u zt77${fO|>w#RdxEF652yH?+@3s;5!owKLnTC|G=uYWcnG<;2uV|Cj9;HkA3%xQg}) zV6kPEpWR+bJW5okeF0y55S~8Gxw*XxU8fY8Z`{>h&CGNo?#t~p#8mr?iS4z-WU%OB zdp$ALp5<(BAm&h#c5SXi z?Ont%;to!`o70^*gj@65yAf_vF3z=kI4_$jJau~y!)M@)A-B{nnr)V;s`8W_h#)&;U% zOL>&bt?e6#xh|X&(Y}#cQ^drmHYOXHe@4MlLI$L&+mMVsfecRII=|xtZuxRf;Knp? z0vEiS6S!&nIDw1X%L!cANgq5Dw`=jd{eTY7{s(;V%{Vh z1>iZQN{^@U=RiDH+eYBIWWq>1uO1!5=eA%x(@IC-S@im7JT-3`@T~bqB%aRCqVPO6 zDjLtQlo&i+kH+HZGkiRrMej}EjMQUSDs&r`nym;%=f-o^UREfejuq;Bg%#TUB`ehR z6DyQc%?fSa!V2a4u|h|`V}-W(u|l^bvqG^YtkB#YtdR9jtkBx4S)shY zvqFi(SfMqOSfNcuR_G=#R>ud9>0i{9{pSlH^*FSWkUwWg!*%6Q`d$J3<>q;q^XXcZYcvJLgG?cg6G&< znDI86wolfBFfGftAc&x;cDI!Aj=&*^*mzgQyRd?7vbf5d2=lIgN!Y8ntGrsH%J=|5 zm%u14F9Q<_WtCLhlJOC-cn55GZD9sRl!nK}ivt-LPm~u2;+AJ%^iW(uW@g4$#O%GD zJ2So}X3tFfA>$hs6b8Igo$)Q%a~poeZ5bDdBY;;$X8ge7WB6)v#@_*-iqmy;Nf|!^ zKA(WEMd2ng;L9oa{<4(u6X5IV$miFX@eA-fS-=xVW&8^KQ4VmZIpZ>Mt^r!l%#gvq z;S1#(LGiD%pG^{PE=>BKIH5#5)A&pbn2;CnHk-1MQGlfiQGX{LVz_8<>vF-YNnK#e}2ht2B@1w9$i zU)wnrFadDBy)z66qEPUHbiYm%(b%M0V#kY4NPyktB^^>{0-;9N(I9mu5{j<`EXe3g zLgFlB-28yPGZXkGwCRFromnh{&Q$e&=TrtOuSz$L2D{B?I&%=jdK}9M>4HFwKO<$$ z<}L~(2Dh8O?t(N}*a6ebaq zjK-e-q{Yrk+cPRffkspHeKi>s^sO&n-$?t*!lwF5A-{_jotl|?! zL3MzC94goUW_{O8g#4hCo5!-KQ^=K1%mK=OU)L;P<>OOniTbW$jH(lq3?)}&uncDK zIn_1$w+z#?UGtEkQYm%*V1|7&x~zj4yf${h?wcxyrdLhPii9Tk%*L(-h;xe}tZ4!) zXVfEI2N1HJ-O`bmi%wG9b&$W7bR9%X3Y2|w-UGiLJV%ew9bjeVFQg-UcU9wQYVA(yj%G^arFowX#cwN^qeB#IT3EU{rY>IPl=^M}(R6-* z*e&$fETd5WfUquJ*lHPv1eEf9re>ilBf4Y^1B#-kfe%TrGS_YF;^i&8t}Z_7(#16g zbc2}I)GlSwA#{`V9LoL{WoIF3?t(5}v1)+X}~`-lh1*+k58^cMGKVo^>^pnEHb z2mST#gP5d52f&M;b@wCaG~o41-G>1$;e{&qbBNAI_K7C<^UO{b*S_L@0eHSf(t5l9 zj086#FlxE`B?J~Sf%|Ru%f#G~T;lD1g_wI2`c3Y?67!TI2M! zyY~~*0VXVW-$u+KeOQ+JcH$77M{*wlCk+Sm?3M203{3#uA-hiyrvR(|;XXyoLAv28 z_npKXqz#AMcN24v?waVnk2n|D_BZz#VydpH*!>6MLf{%-_k+Y1V81r^L%{RPfO9vw zA10m$Y*^|(OKb%$dEEU7u?^VkUH4JzUQd~78f%PKH;e*rkPYH;Da^5{=n1gJT1gD880(F zPzcOD?w+4-)!-0VR#g9_DRq6#N&aZ zukzeX91q;nSaqUAL+T5mgAemd4}gnVjAM1r##OQn}K!9J?OboFO5?Fz6ae>>MI5| zWP9EroMpW{>p1bQbT5 zkMqbI;r1j0lz+}6!wD%KdZ*hX?;xQ;Ozb6(xX~>(ASUApk9->me-MW% zJhD)c9>noXk1TW)1Y*(wk4z=?g@71q_sG;zUl<9SN2Z$k3?TaUc*F);UyL*ZYqx$6 zchFqT@fr{J#M-7KNl?9qTVmMgiY&rk3-a(bwX(-{;2{sMQZHVkW@g6=9$utw^NaWL zaF?uY!$4-Zwcj$oCNf9nB4nwm0J^dU(gTy$y^`P4n=IFLo|KT%F>PFN0XgcBmfb zK|V+w0U~3QM+G*xMFb+T)x&$h?W1EkYPL;hjv#SML(mw$+P4Z?MYikB9^MpgkDjTL zJiPDQes|=&`lY}+^ch$y(s*6;@TPD3o|&3pk17CztPy--rg>DsU zBRdE_@IoENV9MVP&)+de$S+ei>mNP565Rf9yvn1(OtRw~N*Na6QO#yyy!Q+`Zi0u` zeo2e#`l}rtRjHt5Nk)A2>mF5^Ld&EN6nIn%1+7w%zG{X?wP+x};Og4!QB{H2!uVMp zRXs+b5e7_9QamaLQw=Jl6~vH2+DQy5q??4V0Vj3Wc~r|l*r<>V*LqYdNd$n{w!@=Z z2SR8^y~LwJe^#_pwcexJLW0`Ko##=($90?=1)?FtquR|F_Q$jl9@Q-*LP2=vdsGKW zuygL;=}{de5e}kvu19qT2+>ouzj(x!WFHNw*w3T-17qSqEJG_iMj`>k9H&S16p0iN z2l_m!r$N}#L9FQasGea=28h7%9@VoXrh-UK^r)UA!S0@#=288L#0<9KuK6C-^QglM zGY!9Z)VD*O-ylu+7asKiq!D}H*Ddj=h5WRyV@P#~xiuhee%Pb#C!qxq+U8LoCgBI- zx(_|-<1me_w6FBj9`y;t^ir1PT95i9iEI#XZ)%|c3g&apqlSfbeKR8sMc?94--Bd* zhEG6U3+i4$eF3Wd29NqaL45-XUQvC&puT5ZsYk6ize_aP4w#->7AEV%>aIh@px3VO z80KV&oIP{O6-xJ1iI4?Zt?16HWVLha=C!CnWdVEul za4#{ynj<|1hQ|SKpW71&EdJ691dSq|#1;suL-ES}r(vAhUNttTXA*+mN2b$fdZ;~d zs6RvBlSs@d^tF%mBoT88z0%y1Ow1|tQcq6`u+ZdIYfmaM=R07CrpG6h$e{OvwkHFv z8;l4r$Yf?V!^HnX*_(h>RdsRW``mjGxZV-boF!B)I3$S5kU0U0Gm4^S2{=Nj;l$ts zD1uz9EaybSlro3X>V31)>`mXavh*!Wo7K!Ttt>08EdRgX-uqsm=lh=L`};g{e{1cv z)?Rz>wTH9MKIbIl#}PAwzPb7FXpG_V)WC*!g7WW%0#Bwup{Gv)9$^6Yd(?}V9!))x z-E0F4=`?~BIl5-pnL?$yo1UR!b9ae;otcw#LPL;n%^H--npD`EPnv`42;+| z`KiQQ;<@g~A4tr03tW*uh*;i;uij@)X~4imf=Q$VGJ!?glAVIU!#BU^Mc!&x3Sun3 zv)l|%ks*e!Lr%#TDG*g&OifKeh~;-?an?VdB14P|L40uo7WfS}wA{Rd5UF$i4SC_C z8?rCSZHam3LG#TeI3Cg#rT;LfiR?MHKDcJQKPU%Xr}dXX&*K)(6M%^!L3?N#l8t5t z?Uj;2B#MGwkc0(w6q*oZI6;|uO%A%J0P&sAvjER6EvU zTYfH&ah88sdKV{x<`p0s3mByK9}D23QhsiJ0dma$j2AMU&la?!p*-MOy9(OVx49xH zxd72tzynLjHQJ{LVHs>xj7%y(u&F~9Q*ikZ2v<6 zMj(}A=PwHS5zke*Cjn;^3dh0%G*`hnw8x^)`FgKm(2eB+d}Lz* z0<7SE8!uD}5Jv^)eBG_!XITvk7!5mamK0$0DddTOt?dgq_;`8nzThc~eiFN2Fp_(8 z!Js&n`|rDd>W_)bZTC6OK6 zR<8m!p446WVTXfFy-74cN|TCUQy)e^5Whp*WkOI0LbhnD69ITF1T7r6AF$U4AsCSH zN;3?zWBZ59hO&GRqxL4orPhyFKzFjD_KLnh-4FYcH%lg_u^lG$Vq<0Bl=r~74_)-V zY2JVGEY>nm5dMj_>j^AO$04ii3tv!t( z>UBBNim`J(4nJcUv0~`t7a%5P&lc7M2-b1{o3+cDNF|QPjSgDjxVp!;=@TnQ)LLFQ z?%iial@-0j3FZ;I6*cBu9>yq*JZZD`MFt0uFre6qm{EJPlV)0zA@sUD;nVv}q!n>K z|4cCQ#b7!A30O#Dx>GEO)2Jp=E^k z2Jq+;acBzRy@{bOyJ;Lc(89?EZXn@%ws9<)@U$pZJ|nh6!bX<^}HSrOO$ z^jt|F7c432bJ2QL(hh_yDN2W$P^CkuxeD;gJ7U@0;yOcUyJ0~_ZK~q94%lntCCsKj ziYQE&9fP+lDWU{KHy^PaM68ck38JfySPvq`N7R6b_7U3?W+(XYo&;>zYs32zX0txf zy^#MK3A0&Kia44un{}v&6G-tBr;&nsS1D&;z)xIEn9a6QDOVF_vlSKLufs*^{QsZ6 zI$WgA|34^j<|Hl*b#mI4i_fITMIyeuw%i^lHRh*^CFWvb z3t}g5KSv?DkGkD+N5ewdeYjn9_m)D$sM@Z2>TP_E8Cc#v4b6hdM!Mh9`6-~=NnhRF z1cs88)kP+XxVtB(Cy(lm3N@z9hNdfJ~zy z9{C<$+E8Nr=@%5*DY@V10mk~AthHHLb1Sk8+%KB=lxxkz?7XGRvnC1(&6}8KwGz0( zGt>KJj$hIuEooqM5I(_@Z0mc%Y7WZmn>?!r zkdOQdaSM(KV}NnPcEe@_fp6H%WL?Lq;)cyn+vQEiYZWN8N=LAWTelig6#q;@rm&R! zcjnfugJ@^|d!u!c2ud2+qnkU{8tp{~_NlAn68y+Jmx}cNCBI07_O)gvjZ7C_I&Qr$ zEj_lYf>~)PKA4j>B(`f_T6B6QlL1mPnV2_wu7u#D@+nheTa^}*ktw#(*rRmG>PSoP z(M`c7X(>J!kv619x4g6%T9kkmB^Z*)q%sorTqxymY%;Q4MFCrn7Q)zOHE+R1 zysLd3`_0nE#>6V~c#Q(h$Hdb7Em!}5I${GY1JiH2A?3P7Cz-5S^dn-zU9>_?j6hvP z;E=SGVTOno=A^y^=A?f33F@DWzpf!Ix|n^jOq=7EbRIb>2_;m4-w+|sYH4b1Jiy2k z*uXc1Gqh)m*}~MINQ_?+H@IK2U)*dC4VIPfuTQC%C9;G8t;u3Ce#1?u*6~X`Lx+#{ zD>@tfQ!&UI5YF|@_$7lZ{gadYT`^FEHdXD*0%X-RK$~t8TP*$@TUeV8Fn%`wjCTzV zFs_@gqaMTihz=H+X|Ew^qx_j#{H9n#{|8ept9^h`Xf8Ad1%;PL{S-^m@S!oj+6ge! zfZ+3p_4|J_bHjYYjCY*5q?!IS)Ab)_tR}x5G|>Omj_C$oK@%PXJFbC2w_^fHpgmq4XR-fxdzNd3Yscy-)aKU&qtU+B;mu-7Tc{`81q1-`zdNc(4o?#9z=a4 zHDO5C{^y>i;>mlI^&a$>;)O8e*wSN(E=tXobj z#_E*QU9X((`sD;!x11sM${A9xoFVng39@cEu|`Cm2ou?!jp~)NQT=j)tXobjGV7Ex zv|c$w>z5N`-Ev}4T&J9k>y@){{c?h=TTZOhq3IhTn$#<2lltWZS+|^64b~~=9ren2 zNBwewtXod3*XxwCX}xkbtzS-%b<2t6eVuYPt5?ou^~(veZaHx=P^X;D>y@*4{c?h= zTTWa$)F~&HL&|sAS6b9BC&;?x#HGKIm63oK2!ryCLoMr<6J*_TwyIaoR`tr+s(v{^ z)-5OYD3FVh-kU)rvVnKLO@WNBF08EGR& zLjtH2{AH)-+s`V=c+cA>Kyz_$5OES&P0Ei4Ch^uC+Onr@Nb28&x_)uo=@8chB%5 zH+do9R4Y9?LH9!4naKmw#Uf&BiR3utmBu!@B~wPD&d-EJtMJxf@#X%23$BzwEr6<=Iw~kUwUT zmj%iqwq=JlPf9~b-`1)L$il*&mr0@4q_mVlrt#s{qqr&>Dc8EsTf@ee+9ZKLnSETL zgBk!N34~U9Cf>+}4Wg{4`UkAZs-PFzY?jEbu`bB628#I;jfq=qU{ApXA{KxX^A=1r z#H5<=$5&-f%9|uz&k{A(Rg;Wiqxz4_GPVTCU#odumTOpW=76*mS#S2fNofP4qoaEW zRKk$xXc5{tGX-CzyYKe36_?eaE^xbw`_!TxeoE8pPF zsh=eEldOJH)K7oD7G!1K{A_M>>fM!<>ijb{Td|Gv{Q|6%SI#mbeTkdpR!jjCduJ`c z@^a-Ph3VL4DMV`-ulY7!$f>{aGJa{lfTXm(eRsI_VB;xhU~*=rbw|BQK^dHxL;H@x zCIKRX0-$+;4my35rc(w*8*E>aIq)I&TVJY?WA>hTYZ zlz%dY)ML1!U=e!-nIR2$PKLN!W=N35YC?Y@)txD{kMq(O=sWSU4D7390_WJhX zVp!zDL6TSwV*ULKhe={62-nDkxbuZJn*d^U?}gau1d#wD@8}{G0kI%9UtXjlAQ{A+ z!HZM`jM449YKe^T4956FXBQzNR?Qy6Rvtt5J#||-Eva5Bchy}MGxGQ)?bG{m>m_~k zFa|ny1#P&!Cqf;WjA33)GYMIA|6&nVDsVFz#G(<4!X$AIh~{@JYA1<7y>PfRc)lr> z-Lxl;*_Pu5P9yH!u}0ND@}ip7=lRlZ|6(nlbD(4~E(TW556;759*e;V>BlYGS*sRf zy}o*W825;Ivv{?7|9=4MVd^j*j9NXqgr-pD5{}RzcQMm{{0qwZ@<#TTHzt00W73y5 zkmm9eNPuQjm7=83Bw-Nqt6*%6^b<%x{6^Q+m!Ie9a4V=7ON%vk!|CT17u(Q;O<4fP z#A5t)U6VKWUD=jmlyXfLSQWn%qm;OV#N@nUlyXg$e9UqUy6~EZ!sRV-NNoJ!j$$n3 z*X)B_sHGT*>b6$rv&HE7IJ*%1;FKa!jP%b||0HYV}0K2&B|DCNX$g1jY>z>gx-r#dQ^O5GZCd+Qs*5j5op?s;;`u0c|^Fb8UP}#scQ=$-X>JZE`4@F^0QH{Q0?!JjlAGO%$SV-7e&~ zpsgzk;kSMhWMY4fV!X%$C(8<=7%%cfOH5o8;zb>eDb9}SOl+1nhokNyW_#V89fhz_ zAAat9HYyr?8K`aNM#&(O2Y1Tag+_HlW^V>h!hMn`#L)U^7Wmr`|({MW@AU+DQvf(teJLW|7p*Af&@k3N!V!AYHUQ|C~hS1%) zQAxx+Wi|6!R5GwU3*Bu)R0=WALRasI>JKd6_YrT48bHh=MomXVA%fIP?H+tN3L&Ik zYB&3}D1?xDeP2Op)KFsH_Z~bgN(NAC;7!w`5I;EM2E251R2p$RVEdjZhLU`LP~i0_ zMv{DqT+C}x>BP~H>3DC{DB^BxvW$Qz#MAn3QTAqSj3@-rhMTI1$3h121({}TqQ-&$ zwZjrM5mga`*jmsvY7z%H!1T6JlW7ic!$(n52w9W!=2@e%Azgxydm>N-PsHO}QPYrG zi1*{Om2zmmLGYxh(?nD*aiD7Y2Z&j>3A>{nB$i(-A2TX0Y9=h5WdR08Jw!j)FwP4K zTb0w2&%1btONm)oD=sS>35<})gHd^KymU>}EN0My{k$ zUbT&JnE0;}biL|u*44DWCFpt8ohd)3ssuh&$Fn4!XG-8yb!S$|P-_XCsvg=DIH7k5 zysGZZxLVP!1a4K&W-Lu`F1*YvoVnQKAL)2? z2*cUSQM5V|Fm0-Yu@U5gHx#0XD9P;QWAfFq)iao)zK<=k8h|lP3Z?smRv_J7L`gMN zR~PzHwt$HntWx}O3}PG6=+!UCPg-={%9EMZ&v0m41Mr?4Mdi1}st;h?$$qf}BT@Bx zF41t-9?`n2ME(N%6#kY9@{1eQKR}`2uM*5v)qmS4Y{YaH=2aD(Vn@GFf^ns@0l287 zBoX~(2>NpM3&sc!UIhJoiGfao@022}y2qEIH*ES)c7RfjznFmY=ZI2fDaVt-TfF2^ z<4NRKr3e9xUcr+liBgWf@^OlJ&y;fXm5)={a!U~c>fB}WU!`aj3<<&6v$91gDu$22 zXU~}>N)ZBLZ)9-xBw&Pq*c&aP;YV^%WNBM0L8H*XYp0i@w$xy^VQeWUemU47H`cX0 zoD=a?aRi`sDJJI4{Td>p)AC+FVqo(~ zS*P;p<4xc8DGdW_3aVr?Yz4VWV}bsyoaqLGa^!^r-H93T8`hR`JeO}P?zgBkj@T;S zTUZ)T%;@hTO3@lzwK!a*F)(;sIfJHaHU!RWp2FT9^oy$$Rj~OSGygZbDn^EH8kAyb z@MIvKGoCI=`=AMBm&>Ru?Ms7lYK?u_UYZP{0m!N2z*3Cyo6m{hNwcPi(*9)g;AMyG z(t%X4VicdXtaK=FCp=G}LU;3VWVLutNNF0xxzK@?5z5LOTEU3@e5oi zqKvc-(@Q5qbtvns(LJRYx1S8;V7YxoDMx8<$6&nGu@r-JO-UE9BYrD=fa0;hPcJWh zkm4z_-);I3xfg~fmtuIXDM51UE~V&&>b(V1hL+}mUCuEi_7Ic-+ESRj8k>ufF!p31sEIc+fbS{aG zO9CVjjX|x)nmf?Tj74CWdZi)N-S3W}@`Tk(;P*SX6dhH5h*=2BEu_Onl=hPmu2D!cAesbMa?ZDoJ@RpL9NXKySs9Dbcha0W+~83d+L#B#=C%1#sJ+6$$GL_bo%fX31UuK|%wHEW5_*NMo zV%A#BYjvA410k%nnAf_m%M3KK(%Q_t?zmXS8AxeuW?rQ=Wd{1V(%Q_tnpTt1_Wo^-K z`3z@j<7Ms8kLA_Oj0Vd%Qx@`k{?H4{I8(|G;I4UpnTIkwlfNKi87`dFnfwm(mT}gU z&r+n`vkW1C$xJlB<1Bw87xOoP%c7Bsy8c}jM@cUFY%`b1>5aK`|7}?!M>Mm*2r~RD zDL)yyYs+2B?neVOgUs%>5~q8dwYc#Kz;Wre1ye zVECJ4Ys;URHh#hk1rblDp%XMXSbU2QytZ#=Lq1RU=7{%tA1eQ0^GJe^&jfX~p`Jps z0Gr?ChmkMaP-Bui`F#apDRQrZQrQWOjz?`BDTcJW@3djz7Mdl~9AI?WUx#6b@Psk8 z&Xj12ONm9cE)+aq3}qwOi1+^irHT3Gw0ZNt~R!f zuu#h@f)$-@)!<)LuTM-G!&x<1KBtttl?_#k#2a#Ml^-z-*=5@V&N3uDa|5dbb^bAm zC!iNs+t9POn_1p99C4%e*v?`ruBWVk!=2HQVr|Ak^o)Jvym*-AW1(@sG;fxF8w$v6 zf52v}!p{K84LJe1(D5LPr9>e6$M%O1Ef0TW;~NaN7t0*kQ)e}_nbDhjtt4mlMR3Yj z+RVTBIs3qg9b+^9>E|p@LL(iGZ-woXX8`XFiHC?N1bi$megZ0$-vr$f7yq!dSVp2> z{39e@d;{I=nW8@BL3oyp>zu^y^4Oj1q8nP3TVY3TYjl`b-jJA&$m}>$Zlir3N^Q8i z9DngKG5pOMQ;u0fJ;Bv6t=vhI>~aB%%aKd73vGcbhLmG<`s~U$xq3#-JiAg>h`F<>+-rCPQNR@$#m`410z{3ugw}6xTBe^7A_*Zf{y3&sKk#O(Ga&#qSboV>uoyn%r^_|P_;s6r?{CJ0Q z%wg))_E~ewqlr6!pKB^d2NH!HflVRhUCHOmRAP6PBOXM?UBFM6%DWMBv6*$aoNN9J zt`5tbWP9hI2d?Kum_3dLF_>*%2GfyTy8WZwOCS3mYW=; zW|qOimOGc5UHt8|-0bdyMgGakru_M;vKh?Od{^0AcEtVU{aV?gjS%1afOu+}Q@)}_KBu#Ayi>lSMLrb%#IH^xonjV@>#6UJ9aOh|?I$z8ME%_(x6yV>jL{0OGN5CtubQ zxT~K)^ymC(wm7*I+Wk1vTKwrWY9J_GT@~V#&ml=yYnwUcb4Yl8eRB3B;pAFr_v2>t znN?9vV;gnM{ufv7-YTovq+ab02Y0_1%6dP@@j0o$(*zuOQ8D8%86|w7j%HZMsPv#u zD8}?;G9LG!0(U>oYR)BN;$_boSs`Tf0b|@Jp0%t8DbWs$k;^&qo)8yJ&IHo|pVK%4lP+=M}$=JleSGIpDW3nJT|~4*FG6sq%{FuwSJc zRc?5W`c)#qm~_qajz8OWV2ls-yz93S1V;Ks&k3K6X}^H6?6~Ko&&ITiwDG6sW1o#_ z=V_y*2VG26^0cF5wDWxKXY2waeX9pkt*Z5D>%o}n@_gfGu(adnc`o@?a;S33^MhYv z6d02`dw%w3n?{vIo@;&;mNxw>&kesy7#IsKdu~EPw(Yb~FeYVq{`RR%y@3vCeBRE( zr=IrgLzE}%_Q)5b$!F!_zw+?CXxsiaA*HsNN4^Lx!zQELV_+0@7uk_g)Wl=RDbo$2 zAq-%caThfLku}D{OD((<8$`!6kAd;iUDOmrz+#VqQQTeB5=6xikAZp9T_o=w?umpi zM`fpQa;dSqjmH4BM=nVwbA2%R6A$jAV=|Rv3y&T=i!p!CO{vq8Iy+l6*Kt+>0Se%1({<;<8X$Sp7e5uI5hL;+>_rYs0-PCUYA&+FPQzaS7fE&7BhG zeN=N>w)SFJP7_cY~*;_cI}0_}b3E@}fVW6@W)yP?*cD_^-TQFvPeR?v~;GiZYJiIa6i{?-{Cc z<;i;nfeB@dP{-Mx&)7nZ=A zVZYe;K;Vm9awP0_xAb`v|CJjJiy-GR<3$L*m?CYZ2=tcS&E5F>Vt2+-Hbfw_Isg(?J~s*w1v zst|!b7gj++#eWZmP@k<;benIcz5h`As?$Qev|7I0t?Cn+Wrfb#RrM(`D{)X{6)Re9 z{}zp?LggZB@O!kV`jVKH*l=wXD_U+ySKF%20LwQ%#=TU9iWV8IAT#H36)IYNc&Yt; zRbLag0pGQ*>O3)*o>hyhP}AzeOR?`(T_EOyW9p`=Z;81;nfiRyMdEe>^VFR9sw*H6 zV*j$I<%%i{Z=yDB(!?B5^$U3@?n76reg|xX)=Sw@WduWFZz4Z!Ql*9;@Q0nMk^_zx zxWmROwy+?sc&kbdH(qYz-?yO3z|X%>vAkfK{0#rT_@Vr}3a$jVsrsLGC2=IYI6@L@ zNF?QlS0Towmjx;bU9WZj7Y=cvg*HBT%&rS+#<5-C9S+You749 zWcnQJ>q=M%JC2Ej_{iomcgg zO8U1`C4uxAP$@9r>04E;r8+1nkjjAh$0`g3EbqV5R1!#^0hIy+vy-Y;YN-d66i8(t zszsGoCsnH?kg~$c`>7OF8YKi<JCt_?#3)6 z_l2(k6E7<`g0VE421lS}(DHNH@PG-stL9M+|Bc0k6PIAtc- zF9P!M#7<+~#=kV~lIQ038D4rd0}}ga9G<-V8N|HD-Npu=*q?6h&57DXK7Q@yx)S}J z!9Ama+jvz=4ZYyz&YR3+&HHYHp_`F7V+u_lkQ%ZByy!xK!Z*0(dlY4XmSRO*dqgsJ zP5_>&uq<3^W4Bt1>&%cWGhk+8i4!NX%=c;b@Q>V_k-^RfcPdbZfY?3HyNy^7h^&1l z#<4SKdK`O$!i6yHm?*L9ny%vR)IrV|nvDduwYV1z_?Me+MWnG;9NGYB8lWKX3ty`` zzmx35T;u>FP=NMbFSzA6LG7_xo8yL08`!7q^lOJwdxR|09c0QV8tiueMLrBwB8pIh zAa!q1Dar}N3^WjSm80FiXocsL0?3{Cj4Z^4SuJv2oA1EobeaQ^>TO_WE4vd7C`2FeEg*n01o{QurLP_HA4IsQ&1@n;Of58y$wG)*b6_uo7L7(qt%XWUCV;u; zAz>Q71`_)~*xak~K-PkH-*O+%=nCF_>ybPPC#S;Q3z79fIdT)~k(*GD+zO^)lv>R3 zkFkYSSt&(vU4vcZ!R}csIf}UdJZb`opb@;#Knv`12-L%{pWG<2jQayZRTpT)-B`>q z?|4mMvF;D_l>>{{1lRP~?KR~9d*#^eHRWplwC}wp)CgR_kkNFm*VG>bhUNoPF$j1~ z14$(o0u7RUIFuLSHT4EjI~z-ihrE32+JP#JNEIVAmVq_fQYK2(_Kpy{1;cXSEt}l|aI?*+pIbodB#8&UsBiNQl=7zz3=@L^l4!%NNg~-e7jlbgzMa^7;rRM69%D6?%Ew<#m46 z5XB?b2^n4kf&V%u6ea+xgzkY}17p|g)j9!KYjpD(A0gqOP5?eo#VY3AAT@WyJ>iwp z8k+B*31YQJB&}yEou+&@-lPoY#fTTYl0d<@(0gGC|JG)rRI7S;jprbC4@~7Blvqw^ znK@o#FWV2(h1Yn2NX)~nGq2a!4z(3OdyR*oHVVuf1I&_8WtI(G%M7wIy>it+uUG^0Dy@!Jz_R<% zD|SukRgW*dYE1&AOIm3_9k1BwxPZ!B>E+9v@p)D(@h*9J7ga^d9nX1}lpd<5Z- zuHzUI-*n2M)peZaQI*AC61s~3Ba!kNm4h+Ido?8c~>x-8r1N zp~=bHY&E~Z8QKlgoaPU;=9D~7V4n9Up##dK1SZY(C(Vae4U>GbTpCTB?BYZSPY%sj zMU?s$*=vs{++==rza=|HxGVKHCW8A=EXaA!m%2isNZFT+@LDs=;2WgIlyrz7|Q}Vcn|-`V|)+HK|Qsx$An%hGBS|gAuu9dkfsg>$?M!zk9&-F zXbdT7xgO(Ps!7Agfoey@&7L+9xu8mM-ke*#eZX#{7E(uSp=wJI3#qqmav`uMvKYhG z?;c|ZN_Qkimu`m~T4&=LB;UikJx3NIf&1VbUTT3|RH&k1))E?vO^ZTYaM7Bq#z}SKekFku2vW3`QNM^a!l;@Ef zAqZDA16@73N;X4FxgdKs5cT{_g@?2M(I4cDDzTnXCDt>l#jfF+) zuxB7}n?2>>Nh^81@OC@hf?&vnokxBz!f#;^E#Mpm+Gjo5sW+v7-%f%Ws|pNEwoAZz zIK^pvA(P>EaTllYF~sIVY-?AEu^P(94ZqV6ksBV-t(?9^>)Zd5YdKBJqAIM`auQ?1 zBk!R(FmM1-c8!bg>NlO-F?#z`tpKdIC^TPI$h5J zE$QSmTKlw$v=$ityksIJA6V@)?(j)&)skTBoFLc!a$iD)i{)jfZ>9I{X)TDr)QeD^ zrYi(|RjuJCoxJzPG9P0Hs68TSzmiHr&4r$E8Ym(=$gv)}5;)dklWy`9v^qva;D_?3 z0|x+S@X9@Qi}Mf24@C!!-Af2|KIX<&&YxiGSRVM%InJNJ=Oz>a<{GU~bLvIsB}hCD ziQwaeqEJa(mJ*nb=9W4!GjO}ewF|#JIf)&6?S5GVB%nzJPWnM`^B>OtQR%8^zZ}2O zQt-EjFh9nC#kE(E^F!>(v|rCz5K|^rb;rPkqwC*yz79vp)if}o)Zn*dJnwp{jqZ)Mdj8@!4l^rA>Qu-6Kxg}%C&uiLkdE={8#4` zW(b&j!a0?YF5UO4GaY*OL9hEPLb=X!OjIz9S9(slRHJb3qt2lao}+{Tm5qRho&CVx ztm+<6x?lVyx$YvmpA4R?f&9MCIEcQjL;-!GfJ#(#dSv$aResm)eJ+Nx2N7bq4O21F zQ~`FG8#_@Jkpa>2fzGx<9B&BGweJurzt#+PHUYc4Vgqu)9wVGhC4#M10JUN^u9EJq z%Z^=FRaE-XteOXl|~6L$3NNw zR`$XtRdRYh{)SEfu4@mfcW$WUW%!9uEdeYyYif^F@qdYa7Tss46-$S<=NJX=``NMqwx`k^VLa)}nOEveiFNDCDnKkTr` z51;Mthxsl1Fjn~C%0K*Y^M4fNCb8$O%3QhVm1~qi0kU12R<;)6!(vrmfWG<)gA2O8 z?xX^&{ti0MID>}1H(=5ZRK_*QEA7A0tl@pn? zB7`PzA7Qf45cjlKG~zvNh<2E_q6yM@pL7MfH>aNm#0vCjcFwU_ea~{3(AGOQA?s(x zArnPTmL1b!dYWzk4-a>kcC)&%WOkUIgLm@r&(>f=>czjqy`+4%h^dR#&7OcLVE{yEaaZYseei5KVll@Jr+bw1M;FaNwwuY~)gqu|P z9<5WpRnjZibfB;cXtPG!#Ec-XHxTK3{bLQhNUO2 zDHcQHy)v~aj12%N6sKv0BFdo(ElUX20c?RnG5X?d1(_*U7N7h^84Qb-k0$`Ua8;Bv z#gi7oF&b&#unbseSbiZmgS*uo2oMDUsc`7RJERVRnhpCUeT1oB0UespU23^kontD1 zPs|*JQJEKlfh|Uq4$>%eV`|K~t%188NG`z)|6UoAd3)WIUrZY%Cy?89(sGBKcf!R( z6oYviaF7FMJ;Zw};m=BD87eSNa>Rabr78Fp1O%Gtn^GA193^b(Fs2Lf*U3$euZ`uM2(<2GBgd2vV@yPQsrF&wG_(@`J&Fc6i*prA&cKm9 z4r4Z~pS=X@o9Wpecy{&|P;V350{Cks6wWm?MuTzg4h)ekB%`hAu^@7~fRjwk8>A9( zM$k&oAD|Vhr>V-RQ6C4d13oWDZr|LELoDNn7tNt{?lGv3 zf!B@3%ED|iKX#NgR<=?bAJwdDnc4vn1Zkr@W$FallW=EY6(- z#U?(7Dz?2ya0TEkf*Sxo0eo%7K5h(w17IfsmPif<0WM}7od_^XJMyyt;y5}qs)6@X zvOoC$6_WP`cn2vv7QCB+E}SL_r<@2=M(DXwSH-gPNVw|YW!aYwI*hs8If8(KlTq|? zmnwR$`LSa%h>D=icA$EB9}q1aMl#gXedRYLPpRfA!S#hfVa!fuW41;nsf^a#w zwfAKWbQuQDe-ofFoeX=1f%9`(EA&}YVO=OaVp#hkqkKJxPzSeezr5lz_Mkp_ETIN#1D9qhgs5=kak4-ZGT`cwb=$?qK5(#TbV%{;KE*FN|%R&dz?W zr?c^DI&&R+9AaD=fx*o#w|SZ{+H8dm8YCdq!5QtVkEVk6A`(-PUB@gOmzw0uj?!6R zq5%T390tEiQ<);NT`6(fGl>8R|Abv@;AhW54+$7(_GOy zzQvQ0)e4nL){_XjS0kYIBK+gAEty$~`!gZVETyFqH4o#cQ#=oVA&*MUB@eC3b7E(!X}E_J zOVh09$%?1fo$mA1UIM(9<>={~6y!8+L}NVU(^AElo;?mD3Qc-$)Hu0dg7vR*6Q@qZ zTB{?kBRssCcc`s#;0IefjA$5@d;H-JBSyR@`M0smv$a06#!Y8^zi-J*YOPo7{t3qBu zdZp;vHy!e+6W+r9nzvWzd?1o}`;FcZ^Mv=9o(_2;oCQfJzl|rwYn(V67nf>JJ#iXg z2(2VeBy1!h9S)Uf8c<`E4AexT93V`Na#!l>bmTH+trq8X*4I-sN2w)d)VB51^E4g=>G-Y*Npgj&Qd&l=~%N;#Me*@dwc#p2}+Q{MxLlKIFhAW=9U z`QB>W19bdOS!3F217-O`;+!-TM#44N22=<$MZ+})>w_0bu-zy&jaBkDDTo2y(g}-D zELJl};pKcJYT)^o+bpLkQ37_ZVoNh-&Q#*4;@kqP#eDc6hUA%!udj+bPlL0X zb?{Bo>67Qo6^^e}BsF?#`kdLgn(>jhP$h|yq@SVjAaU7?R7pMr5*HLcay^!3oQJ~4 zB0bb`8GV>jQ0V&vi1N_01nmKSLAMIm>xmo=>e!e^;T8^e9Kp{w14hbA^&|8tUHYTo zbR5ie03tXkzW!y$c8Zs#v#V`qPfKG@+ktU@5jr0BHFnYjcYx4aUQtD)=EHwDrsC&9 zq|}60(Bvkl0|U6+=YeXjPZfRfQLuR<{F{$q3UnT6z-4_Lv#7xk{N`ts#zi1^wvfhA zPNrSp(@fAS0YmGR$~3wLemMxOQz7}PK1#zJJnL}b1?eV60bM{0WxfI?&`TI;`#%TP zUKk~SQPz9OhEo?RR0e&KrZeXFp`6;P(gxj58!XebQ=`boe^yxJKt~%h7rW^)TH4UO zJRj=-l=mat+a;_;(;-60B}8;cC^x}6eCR+=|MqTW1JKvH5<(i0CWiuL!v|qQLf!?q zC&O+T0UP&Y_^B8nv43;^+Zn#i{%>bs9BFVcSTvyM9BkuM+AS#Nx2v@p@NKniezk2< zt)Wy~4Ydan?3OqoE(U5fU>t_zzO>zfikG({9TV*q)Vv(ooA$I@5b(Hn$E|6*r6=n~ z?V{K%DRK+kZt2ac;g7jABg66L#}g+;o8BnK^dz8C{~j3+?8! zSXc1iNKUNXd=C7K5pr9}Zaz-}7`m6CyGh;}$=zxdsxR!P^y8WdUS{3*o66x`F^9zu8PD=p)Q=)^N-_5hgB@%f4mG*(Pna8P%Y8w5n z-Mq?YXXJIe86DxfnOYoJ-YBBbT&+<2qutD5NM=0zh#jk0@!cw|04x=Te`Gi3La315 z<*u`v(fPmIrGFV-(63f^AKvFiHz70 zifF0A7ddX;Za3SY#&e-8Hn7TZz0Gb$zr7r%6M$91W<(DBy_}{KfOW!5y9rb5s{hH$b`z(#4BZD!-`p-l zmfiFjGWbd741A!P5@R3sSnvr3x)XJt`mU&5kAXK*-iP7 zh|m(iN;Pbd-Gq7e``$VMSS9p=OAjDntWE&d2}yR-WF*Ye3BWp`yWKPa30|E5tP+-< zu$x99;dz|^jK0TP_;wRQxb+^kUa!V>emnj9qgn`9n+>${-Ob;t^Zyd7gnNFloB9gz zLj$b=>^Ga_Guv#I-Gs^Fhc;RWSZVhhZZ~yDLcC4@)(L&>yp!;QI{z=RPUvJeAy9wN z10k_WDEZB9x)TXYwJBho@Q&To0txE;zr;FWzunXb33~h|RtdSNbxbZl=z)M33B20K zO|cudu8JSia2+St)z?PwavG7toqh<3#(`@M4(dEm$U(jFI?$LPOcqWMI6U?_2BjNV z6aH9@lbP|7|6|fr@KF6tpFt<;7(WrzVo(Tp2w%qulpha+pJO)#2=Q|ogs(3{^8YBz zO~LC=fcl*~m{;4OBO;fp|H}gVY5v*EKl^!Me)4AsL_%kuo%?qua;nqhgI~|yLgfMSP(BZuU>>;jizB&Fqe;_RRX>!XDX&m z2#K03BxG&yc|}&F!!(idr>z~8KSy{c$=!8`J7F1lPRJeHZUH&=c^OJfa z+F@FWT0e!Who6r@uFzpxgJx|HW2f4~*zZ&>M6;e6z!#{~-&5(z-&5$#%~P0!fuQ*$ z0*oQeO9_?$Y$13A;1n}Bgbc30R*k%O^wVBufZ@1BGiJbh7N@=hHH_dp051+5A+Jtv zz!^K4n6_KICs}8N_=!7#r~VDrk4o$Yc--7RwFA3(CN$nPaBepq7{4U{gK;gMwXABG zI~(&+8>)$SLV6pBc!y~NT1w$8H1QGs`4B1m$JV`3iPl2Ph#I@80jlHJP|&M!%)w;` zb&Wgz$Hu{oax0XX=E{)OnctIY^tb7Kr$EG}ha1 z3>!H=VIVm6nhLIuP!Xg%r`ad40BKqE>HtH8^^D#41$pZ6k5~^{QFb0^zNW`NVx7>+ zZlIyB>G6+PCG_5F=b_PSud5N0_#YEiqX~8cHFNEhmH<|&4IZ@{h}~;fbpo)?%xyRR zBg8KqbpkM^0}hDBAr6Rgv1}aXSm=?9W#hl7MtP0!NQm8d8LCsYDzH!WmD{SX)=@>J zDb;Cb?Z)#^)sr5vPjxREnf@iYBZmiTe z@ew;;WhOVr+S_j9ShUev@)LRQ)Xr@TS#xty&zM~##-#E+{GH#DcOLl*bVzWCfp=?Ng)X;JQ2L)~5~~0Uem~_d zMnIr_H-4_aou0=Q+$|ydA<)iEP(magqW*|98Cgfb=8+r()=>=+S8r2To1ILvt6#D| zNwYsIvrqcX0zs1Je`2@WD=|)YgzJc2K%R5NSzo)1dt`x&49rn-k0!XeUG@N}xNfl> z>wz15?mO^VLMej6G5X}$BRggc>1A||9V-=7+;}X$TH7(&?wpLQZ&WH>(8#n99q$1k zbx8Knc6L6`b7KonAlXM#L*_d5NBdB)Ux8-uaYD$WX@PX0-1m)YIz+b0#(Z4 zWJu$MGFBytjaHO!1V*R0(K##BR;|_IA=tK2{E|#IKM{~k8Q3lCY=i?U{Y}Keg@PXB%hwC62F>vL!Ec`D3#;%rR6_-tBkFg-pRKYuV{pB@|E4VimKq~*<+ zf#*>)yWQA$RISV)`R{miC0WbOzfcebm?PqcP*26-fJrFoSW`k6%|0ZHnh+*Om?yv) z*xP2oir_3b4xZRHf*Y;Hi4B_tO)5H}$bC0LYWMKlj7P|L?q4=b8k|@Ji7jNbn0uS? zQfHiEe!^x!UdE!J#UdsOk4!yDsUe4K77SdWSx`Gt4aPJ0LS%4TJ_I!IB-i5?(A+!^ z@MkBC3->*0v-}6?{jes$p$t=M6_yv29dKTq@wkj>RP==O0vbJ9*0au}_`0EQBvty({bb*Itt6S|kRU*hkGGkZ$>C-L~6TpUKC z)o(VX8ivl+@1bnCU1?gI3XhyiikB33Z5JNfu2_VZs(YnqJl=cyx({Wb*$;BIqT(XI zoGJlN9+b!%Q0G_Z8&FN=2;6UtX{mpFb|EisN~x`N+|o5#n$ZoTn03$`4 zuaIL@pDa+*_-76lz`qp>5!R3Z!4t+$as0LpU;x2ZfLR3318iUor0X13auPMn52DJ# z(CNeWA$r0l@j7Q;s81xE#~=2^FqNP^zgQ#9StaVjfJdF%4x(#&3zn3BOj^1L9 z7h&Y>hLHOJR0lz-38$-Xc$TTw)LGJw|$ zR}O=)xp}JnmH}UQ!4Te#-~)hof+GM!VDHKay~;Om_nuGqo|ISb(h8C~GqOI6VMQr<+mKbT`+r{v5L0ROHg?EQ5Ig#q-wf?PZFz_y_GQ5@` z3*ZhwsqT)i`So;}*`w1*^+i;z8+c;m& zgPC)h&N;ZCSQfWm{o+b|z+9!zT(-{~Z|Tc|RMOl+UpwHT>N>S{xIfZXD>H~? z!80ON1WyCpf#FGsBJK|F0jFaQI0z^_ zw`&+vQ0qoFpK+#q&a(kXnU562$$z<*@;xI-KS2IpWGj8Z4i5Pu(rx4m!{la;En&YG zfd^nDL05oj^g)W!2ef88zOv@~8`=l9yn*-Du!7&`fc^ulN+14KJ{+eHKZM@);kfqU z%~Zu_Jr=@;0m$*qQLxYO{~=5%JYWh6Q^wzr5qGhM@0fvfrmyTqG;_U(gNDnFgFgp+ zUnJ&`hr}y$wbG+hilzJ&pPlVw#UKk)sS0Vdo6O)pOz6sl0+oRAS|)tL1eRFk%#lIz zeh4c%7Y0BCGtwbg&LvLvL zv1IwjCsR-#*}6xmfE3dB$DtdKZ+|-k9X^%ULWcPQhi)vI+HK>gz5k#uHQa?7-;d^K zw~d2kD%yAdr=UKjm>gnhB*$HdJ|{=l4ml9v=-S>wh2^9$y0#Bz#%kqqDF`4Qnf{H$ z-(E*z2Fnb0OsU@p!_pF-a>MbR#7c4Z$yC_UfOvRQ}tnfb4DT`)3 zO;)O8g=s$zXg}|{D%lA8-={$#ARN`AYlZ2PF6Rt_Q^F%N31~_gfXj){joub>i#ZLnEF(L z8_d$n!;_{(vJSq(IU>2>)dz@+P*kpmF5P4WK!Z!rjSFG>xa31#@zcmh<#;TLzgqJV zl*YzKz;Dksxpac&VWwDD^F7B{^WWj%g@2iy+7haCa=DhpHKT05R5_M>w_TVzErN-I z^j(F|cPBOP!`r;eINT`ZzOBP!3p0C;ehi7!Abff1SqH?i=C zNli;1&%wuj1<)J=F4wnek!!|>g=rXzR~~IO0%sxFY)!@bKga0FzVvlddP0E4X|)@& z=WDcVEi(w}16%a4XBu_lsdIk6FdF?z(G$W5#*`iSfi!Eb(Xy*Aay=fD#jMYt*D}8; znG-&leUw4KQ|5+}3BsEt;GPBU$vjstmv(9>^9=?{jtxN=g=Li`Eu=44T$@HVCD<;E z0iO`;5vEpq2=)n6w@;{gQ`L6Rbgino>xCfAUaHy2`iC;&2svZn3_U zJx}9uSE<(;?k)9N=_|l_Spc^zz)AS9>nEGV#6f2+`g^liY&ejS$Pe1t=&P$J11YVL zL&OUtI(5v_QOV?VIe;`z7RcDToO zo07gdck`_Zk6p5vF+OnH#IXL38o)(97z*S1-j8t=Z+?_l@$%G)&HR|owSAGz{5a%q zAqP9Y2C)iv?*f4zyUS)i2pQI7!7n!R8yY|Ljm`WYV(Emjh!rL}al35PV4EofMD0~^ zyc1@!$=sO;nNwwC&z>fjgiM6+^amqa(k!a*oCO_on~pSr?plX#J1#rcM~=(xb{lrT z4SU>%akpXoZJ2Ny#`rTImmTBJ7}%dFc0w9YvYF8K^5a-W)(LQWKW)QvTqqBRm8_HC ztZ!~JH34U71Ic+3tosMqOijV6q)_${a2^b`nGo3_{~uf50bXUXyuaUf0_Ws#fRIFr z1PG8oAhbY2AhggU^*|sHY9IlUkU&U*P$WkLfq*0+O^VW+sDKR%idVhrm5Zo&ul3r? zReu_LL;b(+?0zTF`}cVav$M0av$M0av*p`!l9(I5;Fd?#bRUmuxeXIHjEK8#^x5#* zf{=}xR&V?4R_sGiyhaL`vfYNNRjO0FotD_M9j%LWlFc6Xe4pJG_WUnUOu}I-+6#Ld za~jDT$pJ=h$I$43*vg2b)sY(Y(lzjm_8}ydviKG=ynB>OIBiAkt5H`m3#%DE z`wnF_#ASFZihPe?X4e^*q@o@I2LB6dY)!nn0VTTl>?o%<0u4q!Hc`vBZb z0LI(-B!L$Iya;y`@mh`gmk;A8*Js@Yv7UxB5uYLReTE~Fi!SdF@Zki-YWN>SV8~^A zBx?-Xtb=EOt-JrAJ#b3Rm zY~S5L%|IvU5d77*42nmJR!_R=S3fnVHAE!}>N|tlK~yqPumsIZRsr%!5?ZfOJOIYm z>FDx*pY@BCRgcL(KqS^Tmolkkw@?f$jh<5aoHyGO=MmEOV+14 z3z2E#|LQF06cX6Jkw9?{)cx}src$E9+7ZPyRpVtUrDb9a{zgW&Y#r5>o$(shMM9NE zDn`EkTZif~L&bncmQ~>;LWRGY3R?%ljuya5cag9U*_8?*{?@X49WjAWG2pkj zQP8+dsPNZN!2(|IQP%=WL8U)?g48dTqD${VHD7>%2^L>O=)xedNmJnH)CRuAaEITp z@Ovr73;bY%r4h*pWmiKvNMesGh_T7E33ia=+YXRkp$rIlWCy9_iBt` z_9`rfVQu(O@Nju;5$sijUV_XZV+mMa{|?swJ$mR(^kZ;kHF%iBSC}j?^F%Vf(m#?j z_$dS}g1ud^9w!P5KPl-(3}V7>XUq^7>*M#pkvJ*BNY7kUR;UDl(g9?bb@5q`(Ctk^ zI1%>|5@g&Fzss=RXJOSVAwjPkAAfRA;7Nmg)m}0Yx(oOwBkjH6yUo?xy4DD@H}4-IpNe3R!$~vzrd&>XyH91M;Xngi!wMyE}#GZD5FbI8O^4PGMZBv%|=rh%kzBl03F9n zz)?o?sg5$H7-c+QlmWjb%J`R2hLir$D8rB83v>>3`k`dkjgNi zD8qrN3wxSNv#+IQZWXkVhl*d7?6rFAQfXkQH%pqF%C?{2y7N} z{Em)Jw8tZkrm&J0#FvhyBDAIwu>RwtNInaLgjSxAy3^u!RJDk7S^x3s&vnlte>aw) zSlL@mxw6N0rK9PnR-(~z2K-SsK#?DU;Uu3GtE`p>5%5RNMd42gWCHjVk-w%u#2!_s zRL>X!SS0r30xarg0OPoa+QE2r>i5MX_nC)+$)2cCN`)X^%DfN78L9mfA=y+c!dh|*ltCTrlW=9nQ}XggWj#s+D-KNP4iSh776(9`#w=If}X=Q_u4@O%y(1Q6VxIjPa5E6H&ez z_B#pprDG9~)OF8JME`xPGdl69MBg`{iI(d)zHdnm?Cf0McLXQ+@x7n&{eX67;Cm-* z9rW;hfCTr4qMl5bodcw;8}Y=D?;~c&=U}UM`0fHlt5nn#-`*z?P;2}&U~{fUTcuK2 zS&sqHX{isPdn-Q?v-< zQJ_-3krVJN-#~1T=^F@=)&n)kKp~kor(F2}?(?P3n_CNJ*Md0?NFLiB_w^?aK8V=$ zXCJ~zTqFd(-+R7(#4pl#td@a4f|j_K`cfCwaX$E zRswBSX)>e@i;=zCWf&HRbsmxq3!MWNU7l(;#$oYF5|-&xK4 z)>3@S{#di&u&C&Z;kcT2TeBNLDNm02bDE_P{~9Bp5d1KTkSkPm0kaXabj(E@;iK{t+qQ;7L@>;fqU`+y+h7~)pno0MAy_! zUlHD=7$2hE8?f#~4nK5Cd6+OpC*bl>1E-YcVDWp9B(kx+cQH=mw%-}xW6m_scKmRw z-!Yxe$SlUM<`LHT{WSq=C7T7B@J9p|?st3~urMV2LpArC$UP+wpJNAjdl`zPd{b+V zqp!Mu7O-TLpxVZ}0=!O)PhhNe%Tn?{y#Ul*CTK2LAVNky1=iu_fV>)63A%?+HLHW$ zL3L8aP*%}VOFaxQuK{P|2P7b?Wcl$A1mxWUmj7Irk^VJhl1!OpXi;zSVwri70R|FC zSnY?R&a!}{n=H>{3?eXI9gzB4k_^1Mz8A32r}zb!lF|~8v@&>V6Eg@*kRxhybl|_t z0AG&JMsu0mSC}qrCC5*$Uy=rP0;XRX@b2RQOp}5gv@d{-WVu=i?%x391=eLx2QW>l zN|_M?-w}kW&2Pc5?$DEg*NH{lHB!rem_kV~c?X~{ITLtSXjouu{Q##A6o}zVryyf8 zL(1OG4F8;L2z!qp3sm4<07t>E#gG6_uu+cwAmxF;8Ze-Hhe@uXMFNCH3g|DzbJcfW-9nQtS zil9agy<*$fMNp<-uEZP1d&J`wuN8X{Ep9Y7eg_ASX1R+j{Y#gq_}k$>!~9E&RQw)5 zd8?(%tk^4<{(FF7cX=Gdc`7vi83Y{hk3r6(&|IkjS#ja-@rQvv3vlt^_#+1Nz7&6y zU~thHdnJ;aX<-c6VlTqA=6oaXt}t-w&;b|0!5&=@wmh8@0ot3FPANB1O0*(&IYBYK zlnwElfo&?+lH;p^6<@t2HNJ>28SYIlC|jf?O_%B3PcWSE)4CDy#Uvm&IvyLa9rl`* zcYv^4Qh}e57!R*v-ZG7cqf|%Nqc4w~ieF>AmPdmZAO%YIWi=o3=X?2`Bx)4GoL@p%Iz;h}Xi z;>cRMvNQQf_hMp1_tKHZcfnQU<)EAw6^}`z<=g&}1uDK9B)bpDroYA~NNec{;`;)m zecswGK809-QJ=^6Ghj;F`2GZ8k{y`^qw6H9pkC6Sh#$^O>GECcLGqMn#AdLy@nYQ5 z&_$eAtT65p6+kYZ3zxWmI)>fxT3v)zx5?#e95)}2n_Hu{h2c@W6O1k6zr@gMG&c^) zL(rsp-nGM`CB@~CKhp2xPj?juZx1)9dbL3E@NaSGt#~-PUN>{8MnCnePnIj^`8vjt zQ*jqi#djdB%8PqYFYBg< zh~?@tukF|#kh0rrb5ofshh*EwnA~%5BIY8;Rq_wnsOMfhvXrP1tHsV0 z+pX;R3sl@e_`-*<0^EU{v2o%(pct-d2Mz|Cx1gyWafd)Z0UQS|;-9Jflg&Tlu!Pkl zSxDhcLu=q#l-^GPu$UA9Y`)ZmLyAZUAnRAEYC8{NKLXc95RqNqJB&o7vbx<7$&O&F z%24|(WgV_UiS6kA191N1<(LMwnlXFiGV`7-r&dCjD#JYhxDiWJ`fuWe>-KI=+kG@=PtG z&P(P2C8s3uqnTOz+>%okUEU2tKYkvwgRdmArni)p@CS0%26OcBN=cmXy#}o`K=y8( zO&pYBufsKwc=_PfgS$Y|+}^Yjv(VrEw6gYp4w6@c;_%iQd*~|dI9ON6QkB?NyVO1J z!QU19Jq~VDym^->`a2}y@8GNT=MkjfJ4N;FI27Zab|qXBe(Mlkp!@EQ|#VQUrNLr@ZTccZx1K}zo!`|9s zy9L)7hk?=YK6Edyo>d~CQB=(sKHbu2Gvjs69F^RasqQPQq6D zFNCFA{pWxN?B6LEKPORS4Dtqru~Kj1i6J@WAwt^aTMpz25xs7<D-UqJPFvH+8R(RM8EVtum=Ep;)bE~T-4H~FYB?;31vfmm>RTbuYq-T zYgKDU`g8Bi0oV~wJZN$9eSMP+F+4chd`78yS+s|QpEuEG1FM~O?<<>Rnh*r%iR6j= z-kuZz@W4!w{5-b>%gSP`n^+u(--zgYcZ{_Lt)Gm0s%b=YeJ{o=HB_J7M2xJcMO@lx z6_yo%>CF@jr4=cLpNf&6%)X&_71{mDN4kp?%sEeipjhaz$Ac z;#>5{g)HJxBXgD2BL!;#GXE#%LcFPIRUmG!jsm|EK%)05_M*x+2vj46b+H?H>9Yc7 zc`0dG0M5>XWBC|`dVp_8>^%@;+k9n@Kq_SkfZ^W(*a*YcR4~fOcViy~)m4Y;4u|SN z+&-<|Ovi?vp@;2`lX>wDqXT9ZP>>lfoLUu6fa?qB#m)>(3ody7xmjgG!W zP26t1E*iRUdBYT5BevRhhRuon4%~v;uc4;bV({BVR<8txJ!imU;8CUe`0+M8@8zcO@5Nh1Y_6EkVc}kB{S8KO{qf`SIZ^KWUsE1 zjhG6R{E5o}L$<#TS&v#S7ftrlb+W|?{h7`x_69$n^I?M)Z{4qdzxBL-d#Y6fv2+?um$TK6n>nAk$eV8aBz}eLPe8J zXD7E5MJRT*wz|5;IXO!kOfqIFXDn;uqrpsG%Zl;;?AqKqJdDvz-fno@SW9Jipfe^v z#$3sf&M=m*u;TUq6jNHGhWCd{4q+SnRu)JURjOmAfejIO!+J_}BL}{SG#0jS;uRane6P~n=ZJso=wsebb#;yTaj1U!F4Jk`%2R|d_9 z8sW`SpOGcTOlmd(jG5G>w0zWVPk)}urdmWR)zE8^Zqa_=U@fT|F_cC^6=D3j*pX;G zhf?1Jj1n{bj@)2y!->NTOEr$X$`Vv#n#W{g5ttiPV_JXY%lI39KOHorpmXj5za~6r z+1W>8q96n;djkGN1cP4hKU(*CljdP)Wk%Z0_P1BqpeR2LEbn} z$w+|uhzm2gv7%B5Lngv23Edo{W->$gqffXUwKqUS-S0LnQ6FtcL#ok@8Lxu+G-?cq z>4&-=Mek*N0=IO}90xxa7?{J5C%Kx^^ykrn>X`nZ|HPrc%2^wy_?q^=Vj|?7o+`Wt zq4s7D?KSY$ctbz5v8F!-{3M|t0(yJ{X)`<;+K%*sC;fB4Bx(8z;B!Imiy033Wu)JV z+%(b)p7b!Xp>T>Yv5DsumTUx`GeG(n0%Dg9PN3%#w1UQhC%Ss*BG9J8g2gV=-_l0b z59aLb224U9(N_B*=FN>5gXyq`){U0kJw0W%xz|YxcfTq z0zvHkBH)Wa1eMgg6SfiGh=4QM`3V`^o)nP{1_QcFv1~A4vFt?=If7hVR;u_D3aU#w zp4!n6@^9#id)8p9YY~o>V$#sew>w=Q$b)aKVp3uqrPiAELacrCLa- zu&Cu8=BK+ToE&-WT8|Da85c2{Oet)&2#e(2Fgfr+4sJ(?1Y=DbTiz0Z!84#5j9YDv zz=D70|M~NBR0O;irZ?V*iI_lkQo+ttcz@T85j|^E#0+5NdeFeI0&21+Yk@J`gmI5H zAju~)hMvc`he{J!9g^IHL0cgA&i60__uPRyj}gcq?Jz$&GXmW!#utI>Bh#M;CNf5h z4^3-z6K}gq(*_QfrXjgEOp6{%(E&z|i|9ZiIS=WS+i4BXa0hN-w|By_Napdb?-4{- z&Be#xoo?nZ7xfTSUHp6!ywf_Rf5flTEyM}4%+npFli4%rXi_U?AOrMy`cefv8DMKrB50bfXEJg!B#oI`@iMUhmz=J6g+u_mz83`7e-{M9 ziYl&xHU$KY=2pB)k>Rq?|G46KuQji@SXIEEGWuKg4gc=w$D^=QSy=m9gC0b^sEi;* z057<2;nnb~iaV5Q+Z=4~Sy6E(X#vK5S#bc;bfGkFR~$58WJtv!fM?I>>MkL7bCZgT zDD#*RWspAO-O*GeSR8?NVl6)C?N*xND`D+Z!c8cD>%6$m0!7t`o$Q~%(}Jg{1` zr(%wnLX-MN1%oGxG|ec@;Ng>$^7pL3X6E1nUt3a4IwSCZs!@tLW*R$_(CC z7oksOOs*V(-s!DqLpf3O3fcwRZbRD!2phxPJ}3o4p`smyR=lmX?%plduW(F5c4E&e zZs-=+gGq>1n3FFLviyb3Sz5}7zL-@q<$dWBK{YIs{iNEswEp|_)c>RG{ ziISxh?|-a)bM;IMQ^MHds-|enu6!^U9O~^Hdd#LMWT(RNY{}!H-sr0cBhN z+_Dm-L6q;*y9!&)Lc2P?DhnXF-hR1i4rn_9T=Yj3EPPm3fZ;hB^ykc5s;X%06lV0K zDjIt)Il`-2jLuyS?Cj1}9D*chUt0B`0UP?N5Q>z{gj$Ebh^!9hst}s%!|S0x$Rko! zOF&!hFTy-o1-r$Zn^(L_e1_IyH5VjqKR!g zzQUfsUU^f#AYEZ+QeO1pkVY%)*~A0hHIp#91#n#13LE2o*yn)nS-rxBbZwiPZhSF7 zhR9f%y~5rDqOSp0gshNX?7Iwj~!LFJC3`@B<**kpJwD5&4T z^34GIPVmoDO=h7_b@mlohx67jC@d|;Ekr>kVfUJi6!3(k&XqzzJ);- z`pV}*b;B?CdDX5whhmE1Iv@I`3%`)W0{d{kig4ECMz+{Rj{rD+8R@wifK6K?&pf>@80w!#SWCSy9e00tqRs z0Wr!Pkir@)g%uFRW^FD{AqVl)S%8*EFZkr{NWX*L-H4t=NT|AX`KAE85_w@YEYpUy1$To85I0|%+pl>p%Q>eyETY% znU%>eu^l47rr(n>H;<%CsrV%MBtd@(9z07vMNoS9#xFRX?EEbmYt@nb(N7S<035>G zgb;Dsf@{fxYOJ;~;4Q24kq;MUm#AdU8|7BM{3vYlP$V*R1;d0zF$R9}aEeo^!^;-~ zFzu0hP)*(vyfjWBh`0-g^%Ih@{W$VrdBF{dG9;c4TKCB3MXzqL_Or;sXLASx+@jIe zk9k9Q+>^#94+l^2hFl-sU_j^Ma@tp&U`2$ns}4Zh&E4LRtQs}wqEhwbV}a3+bCa3Ez=YBO4qLv-Duz5rj(!};qu6ss za;{R1&ms8|chq90dPB02|1=OE-fGpT)E=k;6Y&jlLe$}$HzY@#rGl5>`q<+E^?rRK z;e za1l4`2v>hx;dB2t*Iq?DR)s^bEJdtujl$~R*>~nns%Mo7{Vpc-nr!_J!IBl58P=$Y zK_c5DTUYXK!w@Vgga^MQ6aIM?_6Tx4OY8FZ)bOa?{W+g=}Qk^1vFHJVtZNOG|3s_-7u~dX+qSU@gUJ z(HJHj=xdlPhQVPP^YO|bcgVkQAe-~Uuv*80oR1>glVI3Lql3I5_=doqgyA=`IlD)Y z*c+GxPdBnFftvuNf)p-bG()voljWePP3ghAn={LbWDMa}c*i3ZLwJk_Lzu%L6%3vR zJp2@4*mVlum-L2=0nFd?=!5|`mUwj*YBT?mahwbLrWip?9+Rd}nB7f2EDgg2y{LGYlW;dy0E zz$7_lGc{Kt+HClo!5z@rriL4Sr!4pYv|rG{9xsc%1LL^@=@ft zfH$N*8wov)jmgwatIwuE9~;|yLn7FS6fHk|DRgragwNRGbp=eZal4>WI3*zHA$cXr z>sn_5ppd0r*9j7$^Trl{C%VgZixZrUeMCD{7XlL$Wx;9^8)xX+!2}BJf885|mz?&x zb^=dVicWRyXQzsBjAbnJXa4-f-C7KO<^nZfQj^y8Pw~3$HZVM|>poVdEy8s_U|PiK zHeS~QfHMG>bnvbhIG-0@~r^-fqT{oCwfpp9 zUYFkx#ee2?A&`&)Gx~a6GfAW6+tk?W>duzHlE%MnDgq+S%4A^AOvsu!7yGeZ7pEY; zh)i`6J`0#?bYS*}L&MG&7_v}ZSSXHudbQq%7(5yOHb%yRAH1$Xko$Z}5w6;LT{6@~ zr?9uddVb@ani21HwW?9=FJVASfa3q^9MFs30vdcDxAHexrHjF!HB-3Y5-(G#D_T#f zX_*|lDW7`<0Sibgz@Vm7ZKdf2oIqj2mVYJ*X?pE+++uUKiH}*kZWWp5NT{T zejV7FkPdyYfz8-#yV4^eg@P}du-MUvWTDV}33`IWTAWQEd0iqJ#9^;*5OKcK;)H5( zoZ1_h+E+;JJy6FhP8~k2^&9?1txx#K=vZSNvoJIqCHw#8wZB7cbb}L1GSPG-(R4k` z?C;GmgIN-mk$cabUi)Xj9IR9YN{)USl}(&zDzildVsie3ajMt(3KLafwAcOz%BRPh z`uL*=f88cqPba=XE&ES?X`=P%aacD_t(HUt0il*I)(z`tl@ z#c;A=GSUXN$AL38dhM5hKbx|2P66n}b5YijAzu4qQ#cj{J|(Qzed;JDTXhy~7KC05?T4)|%>g|3SZG$Ah-fyue^XcPxvT zj#q#tH>fR}CK)Gm*~vJImE*atlUS-$moky@WJJy8a;KHXY$%pYpEgWQ(<#sml7V|D zZ2x2)08^B%+u53>Qp&FofFj(Uyswt&4PDfXnT@EN!e(?vK@ql`!fFlpubE6fej=IY*_jg} ziDpH({RCpuL*rH%YQ|qe-37S>bYEzm<2K-u6Sg-q^o;~zU~u%onI)YkmIp7 zVBcq4VvcT|>Dm6Kbzjux(0FpWMZ}UgVq@#4NYCq%67TCp$M~tb$|vt4>d(38Du?*g91L*=+L8syMql8tan~TLwKJlIvlO!a%O&c7 z=19drE*Y%}$zGcwItFy(ig)a$)YMY5 zDNYv;z>0<3rh04hOI*UOv@W-|L}UG*)4HCT9HiE|>i@3E@YiPa6fRkHxtzhy3HGeL zUb`2Z<aLhFV7nK^@c(IaugqkXNk8mu0Ph9R1j^U#(JG&^kNBGwZgi^&uni{!1HC~@KG=`1?|N2%XZ(_9LRkjy zwIHNa^@*kUo>CQhEhh92CenaSmPf_#%b~g=*$skbz-|}(rd0HuuAIC)GkEcN7vhwl z-|T%+Z$IAsir0#+QBC2p)G&IBnHwCtjn;NM_BO|EiGbaXy`NXXXKv7?ta7gv12xRt zfy$d=6O5J5l$L9qc%oT((;7}fB1|gWGC$nmkQ)=_wZh5mkZ~m8z?UnIs3Un^D-;E3 z%$q6MtgZTvJN^W!W!YeF50fNlyItThZu>tt6WyIx7a1_u~p)7@GH zLH;l6>ajXQbB{mc{guL>N*9m%tLR~&QZuJ|zpqhoex#$Rh1tCdWLMyOt%GsR3S<&s z5`8nS53dPx7dCDZHs{N|KXES{JFpM(p9_HiPEQD(Qy4kieI1uMn{*g3*{`6R;tJRd zbd$x#*Yo@_GNuh`=7(~v&Un89K~YeU3tA9t&eFY&TcHJEl7j3F3WBg9q}uzx4{8lQO|#ifll_-<$(Ib+|RIvM7DSy^+2!}90O zMpFmD@@d+0>eaE#R2uytI0TyX9EtplPa1~S^2#&}c2KVFgP_6I&?cJP6nGYaI%=eU z1`Q56y|_U#hmU{LJ&(W7xaaZD8uvW@1Gr~RiTF6TS$ZNVm)A{ zet+qra-45HZ>suHJfP#i2VONozZqH zOy6S<`HE;H%w&lhkXRU5FNreXSA*WOOBOAIW~1*hasW>s?B&M7+=Y4oqtjq*uz#-&y4!b{Zbv5$#1zL) zoQn%^d9IRoD3h-gF&ci7X1irxpBxC`+2m{qf5qILCJ#(BS+zzWO~x1)2&Y)vWH`$_ z_ZE-vL>=xep_)BEnag<4n@@?+&QEM6|a#z;D-GI*96I1`R7;6Wy_u;Y*3XSH^gF1@Q7) z@ue-oZ=$duuY56l4as#$0mb9>SRX#FMui_h-ec75yk`sO(!$4)7|Q$rF_5dZBrBDg za6PPKggYF~S{{INz!%JO3RUk8XjNzF7xfL?6&it=OW%w5+N8%staG@)d ziRhukKg~ND9F82xu)hfSU`|H)ZoE9mUwMHAdf-<>uU+3hMD#L$ZFqm|^U??9P%ra~ zwO;xI0liEdul2$tWS+Qk2Oi>Dpuz_tjn+++&k|fXE}1_TI>MH6_%K8HEi86XVfb)l zp%*58%OA9Af1;l2tD1HNwPKcn8ZBs#xu1*6`3wG(#Za;Rb3kuUcu#u%n(IMb&Oh>s z2xO(#n7<~x4UA$zQ}G(%ZAb$vMQ0MEO`s#&u_OJ`iLvZN+=d8`LpF_gdR{mdaB}oA z|6^^Jy~QqJsPli+h-3$`z@v?|PtbB<#yX(_kY?87q4rRUlb=$Ow?Kv3qvTpt9-z^z zBn9_3Lv7fVEb3{*STq>?y8*0N6WxKNJ`cS(W7DTO6vKJxhwVRV3r$(VRb;qNXuJ0KbO#gcS%Q4~1ImC1K_A$Gz`aE$Oz+Q3#5|k9h(QyW;)Js8)K78ft9;_6bwnHtxo@ zjeu&~4GXpCQSzd|2x_x1pssrsaQrfXWk-2`RxQkif<~0c$|&u_t9503rK8<2ig=_Z z6ui=^eP9Eyv)w#`usxcW-J{aEWLk9sMUg{Q%rR&SccNA zc{J3*k<7we!?uC2l`#lBh>T3(CuLbPwqNLPpRx&udfz z4ypch;tRin*Y1%U`Z;MaorWOUzLZHeZBhb~5Y|b~!dw^8JM{lBLQ^r5!lJJoa+wVLu^ko5O`TM*Uig;gPVn(7a^tes-#dD z6@FF zYcsk@MmZaV8l0Cu5|Lh-#AS8G#BdjQ0s6zZG@J^XcN znbqP~*TRd#Jp85SCi*h0fz5D=YQ<{lVRoPJ@L_VAKc}!s?@*$cSsp8&f3hv(zyj-jI*VpER^co!(&Oj#TNPf9&EDe zc1L#ca8oOKpl;pdRRMaOr#!N~RdmGk3Bs?iZ$;{+7*E5%<79o0)rPRvm-^%gi}A}i zUn9>?B!_QIgk)#f4NGEIA^SOIL=Lm^;R+Z0sHrdv-(N23yC(gvGMewOL@B?S^nAQr zi+4yo*ggXvtb3Njr8EFP)x*iLO%7y`F1iN}>9z{bn?Ps7%;L&CZ!26b2Dm2O^Das< zK<(AQ^BzI`ey;L-p)2D(((3x2D=2tNI%94F^3)k17hSBtzXuh}dDDaa{w0UOYWOM7 z1!SI8aGGtu@EjytWIeCzK5XjlxYu)xSS=%;5~&~Mf%k#6Tg6S`VP|b-QiNNX?Wsbs zujM5<&ut_^^z7M=Z2a=D^zBaM|EO5y#^t#2r`gP7l|%8Xy0}2B%VJIiC_^hi5O!2N z1^wyiNvg;!SqNU=%>z0lxTZY%qh}$A@In{IBW4I$Q?@VlEN1Pf0DX^f8~ok|Q|2+~ zZO?5U6ow^Q#sAVpku(o5N)EmwQl1P9&s^{TyG&45vciVLJ-CZg60J*hXDO26BaD)0 zP1=W~0Q*&X`U2!a6G99jL8-)n>cUf^){>dv*Y*z&RxTyeG`|)Ozm|wD{-aCA)DgcV zUoJkwkC)^}@3guuGDH9@Fo z8^z%$xS?BbYp5ysUsDiixegWoy~%@jxTCXy4a1RS$Pl#OL%k&^Ld~VU4Ff1a7<36U zd0=ol&cKF2e=@-EyrFMzYk&xV%>>orZ@sOk8mnzIFtYtuI`bUR>n8xs$6n#e;8J#+ zDIEmgQTnjIaBiL|9V{S#u_$%aU${6&m5u}M2|eQROG7NefMdq=QfQ*|8GyUIrBDTy zdW@_}VbhF#sFu7F{G0z9|1L~{(MDEQuP0+=ExSH_X^BD#5K44tS-k;ZG{Dw5098&` zfO}2|wgW(KLiI+4kIDe{yqBO5%$^9)TGj!UQ@sheosi~a54^mBY=EoYtiBZ>zogjM zw0aA`b^zD@Qe8#RUy!Y;8MM&6XYH@XfD^E3QT291+O(_|ToDAjeXBufZ}kpS?9SHJ z7@f=bx!BP6s&^T%cR}@T!>nvU_3Z>P7|ZZ=p{l;qWZ3UjA0S9~Uv`Z-@a#|$)m)WP zeF}MO*ytVAcbO8&&sLu%2?{Lb=)dW;>ieDa6r^`Gu6~?p{9bupsjB`PVW98sRQ(j0 zDPfJ&KXr<1mcf9I#3L4C6_jKtk26D(tF3632HX`voC6=8R&BLq;RzTC)%e*wR+f^D zZXnDWWTx^jskVkNkNiFq(vfvY0gEtTzP+Rx%N^lDhVuxf6cU^-Sdc`0RE_N(%^Wxy zRn9*CRRscfmA~OIv;NzwF}aGF@%_tFFCu9zBY3Q>fV8tEr!^7uGU3VUBGAv%Jm+&Z zJoZ+x%}I6HQ>gi#)x|cVn6}M1k)C&_*t*Di08{uUDZKFt z<)4xX+ud(_vGok7&H{#_ENm$)drEdaisgq`AO`E7zdHh2gZC}}RJ?CEy>Izz@JEv> zi@63{9+#3mw-BPZK)e=)Q;gqZMJvE|cCLXZq>uo2=9Xh&D1Cno4CX`^zextu@W6TT zo1EX!!TSamzem{t&VRP}eS&m;8}BH_>$ukPXZ+c7b5-%ZN~9V79CHX%+^y{LNzAgj@c?1V73=3@8rBv*(K$LK9ro&jzAEyZiu>&jX&K3$|l@_~lwrE_2@0P*1u1B2pQ zXn9(`^@4@WaHDhq(hx{7ALN{~PbL>*bg=prw__X(KgA^89;f#f@Tde4*hL1G#i1Hl z?*k3N{`!xK%ZS#Tj-?gPKnhzkE3V3#nMrvj9cp6EQ8?z}S$u%n&)dhvv!yI;?$&x+ z?e@_9%D(8*dsc6?(T5V*Z@q3Scf>IIc~-SGcoAi#-v8K&F=p;ttn7@U9nLuzJ?xy6 znvBf}*H)`JS+SlBKJ3giU&VuB$E+y2gL%k$09u&4o5_w#P<2&a(GhsNujO0QA`YCR z{@k*;s^}!P*&YW${P#tV6HEWR<8ski!T|fH6rCdr{TmXY7n4G&n1d;pLdeQw)kNH9 zQIZim+REpA+-R;Oc?O5(xHFPMwkvDZM8GGkq>vqer^@(A3fToNxJQY7mZT8ODdGuM z?nw&4q*7-m18!i|P*IHLG|Sv+)x2`_NSXUBjd9M;{2M!he`DU83MZVC6p}}72pJKs&OtQFPt^i2IEZ zmjz~V>bWt*U|1|i{MZtdETLGs0Uc`~?ronZg|w!C!1HH2=kAtt$0dMATs3)s+s7n@ z;J(C-&w=Y=2#LOui=f_qNg!zT-fj%V%(V#hCxgdjE;y4yu)e+V zs&0=&Ton3YBQ)96YMqRX*5gi5(_MS>ZcroO?oI$M}Im_O(9NuWjd zEPjQ0A-iAs`XrJVHqcv#_ZR=0NPy$oEPfsS@QlAiEq(*QWZ;%pEQZS!KYQ03i{BzB zZ}2XD8wAt+#U)_%AAtODvAbIQj-hS(>tf6xdO&qJxA-+wwomu->;*SsdLO&ZK5Jn> z-<7nD_m4!dijEx6Omjd(=(HEN{maQ)L7|b-mzw(LJ#zY2wgE#U(kQlQa+LhMyvcM)J%rmLXZ?YR6_+kRBrT zd@S4oT_$+lmKF@(}VoE zL4XEogyF9f-0>N|CiXf!!?hM??*VRPtZf7@b7)O0=8mUB7#W-dus4Q!Q??CXXgf!F9ffRe<=5GPw-kQ zp2f3nKBF&&#I`YPzn2_8a=2HE&sk#IiAvPe)?j%o5Gxx$N=+S!WdD>{gs(i=o{F;! zRoWtUAlSenr1GEW-=bcPUhIB6%G=y zzi4ix1dxXpf+pdkkFoG?s(EZ23gW{_`R-%t^8`}C^et@UXae)y$JDQ6^K%UL9Vf!K ztoemJS83b{{gB_ya{GZ_2I}j{C%BghCi0Ho&AnNGpZu90MAT)+<|;Yfy?K04M(lsF zT)<@H)@JnKt%Fa3aEM&Ns`=cV2bN5U8PQR0rxCu_G?>9)cgmBSn4f{ zFskMHz}o2;4UOh9y>9`)_N6)t;Jv>Q#1cKbv|KG(uhdMxS_9ka^J}8}ArwE#-^v;F zZKC_I#k~V>{lt0;5V)Wky?3zocD;81wAni-#yLg5#E{{T=22N^B+6HdN7tcva*xCi z{4N2Y$@>yRdSmpj{Sx!=@KZ=oHqObV0?Tq@a9Lsq3=;3kvdEVA6GJ+p$hxi|i~JiB zY@R6&I9Ocp_`~AegT=$axB-h7nBooU6bBqEE_hQMdPVJMQt~^Au3u1izpf9k%Gf2x zO2k7B6bSh~(e;N?Gd$d{uEC(O8yhCNc)NGqlUg16b37hz?U|Hl^H_NuqoiiP zBVj~>wK&36yiY4*^p{Tj|lDJ{-L6$pi=rKNDzPqYI{Wwu3i zH)ki>H-TBDsgA~bl)wG4;f_Q*UJ};&#!xxR#4CW{OA&PzL#G*6L7jLc(GE4#>ohgC zii6aWh1wb%P2|HUnV$hJ3nbbYdF$6fI&yCTc!!ZLx{h>h!Pb$kom2tyU|70-hYY(f zWJb*Vj7I`vx+PlQlLno&{(F%F>7X1sPuIuge&$47A6NC6HydrBc(6XO)Y?dYF3}n; z32Vb4sG#35oz4J!JYB<7`LX(mjP&IA-2aV+X*73yEUM11n1 zrq(DVNIeQA%e@L+u|y?Wh@&?QhENSpBwCq>l6VJw)lZ4&b;tm?%c4XJ9>)2 zc1dPibjjTHiE{A`tA`D5X;t9MNa>Q)TO>=yUYlr#j0)_GRA=&m0yoyzr8?Isg}i+W zWZ8QCH;FY;p|ugeZ-EZ1AsKudm?J|x9(W6lzhqv4N<>F&|!CN}&dY`}l_@;ZD|l3vskt`K0Daa0`ln5y13#%}7AT zYuEQ%I8F<(DMA+*X9_f$%N*I&t%}e@Xkh8ch3TL#2e{_#h139>ow#rzj1vA49LL|a z5UZKWEy~)|%`eTmL6Wzi17a!{_5=Qwbnc%4#HA&ho3fM^cnn09PLzGk?BkAjPBz0g)`bHf|1=f9uo zw_m4b&_#!T5?Hs&e#7ZZ4I#hat$Z6gA9I?jS$iPgE>u?4ip<V#G;S|@1v z?0EaQdJW%H>Ri4J7l&qwG9JA}5W*gqCl^Pr=S{4rf5| zw_~Q!n~zPw3|o+#uP+v&o&{Q_>qR`N=6a)`Jqe_ucx+Zn5sxedV(gc1x2mm3K*nEF zlk*vtaIUDnRhT1*wqut)Urrk&O7mvr^J<|`y`rf;5D~~%=VY=00(MEkaFXxpaF*jh zRBXXR`PQ4L=X=coAao2v0g|0R6%j?}eB30IdbXZ|O8ahR+S+FLF5n?MTXlobqEeD?cqJdKiVH6sjQV0(aq?q??E!;IENW!sXZG&8A zq_4(}jW9A_6sJ&+Yl`sa@+~Z)w|;G!L6}X#Y(cyjGDR1dZBM*4U#_>IC$`Nuh2SI5 zc5ePk-k8(0CoAX|3`8YsT!k4C(a|E%V8TN&&f z)jUfofEgWh4$e^WpC^gGzyZ)!jlnQBS@6ReDhfiSwGbNo4`ES?_8JI-O(4d0a3cSO z!JP2JR{)R@3(n*-;LanchMbkZ^REq(DMHFE0NPL;s|v ze}wdM>#lu9!q3=PQS-7B<|5AB{um@Udp;o-^cet$>`%yJQGl(z3Hgjz08ZGLfRQ3# z-^~fwCPw89brQ-L>VTln8wud~N(I1KjS`kA_40?SYd0U~W%DE}>xqOf{d0>|LIC$f zy`ZdoF#)@Va#U3Pe8Q~+<(wm7n~|Wfeh?h{aS*&=eZp;qpz2`40|wkRFyS#1Lhrbo zaKT_(w@!GPAU7g=!#L^FuP#sA>0%fK_vb`vsJU^664Sv$Fz#A{TP z_0Bilc)7)j-hdj?DC^Ggf06Y$JX3;|mD?2!5^N4;4snD>A9RRzyRZqgbC@IiWJmbC zpzue6!tdHy@f{={v6U89a5YPI~7d)J$| zEUMD)0@}#ABROxLa@)T!&xa2hdd0YE?18J=-IHX0KOrB^3y^Iv;mOL@9U3JLx`Vt{+I={Tw*-( z7TU83EE}0!vOeY9jyv+9vOB}$?rO)~HH;AKmK|YV@?#BJNS|u3qGX4`HV#5Gce@&Z zzJj-$cb~D+DVSV3-TfHakO!(B$}V~ue2%8oNJ3giNJY`|^5LiO?(uI*1q zQ0$bF#V{fS@78Q?YV|I5+s~8eeGuKV8VOz@V9umaw|y^iZcjl@>+VQk*5qA=?kF$L z25{ux-1ehj%k_BXQnwAOm&=_ko4M^L3G*DQ?tBfV@MEzF*@yEynW9Kpmv@HOm8Sgk5@~z(LaoA)_I)StK>Fu_Ef+z zkpC)v^NJ(H-p{H~wmTG-y{eAFx`QJPKATnwgTMVdR!6Zp4-L~T6<4%CvWe(|DoaiCpNXV)JB6r zRHPffmrEGZXpGZ%os#>6Sz!H$M1ErwwcO-Yw{;1^?>mf=egEyYFc{>K=Ea-c*1xF; z;QPPgX51@#w5dJZ*4qY;23r3mtb4`!%=A_g@IM=xJD+rOe^V}4?Mu<(S)V%s?;8UQ z8g9WO=!Wl`^*=O4|ASehF}5$rXZxQpPQ!J+I*5i2obAR#7mx#wdSNzD@~p)E(HvV@ z6HOL+b+vJ8*2AE|_?mtv9QA$}bj(}$j_iutdKAev7`(14{3>AoN|-)IP;4|u!(T?i zGO&Q37pEBW9g2MFwl1JdU+olG3 zzW@m`xHW4tZP^q794rDDMHo{wzTR!Et5JP?z$9|q+_926WZ`uz43(WDf|UY+Lkl(i zKSZ!*Aize=@Nz=9b1>LM1LJX9>%nIxCgwY#*%|Q!(g6(QcZ+@cBgM}I@k>lNp@O3D zlmq_B!=+a2gyp*N9IbT+H@7GQ;>%zI00$cY7&W87ofF&$bgesn$mCTv!f=wAc|{Ir z8ZT(Tl$x--uLvh-!B^3DgVUjx+*SdbVK@~CCvg(MgR5cXz+^=@$ZD}>#eOY&z^$(l zy4YA0EG{<)!1r`Bu*?`Y`Q27(jYgYSo*mwL~_u$ zJkaL0t|J=%k5{T&6ZePALaCo8@@5W`9hbZY(y~%7a(s5(JZSnFA#y zN0-FPQMd95r{o;J`;;zusD&5$Ap@^oA0NC;Rsp7)#AfqYj!Ga@Hj`TQ{6olPQ~Zq4WOCj8MLFP1}a2Ye;_$XaBa zAONBzg>e(Cu4UOTjVhAnhk-iuAEtg)g4_*X7U9&Lr@6hFv} zb01jwC{poyuL|Ur%Wg%lH7p>nTJ66l+IpC?t?RC6c@gVqiCln-wvJJoaGOVYnX<#V zXzREW&m7J96Gq1~PQLiOZP!OzlOXP~Mxb2xU9>gLzyngFEyxV_$16_djM!z&*kbqg?x0^eZH>kU3S1iD?)UuWLsC8(HPl`@FHyZvn2MD}{HBTTZn2T}2r#pfpqv~wn%iO%4v2l)IPoMW3yCaavs!T3bo`($ z3u}|IC;-rW#zau|=4MQ9ffe%cgASVyv00cUT`;^A`fdM;77~BdsI~`CLSFkh(FQ*3 zp4H4~+Z^NU!vcQ#%_Q!}sjM*M&X^;`&?Q;@Q4=aDVkJmUgDIV8h+gY(uEi3?ZwcT@ z+dijk`G8c%XfVZQy;?x=d@Z+CH2#(6r%pTy&P~@dgYidJA(B1QG#!##P!Xic&{AbR zh~$v{EvBI~Y%J^QcKk+NfocKMR{SiN4^cqqER+2moNFsYjeMEx#0iEBjIJNSnzq$G z-i@NG&EAVxpd11vgW5c|WZ zo0lM0{X<57ixDCU+J0nri>@qLqoOVXmqkx_^0aO{GT8Px?peUS42sv3vM;vij?~_h z6zC@f_jmIDKr)cP`v7L3&Gtn^Qm0%`?1+NUT$tc70#wTXW9&?zt16a$zxO^Ngi*jGz)1)R5P~5<7-TX) zWKaa6LFNn)LXaR~Mg>I;D1s;gGDSrh1VJVlR8Ub65fKpwP|=HsGhVsgD56~T>ihk> z_ep}^_ttx?MNV~9b#--hb@i}&_rATsG8+8)j0QX?+0-9$vmSsnBH-jL7F0KGIJ-fn zB)n!>GRs*);Ep{F1oBZ4-c)TcObmqh2F641%1vAN+)9HShtI9hP&=<}fW?VR`Up#d zDdkv-0&70#(RY1=Zshy7q;v<(YYFf&9S%uQAc9v@wTK1{TAQ|WH&;VLbRkL1(ksc= z>}(K^>YIlRKv28{**XaHs~G~xC(u8TYu;78W~WN!cuB8L&N$B0JlddcsT0q9!|5l_ z*}T07sdY)x4My%@TFfT1mwt-&t&NYjZo;2N+6r}_DrNU^?B9?ZA_!nw#9h89+U;KI zHr$J(gA%+&%iMx#pbpa5`=j0K!99qtCCb+diYe`V7K%<{DfnJOq0`7x0V_hlT4vFK z!csS$wXm+O*^(r;GY1dNxkfj>x5HgK5U#QWHXq&iOvl|ifej_MA$x&3#kgg-s8#+# zeLoux-ur6^w?NSJt?Rvbwi`cP{NgqD-)PTU0vodVcVj(CW^CKC%2c=7?r66)ByFIX zHS5+1T7VYy1y=$tBHC>a^9Rbl8vH=BVHv;CB#92u1Pgb|?;}I$C&(QCti7{h>uq4S zTOn6bmjZ3#Zk-bzD0Oy}tWr1Lx)4kGJd2cm%qODY)(!fzOMmw1&s+NQ5w&Z$$8opm zBEqtIl|Y%G1AR?4M7xdMmuQVTS4ATa#)HFdasU;`%q^xqOwXP$KHBx*&^fx`7twBI zm~=#N?DS|i!iTdDM{{C`yx^-|5v})_3_NXJv|AgVN9j;of7y%t>&_bqk$H@^?zSpI z#q_F(iWMs3IV0QWY8B!_tdHt0RPCr}EzW$@Afc|kw<4-gsMd&&D&x9Cs0BAxL_H+b zRSD5<-7>Bmv_bzVCsagFw z2;fsE?k2{Tf_i#bv6Jzv*8>djFE_DU1l#AyED?*eC;c){N4m2oz1=+j@WX;eL&#Y1 zWga1<-*2qQ7-srTzi>K zy$+YT`O9+Yn6|lq87sVekTT<~hD^qGwlf-@s;D9HIj*FN$5684?U06f0;J(IX?W^y z8qTm9z7pnZ_%B(iV%b)=S7NPhJ1dvdr<&(bucSyTM8A?L5#?m7I@Q#AoAPCdodv!a zt$r2NJ9B;aShp*c)HACw9Mlw7vClO-#I*&kK-FTejIXufW0fs~?bLM7NZT)I-O9ME zw2it52(CBaQvVQ7JMmcZIiLKEAL)pY@D-)&CvQ;C3fio6!lIh)Hl@lSa;XG;wYzjQ{ge!z5719 z9Rhd5k?=g;o0PeTr|EaVWI)M`9Ev==McMyI*eDPA#6KylvUTE?8( z({{)F6Gha^&s6coIqvfZ)R)gFfc%Po9RVn0f?9A^Y82LxV;ZQwABzeT9cOena&+tE z{_V{8BC5FWIqtLfqLHq>933ZsC@{K>0H$xF`%px~2%?04#)ij4IFZoI$j~=UZ zB7GR0k@TI0cZq(LDYetAiu*6eeXe>)^ze}ADIw7hjSR7ti>KeK1YoP18c-q2R$d|Ob%1?U*~`ptWS;{wNyJytiSXx* z#SwQ?>yWr!A#u49XIRU{Ny(M}i+zZiG`uc})}&b8eujSY5(RMQrRfw`0gRPPh`Nty zoMv~=XUfHhLEv6x@}qwGyuzP6#`b}L+|S%$bfBl>Ro@E39A%2gR;B|49fLD(!9?U3 zT#k=3S0P2@%AXHxSAii_rdu6%{Os_7aRh!SfiwaFcSib}DG-{NVr1@YVwKyi@mQm| zx^8RrKy0UM_@pYdyGbb9B%ych_p|jd*-XE7uPdw3v+Y=rv0mLB3Wry%l(NsV>s_ww zc4LQd8CbKBi_r7v6Y&Dxk+}!-edMa%SUWB`Kzn`&(T=sxtf336!wBd@KEhm^SyKm za~c*#-|Dz8e60an^Y=aHsnlxLm1BwoJPI)1&~U3gFABx#Y0PtKmFG@b2ibFsR`DWC zoPVy=$0^2o5nYTPe+cLEDE_TmRO&p>tgzw9%5EbHe@&)6iR^WcBm1}jcJ~S^W0`f& zaO+q4O{LCjVf3|HmAk^uhkU&ByJ28R_R^Uf6c$UJ=eO9d^1^6}lFMDi(oV}D`tI|n zHQ-8^cGuDr2qEV3&j`jZ`_9={l5l{TqP*{gwIK;-mHD+;im8D?Uu)+(l$mwtVlDoG zf1Uw!qgGR<)Wc;hR`s8GzhZ9oXT64pDLaxXG>g8S+Q#ddO+(CI_yi*4Y%`$8Lg*cR z)N%L6QR`~?K5BI|EB+T3Nc&8B+P5TnQkZR3Gw$uq@$tF<-r&86PgJAb3`-`1dAu5- zaovmfP&)6PCQ3Owx}Zi;HA8XY_eU>x+yE9bl+{>j54UkOgoMwI<$#yG_D<_TWAVT$pvzarbgr zoI7b692Y4rAr<~f#q5yh!#`=h{w$ZnCuG8^?kd)skBT)@#A5N!=f;~j!-{|GsqRm! zU&qUO>~`Fj6d}#!Z@N5R?QqD!|6YLdA5jn}9C29Qwl@}>JSU9@wf+X1|6t`15zO8v zXRpLwj9HZR^~1KHy&0w;w&b`aU9I~1nb3ZguAVclomQYYc_kS&z`nK;U?_zil9^Cs zTpIFT+o+8$u#bgQ$y70~?eWn&eRRe&74q6qp+lTQ>9UBLSLz%jSSC!0aNnhAV=>%B zI`OzH0XqR^3wQ-!lK|q%xc6n#Nz&tpQUXo@Xk%pJ88&g#Ofzt9_T@sMegsvBRtG0p ztzPaOQXx}X9el9NR%KOZSS(Zvn5rKn;%J5X^7BZW#00BoiKMZnP}N`7cQDlowvGq) zhoqT}K}(P{P4takOov}_B&jx%c1V(JFG);WZF>$idJ+9>8qy!(}r;LLhRuB7m_8?PL2 zrRcBCgg#4j>rT^6A+J41CDuV%CW_5-5SJdnmX32UU5<+?uNSBqaB2EqmS6R_-MXY& z1>b)~wMR<1OD+<@Ak{9WIp}-ng*MlIY{O&peWn{Z3HzfTlUERPyl7U%Ui9Povr&I` zDJHVar@J``XLwld?lT_5#M!G(_bz&e7eGd^x?dWEP z1LbSt=TjJ9{1Ga}M_m-kESUDRv#9;mglZ>Id-{b$MYNF)RJiUL(3w>DV)O~dg$ptc z0n)4c1C_cU;5Uw%Cj!(92hjH=_MoGdTKlIVSdPm&{clUHJ;gTk>|gA&q?M>?Y+TxN z&?jyS5uf$j4dE|1c0k!LH*j%Fas^bw7w{O3H2c;5n$kfq-$**NQsP3Q&Y5a)M%v_X z8r6&bz;O?>rCN>5q0Oa-@f`-DrN?2Q7c}bFnlAflTiS8y87laOMyW|`ue^X!8fCU- z=J%>bjYgU3iaZn;e@Z|nfZx)5nciIJIl&1gzbe305H!wY#7N+gqK+Q?(B*-9TOPhi2ttkKMFTM%7L>f6b zM0a*u4n!%7?JlY6O%chGM(xUrZXSkaerRIB!en7~se^KCxkdBp&4FQbrWYA0+I=j5 zsX&A6veIKOnv~OMUi9aV`+6f;X&#n%>@b!XD1c}?VYUD)J7Ki|nrFf;0T%(j16WDN zn#fmi-Ic7HCXN&k3vjowEg|s0+d^UYiI1DG*yyn1zE)diUfGRmVX-%QI&2)l`CF)_ zCS=HDL;Xq;6XY-2}Xd5A|#6+?W-l`GVy{^_zjSII&pGtl_+YHAVMiy_X)T0A^)aq!Q@XdK@XF2er`55#G0TTdr$V;2VQ^ZuE?gsUa{G|&$V{ba7 z^vd2y$9-cG?b_uK)Nhc}B%Lv!%X_qEms31g3nK`3-RJXfjQZVi4{e9N>rrTR#jdfb z>qoG6{Q}gL0(j^+dA$I7(UgV&-2wp2bi8gg9cO9{sl~d$JycaF9Bt~OiuK)+N}aJG>7h{m~I^)Zl##S-eT=e>Ma2o0N)G1%cdDAqX4cDhKf%!%rgLT@Xy10Fk>^3 z=77;bk;64BH4RhSX(TpumEvL|90@eU%vhdWg5LbM<@c#g>FTg*= zG}Hp$h!gu-Svc5Je~6^mx1q8h`;N-E)Ih_&>4SgR{;BA9N+W<=|I+A>Vsg=Y;W&#S zr&rd)iNmjA-7XJv6uc_LLB+Ho@i=i&lp6(cEW|-25EZxvEdXevHdur;2R%vZS{v_7 zwmjsgMDgs#J-jZIjXgb^ZMfXUaD=k5d4aBn!zx-eojRy8TM(soI;^3HsC@Wi^|Hkj zIA42YUYAug5F?6Hud>Ie^=2f+biwUz-Hgbimx$bNMS9(unL%@JGgkh!$$!KOFHWuw&nTIzB-Ci)efjxk>4 zHY}3okYS*-tvU(!w#$aFi2Kob6xrz(|Eq7UBl6taIeM*oFF?+}qaSdExv_3^u>lq> zh#uqWL44PR(RzL0$T>a`Gt!B^K_F)V#`V>m#^(ISJ@cXm08R&6qjGc(3_tN$^T_Es z#F`z^gBM*KxeC@Rv|0UKelmyY&YJLSkxHE^ z8evo1l`tJ)=eyo;OTe$+_t#5Rh-pq(c&@)*@{?LGS&+zV*Go*^R!#{Yqz3(h@0qRAQtgZuWIq54Z&Sh%Ub0YmkdxmbEuIR!l;{AvaYEjw>(7&4>q<;zaP z=8G|ukQj5U>hdGuxScuecdX?AozXGr`NBB&Hw#aNIA2$_Y+D>oAv&eu9veJh{8Yy# zW%JqR!{db3t+;pG86F4QbmJehFND{3ixD)6<$g=C95iPg3tY-H2P%*0ZI-5N`LKYt z=NpebcL~NGs0`6{5N!19f@gh=-)X7K`AE9vM#1`T7relpURP`#{d>WSVgl^ZvfvfR zeWxX0;*5g*QZ7@+e+ym}2zJ`z1qT4<%fC@&AJSIZ2$Hr{%3o77%Dn^S-7A6DtqBKduQ^(J59xa1d=Z>2dpn~WEl zv-mK}A?G74afSi)y7u^=lK1j9*99HLo=`b?m86t9n^yCCPGRJDV{=m75UAyCZ7^Hq z$CcFkJGb4&gmy;LxmU^N$t-h}obIl~dG$f1#CJ7O=$B5%jGmi}6LFM$AiO#4 zl8yJkn`}>JCU27lq`S-|@48LN&tmxZud$X|YubPX(eW!voy`$6?xJKCMDMR90P!3J zcNBmVOrI=(iQ05MBtCvMzzPBF0rdQObJ;Fr`Ew*a($TbQ6Uzl{UcdjmrY!b3&!#i> zIm-LT4Q{=izfmD&*v!IyPHUv|(2)%6!kYPFCsvoCqZ(#$Vcs8L_OqEe-P#knbFK(8-JUuS+lSYtW4&>;E92m1yfOnfy z2za!yIlj9@!;>r%*J=s#t2$|b3&$?$EEji*X~sUE1j8aI^Me|S#Yu;PVNs5mzMy|n z$6(-R(T1709t?xu3`!q#G*LVl=7oaA2YoKV*ti~|JFCgKJ}emcvea3{O3A6GuKU3z z``KR55=*o4odjK?Y7yr_oW7k5O<=u%7wYIUzU%Sb4kK{J>0sbf=+xX7cp)V4Q(xd; zA%Q|5a7MfY(s*S8t*EBUf`MJ7&J*ov0L z0>Qv@K4RS~AX0V(1J8q4?})sa)P7P#rWpqe;)Qa=ndRoot!0SYtKeWCKHOQ?+Xe$K zm~3?4C(?COCX}a4<$> zr?j3pX!CtktDM~1aZv)xk?b)WVGe%Ng!HQuDv~`8slhhs(ks%S>Ix(C=rfv!bt|uME z)^nH`Rviuo2yhDdw=WZ7OS52L00>;*cJrCYs69xpE>cSGU;s3m0M6~^P4iY%ks2xU z9Ua6`=el4(Lp)q}3|g)=YcMd%Paop`iczF*^3z|Dodbbn@1Gllc_C8Bb z46x;&!N7FY4YB)Vk1#2S zo)iq+=eVEz$q00sfIU;&`={>%c$_d5%|@Af`Uz6(9l57BInJHoc>vGr&jF#1foi3F zmeZdE7VilY>Kjlw0)7IRsNIL`Wu?wzdnmbjFi_obKc34ra`t-W@j3HC1h);i99*T0 z|ET4!0srnx_zmHI@}IH%HR1pE5`IId$nTzsD0No$gFiJG;OOHgji~dP`e-|w#grwW z|CvNED+II#*kZ=t$Jo3$)0Hgt^vgUw4ltWWJS{k8imp#*Q_jquDiJbOYsBCWK;^(S_G*Ko~aPL0)f^LLC_tc}2)+6dHsAg-@GTkM|4 zC-165+6!`TF$Ubxcn6S+4I?pN$1&PQ$6~9xX)4l%V$=N}l%H z?yf&*J4;ZL(RO#U&1u^1?xuEg?9o$damR3d_C*HpeMq_3l-G3b)Tc6b*>tW$bqUtZ%wyyzxJZpVoS9rLd*u~u z-$h@pnEj~P8dEmwB2u}$x78y-?|jg4KTW)(_ZUK1??Ht})c3LCr=27VFA}bp_UDP? zrvrpDH$hh*o=s70aqzc(q``PASl1<$Bw9c`8`h?*QH-+r?x%UVcF-TUS z5OE*%DeoH!jyRT{VklJF$oWPTpZkoDGf%kqqV7Xb_IohsoPAZKO58qHs+P!GZAD{*#-eTd5eL~ zbVKF^k9o&BLGKl#1oK6;b6q}6jXCO{Th0V7Fz3sq*&1Y$orUgAl zFs)HXD!X~n;`2tDd&npy(iOKT5ke)yyOY`P-3NtuGSSZrqO?N+D}$iN{3cqDFFNSm z(xCSw?>esc7RTf9Bh3>FLd+5Qb@@6mP}MVjKk}Ts7rLImm;uT^&0^+t`LUMzdAOm* z(_eH_tb(03t}W&wjS>c1WIZsg||;OO6j zo+e6ih~*f3i0Tf^l#2&FOu2xWF?q~~OkYXK40_puJKL(}s;buKy_+Ow4klWMBj~Ca zI+Hg^NT$r6zYe15PE$exTOgfB^97wCPqEb~()h||K`%wjX#7Prt1+S1Xe`YLrl*tr z6^jxGF^$=(L(u(Q`AVHU8p@5-MDmM$54fr`6fN4E;#f7^*eX6NhylypqWqC?{Fl5t zK+H$Kj;(@Ri-s(}A<3hLj96~o_Y8XRqQSe9md$(Dw#^p`{uNu!v<=rU_-$j4HYk)A z!sVE*Q*&^T6XLe6UtVVFsuSZ0%gwiBM03Bq41K6KpRlIh*21poeZCDukPQ^%IEBGJACo98YdR29Du=jp_3A2rREUI)+i^ zSIUfQs65qZ)^!>Y@=}QY3{_wL7yG)MHB?MBT_&%i<9=IA&FaeV*1Xd#r8krWD0&1Y z*OHh#$Nf4PTtDIL87|WprUx>jc*! zp#jr@EKG9^nHjWiy!%Zzsk}3}Q$n3-N6@7nrZep<3A(pZ#{ACO2no7(plTEH_U#(v z^>z#A{VQlbO|D(Uud6_mp%9FrcLTB5I6;cm_a-*gfxzmLU5cE;*Ng=-G+9#caJLsVZ)8L9QQP&+TS>SwJDlv(+cNk z*x`6e^@yO`7KXme`_A3NP5K!EaE5#G#ZgMjGB^1K=P}>UptXlzgkiIF96PHT@=vhO zQe141%R$|59^{GZP`bfATrBDh4FK!_81gH?cM`zFZs_$P0j!_BA)Lb-{w@L{gKkr? zvNL(l9|BhK;4lsM8nQ$g842`VYySxJ4USVXJ;>OKA#hsaF~(({d^&l6>5YJ2UZ!oJ zAA{dJ^g2M|@HtshU}li`;YOL=qu@`H;s;*0k~U$l_JSvbBodVHYwlwFwwPdz3|3 z-awK?`Ex#VKFN}d;BG%zJlZOs`!k4I!IvEO?6rOc<~)JkxqqkvY5{_cZF_Y(93;m$ z1N_-)Pmthpn^~thJJD}r;nKhniq78SH=l6ReB27*&`7vqABTgD^=wSaebC3T2^2cn zoLl1Kj#rSk&c}T#+%zk1yN~-_IKPa&7Wds{!ue$!_Hm7cyUpg+gc_Z{>mb}M7I((S z^%agXFiI{H5QRUEl2tZWo@_i9ydU#u82;`N>z4PcN%0nZ@xgLmT%g9XKJ<`jig6V3 zNsv=UD;V_cJ(}nGS*I9ionp=oDuEQ5+<3uRl6V1O)Of+~B=Lfw)(h@ytz>3!n4gpv z;1r{zoa5X#e%+^|2fz9pZngye@bF~|0!t_@*m8uGlhD3S&{}E5u8jey=ST? znD>3*KfyG#@+X*nQV&8cm`6m|MRsI)y$Zng1FjdGf|4=Bk6z4|?_)vk^_t>1bM-Ps zNr83{a7^v4wQ5GInI|IV8G*hyT3ZKkzL{BC#dN^zTy8I_n`C!UDal24z|6+gFr8rbw2p`hSC0iA{Cg42{JlX=sGXuy=y(L?ha)<~LrU@?0ss0wxGB zIdj{y-)xukX^l_lZ)M?>8Vki*0v~S_v3t<7_LQgHe z9pCw;DN~&m-UEhXDC!Sx;i)gJhwEugl$6x8f+6n4cU#a`4e2DxPTpdYdeqorgYf+` zM>#E?CgVvQpNVXAAEI#9)E4()${(6D_Ww)Y)k`|mf{tp>gZxk(#Ev~J9yZ0p@k0ZP zC@~0C4EEKAT^bZ#*J7l3%*aDBG`OOMlID(#C0|>R9C58$P=h*Yp*pTJH#ly(Aw+Ui;lr1je%u8k%YhGpO^WTYco2jtC;#s<~e9@aW&0*^^PKPPn3mWI5_rNCt ziywBm7_VR&2&Q+6jPnvTiCPj7XWoYtq6ZSP_s8i&Hx1GQi|3nJ*21xIF7@RBlQVCe z0^~-rJ3}3}w5IZl+}S7J7218<*b$caIF_I8zx95;cHibL7Vtj6T>=gPtP{U(Tiloq ze^_N*Q~&SRn6$1Mp+5sO?rfx_OLphXXhZ>Qo0&eE=|{It^|W%*G=GeY!Jb(^MKJH7 z-e&PA&7WRMF)SWRcTv$kBjQ}fh=%>W#VLk(4&qFReO0Y$HR8;@hxpUH-HslA{K`=^ zBOo)*EuaR!;(_yi7f{5>k(whzRBdzqIxDdFM}@1WnG|(r*Ne7%4t0S-|i%V8?C$Ck8_*@7v_ z%zFM_(#Ah7ElH|1@iVOPt663NvvI)%3tl?Yh96%wWSWhDYhUN?B>Qbx3Y{kgKYr-b z4RW2I>4K_jM=8CMRp?%A$XjflpY%GsKU>>C)Kob?F&1jYXNm#V%UddjF+;`tq~qU^ z4ep}dh5spZ#=GMw<&uLH8V6%**7#RH$&;JSG#j=0!W|+vu5;WA0}#0gk*0lxL=Bx; z{b?&m4aprNB$Mt1@o8Go5VZv)Vkf;pNr8qq-6t{yvqTOkmJu1m^s>eIs-`SsMI&HR zSq(Q~Xzeqf?+#1(K69t(aQt684KBK=gube=*6c~ySF|p-JB#PXM(QDWL};h+{0x(> zrA?abKjX{|EgI_1zrnmMqu3zK6{ub%OVsnh3AN(fI`qOH%+5ueT}F1+nVL8^%F)D& z^+orLxPJgMHm+wJvCD`Hbr~Cx3PI8J{tF}#MzY}#WJ|FJJmNl8KGLIRI1c5WF(RG$ zy2dN|c--fHaw`LkO)PbFG%4;2$LX-jTO7YsyF+nbD zYi3vLo^kaNnK-wa9@^DUb=;rd@oN%JIXmdw7aGvHiH-Gp$GPFqUm?t0XrcbxI}fNM zk1;OL*XJL1oX3e*Pi^sCl~5xmSbx?rw~zk(9SssO&28JH>R*2aMR|(a>DAi{W&<$d zXMDrzq%iYTtlup)=`q7+hYL&=5|77eHOk`Oy^z6>H}qA~fU*T)nxhE1yetk~*!R+) z+u;;#(Wyh+Vi9@rjx;V$V66MKQjyHG*fE;~^EEx+JTUGNu`wBFW9QLvkCG;wJ}^e+ zsTbk6znr%vtPvwi{RcDSs7He%Sb8`@ODW=BI48wzfVZK-UsbZt5kQUyO0ZkKNhS_P zd5eQsVReZOHos`<=iTwQXuF!uXQHk4hs^2YUzx+M+Jcmgacd}oS6kd)KSAF5)p@eet8|qn(;sIia+BwwDK9hpVW-s zf_aWV<7Z~Onn`)@ucd?^k$(9?N)Q)lTWrTPUTK1e5UWakM4;;B^URUQr9XZK>{XQgLJa3eIl-7 zC|jw?)=}9kFY}KEd_#v59joG+`CJzh3>TB5kWPRX6KsZLlR-Y+;0W0w$HvtQWgBX; z)ho{icyXxB7A(sa*MlkJ+)jBXl?{e(Fj;-qw=a`L|O!Qdl#|MbDu)$_jh!G&Yx;*q&r?k8(A9*> zJeM#`*|g&Fws|$u7 z&qU>I)bCw;@}9KE1C=*nC0#*%zbh49{2O~aD%AbYN2bC``V}7Wyef?NwWmkC>epgU zW*OMz>JbNgJ8Zsu#6f|!&=DV#XMFn+ZyS{q_(vQQ2zJ$Q3-&i*VuXSf@q`MmcxVJ` zDpTR#Ood6>3g7bbi0d5px9c)T<=^Iv$lyTf8>Yr1(B8=0Suz66IZ~$BHUe3p%8$4$ zbJSGw6goU%u=SUyQ2pD@e-_&`{%E-S{7`zwH^a?lE0*|e7NgjciGCV5^Ctt>p5bgD z$7VR^s}y2R``3oM%+h{)mBy?*csSd*c!M@)YvvDki_taBwCr$qmNICL?cCaWxZBsH z+~5A`7i7|YLBM`N({>JbjZr8l@&4g%E64p^4`@_S+lmEsbey(p{DL~!f-ugAj>B1m zs%d}EHchLf-?YOCEv9K3HyM7rT27ihxja|j6*D=088*o=sl>kMRWskf=BBpFgL6GL z8Giqz^Rxn3(5=lVl$x|P*TgG5OR3s5mr#u$a}{hZvnXKj%i?o2l`>+IU(59{N}Ex{ zmEXUC*mS3ntB=L&#+im~oqP zy`EwLzT%5qua{sRm&vbly#kZc%uE^n8(CK~HQuSmE-QY^bq~lA;P+DN{1TH+nhbo+ z37-bsxJj=2np&FzCcc&H9+52IPR(=Ox0M%oMVnkMM?w}bR&qa)mHaAI`3mI7v|N{< z*Ct9@tO7wrlzV1@c`BhitjB);#XhSt3F>HDvGsm+xwcp5x`U^%Q=XdZ_IBJqqs`&P zT(=($r7Md6d%>5Q5jwp1XXQ&UA<>pD3)I}3<3$?-xqp6$XPA`lx(4=LH^+;mzzu2QOITnP4O1P&e*!p*ld2%QJZa1lOaYD{X}<{bCmA_HIXMGkXeRW#(!e|=^B zxusgO*1vNUVex0rdC>T?N&Ein(~LjoxXh4!f6n34b0L4uahEACMXhL)<1%ga{W-^7 zE2~uWXByvqhF!4ggUK<`S9@6nf6mc-_|Ffm)0srMKd0ixSB2&9fjZCm)VOgDVcNK{ z=cqe1-I>GYjD5GlbBS(`yB|27C(oUV4j=lp&c7vFZcHClw9R(^0X*N%v9i6oRMYE0?xs6c zvJJMLmuC#;e&LH))hFBiQrQTsp0~^r|1F{kz1h}Pk#fZs+3wH2p33yA$<*IALqvH7 zuZoyLzU_JYt#8*<6W_WuTMv!p+kxK3w@upjZJ%a*JKHTR^X+VRA|h?9&gOwKdC_M@ zn{4;iGT+X2?~-jR`u6yq+3o_))4gR~O*s{(&GawzA$+&SX_?s$}Y8aN@4r6>PM z&8%Z)xr~EGX@jptH=`}W zGT+W}t69}6Wgx8bV3Vew>iTj^o9+v!Apz!g=?zzB{YyHsk@5r;B@@ZSzL}$L8slWq z1)8QYtES8!mBUQ1vwl?}jCj=VceP2GzZro!E3-cLwRqPGB$?P35c_>jG4EP|^fy${ zG9>B34Qx5*WxZpjpt`$&X@Yct=~L znF|3XzvWZlTCg;0x6d`!mO#>!fUG@|h1dlvvtBez1F=O$7G??8${Djf?bia$07LmW zVZhWG=}FIJm5753C&)nSk!+$RrlCoErp~h1#y6s4_DiHS$F$f!{J(XLdnFw)_{frmM#To zHUoy9_4&!$@b@eNifma~54{j;;>!Tz1h-P#%WdArMN$UPm0ei_?3L*ce3aG3&v3KNKr&pU{<`Ix z&TEj+!N)dRYC)~5opEQ{Fv;afq7qq8wuvcAT(_-FU6Uw=lK$xcFH$8eWE`kcO#DeY zG{A$Ihj0qhO2wL#9v-%xKETCWsvLk)o)d7&5-AM^GNAS5GuS=#}esq(5uUdlMNBI7KLsf%|F2!-vcTCP5s z=%;}*e=>0G8B$6bDsH0)*`91L!0kf{{j2I=u(Fx7pADFmI4w1I;Q$n_dOzE!10FCL z?nlpBuP>cwes?b|q+#y-VrehTR#l(dxbwTEy~GDNVZ1sq-% z`?NCfu0P7aWos=cVSPVX8jY|alri{zK!iEBaT3c}s=51gsdneBtvb7SWVgkw>Vd;N z)n10Z*CvzH`=28UEd?<71`C?U&8_59)6rw#zgyuW<}J9w+gil~4p!kCPef)R?F1Yn z3L~{DG(BO{osk)!_5MHT{st{Y?tV2gT`z85GbmD%S^UqP_qQ*{#8zbwMI(6gWPh)=1{VusiKwSyIFW)ON{C@Jm zO6=9vO?Pw(!K=QIt@yxH)-OD}uRByoHfzKAN?gQWLG9Al{;{~Yx1*;V^_oUrCV{0+ z^w0e2>Hx3$pSC1JV24~63f8Uei~eUt(d_Y?^BEz57;w$`O0)SC!R48^I+gA>sajvh>)o~9yDn*OY}-Y%tdHI*LLtJ2kopwdm{KHH^2%~4hb z5hVLBY%u$rCG~}Gi*s$7P73azKs=VtvNHu(~ZLqpi z`7aJE$?rA=E45H5eD!e;zj>zkb+&jz;Fa5GTfCAK|4@g~2z!7Ge}D+9l!_8OJn@D; z4sDc-l~^j>{-1iO_%*#N5o~p1MxCMj>IkA&>k3=E2-N|1llDl9KfQg^B1BO>{Q;=%thYXKO^qqmLg63T-5~v|Xgr?n*JGPUN!` zqJxuO?Q5-0CTvow&QanLN}|)kJFQM3>eJ{HNwHYoi$d ztus&(j7OivqctQ~8FVA-QK{h7{(T4sZ_;hrj2@}mmmPP!Ix+Ocx%~n8Oge&eGU=US zjV|5emhFaqm8I{lK>v1~=);CBWAv$WBg0JFYRm9bikZT$@>BhpJ$QA-nRj6Yvj!HS zSJ(b7bFn&$P-Jd@!IX%@Zf)IP=V=H|FkQQ$KZk9+I?wq`tt&8fG)$V+En3%~QL4^| z$VL*QRGI3$5hI3GrTy!}@T+C0e<_2;!pBBsUa!Xs)h1`62UjC7K&RHpw86x?ybT$r zJg?-=FR9<%A7`p?Q@_Bz7#GW5e#$r2x8tcpw;nNOF|I9zrB}vi%QrOpigAAhdF9p^ z_gj#B!p*yUj=ugHqt$t(s&o(U@)dB5ULIpM1lJqP+hBSZ#_(NUCOg2_yb|MnFBO2- zj)-y3X)*;|a!rhR|6#D1OiIRixQO%Eve&{Gmk4<=Zhyh$9N(^!4g+J{MXDt52=rX6x|v0EjM+C_uQLuSlVjX`sYCdW zyknSllq_PtsIgDPnAsy2$as;DP*A<$K0?$jRE0*+^)g=MZm257Ak3Hfdb}UwrlaWS zsxfX$I6g0H4QtzW#+{QSRRkr2g@^-WnVeVTVe@S%odotJ7zV!|FFEPFVV=#eZEX??jtb^;nfNlk%>W|vn_(Hc|Ujv*MJmshvy08L3va?Gv-6|haIgyyOyN7e_`8tZ6QsgUhEN>h_dXPa#;1PME2>JuwD}wlMbbNHLMN& z6lTMsGE}>BsqSg``k8Jam_CoB;GT}KqA@~}d&n)1R2rSe^Duimdd z(}SVh;T==?9JE)zmQP?#Z0iu7lIqeY>R;g#Os9~jYSelhgzi3JTv?7jwIx*gC^PSj~@Do3gi^Jr)Wjkt&zkWJ7Gcp{seB^L3s&ZfptnJ& zZV0#VQpsYb*y^h{4o&?J3`vi zaDXXjvtLk^;i+2zryG`P-BSsZ!5?lk3al23!FTVFO5cwO4q!tTNVUihLGaf3&>{_Q zlb=)Xgtv>;r?h-P(0nI%)x}S$S zE4KCdDmB5#@nXKQG%e39ZSKlc>jYk`XK4)#O(j-|Ol4~B3>LiV>(ttUrvSbetC?7= zz9~PqzhK-qG#HujF}NVsO@?E*&q07L=UAtu-;C#C-y!zI-inqZ3S&PoWe(&h{C%-c zgVts+qMxpqZ@jVn<(AqHdN*hfqmvR>nQv9waz%+u%T0J(OteG}zetA|pcPQ(a3R%aNXPsLqwjWuG zZPtF}S+7@CjY!+xilrDD#d zo9CIAPBtx$mG@4^%^Ft0fXy!`?Z3KVNZS9yLgE^nId=3ECpON4JOPQdJ!T5S{P33E zHOOc+Y~1J>j$qjPYcko=qXRQh*Me%}(=FZGRUDiO!BhWZ(}Nj-Te>r$m>sw->s$T; z$E}n+w?ANcgMK?+&lJMGYiSGS%PjD0+-Z{2Y3n|>w=}&Luy$U{CMpWB@2r*z^a9s5 zYN_5YFzXRrVTdlbvd>bf<>fNL>CEX)OI6jZRl>qDxHG|P_;Y!`rK(+KW_VvaUc8;x z3a+Rh()&D}!Mz2lKZ#q4GQ84I;^7Gy-g$eTSW|)SCo{ZHk(6g5fZ&RfG~%@VB*S|d zjvYS7%i;i55x}A8tvmg!_Nv!y%J4p-%*x|4yth@16i|YpLT8u}*p(FHe*A~Nz$Lyw zaRI{xQ__+Qj$V23TJz5BFW8nUCSc1{_lgW}jN>KPpd>|BZXiw;3M$ zbO|SYZbpeRZs5Oj|0Ba=vE3-#=k8vC8~E?sFJ*Y_C^Ty4b7Sf<*}#9}Zi+=)!JY4O zx2nJmT+VF_mog`Va}-{qP%UZEGTFd&?2*0!ev7 zHNg()=zb<0Lsl|U#%E`^Z#iBQUHXBq1DBTxTqcG7R3_!v|CDk=hReLGNvNL8w#w=W zTqZ?**0&dj<^HZq(%B4cEHs(w>$0PQ6kxw|p3ZPL!BpZiZK}Wo>^EeS4EITxUiO(7 z1j_UQwoF&NmBHZ!ugUj56JviF6L7h?jUy&}n!)J}FR{MQy`Ta&@ZY!_hGn?7!F`X< zeOm=?;0oNV)~4bmOeLcGbe>Q&3iuu@Gab0F0xTYj*KHXY?tSpgm(wJ?k>N7*CHf%} zxV#p?6-qMP+cMbA_Yyzz^%`4&8~E?s>oR!a<26n6xhq61Jqe=o>DrYHb+Kq23Ty>D zN=+PcF=M%yt1?`|TGIi(6hc{s~rjZwEkV}xKehJmT`h{6nZh$^`9cz@V) z+X!oCgfVYt{7ShmFj`ZmUsWt1aUHONj;wtU{kuxfG_LT63J1g!LLdwVWbCGBqLNu0 zTzPB8Ujk7md1MA-A+X;#l`Aw(4e;yD95v>(j8Zf@Wi?`i4rv5P_s}%9;oBMC!Sa`7 z`L3J=&}WHRlktV)HPcA|>h(oA3t&jfOBu&ux!$rIFJ}R)lg6X749)B9`l{iMj5pw2 zWO?5x=LLkvGO7`_-WS%p zXU0>?<_mj6@3vCF3&vbJ7gK4Xq+gzz!PM=FC007~>5z25kaWP1bf$VnRodw;uv)~? zPIrp|FfB2o*avB{SpxmyUw+Lx!hG`kj_`oU))7J=j$lBm>Z35&gAz4v%ot}9-WA*Q zvH~fWw^5!#|9;PA&?%z(P=_z51O8|F2#0_W#w;MZk5(9!nq+9T;k)i-VHs^4FS(Yj za~r?T?Y;&}iD0{&704^Mvd}%dGZ?LtuLF-m;El#Yb>ak?t8L*1G?%m1s+vJ*e$y`) znZcez@@$*2etAZ~P)5K|#u$@Pi{?Q?mZzBC>z6mqVVtj(G6&jv-rR}ciG`z8PDYkMak_abWhpz#&3RL4nYpVd zWgS!+XYt_~JUSVcvY#Z@TC7_X)_ih{h!n+1}yi)0<)b*ED9U~0-glfY7ln^h~TRT+9 z5JIbtux=?gv+770h5c!sscIfNiaoC{vKBjaZb%tsj6`O+Gby?A8k+vflqhqapT=I5 z4o^qZ*eA`EI--crS@ICCX-{*aG(qQ4LeXPny!m%O3He1-TP4*_qMCVgO``8hj^b`B zGL*W}e{jynJeF&>#23wbo<{U>769#*l)80`@T5Ianqap+gi+hkq)SJQ(T!gaS8~Zl zttc{1);I$dx#LU=DnEQ&SA_q)*h-@Q7(nm7kkb`Gcb&+}6>; z(7*EOFZlFxW%QO(EAFD`(88uUy=^|$Ud}@7@p&VBr5~m$j`HeL`On)@`Q7q}Vwvmn zu70zB-UqzC_x<@`fU^Sf0e%-Sf#c9M1uz7zNHE#%vkm#5W?Mx=}Ns$g&NfJAFdla zt3Po!mD?bmjJ0(6otLVQX6tUM6*~nGpjW&hj%FBw^+c*(fcJY!1Kt6!_Y<#nQ*GIy+btvLW?oJ+W$eK8v)rlXi`-*13&UzaOp zUaghW@{c&s{AVHtaj5RBAt1V3HELD_OJHPI`Hbf zc@4VHVfj?OelW&L8xvsUOG#m%F?C&nV|S!-f{FWoBy|t1oD|0s=mY@_0403{;ATK@#qr!%%Wp*&AH&Lg#T@lIObQa9KH($MB?#kTE5rZgs0k2Dc5 z5}>DmAprRVX3L3yG|c%(v4CQLb(pYI_{NevX8w|LC&QDyVf!^ zp4d0%2x{Ah5Z^T(8M`HZCOo~7+BF%BdRx~k0X{S0XF@+HA(uDPIPZ4362wueTiTp~ zx}AfdE{vd$=&I^2y|^#Gjx1k_kS;Z z@2u@P?M7SQ!Kng^=WlHV&@C;2sXtdXyhDB7kIQ(u;ib^+W_dlIHyp#N zIB#;7vi7hIPI;Rz+8EHDdo}De8Rl#CTQHn?OWs^`rI?cR8p`ES%giX3sMKB`4i9Fc zd(t}`pQ)>{I7n1(Z&06sy3$s&m}(Md+82tInDp2XqfW8oHmfRijOQW03AY7qfjKxY z%H<42r{>#+HI`w>2;dVS&t zAWP7rS@Tz@C*L%5n}+Fr3sv|xfCK@U@^O6-JdxSwm}aVZ)5{31RHbPUNljT? z7)iaGKZGP*Y~S=E>{$Z-1u#LtmjH@UO+N-$Bj6aovjScNctbkwRfm_3BqcM&+&zyurrMK>}&egF{WOMnA+FO)^4xe;Jr9CV<5y+e`p6!4(CoJgFI7{N(ZX(Z z+9jZ`I^~w70C;PsXf<{?wg1Z@B5YNCbhCeAUB`JMnuNx}cfTY9u_9(tl&i;6F_YkU zmzeQH2jfO1$QdrwU!Vr5W#3CC$6h$MC$q-7Dt;SM-s|8FQ0DDwz4yAi1IY1S204lh zVyHWijK$T+$UqQtGMT;IPCQz3i>1nZ?Eg%<7w&w{H7 z=m!ud;A()@0@?%gluFb77kAOX$KZH=2J}6^^^#vj_AVOh{Br$St3UIxwx#03=eJ>t z^DiQFri30wUz~zT-QB9KuKbn%J+l&~OZ{)tYDjp(GtC@*y~FE#R@uxQ(f(zR&kVJm zd6mMRKMk|jn@_hw3pDW(&EEAtJrar1O~3Ml_iCZmP7-4}Dc1*(6evIOU4X$+r z-qI|}T}^&%3#Jf=*8orNtdEIA@#?LQ?;XWfx$ruc9_6kB))sxGH==l##PVcrjB+;^ zo~gHthvy9+fA!cX^V+)JMyz>*53_HPb_Iy0JB?BaE47o6b`_Y-$D-^jDF$=BeZ|#C zi_G)iW{J`{NOy#P>3~T=<6$K`cPPqISEsMimJPGYDm{IORaWp|F?OmE<+dP!)wqIQ)k|1jPSkVLg?toL!E;xsMNX`f3a{PgQ|brFYLL9dGDz7w}}P z-$wY((^|KMr>)PkV^5TO74YEB6DExUpJsR_OezFs0M{1(q^ZCRO2FFIk8-;K??C3- zZc%Q!@W71&QJfuO>kBx1WR%M|z;2s%CBwficG>p0I?Aoi45G^_l#gpg!t8U26o&%@ zM0(LD1q=xZ*E|&UlL*==CC^X7o9|^tUGTq`d2313FKA%DLRK^(>KoX*Hi7-}^--Xn6Hq6tRJI%)ax zu~7ub$U)jf%}S5D3-o+8o7e@6j=GM-U={VSEsC@$3Mc6+5?LsUX=$ja!2)ejv|Xqu zqK7H!&VNS@6R4ul_IhA4+`uWJYEkV;;QQU4&&=oQ!brM0|{3c>qNCOa^PRQJ}Oa2_|t1xe$wX6sEKVvqU;>rL5&OB;&7Io zcOhcInREW>H}QJQO^ziH0*|wU%8A6VZ7>jBR#&!nSA{*JjHHu@&{a~{mb}-7V0QF5 zJoio*(MlgD;EuTgQyrxu2k}mx0K`!CqW8j9*s>$O0%vvt(@)LhCH|R~;NHwpDRRK2 z+aXu?Dl&SIbdHgnzl>9OVUPG)9F@rHs)o&B^Wc1`6Wj)dJUjseKLTScjE0E1Ty zFv4*1bB~(6E78 zVYff6bUnxXq&Uneyzc34q519Ljy1oHU7S`5riM*cX4?FY>42yJIB1r@kdlCub1TnF z?hm^u0Cyi)l8%Sbmv}RdngN(>>5uz3DhZDK_<^{NsiqEa4V|zR zXgqE576TrWJs!L-4DXjcBGmQcWsmO9@(odo#vHV?`p0^#K`8>&C?Be%g=t~^VVC2h zW`9W2Wp@CIB%j5QOMua>{qZm!ne>RYIr=CE;NyG2`gw%oYki~1CGeQMcKC!aMS1nI z9#;=g`;f$Kr?&AS)uhwnFw@Pb$-OWeC+l%|2e~&db0;}rN!IVzE>V`&XTuu6I=Iwns8X9LOV8x-rl&%v z#cNLEO=ZM2-yJI#>d9nO+}@e6hVq@BosIAG%(On!vzL4G2vK?T(39G)-N6je>sjDR zC(;{xht*M$LQcYZD`%Lr3^~b=Fuo~LT)LN5AJzlVgd;3kIdx)aW$%Da$n>=5c?I); zX$Y|?&cJ3U?{e0_X1J_XHQ*5!%>=03*8vY!dK7{(mjyi9w3je*`wK1?q!!eiK!SkF z1Stw=CM7``AwdtN1iWqtYU>N?<_i)Nu(RG51Weqaw(24FI1 z5KliA@KUi`FV$3XH3^X12;2Fy!6=3SP^x&e2mKZafVFv2EpF$m|_u$#tDBNxQTL9e-; zrxN}G?ryO%f6$|_sWd`lUHtC0GXY(d5%nYwR{Fe+_k7WG<$ouBO1WX#tmqk`cWTVMeju zckcw<@iWj!A>S?zkeEbdo;%hre<>BX`~R@_Cg4$4XaE11$p9fBi=akD1zAL8NkW8Z zLD@+vOH2ZyVkeWCNivYk3^Nlpv7*&V-HLUswbokP7r?#Nx*#fA?Q7p^wRHiPR{K`l zShZrS_4oOn^E@*X?fd@T>-xXH{(k@Ks#hEC=PdWR&wcK5Z|6ME1eWVw#h5!w0(!*E z$^qWzJNEA)$^Xfpl?2vzo0gs6wr>&F{??z;dT&aP+9_!cXSg|(LUPLCbI!wz4_a4oOteeOxg7We1)r7VEG&EM zSOk;WYx%J>m%(T3V8oT*EeR~{HgW9&YZL1J*Li?g%;^U;)aJn3EA%9v0|pqa+My+wr|`GtH=jYL(v)&vf^-QWg){lpSFjK7-p z{Uufl7M)5Wa#_i{T03Z((_ux3M@!;LYGF2y1|N6xcP`_zDJbwSzC4Z$B1%Km1$H-YI z2@K@CLvEYl2^Wk5p^@S7`WS z0cg~lK7e}_5At9$)>_iIX4`EhNOD6ZpPAtCy-8m#2-`EN1#oF%JvB>90ywY7e+VAk z=(xGJfK>qd(|_?aTCox6{~C?v(tq&+AznO!3i)fHlHFABZSLUWN?Xy3ic4(;*KCg0 zVb|h)l&P554&GNOx>#FH8LoChP*sphsh>l|t$qc+0DFwB+30oI;n(-lQ&mX}j+5!@UJ0sw<|#y-g*2m^?UtrT9R0D7auN6CEdj^}0DH;3|L%Sm@rH za0?bZ!P6}QegW_X)bg%^oyL4G^Qk-yJ5$VGR$#tLH^2nT>O}}(#Y;SlD&g}G!TC=z zdVPpLi#{RW;%XS8elKHg>EENIoRYah{b2#MutLX#3KfCvWj9&NuX3-&r)dw!x(uO<-dSy-DcShOD zPrb@ikIHv#WofBb$q#LKiCy*Vc9lcD%A0#se&{NPdzDZ0sNCZ!Stv`;n>{K&9i{i8 zOJ}Q+3a6s6Q3_nST7JL;G(qrtgttBKI9qJF0dJ{st>MaY@N_-Dcd~V0uSOvFKellEPw^ z;?{aMlEUF_Jf3@LK)!s*W~}Z7*a8K&B`k`}^sNueo3|=(IvV)7k~`R_(tfwTF91Ql z?PNrBywwWg2a48M@f!bB$z`^y6R*oOHjz^az|h6@tAMW15c(+z{S2{Gx}>uI(vtJl zZI0`9zTXW1D*+q7{c_3aa7LQd`ULeqaFaV-Eg|QdWQIz35W?GTgq&n&$vM=qVQ$;` z05-5sb76V_mm!ebB2bAD2?5X@u2{D?50@SadDbf|8xhX2@o!k%7bu>WzmuryeLS~}q? zNDdC968`+sMeu}8v-M(E39JbW=Y<)vBfQX6(g<3t+U?Dd^idP3J59`@p99(&u1EpYd!^>;@W-q#CJp0WosNaeidS5vqw(<+* z+T8X_F^xwdJK$36&2GN^T6a^h9P;@1mbqO&jZ?m!V=7+SY~=T!>`^7NDrd(xexGOU zcsRop#+Q%tus4Cs2JDUBci5>A_B#f!n1SIUU@4-pvwS=ucVNVTK^&WmD4~9$Fe5-; ztM@R&t-$n))aVGCq`m|{`W%;P~!{Ln7uRbPS;|X2h#5#!27khSM1LP zEJ+CMZ`8=_+$Q%~yMZrKzu|lRz+l#>{`p3Ib;mx-7>=Ifs)T0XSNiSeHCx=vHPbWS zyyMqiY}NIRtw|43hhwJp)3{5(yLg2CN{xM9qq?gv>^Io2o962DZ0nL&^(*!3PI7g6 zUSq}mrtu@$zYr_gU;3+&oCiPsXZ!Gtvqw(1HDYGjbtA>{#d`Zc^4>@ZC)q6SJ36pF zzOvPfL_|HT!{&_~q4d7COy=8Hlu>b>y8o(imC+OO@J+BzA2bc$YVju^J@*7aR2JZ% zGJz;2HR*HAGz{aC!LA8A6RoE5>WR}hwqA0$E1#Ax@4ROkS&t<%T=|rI`H|zM9Z7l2 zl^^L1HRD^9!gDLCmqn-k%!%BRGa9ogqbG9uXEItv|6t%E(ZnQ{=oO(kx7dOuSJ-$U z82Gj&SWRyk9n^Oy?D8*p!D~uEzUg_Yv{--G7z~`vlUQ@2@tRVQZ;JInJccFd*4HG2^vbQ`8EW5uacl zXMPq8)#+-_k<_w-MLfm7Av zKfE4jpL`GCJKywr0J|QkuLc7r&|~Q^ug3{RJ%ICL0J|RJjtK_ls)t?*5><1HdH@ez z>x}_Sk0%3(BxcQ?n4Q;cdUsQ5Z{03EU#SWqz)1=0gYv7#1ooLupsLT+=!TowNoOt? zDMGOeyi~HFE)>v3xUs&0F;tWE?0sb(_uD>hsx0o6;O_lSF>V+`LC1C z<3WhLA%N+rRu2UOgVaj7K(!hqYP?p!v{DXa*mpP`aOgbpZG0YMm9_d8I(cVEiAh56lydYBm)j-IHo&pAB+DebTD2PpXL>Wlu{jw)0eDjl60iH(JTj20D4OY7iFo73OySpuiMi<8w{2uGYmo zrM8nMwzzlVlF;%?LManGEz%kmx)GO z99Rx{LS<_Q1&;Djje$H@=8Y*6(1P0rtK4-1u ztJ!XuPI*%`_DMBo+!VmAv&(eKXR5JJs`=4SJ`>@VY1xrhYTPr)d;3Pzo_ca_aHHoH3eY@X5@bg+4bQ$0v*UG}JsxR$NQ8B^s++{_zVPi0J%rydPwPlDzx z7CpC=Rx77 zoKGMwcUQ)Xhpm2)?;C2^YCGMh)7*W0Rs;oZPg1jq8hdtnsxn~v-EH`mBe--$(7ws9 zhAZ&w_uEOsW}*06Juc~r@esU4K}~>Zf9*K0XxqW^QbW`$UbnXsw2*hFm(*ahodic1#|Ej+~;AYK;<0-w~PGRpm=!|X; zK4>ZXv6}Avh&`7I>;}Q!kI?jf%YXC9oNjYq69d`EJshB|`Gmu=X8vhrR~^_+9qu-T zboy1k1T*rr7by8X)evl+J)5?&;g;a=<-+sqCdlLO558v1jt8jU08N_)USWdaW-#vf z1uC+yfF}SBf)5A6_s4AzTQ)E#Au21`;o`X+b6sulrh!-94C)=H>fqMwXb8dD12=o! z0{S5{I{n-u>d{|Oc@q!zyLQc^80*pZ7^_mi9)JwM_7Z?=gzeEc6bT;q9N2yVje7s5 z@BvNG?zGkPv(=w7RuH30mtm!@ta*r6#$1LCRhjo}S@amB4l9S6`C69dTNwMXiy3>D zfUAwU%Lup;U|b8pHh`s1L)K&8EO}mo)Odq@!_nnQHFQ01X_#)z6YTruE2*aN1?|3J z%^nf9z*4cDOu(=hR4fw}kp^+#LWWwwnA@)axIzFKl)LT`Pqv?B8NGe=Ad$cV+c7?M zV?1I9zQEBH*_Xn=bhiSo=2F)@a-?hisBNyrg1wP^OVRmYfzC&)Km~T~>^2A82A$UV ziSS}qVArpqYNvqr0p3UGcYQ`qPRFo;UB4ZxME)t4(Q7BY`X3N{ghB3SW1qsWNe7p0 z^eX~Ylr6i`ZoGp&G{Nc8PNV|du+PruHV21zu-iY<%>o3TT@cuGdw}v9`?Io7sfeq7 z2T!G$&8M{ND-xbPs+Vom?ziG=ZM5p3)q3%|g$sefp>XT&W7$Rr!v{0fFA3|1yN7<) zFFr7Es%mbb?FO1LqWy5l!SC>JwZ*lEdVPH4?n?!{4e(pG0PB&T5O6VXT|xDsb1L|mNP-As6&)~kv_HRE3cIw$dupH&8-$c`iHc-d8UQ=7_B_~C7SLOn_?$H z$Hx`mnkL{F0P^vHkLLi~+6+*yv!fA%XipL$R?A(=kM*L1ZTVZT?|mgKmusW5{3t(B zsh?^aG0fQ8{4py(HVIC~K^3G?bt$Zw`)6QVOU5=s>KXd8QGYJhpQ~&KLBG95=zk;5kF58IQ>yAA z-uEJB^{4j*wD(iVUbc7`w8Df#uXXvfxL$qqrs|aCp;%L;;No)&HLNXtMuzyn<~(X- z0t$U#+Q^}*DU?bUwAwd};%mUoJe+O0^9Lq&Lp2jVk(u9c9KgkzNJuk(*{|Eoq(ho? z{8B;F)fC%#|9y;e*bZaAy=!*|XjKHM`q*$nwptr;fC}HD(yH;+2+}$rMgM;ju+Eqt z>#%FUCV**d!~s_UB(xC+oTE98EfqQwY@J=04Sa#UV-cG{Kc%$DQ<5{~Mm^y#v_O!} zaLu$;d!zxw_2b(F3;=jmZg%O_w1Upi(vtC1l-@+eC&E3SU8LRX*)#Ak6>GG|LaC`2 z(zYzN;8`9Y7#+v7K0vqosp~)RD(ViPP6qpduz)83R>6m{JJ8!&t^So+GpdH4i8KdP z>2tu?8>(dYG2Chux@q9|K=U>AK9%0*!4l7WkA1~M!uMd8I~>&>4h*@dzYS{~xJU$V z(yn)Fzx)kqc0-_5J?+}p%l`!CTLt{hn4jQU1Xd6^{$!!AgT`vv&_PF7sn}_P?S1?< z+x=djutS#rNs_S>$yl*BN2dos!{MX8q;_dUcsFw<)L?8U6#%1MN_Q2tSx@%`J z3F5SO$Q4iLVY*hY{f{j8w2w#}l>;aq{Hc8RWBUQbk@jQvWlp_s@*7?3H{vZo*XWnF zo|f%DV%(~BU9@4`VCnDePVWxPmo(UIw+m;lY6A}!Xyn8XA$Zs2jDyo2*oEux(2=li z*Bt;YDA`>PNXb?qi)Ik5$;8>#4_)rJz8U@Msu?{oRDa|RR^9KBP*N6r#;2hPEHJI= zS|xL7c#b8pLOZqU6@%W@vrFGg=LSpRF3bwt+OOM8>TgUSB$Ah(&Dgh=L!jP;yOrg8 zcmV5u>p1+EhccOd9$$O6T@q@)BvkTIuhCk55}>6fxI%Bv-EuqaNiPL%xfkGC z7U`%*=y(#A2*hzWR4|-rczACtz3xvo>oLJC-oB zn|{VA1WI&)2Z-&R$LLRT4-7=8+opfpL8~6s~iHWxyh*rN?^RG!`m|mp#FwL&?Qd`FK==)SIg)fV4*6v<(Zy>7D?UY_1aX9)BW5pqPyodX7 zz3e00kN@1q{knioN~G%+ttG(eFW?*i!b`>hn1bv$T(Gh82K~8Pe;(AIEll+2=ki=F zQOGKX>Uflsu9Y-R>Na1w60UA6E8)^a@=Ww|6Z3rHs{*D2B(zMt;umac;%U8=wxiLN z;&$>f%k8mZ=P^k3m-XRT$IZzsZY|i%BjRT2bZDRaP0(!;unFKvSTp&10H4FK$=6Ge z`Z7prU${AWlTr$kziD5=>U%%aO1`K+ySe{U%a7|#fqq1wc7p|jDJ$)6xp^6ztcTs) z6(8Gc5Vco&txmQp&zdI!bWm=DNz~r2+CoiH|4RDXZ8CXUw}C^XQte!x&=h!na;yN( zke{s6>edaVMSo`Spk~mhKXtm+Raaxj*M6HE?ly~&XczpY1L~im|0?xg{0tR%sHuPkrRM^R#3-t*kSX z-l2B;(fv)^y@`skbicwY-dP1_mOw@^XK*OFnw00PzOi7IY}5#9d|S`PGr!PSv%hL& zw>kM*hO+*|%4u5Tt15yQFV$wbN^hUrlBvo$T{ZOwEbz&wKb>T+#9gx|*%RJk^-3>Z zc4^T4E(b3UF17E`p8UKoi-mY7SbBt8zYX64)oup1*K1Z@$}Bg0mk3TNwGEpAk~c%a zhAon*Q(&VV@=SloPpuL?WrJkIkHYMdyjDT;OF_F)Vv+d)*j}3nwyTir*A@cE!F%mw zfIlPRueHj7)9-1Y@)CV`` z+xH?*c^9A@H1Y>D_EW>u(3aA0ms2W7*@d;3Q+hUj`>*>W<{ac%!bj!$V<8Uvl%8Pq2mSP+~2${H}S!u@nXYO>(}f7 zgT|ZpYwpV;F9WPTJL_{MJ@0M(`9N8^y@pWB#x`TiLY%>LWf&#C6+z$-p{p5Oq3Qgr zj0VxqsxYZIlUllv3R__P&i;&h)*rBfU85lXI#|(lI8Mn)r_=fw_V06Lp=V8S)$?J& zF#n|UX!bM7RHmGfQ6pVDRE&xH+2>Z)GQ%kkQT`Hyo^-ohoDKM!8Fs^7ri|}223HYU z1vcPtKBHi2FGK$gzvAf_n3sW_Mmd-bzoTR+4`}!}YR|sgo_R^h3NUa3&?Xz1ai&|9 zli}Le1Vx@<7_7Qbs2@mdW?eB zju*`vPo<5`e{)Ytq+E;NeF$Zfy$OtaH|7Tqviuqu+unF8)h?$YK!cQY-^pta`1Yka% z*(0B5FC=r#UMix|v-?`n+za<^-EAscN!fS-rvprv=wDoef#Oyi`Mnnlf%02G=E_vtcWhBDi5Qz$*f- zO_V80S#{o2k z08$VT-Q^L`UdH!@gKOn3NB>0SxdQ$QaJ@!pXOvhkwnieye24mVkD*|qf65nwIM$0U zFVeU``!!PC zeLt5(wzC;+&xecaB^K@P`02&sUfKxi*5q~jOOI}$w&NKa?yil zaFLvU?>~dx&3_Wv0UHqRbK&WNUGQ{20lx>BDc~c3#Q+Ow_uLr*_5zS#EZiSpD@(d? zv_!=t+>`L$7x0Dzs~Ba6`o9;_UpoOtm|*bMl!U7r+rXVGe|X^*m>2g zx9NW;H|vJl8lqfVVE$X&Yf$!&si=Ycx~?yrz{JxD_I|s0f$s-#@i`EL9G> z#!{{*ui->vere~FgwvKjF2VBhgS`}pym7a6dG-`}0|vPjZuMe>&MA+g>w) zCrZ`pSu3@Hk<_-sFr%+C4J){axyr_xK>eR6J6`r_f%dlxhd!2~{qDAcZO&Hc#(U5wrGec{iM(X(OP z&ax7;``1sDXrc{&IZD88fSF?VPFS}P-T2F9%jMm))LFtJl-VzpWLt#l`sFtTpt^qf zBLRm4@R2sNTyij4Jn9Nsl2)+%dttL(8DGNPmf@dDV>}rS7oo?0Ef%^gxwisZufCzvLSuH7< z=ig-5)I0E*H-gUCESBZ^i^&(;ZJGMet9i)Ql-nA+{ZpSZol^SzyR9)2t8}?X{_j-g zFr+##o%=S&!II-TqF<8D`tyf0I)?OPIzL;}|Hq4>S`g1k@^h@Lp;Vh=nW+!i^ z?aK9T3v7t{ZR^Q_Y~}2He0PxYRx)Q4RM5=!9-K z(^>(qDcVT3=S-{r9naU;>1WXYE4ku(mev1$_EwC^p#SBapEbUK-hE?;ZOUq8V4NZ} zf9UmAXR$)u0kgGiVKL+rCh{PKploGNODUd(3ADT>wSmOoB?r!2sd`Uh&bq>@uk3H@ zFI84h^^l}*M4ctsFDVOQ0bSBj-(-~28&q2MtQYe{1?-6m>Y=b-C!rglp17@0R&lor z_oiNeH;*q_VpB(FDq8yEB`vSavGm2sAv$~uTn7Um_ifOu#c*>jICU-S5 z@yL+VOz<1_`o{Xw)TgnBTqZGxDo`B@f1t9t_%@%-c zzjPY2`4LHhm+lnsH-Jw8HupB>*K?G9`Oz-|{_Bscp8;X0&sq~a`!o^+y#8o@eX163 z^$v>q^M8^QoC1n9gupN~Mw#@w^=)%Ic>H~(&70$ zcJ8lN3YZIU4Wa$KCV+=A0l|5lm;ei`bw(jL@0>uC#iv(2QaZ1h8LVX&C<%VfRT{F? zD$TW*I>|rhe#)Tq$DZWR-ys6mKF|8+U(?PXyqG7BqOKcxw$xpCY%6(i5%oa}zzSo2 zbA$kN#&4Dh_yz!PcA6(HH0I@r0=^4?Lv5b89$+bSnkO0%QuD;u+L%9q=GqSt(svG1 zR^glTLI2cb8g|%MJCzt(haYFk4+}g@HCf*vgPWJn08nP=p|EZ@^j91fc#H10 z`Q109qkM9rKcX)u|yqCA}a{4@u%k=808V{Ke!@V!E!S?O0 z*Y;Xhsa~Jb>lu1&Z=zS4UhBc;dX)}$Y<-$st>0$hwVemq9w|O>5uX6+t z55D?c0p$SO1dQ~nFu|_P(Ev|k%N!Pj?b+Fsyewc5z@G%1Y|LxHH~@F#Y`dm`kDB0l zf1^kXYm531ywL=|bpeA&EM6lSZ^h!ZBSb#qdtxE=b^d$;<%*Qs|!zIUI{mwHo4Z|>BcH`nit)pKKCr``zPmjzms z&vljbzLnlYcUCZ8yH@~$`P$R!U7PP6^v3?VUdwmAsiZg7{=7&0-kgoQ-hWnaR^N^t z(5uKu3Vl;vU#jSPyVq}5Z?E631JtiMKWeCVzNdzLmTcX61m2_v?li#*-qo_(M=kP7 zV|GpO*F>fL2i|3Z=YLJ8Sc62u6M%keY$#Y&G#<( z@`_SP?|bO|8^8C(e(&qm`@ur*FRv(-^uCwrkpOmM|Jd&>WwD-Z{SR04@k&=|N(bIY z?`dlL9D26IsWWW4zi_)5Vi51|1uw`6Gx})P1OY7juGiJA+YRBZnct04DB~i`1zY`Y zob=mnyZfr!rygZRSEK#)ri#7~c>Q)C2fPv{upb#?pl-$l6c`*X{Ov6>ML!({WkloJ&TuVJ*K|#ZgcJhBnYO; z8Mx>|{G+}ZV|LFGz#-V~^#VxX?|u|VukYnJNqw*5X^((AjCp;8iXXtH1cq?~?p#JO z&HY1PVQ`(`54(*f$03-mf=6S}ZZn^+ltYn00=3FgF2pk63FQnl3MLW4+PmL*#0myHzZt$0D)9 z4^70p(hAjY#A&hh_T~Q`^}}@`ZsUWhr*B`rE5kTuNlh7Pgsc?Glq|nzGO_mUVpfFe<&P-2ll2|G-d|Cc6c#nK0bUO0Ve{?hwd>- zW{zP4z11avlB|}^LL*-Bt+$6pT(Ocj15WRH=;^V53mv8?{e|G85d;0U2pTXfV z=Lmd#f8z{9V0(CjesV3bCGT@$EfgU^Ulk;{fVS@RBl-cP|~*2mtl(&KJPi|Lz)i z`Px*+%kSKmUqX1PiY6*HL+mf}6`^dXYLwRWwe>~u#mqfW9a?Q_MzipwU;BPKs_*B( zZK0f*a)5T4jx8-wyZG0D^Ae(XbKfhFuuZ@_0Gzj)`#uDCshRuIB4F1rmV6G4=ZgTg zy2{2H^9(WTCG2Kf1~I#k9h*2r0BxgJ(%kF)m`3N*$Q~b-F-K0mtJO$7>gOINnf={cO-{_>xjK{A7~DF>5%ifF-l- zC8pQzc0Dc~svgxA{c{fer8;l4=C?F!sz%s7qtRdTddyXIrS0*SSET!q9O!BlVAoGR z_7PYnyU1<~GIn`C1Vy{)cOOf>cQ>3w2QzI=ju!A0fRq}} zBT(A;$8PiLAQ0_7EWqdBFFS{|-ubyO@22fjq=DYKf~T<%Y@XVer(28@y;q+B7)y`u z3e{2>-Q8@FPsH2ZIb%)gWt@MbI(o@cthJ)F+cUbN2)8<(v`{PCgfHpV)UJm%}EwX{WvSe(Zp*9&?4vbtgVZucBzqUkf{N#xpiI%o#bYe7>Y)!OHOh+bm^6l2dXk_H z(Mx0YUmnC9m?@!9AHGNy359wY6F4tas(;Q2m4ayN)u90P>csyD1!=M<;aV;W1$tBX zZiqyU$;CsZ>V6^!w_H;)1%z_|?@X0^1MpaZ3rfxgJl%FS^}Ry9!EA1KNIsyixt%e# zUUFsVeZy~$^fjjSiO`=Z9&LcP{5bS6@QoqC7l-x;E(N~xhR`R1`>Xtk&|d`)65Jg6 zo8X~pb6n_C!R5eP9|?UXco^^1i?#0PWLdN|SY$c(Ph!!@A*TsNbq^04h&p}+thHcsbZ>!?s*Zyrvb zt!8(J0z-IcpQ~nlLxG{7UN?`2jax#2avsjB&~-vmYP5{OX?8JxtT_{92G83I zfVQ@7vR`_wEj`S@jIHwq^5@l%z7P?-7I;fC6qxG4TPs33c?n)?k=~7H1fRkr-+6AY zTLE(dclEl>1Gl{2OCzduYjf`dL=)o$|Bd`PU;UwPiJ@xCZ+jo86158VK3J_(`d05l z{L-8H5IG?`Am7`88ogwJ7Hc#>goX0{*lCrt4Hem6FAW|_Mb46Xqe?cE21ls`On3af z???~nw#WOzXFKY)JNjxU5pd@(`W_=t9J-NC+bxFzmf|DJuBYTqT5a8{>;|vH)?gX! z%(0Yi8D9nuT!VpSxJDM^)==3!Y5*l$%gX|GrrLa^{f?k`3gDJK{U&mnGe#7L#xcDR z$UCxEBIzA`HCk zvb};Yh#rmBYk<7wMiwIUEuObMq}LQ})wZ7wI1NxVZM%2C*8!z5w%s$}48T>P5cF-? zCsZmVdpR}q!w{c#F?Uw%L$e{J0|LJxwCjr$kG|i+d^&#Lj?`-7J%r4Dw0V;@W6QG? z{uUBmFYo98{2kyHvp<-(4G6p~EYR0$EXxqO6rj#7!{?HoUPp_QXAcPcLFIxM4+x;3 zdey;$J6i+6kwWDw*1**Vb{VhC`=-f(tMUcz?WJK|Y69DORS#RG$}tvP4RjdL*n^Cj zP&zCe?pd&3sjcpPKzUgArqwj`z`i#*<=c$LBAYR*$YwMa*^EYP z#$CYxw}?#WZfu5CvCd|=GT&y9-?arV2imQ<2w>iO9eYqqC*}9h8T<9l&S6-Hz`dg3 zU~tI+7>csLtA9WT@R&FA`@xj)dBU@$;s@fAQacKI^T9wj9@l_3kGbjLNMTZ z|5w4lxc^@T1LKN=fpPz7Fc2vY22%f|U|>>lFfi_aA{ZF=|6njM4tf9I2Lt2e*8Vqx zfpIvz|1-gWM)iULfnG2mivRb)fI4`=z#I|(rC`7|aKXSFsUR;H&`%0`!N9SA|79>h z{r|UMpq+vJU_b+V!NAE<$lv1G3kFo>1p}hV)9%t3UNA5^=z@Wu3kID2`C;(?tzh7; zy92#?GqDFy#@$k^oH?03_aB%vUO5W6`ao{tx>h{BGE5D+14Q0t!tg+^Qe6K&uNw0o zn+5z5;2i-^8S{q?1acFGqu%?xqdy<$&)mC^qL(PTSgkKK=1&I; z_%6W70J6DN5Fe>&zHN(cqv#Qe(xR+Uf5OB0vx5Gg30Q5+pJxd82EaN2-v+ot z!1n-Nv}4@FW9cWxd~lG;F`XZLMF8gbgHr^ssvrD7z~KNd31Epn+)uy^fa!++h%4`U zC{Xf&Bnn@q?95RJl6xG55P49BqjP~}XO2#){v+Ih>d`SZ_=^QI89*{;y~d7?RRHb* z-{#T$XqgWt3#G}T(yDxem1@9b=(bV~9EgXa-~FIaPKgJu#v|eFHAol(12!JU6b=rA zki*bsqmnmNvVR~nStWvp7QxRI!9Od4e^Ug%;K8HAVMcX$Eanfrv1a;X^CFk|Im#>&HtWnphD3u~;tH+h(wi!kS5Fy~<~=V37CVK7_R!)#%T`GLb6$B->J zHg#F)0h0v z!4&sGFz3GgFF*AEOse5uekfkx|J9`Qzx+_ry958_hyI^WO5e3Bpkpxkp-!<{KXkhi z)2ErT%xkrao^|@s5C3jrq$U0l24s*@=HN zLHFovr z_rB62@B@bJd!LGiR8TY>-t?xZ^nDc#9gC;CfueQl{5YLo74RIu-!!Fms*)<%ZOmu; z3wRemwD-kEes(cH83yyS=LHNh=I{Ll3y3rCQq{MFs(S^n z5C8s@fCB;S==c+V|4b#5jQRW^0W8nwcEZF8pT`XUjl$0;E|5Wd!%Dp@*e4!f=9{> zOTPni3LdFS-c^b3kqY)bQo+7QD%kf(1^XVUVBaGhQ|yrn^WRmA_v<`TO8PEU31eAL zQZQrXVc#QFx$lt*_B~R;zDMefG!R_ecpne2+9R*bM4DIIwr1WWa#~Mh_T5oMr-p z13>*$GH5@1hCrZhNC0hCGQ!jinb;35i~+!19cB9UJC=4}t2QMAj_LQ6esx2R+do*| z6UpNJ1_vynLi>_^^X)-55In-ti_%hu1(a@(K3=C%#A!&NUq4lgn7(`E+txr**?!ER zP}^@WOJV;)BR&+ugGZx!4A`#-+rUB{ZvhPHforgEsmI>MlbpK0F++UL4D~s)kL}va zCvx8c+8Q{!pKS(Et{IDk`|lGtY=2GXfL@m1169Et;~|i$5u}C8!G&?f+C%c>^-|B_ z-Wa_ckt28%5531jHKZ{ktIfP2qDlxx74W&m8toO(#}$kbS#Hq}E7Wndukdgj)E!*zrFhP@26F&_NGexQQi{UzLN`$Id6vwk4vJWhG9wz(sQ)OLkQEd9aCt`CAN?i zjsnS3iABvcuZOr!k7Emy)SQp=9>J%%P4^eWm>J$apdY8qa8ROS$(>c`BUaBYJPz9n zFVdf+sGsZgv-@HmbI!|Otz}}?XegS?ityg~AaRq{he05WCcdh>7d_gba8*V4Gq+dXF zCwgcsr63LzzC*tP=4Cw#(Sp6FmtQf{?#ELLR0q+4UppvJ zIiw-5c)z9nPO?;m`|)5*bG4~t@JK&&=H76mMbGLG{nl9l%2XLU?<}tWmR~#*2F8U) zO?^DAy}S->MI%@NX!kK_b_pJgL$}F(+B68&Zw%b`^SZsU_c!8Mq~0J;4;qkuhtE z+w_>y+JXdXO6wexE}OZ(C_Jqvp5g4Z^+oH*oKMfUfN0f!-KTOG_UDYk3>;w_0(nAg zd(G=i$_m2e+MUJCGH(W!JHq@8zg>QsXVc2xEoyNNKO^HX8Gf;>uo@cWT)&QX8w=RM zCA09Y9wmm~hAyVF2gA+}c&pCF5XUYENOCpAg+OX5_@aP>v~q|Q(r*WfWzp~wl9g)M zcd@NeC*;>k>34+QZZ(JglH$J5ekpzZ9WM=XS@ARET<$-6R);(YZw1@*1ithlsO3=z-7Q7aqoI{Y7Gt zdocNj|FD;*O0Mg%Smy?;-2KS)u)6TD{VD8$Z*z|>l9lTz@nuJvksqn{iLr`6i+E$9 zmz6?(J~}T&gVDq{vsRVX0^L%~MR48fF~ja7p}NiQ*h?L6S2gO#+h%uIJYwP&HM4e< zq=pZJZ<|k>rK88x?kpAMaNQs99_VmsK%;O1q|M15C!`cJFw-2Is%7c$MJw- z?O!AY#vIsla}D#9v2~ITaxTol#eVxC1rFFH{}=1+viy&;zOW9m$p`!H;~@oEQh9MC z{zchmYnBv3*>}U_NexmZ|B1Gfef;8z7nVc&>7bqh zaIh}`hd2SSE6=3}UjSHj?KYXO_`;p(T_i(PE?CB2d`zg7zrQHF3L5%bW z|8DgDeUN{5bO(lS;NMdIRe3G{KF7bay8|OQ{4gQ@mHDTB#Bl!A^Cwx&E;38zG&I&NT4?*ts;nG7c|z5M%Hh1HI=Qm4 zs(SeN&R8O=*IdW9rZe%jECsERY;Jra8B1j1(cJiGq@#nKdjKaR<;a zx`L`y4x}kj=}PQ~(~>E(Dw^)9)f<2vDJZmm^c0P?@KUaQg_d_|li7H&Mk@!rSPySU-3sZG?!Go6uSJegY% z?@VRZHnLQPH)vOw&d8dMu4EQG$ra&rq%EE`(RB5sDdAiy+?7m3g`hK%HhNb$vnn2| zZZVy?Oh#||cBM@&N*~UVR<*>#iDYZav~;G!v3OJrHI16U%&ykfc&0Yd);=Q^%b3o1 zTO=FFh8YvOAkTISx2GfF*49`>O+`h8>B#2V8Lr(VqT!ZEHg3`Y?p=fAUMdxXZJqU*R7+MfjYl%!Hl!jMPN(=7UM8^$ zK6k{EZMk;S+L219*TQv{DjZF9Nw7>h!Vyb08cB*1E8=U#2~#(#_UOjWmago~*>fGA zOiL=-p7q~-Mx4_fk+rN+CTE)J7lifdGBRiuw6-h?Rv{=%w6hZ? zuhGlirn3d+nnX61;0TBot~47nVEHq8pE>| zEu337FWfX^=KMM88E%R3X10m8_*9A=-qd|0leLr) z-5JhxX2dXYb!LL1XiOxrZ_|=HR@MoiiFD=K9a>)sC8`=z3c|3>Qps2(vo;JHtpqr3 zNo3LnM#ooK{_w(i3gPN7@ijRs)Bb7|y=uN1MZp_q=|~ql#ea1@XJ1{P(-3ZIn6a>N z?wke_Pp<5Wcg3}eCLN9Dka0+wmFl!2xjK``#lt!22Pv;yHk(SvGcY&R#ixzZx#-#s z$V6Nm^_fJZBMc8(;;d6HW9pOjby5r+9TBOIS<)$sT3hvIz4jz}Bpva0r6*_>QzV+} zK&so=da2mjVpf4l6OZR0iv}i>%cfde&8%7B1$B*$b7qGd=QJ#-n>8mqr=ej{gNedy z*3-1qNp4#s(Kte%OGQ&1#;VE|y92`!ZNC{!GwSQYb+g$!b#qTLs}dP#4ztwZRGO8^ zur%Syii%3p3TMNSXgcBRlYHHzqIQ$b?07cn1lyZ)0ZENXh?ubDDsxIjBTR_Z%pi@@ zj}nFaj;r$Jnc-WI_)J^NJZ)DLPdXmSIZ@QN2i&Iu*e=->t4*{kBb{Y(33PNg+Yyg5 z4QmU!GK_4$prDDzvssf|)fq=zQ&Ao?-P*{icw=YhEJ&MFWssNIb1YXEE`m38vt~5O zaD72TwL%@l=`#n3&k4_8G-Ec5owaDef*A{E zhfi#%Ynl_TUsSiSiCvj$XEkfPS{9{EI+e+3rZci~X|OEwje*hWTdYB&0HlHj{0OGck-?Pb`ug`o}YT{v#K5iaW!Ga0Uv+ z8Z$C|xOxUQve)C0PLt}0VXx9`V$_`EvMY_wl=~9Stk!IqCpx5~qeYfNh7dM{)9q`s z30yj@65dUewZrgXFQsYQBON(>sg$=<>@+0N@s(YPv`i+OCxW)jcFG;)^C&q?i1h+Z zG-}NYTdlLRD~tiowWcziMSCD72^O5iFAOm0iwU#8P-L{EkyQ`rIP`69AmcMBDR4 zQdDM*Dtx=;>GrBGj@w!jwK~o5HHna7P!$yvyIDs8(yf?f$8cWV21}Z1%SHrW7)V-It6w+t8j$t#HQ2*&e5QGwi82 z?vY$T%r}l2QYb$GA4{4sfh>ETEvmVFHSTyW+{4L>rsO%MJ+B-6s%mRa>peMa=t?HR zyeMh9v|(9!9A|445cc?*D58Zk8fKjM>}DK!T^h}t#wVfH3hi>y+eom# zPz!Nb2_>}6td3-2rWR3O&>G3d57tt&wL0Tb(0%Ytafi>h!q%^hIIgd3H@wpy$t0bw zL+zvRQW*;Ea%FRT)KBY5wW1gWQnF?3F_og^kODSE1TWZzS8_xM3tD2hWk^|9X016H z+t}2Zp3i2ecT0lKnT^90p1F7~UZ|&ZtmWiGOOi^TB;qWreOyWoy@NtV&~Q{*hbF zr$HjKz`jhcj@jLaD-t2%lArIioCa*~Y6(X$qz-EFf(a{YZd11>V{43c7@=TtHTpS5 z^G?Yd3L=7LwX%o)c6%2Q$Vi)pqnTW^hokDEG`s69JsmBPa3}hdogqo|*S38%MDp!4 z7X{g;Die=Mb82&SWiqhS)U~XtcbNhwGFUHpqG9W$6(XWoBr1~;!8T^%s*ki}JtwD! zqfkBBcNFqEOUmDiLu9p68K!F5I#NWV&hZu}{IIvk{gm~A#MnBsN>azdW~~$$jB({8 zxeA1-YqU&^AnU=xMa2PpP3aNq+jk_e1nJJoNI1TVxTj-c@9|UY(@J=Q%bxY?taVSYoYs*|piA?inPUt#%8ID`b<;t<%rkK|xg<}gZsC#{ z^XrHcn;PcKSU|Yv>7Fm_N3DaGM$4xovQe`x=~7z8F1#0KNH4Dqcge4@n;sSInY{Ki zQVEHqm9XvUII?6ThQ*x`whr@Brl7?d&IECI0#%7;-`KRMzTni)U)LF#?WB#Z6qb)0 z#yfBnXk~rM6~PmzX!cqcaBcEK`s6%Noa%H}zQU6u)JDlQSt9w2Jq8cM> z$dn4+3p>KOnf0^kW?KWAH4RRUH6W^a`R$BHvMieQOECl;{5D#8MH`NvM}*8AF=jfu z8u7DYob}U8xMaj0_z2e2co{#UT*W{(71t#8%xGHN=t~4KLqzgoJrIeEELA?uq#fg# zXzL4gkR8;Q196jF(B2VQw>IoW2idjBsL`eqf^7Q?t0=x;V7}x)A5}An;afYIZv+<0 zOUh>k!V-2go}H1jQzqrdWkpV!REHvY;`%trO8!(i9N9@uT2Ss7Ul*RRP_ijZfG9FN zYr*XBd}Mi6BZ-SemQ;kQ3+p*+=7M-1kSQzYq=Bhdf*iSQ*(9cuHm&f&$Bm)YdR11zpvsD>YPcjmcBbga>^nIFh`HFK!0=XYUr2SPlm=7`!mQho zh2<57)s&Vi1YYyru*P9`KPZMh4Gw6G<1c5w!HA>!iOc zCsnxI$fPQ3c-+P%0I2WmL^E;BVw&2!k}D*Wb;+5E>rDbbAO01RD`D~1bR}7!Sh%9v zW+jOj>$SZ8C{={Q=tsK;w4Atfq&wMw`4-iA=%_qY<0Z4~p^mnNQ$Y+`9V@Xv*Z8HKa9^B3-noVdk9q^G#eXs7v0-zUqWQiVvft7{fC> z%88KPVJ2uNKM6Qv=AwqCIkRnILuy&rPiQ zv6@S6fR|S1#E^)+1;$91sR`B?4b?IUK~T!x2A|TP+11V*eo^I7O;_)Ee|~95bZF)-hP3#XkjdnM%8iayHy4hD`)%ok_MQ_evWU}MX{`q5jP7W%Tt*p?yTCR(r9rzOK*!+9%bs6$i-+t z5zOjL&nA^%S`uw@I6;mijn&O_?I~d+nN;WU*bJrhk$tZKn}XSK$uTeJjJDtt`C8fE zOI6jxY*u$F$&MRtGS2CgCX;$73gWC`$62mt%lP`BA`exP)mdfTZNF|(-j7ghXwC90 zr}t-al zsT`&91ZF-u29jp7-y5SkHJXu(&DME<&Q%EN{dq*C;_x#qTR08~+jE*87Ej8VOeJ5@ zZe?TS!Ah;eoci#>MP!c`>SWaqsyvS-yBZI)-DWr?nAUI1_eMR>nt9@Ec32Y!i&+lD zJrkI3F}X0*lmb}eQ%*MBn?q%#pEXLRY#@}cU=XLj?d<&Klc|Tr)-FpYa0W)^0V4)$ z$y}xr`HZpUu3QUeia85OyJX_3l_nR<5^p;Ptl(T=6MD$MB-w6Hj2g?=vZgQ-q{1#t zn83Pcx+jBBeZlj}dlM2NyHR2-k`td>aDyFEIVnbhA#07y+xS!%A z@`E(_o(bBAqj`5=)<)7!M+=$MYCp;B{G@*a+#C0IwLoN1A-GvUVzs$Bf==0P_ zbrmPTH66aLsg_o;9&q&(mZGDos*?ZmWk*}1HHXvN*)zDJGn2F56YFL-)q3%0v}H9S z48AUVvZ3{sy`rCRcBQALynKUyx1qXK_fK?6#8m>aBfg=@%Jo;?NX8^? zB&b?PFEEh*3pdz&-n}26HF!?mZ6}?D*l-iE(Y*=~kov|W%rRkWk-R9#>xv&im?sx$ zQk6>sBA+wak!@C1G@@KloBa)kvni)4IE=6dH`Z9^7h_T$sm&PXj@@b9gqvUJL z0kLSjU+F%H|3Ptje%`A4K^%9)hgjYo}_{iSSivRsk zUmFd{k-KLDh-9uaiUKDzHJmkAcb%^{bFy!JPd1(ts*VJ=3cVNt{mojT2J&~MJS)<& zAhM=jzmdVstO&fJVR8PzzpjG?MBCubI5TK%-RZH}}dMnP&DX=Ll^w z9@5H4q9x7~MSH2yY7YP8N_I-Sm@#~>z36nR=c3@I>kP~$btT_8r(bX;ba0NBC>1L& z-=)gPM7a3PhV-1@Ap9J}`gwkKvCWSql_}3D_Ch0&PS19=IB{X7oD12srb{2#J=WsK zp(M{6<}}Wc8|qz&aoa-bGnMRE>urpzm&LcTrduVjgqs`IP=8?>x^!u$!H%>JOp=Rt zimy5dRwcO-5twY(+KNvi$*WSy@Kkky@T^Ye{#=USX}8<}7WpsdxWsUHj@LZb{V_GADS4Ow6joFy3JSChQ_y z_MD7D@lj;T@cif6n=6IlnxdXZYqIv_9HqB#(V}|887nEXNTpdod<9n58~LCi_xy^Z zA9wjd7cP_{_IVjcpUQT6MxcMl8PrXw3 zzCrMz0w*TrYpe56xFW6$Lx;6{abg5d^QSwx?fS)qwvt$sF0yWwPKy)(7XkxWWM_>% zZhhHD_co`OpK$I1>1!xtn#wGDdY}`gM%H@Xsgk~S_j;?)g4^oUcm9}8;-$^zcyHBs zCE4CJl~w$y(aE8d74pz&UD__rCvm{h_}Uk8XqU7_xFCmG$mYDTpOal;F*zyrhM85M zXc3*KO19C)_zfr^j+eY`BWvbe1G5Q(X#3IO4o>1CX%2~XtIC@%BNDf{D+OHn@Gxj3{o~a-zA5v!ovh`)z{R`TvDk&+>;?4 zW+MQ+a)NPp6wY5?@upgJJwpb=`Ba<_NSit;6j93SO6~Mxn=TmSe$d&JCdfw zqoA?cW6Vk|7S_!hq{zT<6Ug6&;Yn<|o_8)}hHWrtPZo5E6NA)(Hdsx%z_sMsIlA>}!y7zS@->Cj zTDH-8&>iv0$+|y-K;v(v2?pn2^f+~zpK61_N=!Igs4&&4YLd#Vj-nOPAO0MrrsSy* zDA{=;!7j$Mms^c*0_}}HwgEVi38+@&NPwiMm4kd8W!ftgMDX%2eA9pim7|C4^FmoH zD96Q|F8EQiO@iBBM-x&GmWVao1smNVw1E_t1aQzydR5UCQEqJY2+$S&*|Knq)825xv1%h%MnsA9u1eyiw#S?Swm~`9 zgCYEjy4c=FYz;?}(RT7hBE!bw*)DelqRZXb&@FcxwYep0=ZEIFCrG%2rIMqiG_XA{ zg14SULce==6ig=}T9^x6{#|0`ZoMum;k@W#Pi$B(X*uUB)^nn3@2*H%?RA@3)|2>O zyuA;QmsgqRdm1_kA;h3ThgEc1(z-ZFwE1Jw&X5Rn1C42*LpKRJ>^9I1beje`bo0-f zYtWE{M2sXb4poyHQ#CltRqAf;7!?h%G6s`q&|$aGusf;R%nUOUMg1jV%2eId^?tt3 zbI$vo_t)sm{<$~$(&u;H^Y=N=dH$dCR);TvLBvQfnvB#W!>%m>8Nu}t^&<=0monl3=Fl<*+jobQ{OHt? zGTy(A4WKCEj@u(OP`eB?vz(ZVGijpYq`s_mqM`8gHaCApV`vzidBSsF zahY5#C75CpL6+;md!2eJEX|vS+Zg;3A_PlL*gLuoSvHGMajnv9a)#(ob}g4U4}1r2 zDqb){B7`8AX&50~9(uygAe4hrW%O#`unra$$y{|3KssV3*vJw$GJvRHA#x_5CW%Et z>c*{WhX*W3RVR5c?gnVN@qL}cDtdq8HCpn zJx@OtA}{hM>}6>Juo5#_kojwzDTL+gH?iFZ&HwG4nxCTZ`OaD2a)WI$Y`#X$GddNI zu6QVbhd;t+H6a6?=$G?CmtDls;kf2D6)j}^rjqJIqId_jj?gIWL(HFDP-oVAVMp7N zk|YdZ$XQEBIw$9BKI{?#0nDdq5izW<$C7M^1+>TlYsW4IcC;<%k^yK*_wu$5b9%av z#F`Not4$$V$k2LJqE&Z7$AAvw#G+ZE(sl^N+s_d`%JyJ+ z6tbO$_6P)Rc4`!Fvi&l@VzDTayv_a6Cw@f`xxf-O%7L8p|FC0;!2qkQ$&vE4vX5B^ zORe2V=q-U(GO-9uDBgWo2^W&=^djk`r)g^NrZCul8@<7yOMkhDBW@PJ4@bbb6m7vQ ztp)tD&=w%t=W$RH-4+ruxN<(nbD|y`Hn?|1UI3bo{L?~Lr0ZI6ZJv2!rAVt;fP3b5 zb|#xI=&C4bxqpyhiICOya%-;(T+C#6FqDyiU0ZbwZ&aa3rU(@gsD`Qa`#NDap%KO@ z<(-z^fdf#^88hG6X%&f(1hsIcPz-ORzmI6VoV!OX5Z_RUvdLZROv(VUhDu1F(?WPX zI5irv+=5jA<)SA8lUSWf%`U(;r<|r?UkpS@1+}l!K~pKeET!pW>HSBNo~l?SDAl0& zw3|ORm|T(y%17G*aR5X7b^andg-5a3il>gdH|l-GaMes@&1V)TQq=+9C>97Yr?c2w z?!W-xXKZP+^h9ZoU{iLnE+~e?sAb%@zAJ5^<&hR9Cw^hhujIPUh^n+WMPPVLIId{) zM8=PYxiAYyuohM{KlFDIK7lrm#i`q(8&FWB14d)B`*z%{h<+m@`2rXz4k3uQ`6kv6 z_l**{p+gB8UGLgWIzkG>O`{B0*>H{e*-MQ~s4a`QOtuauV#gJhSUSdynWcGgLJ|v) z#NSSOPtwQemW>;UO_T1tnGiM|b%jP_=p1A#DbO_v(_`o|-ZodJSuhju>y9=`rRF@T zABHwFdQ!lm>6DeR!=0hq1b(+y>8Nz)aG%1qqV{95M?XR>7PyghpoS|s16aCbqSC@DlqM!?akriyH_`kpV=bJnl}>*Ipe)k!NXEcJNsS zLytZZ2|@F-80rNJZ|l+#!F3Cx6H7Cs3n?}DC0GD-@HFx{E#bBW3&C7m15tvMg%p87 z#;!0D{RsTpE;=XWI}te=jZ&6{WSPTtC@QJ|2a^=|Vn!en8^tQ!sU&$3-U`v+JTDem z)0pJd&M0A=ArZJf)tMQ?eE8;uv;v!11Oz?n-bmBj!@gBM|L?kbjV*_$@FvOiYgPN?4(u_XK}?U zKuxRdn_YM-M>x1a`~}~p=RSgUnRy45(&_t%qzv>aoEP2ks5RjikU8ze5A~G>%@1z* zAiZ#(h|w?E1;rJNl0{Q2!k8R5$!gZUv`gWyAOa=*gh8~}Y*Nq{T8Q0HlE}ATav?0A z8RpMwxn$7I$ruN}}#W+ne;XvaJnJg&`2T z?)?ohm_~vk%u=^3U4c&TMqBX zUeWlpX*NQsBjhH%Q5G zyKHY;x1{j8Q@Wgwu)R`9)P6h&X2A&n7!m6+D+WH}MkhQT^Jj9F#V`?8R`VQ^m%>ir zW2%!PmQFDyf-%CnLQKpWU~EjaEWj_iq|I4i5;H@F-4*jdI+VYE{dU9Zs3t@CfI}c? z3~FxHQ|z_YMKV;ei3w-4@L0OaEpQvmuJ5iBrXzE1X{|#C>y;!|Lax0VItlKJ?t?rs z@Y2})XpV_`mI z(llDb5uuyw2t@MKU5C)x;Z6WQk6awvPYBLVAMD?Tfxw(!K!2zFU#+DAV;fXA7nxio z%V-Awh20QWT?*vuJN9y-`H`t_Ve?od2ilt3moQ*+(ClA~QZuA>N)uzeP}SJrJB%Qi zxkuJ8s4#YI-SJ{q-VowcXjp9jGIX^L-J&yEcPb#TXJ|c(CFUj`GnREPT>$6OOkyyA zAHx+gJNALd2@I0O2oUYQy@wDSu^=cCK_Uc2!W``sk|OJ(u$uvLQFoo(EI3<`csw*8 ztr%vnAZ&R@k3^wpMR4QAAO|B>Bw1$&L#+%t^2!X#p$Hen))r$CpdCbmL`!@h=h}1z z@{^J^alhP(tFmpw#zitBktO?phpU(+avcW++GGT3i>Gq65zGT?FM9I(k?E4S+IoDR3FDr<@YElfS1_s$WJR4i7>EZ!NSnizHrmF0vkBR zB%5j$cEIMr&SP{%+@IJrg|#KTPA*U_nc3MA)nAK6uT0;V7={j?8pQl)fzMKw+5TN{ zcSKKUm~IBzillGxHt>Mxj!5i%;ReVX@=>w=9(*Zh1Ix!@Z>d)BEw>7e%<;fcx)2A$ zuWEKKRvJMD)}k#B8I#>gVn%e9fCQMg*aqcYD|1>BajD98Qfs0-gd9hFl*zItO5m7? z2LZc#x(aWc!7vFxg!*kCnuVQ@;4*iUae$LRnZ-H=*YokNg*rQk(YDy)Vppagpm=k^ z-4FwW8&V?1bK85l=#9B4I7{+BUWgS7EdFN2ZNwww&SvBVwqG=J_`M(I9|V_;%rv1F z8HP8Z=!X6QNT5lA01M^U*#ZNodaP6Ai~MKKA$1pwR8~<|yP%@L4lb6#uv17P7N29@ zV^daaNiDhndl>U5009JLNQ!cr?xAVZl~sK>f=34M$1XJA+d?}Pon)j9JK}+GJBKNy ziUeKHUSTe zX*+hT>j_Q&w{RERRDGNav{*kJ(OiM0YtRU*lB%$kT^1RPXU}nS8Y7Yb9?RYk|K1pO z5Sp;n37~{Wqwr}1%DP)6Fydtx>9Vz&H9KFqS+mi^@p$B{XpnQh@|8z}B3q0Qi~QGz z@t#Nn7yBtC2J`02z0i&1)*~&g*8<0M@{Y6xN%hVNyUe{L;ckTKab1rN)j^LGlpv_| z$G;l@>76>9T$)Z%b!=Nlsh({iAG5hMtS-^m{+H{&iVN*H2C&G?uk)KOUvLYmLUNr4K7R!mZPW+kRwSLPWIE2xe z1lAnawvBH>UNI+{m8!I-AF$IS1#xMPJM6;JVG}zsBqZu=S2&r(Tx?di znI(oOAZXE`@URY{{kBb;IJX4wEAgpoN4SeaHUXKZ2oZ|`L~OSht+}(MPc~WPCgiRP zjAZQ5iD0#9^6Ky)w=&6+rhpkKaP{~9u#L@Y8!3UNhoGe}23U)a+%IV>qQ|@ zCW0d(z&a$%PE2t|1u&-JLC`&@=&!a8EG=VlTbQFhdyh;4We`%JI68+Xk5mz;m<|=U zaJ)E*9wIo3@<2FRAWM{65YpY33g?9a1}UR{<(k<Z}E39u!G)Gn?epnL7sJK);g z1H>Kgkf}g)aB%ZFPK+Z^45CPYWreP$m`DYErG+=nY71{JSon!Vk0f)Lv>}R6Uev%k z7UxXaH{8c&R!E6u$lfc!GA)_2J6-8z=aJ3dB0_0mLr%C$FOi7)?65>3hwU!OEGa@% zab(S!eS-%lDOMo#w#h@;Rr)4{G_G1CIdYewpP~~Kc8x)XhI`Q!6HQ}Q2nb_sF?Izn zYob#I1mvXaOo{jzNztihO0p<}blp#BvB2!BuF$Go285>?j9X^MzjNYW?x&NHu7#63 z74b$Vymfe{TM;-21H`*>Z-o`XZ;myGHt-Cih!h^IR~S83!DQCsgd?`Ba7pT70mv8@ zUbY7JvB-X7_nCThq#38`3}k+xBtj-}gFuTIE0b=e@_0;}gGL5nfe01K{-U!-j-iv< z$%s?Law_oFr?kVF3G~)&wruIP1srd)dvX=S>kY!4tzo>Orb))TD|Ix|5Z<_ynCa*c z0VS>{U@g|M7nyAcArqBDQV?pJQOD@Xu)rq4Cq;ZCjG603A*tF;3bte&%_$WF5`h)x zknoVmKq)#esa>7qE-q`-uv}|ol(;v)vP}H}A-nsxeiRAW5yfC`I2q2ZY zaAOSV>oH%v_&HMQR$XRm@>I0y635djqGeJ`Th~hAS-*%)JRakF0O^Y{;Gu_x6Ka;u z>cJ8q_8Vt%oHEH4b&{RrCU1tk-*1P#-PI23RBHKVEjul-K^PG1vlX;V}-U3DVsEdZ#V&NbJZF|rmQLb@qlOint7I zn!UuO6x-~IL*`i!n$DJtQs-=r7s9x`13nk!Pqesbli0ikUmetF8;k;L4j5I2gC?!6 zXGwQ&&yuAJm#-u$QTCAeVNBM7u~}_nv)bKAVN-$gx-OwzFtbH>{vcV(5xx-v4l5xb z*+r%h0>wA=+m#rF6hMTJtWMm_j{N`%1a4wdV6AYmvLQ?qjB-X9&l$b{oOVKSGVh~q zT@dPt9L|@*HVi)s>By8(7u0U8WaJPi+qST^`aB1w^qntiP z!}9z0jn7G`sa(keL1yX@GiZWcu;#%M$*z!@^Z}uTIf`r*0MspCNwO7}05zpQZ#>Uuhm@lWV z&`~7LsDKk%7f_74z!FnPx#CPt0QZcjaarSgBwe{7S$Z3U@h15BY4G-h>rFy zv1Ft4xD+IgDxAm!12DzxOXh>JICG!BF1!;ww0+`rJDj}brV^RFJf;M|C71uOjv9Ln z$Wwuh80v+^PTcCSI35H-<20!+`S?=6re}1aEL1;3Ky4 z4RlJ_MdS8!R-K2BP3Z?RFeA!+YbTXJBra)|CgnF-Y9GeCAUq%wJ!w=?cxkaST+ofQ z1fS@@1!@$cOa=zKsaoWpKJ*$7?yyUmX5Q zo)3YBK^2O-bVNI-Q_XS2l6ddxX)dltmxmO}9`W)dErMmahbZF(td*|Q-r(4rybbN# zJs3Z$fUshuPn!+hc9$UvtHvF@GJg+7gL1w3K5m5M&;~h^J3GmE@=cfNQao(ov}Og+ zfU7K*r$3zKm%gGF^t-Y=h%MirNZ~Lh+wJKUhgDpVDuiR_N|K4?pi9CH*l6;h$+she z+yv1!z*Ufu1DHSARXd#$@N0g$moDvE+HMR`#sP^?m^r!g!5We=$!-@Ag^rgC@eK}6 za~Ib%19F*rB-QKEdiK<;-s0{?tZZC$Z=SM(ODTHX5iYpovv$IGkwjN zn}Q&Gaz)QGl6OZ{m?=46wG?QE8MWpMok(vy=Llhu0`TCyKpxCo(#X|8x;i zha2OeoZ{v~2ve?|#GN1giE`dMbp3qTSQ?<5lMtZo4`ivoO$yW zV#bUd?T}?n_7Fd)sKXC3N}*hf#Dai^uk|#dzs1hkNzyQviaDU-xdiBiad3px;x31{ z_M)vZtltdzn>KF3;$dI6Q7jWT#}&qtTW&)Ta|ew@YOyJhm}9tVPB=ZXx$ZV5#gZ&s z%tujlI$*)=(f-#r%k=ufD`l=lharoK8Im!`2p|j)Nw*W4?(K%Skb#hnz1p^`2L3%&iRBTfYK(pY8S9rI`?Hb#?Vla+*rk~?$GBfbYx@2a-tGf_$Lw! zLH%M7^BC#8@vsceieW{sF^#)06Bkg|O39jPxW^^guJ&+;2FJMNzBE0Q4Nu%(K>@fj zr?l~|g^l)(?Ao-B6E{wqJCouE4q`P>XTF=0WQiox zhR$<`88R?xDh}2^M<;8cp>PzqqBbW{mfKZUa(-#E4A*A)bk5gfJ02cq*IL}b$0b6# zdlGELHe;HUBtZ_Yh){QLiZ>cd=r&W1T>oZz)^<^BjVX1dNNqc4J-2gX6S05;SS#_| zY`=H_!ESO@>^J;zUAkX%iB8t}(Pz7^-S$Is3ZM$TqCwCOx~cjfnB}+^2~1$a)af#+?>{$>j(-j|f|rUngvg zr|g*r91Zr*Arh`&2N>Foz7@2GsN-Hyo2Es!icKMLWr!)~12Ldd7A2pE!s?EZltv4o zipZ8*Nuz4zCO}iKWNQ$^iSmTp02tK z_~(5}OdX8m9v1G*7biyo!sotdfxXqrmj(vYVx03PRZYy?BDohJhZAJov#?E9t@>w+ zq(bRj-LmB?md@|YJ{Q)ej*1W)?jYdS_;${rODxkmx_>wxi!cb&k8#G#`JHj=x@hQR zXtStjcnE&cC_^u4UrJ!xhPeGCj!V~;#*wUc3Bpd0HGg80iVJpZH)A+OPtrM}S+JFh zhT(fqflf`vuOb1Xo)rt?(X`tKw%BffN*3nx)PeUU6*L@CaY&puYZbXIl(raZjO`hrO3M z0v&-(VPYz~jC;rxpx9klX{8|e=WJ|GiqqTvP(H+1!MrZHc- zv;%0C>SLKiG59QLkvUH?HBRKg4lUg;W4SRTnoNQN-VfR40}JYK%?C zD3Uj)n-j!1WmQ%%Dx8KRQkhLzzBPRuCs88W0$*S}c7Ylec7fAaNEY{o>C`E#o2Vsn znB*dusyr@zyGT5fY*=x`|MHuKUCX-SzF1Pd>ax@Az=ieREhNcixssj4sIi3@ z>~eQ{1+!$GC-hRr$DVfWP6=spf)lqU8k+T^}2;f+MZNnB}?BZD`Tp+qf z$v&_`D2dTJJ4Y3d*tw{xPbP}udk9ybSTqc`x=ZxFU*bMK^uf`t^#qinY;Y*W#5mzr z+C)wSrF#pfg@@@(P8l5`H>7xpLNQG!v6eab)n--ztt$(zLsoHpbfI8or=Vp%nT3Cm z@6=*lllX`>7w>H`p)}zI;3a0x?{6x!MsD2Y>P6{RGIWXx>cms81ZQ((>zbyaYC!AE zk95Rnd7YOkZq1PJ7DbyFW?}k_f3>!|Yrg2OEs90sR7Ix#7CU{~w~4TIjl+oy#x71L z%4BHjk$?HOcP(dOxERf@kSeWae8E$JKkN}n#k*% zDVi+4xM|4H?**PwZvZ2ovN?F*E5G4k<*n)Bu zO=LS6a8l zj_%7RoWw-Qs1ils1{fZZ?-%F;p+>e~ora9K`ncFXGOG5>j^m$~CaLgl*d%-LmZKtyyq=NpEM zN4f&(JbSRXkUw615lN;KEHt96>?8BDaE0iA_J9YxMWX->OW@ta{?j>qEOPp2m}pgpc$>;*7;pMl1x#NbdwdVQWqf!^fEhdAK3vdl2_Lco|PiAkW@#E7$%1}Dh|*{ zRUnUd7}=3q(?7-l)fwD`kt$LSMJt(Z2pan}aQ3}bzHTEEh@9i`_6n&wnX*`KEbwDK zNuFl8HsGc6FD;tP=q~xv0EOW_H<|0()xX0ag$bZAT~TvZl$vY>&{uY{xe?IgClh7( zk>~{sQ5csk@9okR-<)6WTE471ox)y<8-$OJ$~GW6?*Sg5h27mCjxSGzd0ccQM~dPv zR5$L=LztBBb_YVz2*^SlQXii{MerFTNOcWvoiC1;iTc^%i2)$yNO5#T0nhnNd|^wN zuW!AevfSxhp+ID`93a}oQR=1GDAK1fb*ZDX0MYPXUBEEXzfQJ4-+{e+@N~$I#g)N7 zzIOoHPHX^uQXICq-%^$$UCFW40}t8CqHx2TMB1bw%DKLQlTvnJF4xh3m9o*LIKT?J z#()!7C#|M7G@mX5kopiAe>})|W?xhW8r#+W|n3Qn;cchqwq4!=6fc_?fANbHaCGBI@xv+KC)mrULJSb zDsIQWg>1;x&*x!_co~g4o?w(5BwEISA|d>k1M>PvPr3q9)y%I19L$m-hzV4Zru@_u z;h$i;2NUrMjN%ZNzE?*y4-r7}58F|xF?7N{TI?z`%jw=Fzz%VNd}Bs*S>G2LT|z^F zCvYD)Xh0AjcT){@ZBcNGzC&;Q;vXCw)!s`%4muENA!Q&g@m>ZNSF=oGb9!O=fv&Jp z^p`nn(mLpyefpGB+Y;mxbn2)*2^HP4i>qkc@T?MO5`!^Q7Ra?b5q%lsi=PpseiZldZ%vxK0-o4~z<^lpS*u+BdgCUAf@kPv7r z%)QubvoL)il%TDbUS4f#tVu{jcEC7UBor(WeZA(fP+u+gfP=ZW)#!Sf?Y+Q@0)D2DR#0KoPo8s#8!Pb^J zx=hh_RoSx!?$Rn-j$>onL=Y2ez)G8uW65vsIHa$Qo456$L7OoMrlz{Y+j8!O;F*hu zQrl%2NzuY)ri=Is?EpnNi_+czUn@u?V8}VTzV=={`qR05+2Z(ldIf()UB?zQxp7TQ z5Lu0#fy}xV$Iy#DZgtQqxaQk=9USXv9Hg-Ja zA^;(+Tdj8qtSv=~GkK_cNrTcMMFhU}Mj3ER6I*30!&tmzVoW7SG_nnd+W>O7efc?t z0xH6v(&oQZaq73lSYIQF9-=4HoU|5Gjh#eTn;0fi^dZDnEP!pNTPl!r<2SmKd@awX zW1_`MV8x8g!lmNw!7c4l|BY!#zk|tI7!Q;TTaSh*6e?^U(qTRNs{WQ@|3t%<(7AB& zeD0%(;YRMRj4B~!2iFZ}rNr!%n3EFndF;~Wam#g7;<4X@`|;MD&g>g{-56ui*YoVA zCstns-!JH9?Q~l@^27p{gnXW+XmW}|w|H>CE$&IvJZ<{xwY`nO4S&j35+i%Ynd5aZ z&XrI#g^04%fOUL90=n4SD*?tNTtBj@Lub*S5If63Em7Ps6{}S;@t0TjT0kV$buANU z%hd{m+nJEAC@-#dQuqtsrXJ`^L8Ia)vQa5uTu@6?zE4uTP?BvMBL}isdCZBiA+%vX zEvE1U4B8m5Xva-*5`(ODIVRMQX=_4q9-`Zsi*DC1;t^!87S~i+%&&!l0GeUKRvpES zYE-r=h?&|vNej`2273igB&|#VAO`c#Wu>sll!F2tDz@#ndAA`jZghd)3fC+P4 zfxdQVqr%Sy^gZJRJBn*ax)5jW zSj0ZQHa;5oXtee_CwtRzCLPI@el7pfPKBH>bJnBo6W12e?r78Bw{9&Gmies2Lo_l! z+uCbk#>gB6TSS+FF~ebPhjHnPK<1iExvsesU>`A;ozAhA18sKIFdG0oF@uyG5u7!_ zS7>W#xFl@%B^-wHCq>v%PKT`0H=UMl*w}5>uxMX302(5?VS~X+Lvmxb+{AYOkB0(? z1eE9FB<>}h&F+44?#24bW8_SoX-GwJPX>$2Hno32LY=xONl0v>Dkr;`TOSe`tf-UyL>wvzxzZ$oysrBe`V@X}Vt< zTnoxr?IKf)GZ3`xenVh0%7+vZ8cTm?&-7zGkfI_kM*RvXK>++wz%C zDFt8}KBw|NRVhE(%?uaXg4ZkU2elj(0|7$Ddltq5b+{YMCI!=Exws9-c$gw!6rCT> zs{0qL-O(o3wFwTejN zwkeHX6drZW?+u3rK|RR=#^z$yPczF~(E0|Gtc`y_14_TVf;-^+@xnE&3vwn``Dlmf zgh;7lR1a3jcA>!Cwjz3nz#5HB>w+o-n6vw_o$8gO1UlBv9anv$3-kra z*2XTGa?7xt!BemsmtBmyNUDMDd# zvea}0^UPl!zl7e`zk^$swMx#|fqInnT}m*aT6nF%r;0#{ID~6Cew70>wW!UAA~d4I zZeYA_W)`=X^a;wK(Y;VEFzQGjG@~`>0*1B)ogOuUR;hclHW5qU1YeE7 zMB)c#kU=B{3L9(=3%UL(U5-f*6_)074UhYj)^l;4DFaw^;RlgK3rnkejBiP}r7QR{ zVg*~su2GDD0H3W`x1DS4F}@{twY%u_WhXX=kqp6El9u*`aRxf$Tk3{x(OkckuY9v5 zjh^n%Ep7M<@ZA>o*TUXx)F3PD7vsaQXrsQII~KF>C$?B$uu#KnD3{hM4@oik+FXp{ zGrF^Dw%yr9KpOOjs88DzI=iU5vnitho{~&fW z8VO5MsnAbdYX^PIzrvTSsp5{kL|6GCVf#hIwp|DaC6agE1#X9zT?`XxkHV(i!onAO zcOr9Q)s9d$gkK<;Q)-yWvr*dR(mLh~_%eneyOqaQ`vGv>`VBK4)=SJMjnP z9t8P2fGUBh5sEN73u=Q2v0O+s2@I&Q9&;qT0+EsDr5;0#3d?{C6y|X9JCr!3!+H?@ zo`JG@Du>$}@^_Ubn3-MUKXL~jR@u6dW61rvTgdpmosfVH;2t4dL6#OnlXf)4Zc_o1 zj?A+8hzoaC6HS{MWK4wFXzvOEy(8An=EvF41*_=iq|{cyxz}Wkf#F;V6xrV&(F&bD&Cl=5ta?Cr|d;EzP93EWn3Ht84gIDdX~#D#1wf{UoiizLJf4 zuQ*BEi5M)458}F1ZeJ!`mx*rX6*77z77r;9sO&5Ou@rs+&ramUwUlIJOqpAS*Awnw zC>i^A1xmIyKZ~>;mQbeW*ie&)iFGtY)zPOIVC_`(4rsKyjhtHGli|C0>z1wK`fq&6 z>?nO`LPD<@S(hr>uS*yR0|%y%Xfyxmq7M-%3%`rj1OG?{s*lB+!U#qn_9J0FAvC)D zwOy8uD8EVz;M2xtbd+&Q9|y;^bX)YHES0^oZ2?L$k>$F36v?pMe{c}ah)FGy*~Ya) zMksxO>!77$r8MFwT2^6|cT$MkSC*DM*4b!E+!|qteY|_aE*md`JsJ-FR0uZM z0Ffh6cmR!EfMby2-A?B`V3E=L+ZNB4A*sUyNPCJiJmq~fW4&ocgu|!Sa|f05hPLRE z%5J7fyhC+Mn|pC16)s;?H>2H#5N4y)aFQn^-O(~D49X%0?PuaHa%H$~oO7L{pVTlN zuMjcx^^-uHBv-kU2$fFOB*6mOwlfTFhtZk~S9+LPR_EVBnj11eF`o}y`6S#dl z-)=U99ieAgexZf;gH)JPC$HxP2*6>N}E#6{W1IMs42<%8?ne+htN3 zT$237iW6*K(mh`%d~{AXY&XqhqkXId)k4DPI^Db%_XC2KF41sPlGn7!tENOQWMSvQFn; zZp+K1M>B?qz91DXTDi#iJEJ52pY$UHmv9~Ivq7y_> zw2)5hKqg+Aoz9Om+f6YtjU)qyxhqXQ)9sGQWE`Ce_`oD9ML#?k6`avnII(}^M7&Yd z-b@R8nqA0aW+I(xX^%9MdfcS1cbdG8$jQ;W805~a@A%x!YNHznz(6kB;k=Rz z9kgY$mucH0D;FUBb|MS)Al%Gc%2jKGL?&aaiQddWM-hm*Fb;wcOCX>2O?OoPIg~Fc z5<0n6)7Me?BKj7WBp+|=?g@9wPqi7ZG$oB(a!@I%nj7tM3hCNB)o%~D?jiI3+F8b& z>^ow7?9(rI@7dCg7t!1tg;QvZqGEU4aufTo9ht>39yH~)^bI;p_Hj2Fp%kwNp|)xp z4!}+9`)|GC@R34uZn&Lci0g#b5OEf<;gNLpul04 z(vmzRyu$nl*C3=7ozlz%My*!JP$Ku0G5>4 z!jWzYsmm}zd~TTKUz9awX>nvm7~D`E&n$8{-GrWGHgcCyJT;fW0U-{vUgbcJQ>o1g z0_hvHI6VLiZs=1v68}Deu_SSOF&<7Qk;}KoGo4yI)7ckhPB+V?udW!K70Irci2Yk@ zs2zOuwzM_KRwdhjY5eIBy!PsH&QJDto0^<#ZuRTAbA6w_yKE$zeHn!vcbJ0kMh+1_ zhxkmX#E#yXoTl`{juNkn?Wh^zmXSDz#eKkhDYvZOmF?W(YibrWIPfWp`;F&U5dIYz zVS<8=3t~Bvgd|r-3bpI3Ua+nRsAL(pqQu7`M7pC4J05bbwuFwj$^M8cZ;0i_**PD{ zKilB!0!J{iCLcSL_gt4E)PFgoIGx+x&e4M<%LvES&I5rNh*@~!28@Trj5>Gw4t2%G ztl6-=Ewb5~i!?Iac=DsoZ>Tbf!?7Y@n|8xT`fQ3>lre*_*nWu_@siv?y9q{W2W!kQ zXW`|@^DdmkuxY0bis~!w`>;4pEG}z_t?DAiSf6Y1kB;#X0D;Z;ARADj&ns_TVyh|< z5CYLe^bX+@18n+UVh$6v>g^r}hln1!<3k(!`aZO7sQ>!mwI3Q7 z9$tGrq;=cQ4-E~j<3&(!k?0|e>DR2@nXGC*RHheUWBq1?35=x3!n#QphaN?=L2P`z z3U}ta&lJRU!ap-Z`|Si^s6r~I%f-rG%-n&`RY5^Qv(1DXa~%U;@YuT5#7eqWK(S3u zC`79=>&4IK!KAryZNQAMa6%8jmW>b2JhW|-cN=FwGn#<}b{oK=B}k*3e3etOZ|GB! z>b+~Oj_@HGkug7^gO=Bvw_~AqbP#7Y#{iKkyjkYUVNqUB@g=VhR z%;wE^?bF1083zkZF6Ue>DFx!yg1TQ}E9agz0AcFG=6$DQ>Pef;K#8vR|0N!*-`R)DwlHsPHp|-emE4PAH zg=;7CBE|i$7 zw+@p_V?f6m`x0Gb!x%#sI`@vfH z^r)5n^eD+kgXaF}M{D8kNn!lR7KVBEB%V&Ms1(nU^y)}0d}i3Hd3uj%pQKc zl&XB@C4QarQjGnxA(r|qnEBZ?snloJ@Qb0+{bw2KXD<{lnB+ZE?8QA(NVcXI_q5i+ zo(_Alr=u3`Yo^_e4ER3Q=Kg);mn-+_8UMOzPDyQ#ndWZrHE(c$1|K&}`t;)@zZotW zUu!rHVq48Fdvo^@ejc^tZU(q}fMhnNeY|B}Ag=1DgO%CaV`NYAX1Yio@#IkoGUZij zjb|t{+@?P~BesaUM@XIub=)o zVt<+8XTZ46faq%Bah@l_jqrvmHwls1KK-yg5S@l*1Ut~$vT;`yn~Zuy_B*jRW@djZmDo? z%bJvx1_G0Kno`z+N&^n*ob?;<=cdv&sL#%&fv%KQZD0+rUN$=Y+22LW@7Y%&v5_Gp zx@uLY7Gze$|DJo|&uq3&dtW{LQD0MyY+7Mj�bd4Tq~n-hFVKHuJXdo_!VSau1Z? zo*6dkduEVqfxC!k+ygk^K{+$9qGV;{J7!(B-6=&mz*IIL%D#U!AG_xuMf+?A-TQJa z+w&eXJ@4u&luJ;_~?L6Zd_7*s-D#x=2IPO_(P};NF8%I!5<6@!NDEIX9 zcDGaTJ-aD#Buqfs4%4og095Wh!gDm`T&^4t``(vRj+Hq_PAyE}BulDQV`!68&SliP z4>Y>3-FvyOopevQq;-ceoBLSP`&NfbZj3)^|NaR^)bF1_a}vMkXf8H*$rO zz3JXawiE9Iqwbp)F4-1lH*2bl4wGvUIU5tBOYVtnxJ+ z&>x=u_@-=Qk1EtH_?Wjof`kyL4Y4uhXN5t7J^Mq$?OE1-*7%Si+r7sP0V>G$I2F!^ z294~z6&$y}iNDWVNzz$ED*9%HZ0)J5eLVd3+NZ6fN%w|(0?YWmJwe=BeeS85oV2HA z&0l$Mcw|*kBJ2H()xTWz-*;b8`QAxkqSc6b_fBHqARYj^cQVhky4S2Qz?k&#^Wjpu zNtJxImE3C2w1WV3uXTH`+F;4o>krRdNn2`A6S{XU&!KSTOj>WAIjzX{9;(@87xy+& zYqu!{2Kh4;DBr6EVe7L-_wM649;RpGzc0*ufBt)B^Yr_|yEGKEGr9t)!c$-yf#OoV>Y=EAL@Vn7*V3oA>cBAyz26FLJU`Xtu{g!v_AuF>c7-YPSCa zjlRkLys8SfH^_n>-L60WHd7t%>m;iuj0coT@ceNY_dptl^4fV;S83G%SvxP9l@aj! zVyTQK+_#g8Ukz^=`8UqnTBpI?vVCjsk57ug!E zu*myPKpNkL03Q3P>qT#;ReMp^gfMZW@zU+#J!(w9c_v%l14SO2iH0X`znhX)E1Nzbc`?t+ zi(PdZGlY}O$*kn$qrPV4aIL^pTd2uXQ-R$6an*%dxa!R?u9X$LihVeF7-E&xuYV1q zXTtmBHPqM>8dm6!HGc)>6{bA1dDc6#pQby z=|h3NRo$mn5laKOKYa=h6`@k8qH<$JzMWp#;8u~+1FFQ+WsH4#7s*vxw*eqBeHG78 zMW(cB@GPut)=7sMIa0w)O18H&ip|H~LjRNm^{4koaXStz7q_iwf2Bvu0tlI`l(I4+ z{3`}t3kE7BY7-pyl;Q#BfME@sdu<@Sc#WCA4h`eQ>(h7&Yw7E(#p^HoisQfq41WLFCAz|&w++o_|+lC5yD#@oOYn$!O8wk`S!mF zVZs44!vhVL;{zXCQnP5vOU9XuDQVNXF-(!dPIvl~_4xXYHtDR#IPtOVI25vy5fWoc z8dzRt7mexdg4#G2uHa2M=?J&FX3FjLs}lh1jqui$2O7E$G+=~#s?RGc+u%4k!8ZLZ zAbIJ5@yg@3!|`H`2q9{#!X$4$HC31v(9C~J1Ybo!?< zivFvoEjuRxT6AE2>1!eU>i-DL6kySI{9U$KW7EFY5iZ>&rj}9nxK`t4*5%dCg=!w4 zy=dOu6WQ z|1Y)l8f&UmaCnsSe@zSdDC(}(jt7dBX}+&tN7m7B`Kkkrtm?P}<5Yr%4rf_qTd%LO z(qbL4RId2FzTe;eyYlV7%jyo>TeE1z%B1Vw?{l^Pb>{N=L9K)STD=C$v8m6@9BXe6 z$6C-`=F;%*V@bp~k{9Okw1@GZmO1=FyUnfP-?y}?`98;tYyW-EBnb>>a1n{lPrCzCxTOakPPs;{4jP@iJWTte=F#-d&< z^o_GBRF3)evy`ZXOFkWThUrTBta{557lu458}sXo`9g3|U0}mpm{Sp&UIost{#p2- z$mdd58cYs+k1}rYjG4_N+C}e~Zh|6;A0U18Jo{@x#RBl^KBjRvnW^!h$LYurcknz2~c?^Sz|5ceA|zG^?o)0H`=w=AQ*b*6pQ5i3|H z`2SODE&NlbgYTa@N#A9X$}4MX;g#K<+)eU+6O~@MpX6TT7a`p%jNui=kok`Ov85LN z5veCzo}Ztrh4YguzJ`>QRs6fVYT+LcQ~sDgO||f|Moa!|D#;E@o}Ub*q~$*@apC8{ z{yZy`ZJWP)tQP(bNnO5}zdKV4e~&DMAgLzLj#kvovjdhj{=sn>psmUb(~?x>A9^bK z(BF5^AmSi$+}{uJz^6D&V4B`P^ibMg{R6Mgc7zGLa0E=BDHHkGQJy_z;j?@Ay)R6# z%9JQ)WX-&3H0>YWRK+lEG`$V<_$be@s=8u%M?&MojzCv`&k|FDUz4+DV?A;wWx4-& zg0;F}@cAc_udK0Tf^%kA{KsPyJa4?~FP})msfC{c>z^JCRTloIwOTmW zTG>E9olB{M46i|hJ=bo%#$T~x`;~R#HEcm+c}vIA6-xWc1lj{zSb$&7;i(QMy=C2h z$wKOFW}ZxMF%A8)lcy()8v)|KWL;G4>y4orPzf~PgHUp6USHWkYX@nTUWW66B`>Fv4S_|VV&#u{x{P049I z8$J6xnhWhWtS*~Bzt^+YW?6@7;TK>(4DlBNK~osNqahp7`D0^8c^)L9VB^H`r?Zm3 z=%R^LKDS@2BE6*o_j4f8xyLIs#3peLm@{aW@jQ5$fj_>TbkE%rnnl9mG@6E-sLNL{>|S}+}~9~Qmp*!3a0%6ApW9@1~C4toxW( zH}+o)Q~jFVZpib%gI^F{le4{F#JpK~x#uZ&K8%}l zk-U6)e-X>I=H*_Z?#or!XpEiZGvj$pLRm_ z_T^;nT=|QEoSN4zP zB<&B@g(HA)U3U+`xi&tnx)SCDwWnhnedSMYr@qq90RGSBAuE7zimdhuUcYvFJA^P+@^4Q<3! zlD`?Tw{-$+Dlov{9_aUs+&dUI66Ll#vwEBuS=ek+g}tYy~v*7rks6Y$huG z%^Gisz^Bv_$EV^YaghSRHHAR zv1Dqgrv%`Col^_{l`ioT{nyhx*a1c+Wv}nDyxfrdW470iuQ8DS_&SoSEcv&4eQh!d z@Z)CQUPpTqvi2yZ?zWU!r}sI6WX`G6hdnFf>_4XBkDsVYyfH5)XFuL=#d4Y8Cok8+ zPcBq;`Hz|DPo55MGlg!>`~UDg+rmfRiHes8S^Zem&V;v_I;b++FH+{bHT^b|_Ecua zMaqENbU(#(NR=6hWh&CbPe7cX^n@upB{!aaoDr6jrihY zbS#w6AKGXPQ%AD?F1zpdy}wxsR}c-Nmv_|-Dlb$bv&{@Noh_(7!Gr%Omr!0jLEcMY z+#l)vOElbM8}kec%dp3f=2Do3rnzMM-bRbKJ*t45Sg9e~&1b*{RmmvikIqBbu5jXg z10|gN$>+z6 zK?T5KLF;HLP#HsPL1QRdsEi>N&=`sWl`-t*%>f_70g__^yMLqtdwmRhQ-R7DVhb8W z(L!Ymv4F-<6sU}$kvBwf!}5Q0EzhW->5oQ9?j8dYm1UC(B;cPHs0=4Irs1eDYoRin zSU|%m3RH$Ol{Y&pTj58|o|Pfc$vL%fa)%B2ops{-Rb3Kb+^Y zQHtjYd-203NS-ZToTZ~iUX;jd9d+1@Pj=YbI;kU#gc)ljRHr~b<5Ykdmj&_}pB&;1 z{2%$khJ4nNX^`apFb*ptYbT*}Cl4E0OLd@dsg9DdPDW8w=Z7avmrrlAsHPtt<}E+8-7m%Md% zZB0JJ3tloatDYo_j?F4_@=ab(b#wtae+W@Fv*!<+yjq4WKV(z<@b@b~v|(IV@#H=- zxfUK_knFfe7~~^+Z0L{dA-O-H;v@TO;ZKfLX8u1@jj(j_DYg0tTC>u!!XF?E(bDat zu~CUv9b^s%cgOT@(kE>34xS+SQn+M$nDbthVskM*YL`p>NEfYh3I%+A1Z;l&=M{kI?%Z3Kx5gX<-ZXo{<-AN2IUvkv%KF@ z-uw-9dNo8}Q{NQTd`2P4D1KhUpd`|Nc zea}jH*7%YAGqTL1R_@9@VP5k-o)1=~#&bi{rprzhR=ij zpN9&vnLht!Ej%>davvH`ve2X-YOIC*fSxk@_wZm>LW%{>`}gsj_ZR0$7H5w3Utn)e zuosU^AZdrNK3P8kkQQeD`AIw%YyVRMw)eGzPtiL#$y0sVT zmd#3yN5Et6HpkY_&!aEcHjK|&-)Tu}?`2QY!oz?g+e{C&*TNU(7#aNno9GLpo;*zQ zq!aNkXb`(C+nPG(Nj1grGc0|Gt@_X#W^tRdN;7S=J-~0G|D*NpNiw%~edkFHrzbiDX;g6~u^JJXHnyla{Ms%jKRrXJ#!o@)V z6U{(i1^>H|@nIUtq@?{b=nee2J&yDxPimwT%mk+WEtHrev*oxi{&SiDh!OM0PxwDG zEO?mtKRk78;g~;u!joCy{g2WLx_>5$eV(k(KV2E{w-lDnTUz-Ac4zF( zIyz`ewB#U-OtF>y*c6i1k(S6h8t@kbsUv%#j;^y8x3K!&kzS;ZGFrC;6#CdygVV=A zfR7=$vLx2DfUjn$$EdUY@v+rp^EN}yl$8atubfs3E0-IrRxT&Wx&xAxhk1@BkgQ}K zRz6>u`AXJAWqXRU8qmt8yfjeMWWb9+q(uY83jn=HOQk)>wXpc4y;yvbkzT*{f-BQnieLr)pq;s@)3YSh`!^tc4ZGljN>I zo?HPjAa@1CU4qs-3MTqrG4Qmm1h3@x?~ZSqoGDVi_Cz({*{z)6-R^ zmRUWGr)N#IOwVB(Le^G^M7Kh1v{DS%x}0oD>#50;0uAuUFk{6iSGY_)14%#cNb+oHD^6Gi3tFs9Gq+1HxXU8tANQSHDEp z`je^&ol~_8TCumr2Thrb9X5{Iuh{2hGUI!OcWbY+0Y65|jFR1xI>`3R)x6bo(zuQo zvzgLNVJ46P?4vBwywx`Ed4OOcTZmB9g>0dPb3>ihp32gwm7QbK{K7e@Y)(Jt&!~lV zh)1?3Qk{$%sKt-sd3Yf6yv3TA{_%mv)w#7~0b8}5sA$h8ea3qDZRJFbVv(HwEZAQQ z3%(h~-52z?7TO-GtmlG9E$h;i2O4k7J8$1ZYfl)oQ==KQ8h2$88xSx!Bwe){vQ_ar+6+$}BHevSe5K zj=u6R$@8=_3h=HxPyFZ@+`f{9zw(@c^vZKqT82O?+fu<0wRIJkpJDNpZ`Q(FnnOey z(!&&)7B2nxfksr*66SAdII;Q`)onK5S-pHlM7x9<3HEo^9L=B%8JW*bU7mcz|jq zuf+DpJ(z9JW&qU;ImsZMvNCNWWvwsA-F$?K>UL~a-quksm9;hLSS$LS;)=7zA^2u_R)T@aHrD_>DUbc_kjv2pN285TrX-CJFy=m2i{Hn8jjTKl9;M8m8 zV_4qITTXeZpq_gw`*AtsZTWw&w_Rsyq3fsBw`8GLiFYk$A(s>DxkJPK4JA)lb{E;| zFe9>EQ+WHhSzfvx_kxi4TY;Ght|?cvtChDO^(MPMN_sWBReyLm6~bV@OI$v_EziS?d;9BudeUH3OF3z-jWLBU08t`9Q{eqXY1VD&-19Ydh?@* zkx$pRnhF4$vOwOda&LY)2=8xxnde+|joy5Y9~a0^z47xgdT6ZZ6(42Kesq5o$zoo? zs^+B@7;p96|MQ=o&feWb^Edgi(%-blpncOGl8=oUmI{2q z(B!5sqyqV{-o_l?_Pn+5w&&4KAPtQ0>Mow!E%$1)>Z`}#hE-!5GTpbGq5zDikJ;hS~3Y82|hP0AQ86f{v4CnHs?AnE8;EENA^THP{%;k$yF> zyqe<;I`ww-1fI!Sd;R4hfK8t0tEccx4a9ZpFVD0vGLegY`8>NuI1g)g(Y zlm&7N=H41U`6d(f9&C|&zC!69U=$AkT9zTb%>e&EGj9<;GoU_j9a-%a+2w&FRAy)7 zryCyFZ+VULK9=LIavwk-e|Tz!6h&q(a$DvhN;a`x4;->;IY472d|VBi)+NvZ*#}PZ zyzI_T?bHWe=6NGreov75bB<2pJn#lX3n^=M9&a0K3mUQFgon9=$Vp7B7jrJlW^l!v zTDW4r;pY|1@Cqm)s=^h|^Pu0}D>J|qr+Cg(RI4lc$=dBjcU#f-KlpEqHqUE*P}=fu z-pR#&55Ch<7zrMHm!%Zrau+b+nV7G>v#kH+DU_TRE_)y#kLd=nFN5P>ZcMLv3=0DhvboZ z_*hv02$SjqfPH(79Q5raX=;Xeav!)&%^ZeS_Aa!)%bqR^R5(W;JE!li%F22}2g9U^ zcZDyd>k`VDT)|kcXbD&BVRP_P<;femQy0TCi;LzIQWjE$!b6#!jLJif}bv)Ks&Z}FQNh?TK?wydb z2FfmP1o>`6*k^b*PUV?r%>BlBBzt^zO7R@^7e`4R599W!+HpDnSu=aEwT6n$1a7>R zr^6Qg#txF!nikSpd)!|<&QG-lj8bbEg-oq6MQg3o=-!Q;YC~g__+_m<;V+(0E5(aA zx@;*@d%!fc2Xijl+nCxL2;$l|3bd2dULMDMBf!29fozCBz(oMaAbjH}*>^dkJFVvK z@*=lp5N8YAxDP|(klt&Quq*q~%9f$M@ptB8?u`d2^(ZjX>O86%oF2(q(`&LaR&Av? zgnDNx#aiuTTssfhGVeS@@-GZ=cK!v)mo>vYBF@S_YKyp&4tFAH0F9kzQrR2}t?WT> zjFId-ZR@)8bSj%8ie1d{DG ztX=J?Y-Ly~i-@eonEfuWx<`L_tlfNAyC#$Sp~|o(PQ#4cDzc%!Jk)2sCwB1c^yE&G zcZKo$q%cpsi|0hO1(0+i{IWm3t*+3-_;!8yHsiJLeXJJV%LZXfzLyR1-cvTw_nsno zrXDC(_Gtskd!MEN3YV%qm&)cqv9b&VpuG3Em(2|7mUWV@64unhyPJ5RSG4$U=+(QA z*7qI@T)Oc<}mxBrSQO2hK($2N1`_|!DAFVaoS zublCZd6nuw=qZ++ex6!vEoFETo?-=QypknA*V!EnFc{y!#-}j8@w)NhL-|b?0@qV7 zg^B^n^8VHcVM{R;eF-G;jg`13r|e3`TX_aTKH@B zNQw8n;Vrn!Qh$ee{59J@yTaqUqqXqeKMRrWlq>c$Ykz9 zP&L)Yyo;J@tM7jEe?OhI^hP*f%9;zD_rks2ov^d1(bFrqY^L-MjJ?@4mr?{RZTinQQdl zJyDt5H|Fqm9!S5Qfqi2h&jDlisc0sUeWTsqZYdkej*EW-7=GiJb@L6n`6hd!N4@dX zEcwiuT6kuFWEvgipWulx|KB)C`d8k!DnWqy`E%at8}h&`R zEqQ`5ooJ~H&u(bk+XZBIzKN#@R+e{jN=AgYD_wal4mtFt@#+(za zweaj}lI6T&hlZ+gXr5LJpd}>z8PM{X3y#gPugb3aCQ#Ox0nIU>cx;mS$<>(p$~@vH zCizI1+zCMZy>^@2_xSm}QA<8Ml{#}O^ZXv2e~%bByHEamPxIqBqZ!|Oj-pdz{(x1lsovZ1oY_%=;E3A(M)2zmM|wC&pf@Y_GHs0ZIZPu2z7c26>gCr?>VPo5%q zhLPyvhv)ivhAZ7XIf?g(a?&22Y~hg%uRpbLJbe`;^-sRFu*bd@Qcmp2Ca=dDJbBvc zNqkAQ$bD{@XHP|cdXj89kR?90nd7TQt+!d-3^Z}f_4gIoR8O0bq+vYCjh_&eza$y^ zA5)=5sW)Nc*;Hay#@wEaS()YFIP{3&iDv!f=?phwe%|2m2|kmo!RNH3=yAGN>ABUK zKg*L}oAlgHGVcoG?ok1@DWDsFPhQ~o3>w8?kTrT-3&swIkUR&5o`frAv1P~S@^(1F zqnz#Yhic)4$p+>Zj*@(-f*Q|1N)~iH^AkLOq!xZq`>hqu)x!5Xm>Br*{SKa;wne|s zbiRMs2DNFI$vo*@0SWykT+b~b!4{`<(aqto@5 z=TXDmq7$-XC%?BhyiMOMy5d*AdB+qbuAdPa-f^{h-p51F;Pwwv&#I@MnJC#s&(pJ> z!HMq^&@|etzv>+URTHscFjw3`HjJmejJ1Irsq!zJG)Sv_*5C!|a-xs;$$k;U?@#49 z94;H395bvnqPkLnAAmTFJ1gL$FAE%{z=^DYjp10Hag2c+FPnVfxD6~dSvNRlD;g1J zE7bo(vD-A^p*Z1vPSiv_6KM4+f>tdUXjxRU&%bO~`TfHhM-`3r_Bmi51X7+ClurNgoA;L2q`zK0vtkslg=Fz{=HV+|v$FOY z#L8rW;&rAe$GqR$9)3Oh*YEqZ{rjHL=7Zz(^F2&Gw)6H%fo)zc$C>Au7+V%VKL3(K zAhQUPu<3{-1E%m`Rl4mcFY?;A;0=FW{UAV_13KZ z8tU(bWK_y}=9sdbl%fW}sVRnG*@;9-E zPcYSF;slb@LY-&g^3xOovs4yTxV$!|fO6S!nRWRqkJZ9gj#-_r0Pe4xwf*>&v$gQm z;MJAlK{D;pAD(^n?OG#fTqsRnLE};*pkvvH{94ussLPA5vJT!zZh!yE^WJF@~)4MJZ6Q@lV9!Y|Dr7XbqV_|hNonA0=&U0Hz^ zZ=od>$Xobx+WqrZYvIpZNdgYw_vd?f;;Jk4{}T5;V0l(&g7Z3W-MQ&1{EtR)o9Q}#Y)RdLK0N8%q2!tY-yw|8oFg>GHYfwvt?Vh zlbz=Ku3WphzKNFE$?VV$`}OHIcCy#xTfg6ZpL5>lyf3kJc6P51z4M%N|3CM+&!6Y- zizGc6xUOPMp(Ma-_#k5Rvxvb+mS&l#hti|F1FtEF%WG{=do|Zy8%5k?O?Iz!K<(D< z73ypIY>~WwO&%7AJHb;sp^(c$4esiW9E{9}i~~7D=9P{5xXLT!_bX`|bSXvV)vBzA zUq+7pPl>&Z-aW+{$UVgz$bM|)*i<= zj5u{>(Nxh`x2axBm+N*+ZB;1CXa%;8EN1a$S$19}(O)giWr;iQ4iN6W|M1TlNP=DO#vfa`|?6oT8u_mUXq0p3$HM#>s6sw2B>fYfINPM8vw72c>D+z zq9S-gJIaMkSA_c&AJpflwO&Xy3w)?w}^ zsDv~TrCJNL(qZCSko>QVftt|nd}Ts4$RKv&;jkSo1I=xvqECyVYJh8>MYl+$1~^QI z#)d}6Eh@;H(Sx9Vnq_;G6dc`_)AG>`4mpvzYz{(@8|{h2Xe;GTJqH|R$c}b#<|Mbe zM#)Ig)+ZBz{R455PAtkwU>R3?N?q{xlu}u#ow8>o#R`unGxyl1FZNtT(Rbn=I&sf^ zmj6B?#{i-eV|z}y>jkf!?s3{Z!KoJl>QR%^Q+pV@Vn67qJyoDsUufnYB92VhJv!R> z`P#?yr_rvvBJ}ByOK3rW?^9E+9(Il8$QU;J`$OBc65-^#S zS}HcB+0i})m6eO7?XDhS7BSh|c(Gs?peA^H`}6KCb;siBL2I`mPW*$U*ffWSOx)sV zDS)FisvSq$M{P5Jg_ikob)o#Mk;%I~a>%$?&J zhC9b2vxz()44cS)@lvA)x z#MD~r48(#fD=NmN#$CZ_#+}2~@t{jpC2JN*?`;Rus8UlVzvrv55vc@?k^nHu=v$TV zu*J<(X?>7(s*2IY^(1d7*oSTs0Up2N0o3ovLy?=v;!X52gMZTiFqGW^^R(lnx)pe0 zk>T#)P6qd#)284lQ?nAKcTNKb%u=a7ZBp_W_?-uU!=}ih!e`H&toZBX@}H1rxK)C| z%5}y&XH{76fg56z^(lUS<6J-iiT6un|Wqrj~ z{WRsBPW*{yG8ikK;fbX;F}rMfQ?qpwx6(E(dTcD0VJdehw;ha3TcjG=BD}0VEdv`_ zGP~^`U?8(u*6*zJyx~|^Wjx8Ut1@=6Z9xs>?W&SvWWH3E6+bmvo|R2)C*d+#N%5r= zC=zU=8~{1nh)sN{8dRI6-u*c{SqC3CT*Rlf}Gb)OJCxq_)DjByr`n=@$%9Hy3;xldNaYTNTG@z znao5FoHCh70octO<65!)WlwW2&BKw8ha80dQkJtLI6K1U6T%BxBSqjC*g?QXNEOy3u1J2^}iyjRI&Py{iWiI;(fHuO_Hf=L+n&LaUMzp;{@nCKe z?wyUyn?=g|CJs-qIFW=CG;w0s@=A#_Z#p&D0H~PJ+n!M# z5^AD0D-ZWpsitre+go8#L2jsCo{PKp8_5Uc7Q@~_fQ_ZC$3c628&^x{f5QIy@yLvA zAj9MUwE8HF;rkopS)g9UPS|Vrub+Tf<`$6wSd1vXLAQ%g5CdhTF^om8GDz?-JRCca z6>Et4!b6x6utn+rdFlg~qZ0dZ*CtfTzb@^;$E@ys1=JJKetf`_s zasX;rD&!P)O$|W449dqv){rl2nzI`1Rp70vAPw<$jX-;@i)%{3mg%5eQ%12e=UIcx zL0(>C-NEeTovQ2dPKvXlE4&n_ype`F@H#lB18TUVhNB27}}BW>6>+gQ93R#kdcb_Hw0qLR+$Qg5r@}_myE% z-CsHh!>l%S>8$4s-Mk2bVE+E|c{_4xTqlS)>fhyUqFw zi_MY`M&w8Rl+~DGP6spCxH0Fn^3wG-wSUewietIOKowq=K zR^)0>hLft{ypu4LXba9S@w|(aeW1O0-Ul#{P^`u0mjSEQ$@5oxvGA0zbegYT*(jD0 z#q$>VpbR)k6iadPJnO@G_+WWMAC&jk>O<+TVX!`&hYyxFG<=RBBo#J%%#Y`|=`4t^ zFjU#_Re6TcnrgUKt(|i%3@sX+b6PxaXsr$nb=(b?o0)awXkDw3FTbw zVmj~AXug5mx0qa+#=n&U+-6ToKx7G|`?#^`CMBRKYlePf5Pfp}k;4&y459eVR-oM$ ziJVwrM189l7*g!F(EBYC7GAG382;ZR5x)5awi!Rg;5QFj1tEP>QF$+1AxD5okJI&U zbpi)%(fS=e1@TRUzByxknh`m(@`WqyC%1V;&KLbf?YJvcF5(&EwaAOx7-PVwu`yd@ zXoy|GI=jJ4r;Oc}+6~8~4XiW)83N^F5v-waR1!*_xCnns#^J*AEk(IxeS_>kB;4Y> zaRQG^-0Ro1`a`zgECE&KQJ2cu`L||)!yW}!+;peFy@$ONW+xxKtL?-yJhAla^{nT1 z$$gzA_w~&>d|uy7ahuJkfVV{%mUQd2&e(+nYj1+Zn#r33FejPB0pMD=tZ7n;5@oeY zD66H|)O56Spy

DN3wleL>aA31GjMSh+t+T(nUM7eQRDZ_)+pW@1Gb_Q)cU zoc&$AqcJbdC>KvMO-`(E)Za&wqsCd2C@)4pGA$NR)Jl{0SbS1%*;ca5R>n8P6XoT| zrpWYIc2)21@KqT)v+S+nCEr!Y3_sP8^%ecZszG#_ML%+ySTzFwvwMjjWl@pRKb|NG7K@$L%PW{y;EZ zRuY1OORi{eRC4}f!CI0iKLp{gtleW2S)-*pn}H3S^!yKz!8K7ESXxyCsziQ%Uay={ zrd}pLdrW=38Y%;m@*J^`tBBAlZb4-^;gF%@DfH<<)K56N zH0U&~@YK@>!%^+8dwB8epV3HMNU~q}6c;<?_JL@YW>gqn3JnF_pd8TmMO> z84i|_t>RmbF#WjxGHu9!42xFYhlL5hy?A01WyZt(TM zy5$SrAwy2u;y*;4xj`;6;6wgAhYR@?7w9L{VT%@Wp80-T=nFhCks|^sh_vU5$D>iy z@vO0BaY6WwpU&9v#l}G88UvMUY}#Fke0v&~xtPn@``hmThdlle736~350ky5;pF1< zJxV_De4wW9G082i&19voq+q2c=)NMlUUD@K&?F8_9$%z&AKkF;6PmaCK4FD2SKp~J zj`uZX>Dku-YFt((vk#SGB?yD3w#L*@os(sNdD*~2l^xFR9EV$EVmRv(vFFNFW-sw# ztP9wp!QZ!qA~!(v0hfJgDyRyAzi&UNgKU4~0Q}fW@jT$ZS$7#|-z*iH9j~)yUnwZw z+mOE5R|aq&G^=lxmUBsm+s<_VQtl@&-KgEPlprqMromsjjiO9$agQyn0##$FH56-e zu9GdT1IPPT(``Fbh-FD*BP ziV0?9Rl=z1M9G5c%O4Pa)mUl@2hb>2j+}gv*3lR@qG(>lq~XpDd2uoJVAmoKzy$KC z7T%}7M+29-hhm4ZXG+#Nby!x9|CG;u{RjP_&i#Qryk|~-Y1f-3`@+iQdk2gT3C=F^r+gUU~ zam;Xu*mhUZ81-rCE<%&_`@3F9`q&BiK8}UxA5O@3qZc|&Hxh^<0wLW#He#Oarq1V-)Lc*T!m<7Y3Ra zGlW;fwiZQZD?k z>><`2&*i&OaHB;D6 zDYm+u;;=2wP$UvCRG&gA9Z7K=ja;{xVx0GD@oQ~`)z2Kiw%!(-DYlpd-;-I}0wB{R z2cX;JrD@~ZZh%*}($B~dz^nea6hn8kd;CRriY7Exu(z;ffHKgybuN|T|#?mV5 z%GxpPwJXat?G(A@p?6-cnLry!5iGf?qTcR+*VZH2rSp%*pw|`$z@F5iwvTu-*rji1 zo))Ebzto~OE@g|-O-F1|x@jZDpb@r1@{8m%lN#g!uFHh)Y^Y;An;=_rA7lAAf{(G5 ztrL1r^&0Vl7z^IHp|U>6f_FhyypMADv4^!s#g=Z=H+>^1`ha;;_yzalc-PER=at0w zm*|fRToX|}8IVs>|G+CgZyNYd0IjQ`Ugyol!Kofaj+N^f)2kbe zYPz%f0N)9eI*X9hfEmvbNRp%A!+qX08*pkWYhWmfqzX2i)o@jBH2GhbyOh-%0n&%L zcU>*8L3?o>Ec7Cqo3H6+WgT23lZeC)DF5l2B>GV)GNO_s46J8ML9PSpH836059^u$ zOxqXdVr%L(T6s3ysnG6MaV*>wa2~-v-?8a6&)AS2rGCN`Y2AkO1ejBvBal1}o(o^W z2wXB8nI-n&i6wu-D$aCGyNYnSs8LsnqDG3%CTDq2v12+3Ejebzn6*_*dBc@Ld0A^Z zu{5gI?2b|GDR;PbE@9SK^1PZ}@;pWN@J-wZWk_4oY0Il3%Dajim6v`&{;B4l`r9fl zDemPntyeLN^E`j7q-r`cRVUO+6~VfinSz@|SEK0aLEBa-0r>rYEE3CP{nZARZKjal zg5mS`84*_x`Q>yj-Q<3>iS#Gik!*BAn$A6Pgu~=jGn_`ORs@QMN^qAGlA>04N3vWi!`rg^tTi6&FI&_PzmuUb zq900C!;(^piw1b%NMs5RC_^F1TNvefSXd3V$ucxi?A5DHg}oF9>?2i$w7w9>gNscn z#3V<46t*jsc_r+#(kkw;x0u5F^`W4+GZbHswE)Ekfi;}W&R&Sj*^)^C*9N%QR*(dx z1hSN+f}od90Q)RQ*5KPa*EW==UG#!lrgZ&lBSTe5S_rvm`%%y9A{Y(l@e`! zSqVkipoc5<3i=%z5-DdvI(dcFFa6@Q=PY7nl~C*i!A(?CmU~OoC<8ez8p!do4JNtM ztQK!c56d1#v#eQp!b#+URAergRnIPD;#s+oV%$|LJ3(#BMs*{JiZU((r-wl?0S1f8s!2XhxuD8dk+iFrtmu|iWa>r9#f)es{M>Rj zt7aG{pQ5K$%_wV52RIfz84!+Da(6R!R~M<))kPFj+7|8%o7I(cwT$Z3l|YSECMBTFa|%q>l2{*HUfz#ibO}+65PryBB9RyB7~q z8-oychZm#WD%Ptly|~wlNeH}HFqTzprA`JHGuK!Xav4>5Sx7r6vN&RmK!=0z;u5g< z=?!kfVC;^k(t+v@)WF$Gx*~JQkhbxXA$~ZdR-L`HmSU&a36oiQN7T+GBZ$qTNe-Sj z?7~ZC!Ls-KvK)ZsoS%oev>D`vte=Mw1kj$#*$%QZi!*MVn7PD#Y2=bal-XeFH-;}c zOy!8?`6Wjv&M7_+TtI7+Z0qGwmW*jvkNGYovG6lz6s^IhHS{YnT|>XFar;my0S7cL zYYtFcblq_cGsYUG#$eDXBd!L$vWB^6&8#W3zx5J(v*tK>=034|irYVqqefbijg+4SlEYNtW%_|82zncY9h?R$|5Kw8t+Qd zv6A5}Vnh#Xv}238m?%4w{8CV-e7$E7WZbyQY8c2r8dpjFRch43W+;Q*R#Y~@aGT}5 z&GUx7|C4x!(C|I0?0Xa^ZTzGJNYBUtSTwyW!;C3dx5ZS1EfKky?1%L#XMUHiIez!% zQuX4BODR@(FRq}UuAtc)=nfn>10B41)VI8lSi@RGI4pwg~vHAJQ>H8$2l%M z8OOuKx*`eXquPvaC{m z9``M_>&X1;+dO@-UVn{V^>U@%{_Zd~&?|Deze8Np3GGPSyqY7z%S#~gd4K-7;4-=B z=%sUi3R|Un?ahuF0#kF$$VB1T!`*?ltJEytVwx|K2frdwdtE6|4)U20$<$1Xb2w)~ z9?eA_rA^u5K|oHan#{vY*NF!5#6H{<^If+Y{A`Zq>+ykTg+2rlB<*$o#%mH60N&~H zk4;@)NxjAtKW%>&YcfSFRrbbjv1V z`uY)-3~z{CzYR2V9HaModg6Na$2<|{8H4L`*N=ieku{L7p9J+oEBiyMIT-oZ&p|y2 zH4ee`)1VG5^4wxWuWIWfQ_BfF`=eSixpqWf(5l7#T0JG;!FNiLxsmDh3vvM3bM>l{ zhjo^#eHeb4Mnr0dyb_6sD!~wh8!=>+gzK1B(h099VY1yQ2N4y6GWV+z=5Yu&3aBUH z!tRx@VyF`Oh9K9{H&)4gUP+4*Zfx;N?hAHWwPakaJmf4=Fwk_yjB9#<437CY(zSH! zX`+_Hus9+)42xTv!?3s|F~f}&zst)T+u>lYr<-p~1IP6i%ZCiMbnc*d%!^4^da>X$7dP&Qi7Qvc z{l=dHSd+M0Yl8JMLGFL7CNduz;XJGzogbT~1r@GRM^I>v{8o72*+CQ@&TgYah5kEK z=$l2!&7{_EBo`@^<$<|(5kA}t+~~A^G3NT%7*6w;=oWna*n~77>t?o+L3IQY!Zpd~ zUp>l1rnw$?Mmx9p8H#p}ZzkN$^S*PN=Oc5gA)sC^BbK>;rn20Wwm%#r!YZ=p7Y@|i zX6@Z(MoRNh9gp5Xu=%+a-)^l|zizFj*kqlFJy3>}rq``07;a$IK1+_CIh-GUe>O6| zKd;(;AJ3RDb52Na$K37Z%5Zx*#muFy+sTpJYb~LcVmGDlr(?2B`e`69`Vu`iPBcMPI4 zn@S?e7`%fP3Kea43VbkE<)zg_!z_^HAQ)!I=(vC8C(W##=qUA*T5&k%Oz zJ;$<@F^dF#eR()CU*_Tq4frw_U%ou4f%)>u$UIt-6^ci({wTRd^Bz46oYdkL`hLp> zTO_VqvIpd&WiX}|J*oX@73g~2kIk3wU_6SgEycFx0|T~JdDNU`2)%Y1bcZpWQDLjG zjx7^tp0dtOQDmL{N=*H7u{Kx7w6quBDaZ8tN+WY0DYKCS(hoOhh2y?z&@`OSCkplc z<5{0vyRY8LvXw}@;*owX?Kh>P|)481o;3mAmt2mvKdZ2>0CuB@KP^JU(fij9IHUX6c z?17XWE5ZEqK($2$(hs2U0Ur01#}Xen5t#>z^@QueO3N9TexSpmg8qMCGeSg}ldA`r z03NKQ7zglyUMmocqz6u^1^;tQDR~R%!6U$&?*pT_E`0w=aB<}!+m^!I>kJR}hJRYQola~3wQ-k^7p-#|!>g+>( z6eqHV=R<#li2`GJTT-zv50mXk?1sVuMbE+a>TL* zqf!-(XB0g=lBMXrZp@792bjJr14V2-{F1N7-fm8zc-UVa4Die_g146~1AKjCHgl54 zOxh-TH_t0y!TZa3@;G2?1zqK@MoQVSEzM$kWD@kWowOdArhL#Y29MBPw4D!2$PwVZ zxN8ITkDOq8W2eeTY1pHONrl+>Bga6MEZRvZ=S&voqqzB~j0_`30CLb9k9LCM#5l;B zM`u9IB0<|9odxXs2(j@kAiFzsm)hMCnaAq1haRh=*lcu{DkWYiDataXVqLmn?Ivlu zS#HRI?jc}I7oqMknA3j9COcpJvm0@m}L>Q#aeu-n4&xhD36CdRSJ*|Xi;-aDN<|)Iz0>ReQLQ8lp+MKmN5!6$Ia&~+q7{)yY#uYM~`#4OZ#L`^*xphI&rl*MXiv1V?0vUyQpc z#My+vZ)@);Vm}kV^(}}%_Oyu;(B~06k)16xwa4%pS1PdAL+(CZob8vx$%iW*N-yRm zGs1568tOw%!n8nW4{Puv)f3xn5F2498A`l)G;3m+QpserHA zJclePn;n#+uqF z!S~CoO<2zeD7|hFgv#NvTpovyD-_|F>2bKMW=z4y$x;@d!(}z?0DNrzviKY>%dWT_ znXIb=JrTH5Ibm_QEE}iDmLijvl~oQGhHuAUWOnS+nR>^*$P7&D>^?9}@qlsr%mI8G zV66^TaxccUTNPuc%JMzX;l*U%pkfCt;h<{BxxTAPSoS(mLO8`X9T(e{U4*wCOlv#D zIWD&IhU>rvfHhQ#&dGb@z8pw{w#({(=;ujnu9et7Op2OPWCPS8iwZXC1J$6IgoCzw zRInX+wTfTqXw@jb+DdUyTk}~GRp+^u9M+tbXx~vj<}t7Rzi&P=Q?=SdQ?(Si6fX~~ zN+~kmXL}T!5{TGTzV`T3KE;$~$5hITNso)z)Qly}sD_+TwC^|!|6CVMo?9`hD`^`*cq*YNm=2F3)PKM+F0U>JWlm*<22F8m?fc=>>zc zA&&~isYeCg{}uiDS5w+ge>D}EV`LrYEyo5U^X@6%Pwz5IzK8D+-YbvHU#Bb~PJm;? z>ey=DUk|oH@0G#bX$tCZt&n$t-edT^H)eH=QG7FN=6R0}{+XdmW1a5}gW8|9-FS}) z?Y&d`*GK1ocWotEPfpOr6o>KKQ-kMJ-^KL1$GA|MCr8WK;W$ezdXBCVH-bk#RO*x|?00V! zIK{3Wd*&M+xZ_a8eWs{Fp6ct^e@Q0q5R{uOOnuVFDS+#JMX3S%k;+=?b(T~|v5ALj z?h?@^pv5F#Y}FbS{VU<$GE=zA44TV?s|=_L8lg8V33QJ?U^Uxlq{nM;e zr!#)8@O~y1Vmf8-r_$BW12H}SK*mp{dq3@Cpz5qp4wd)q@bW=B zl%8ovF@A5e+f|8eK4%g#;KaXVk1eY&6RwP1;t`zDpa~tcKl1>P=y7eoS8l{f+Y={D z;a9$qwDlA8A!$IJpLn;n^4nEj>6A@AIpBQ{Vxjchwg+uhI^Nhn@yq7Y=hP4JYuFU> zNe5dW&g7ETC71H-jUlaTAGO8&`EB?$sW*<4?)@THY+d>!is{}jPxo$_Qc9x?e%uk4 z*y*vy?(^HJ9#CFqSr{}J%y$%>JuRZFkj-CaQo*8FWe3lLHLioS zD1CEM^>a`MU~t(f46gIFXmd`A-jo!bDTCl5QM|3}{%^p@PX&}>x z@VZ`?*$wYZ-iXd-d9+G;1FY{2lxc5FSnLGVIaTKUMp<$kungKUk@6PQ;CH9;7R=bz zpse7O?ITPS7TeZ<^?y2`i-T{a5}Tx0lpQg2#g$`IP{VF+Tf@jNU2$ z@4+X#fo*)3EF*cmFZj+=pl zCh;&z#sGprt27w1TFkIcqjsas$Bh*E&}YA?m$_5B`Iu7ZZBww2p@gzxgn)3+32cb6 z6U@`HmDF-Z44fg^MT}%m@Yoyg>uEs(D|n|O`Qj}?aOPFODM{49PZkqe4kBYiE}d{#oz9G%aFFL06LJ!Q*}(sK zRG>rhT+)NRxF5ZlZMho-3-l^2%3Dy*B|H3w&>eqPSVdi4r#6R!$?GxsX^9>MlgDtC zW}W~}+2Scp`<&?HO~T8FrO_Nr-Z2+e3Wi;fhSloG6%^y`8YvF)0WH;$rZ{OQ4Qo%Z z{x5ITQpMPe4FzrWK2r35+Oi>?Jo4B$_Ll1o;IrOkBCtj3G&OVBntIsH6q@ZL9tRfLCHUi z19QrdPxF&xlT77xK$Et{nHH@7OOkd%B`C=@fbl@e6gaPf>`{#sswPe-(f80iKoZ@~LT?)G35D2FuSFjcaLdwY$2U9@y!OOuE&~jN4dw{eC!O!e4_`iZ~ zOBI<>fUNJxmi5iy?0K<^t=>F%n5_vTT?dq ztudXlVSdWcDVqYG3CQe?=c%8J>Arz_4EBR&I^&1#J!Kuv8;JLJl)WEHS3fqy^!yEE z8STpKeQ8$`zcc$o{C0lYy|44r)A8B+nYH)TDVzBCH;EDq*}SAF3|EOSH~b zmDmVW#Qd4|7UR#D-e~$GOo^{*k7ow89`X^3jNcL$bI24jo9I4R<5Hw_eyA1OMb^G= z2fmoRs(@ZaJ&dFDUwKTYtp0j=d^f~W?5lq9GmN9}Ur*2S`=~xs!q!>)(j>?OHrpB} z${Hu?N>@L7V!Eya_?d~T_*oXyDXX7eUi};i=p)c4w66Nq@7b81oTVKnV!F0tE~XdE z(I3`dmCv+`co_C4oq8|{Ml3_x^@0>#2MB|-iFgXug;lWXsTIplYZ3@n{41EZ^TWKR zf?zX$Vs%>Q36}t}S8`)QW)Dq&rWcC&byg_@Q5${APA@jUb*6FpVaWW6ewMxtl(qw1 zIy{$kAA( zyMd$hP>vIGX-n2gcs`SXw2zBjKE9djUf4#0sYZH?gGtb2n!!O5PxtSM!`P+DMli1n z7*J*o5@cb{udoJSkO1Plo}Edk=*wXLC|R9gsK`RN-!f9n{2fpiWbRc@%I!weab_*@ zW)4OCFAJqrWVb&VRk#d~HVRh5QncOdF#5#LN$Z206^kfMmm*Ea?~-oLGnA7buMEGs zf=ro}3zlotnnbBu;UFywwmZIo0ly1b!4`WmlW4Z~ zn<=)rZHlMojnYL72V9UHsq|K``%ly((ykd9%m#TUEMwrdG7jqaP&FjFXpEFGXt6iz zH+uA=OGoK&|L3Ww@YKMm{0Y)&!On0C6d8-0J9Cf>F4*SI0_W*0yg(}lNit9IMnp}r z&gKtC5ni&*ht~~)tb|g#({>UkN%Q$opnj5!f=O1#6LzFeZ)EJsr0@USUS2|+Bv+Dr zG^trRAP#{ zjRZ=PJy`-UUYRDnC`JFL)K(QuwyL?HH$6Xk{a-;1YM2KD6%LgZOU2cz+Jbr{xLKi> z9x`f}aSBE)oeV9Q%B72$S`CQqbMa8l8St>6N7FTk!vMu1l-;!P+4GaK7 zz<5kQ=Tv0QEdsE2Zh4H?Z!%)H6uYJM0X~BR-xA=_T}oU^iA(8JjMtA4PV(8oY2ZMN zKfjV+Yed)i#OwT#06#??-t&pu`3Hd+U=}z8%mKvk{CNjK99Jy(&ja$AzGSSgjF^68R!Ox*M+^n05Av)10%o~Fb>d`3-R$n{JZb~fPWX_--U;P zBfv3W4#39?@#(@7z)3!vXMiM743q$6KsitWR07pN4NwQv1I<7X-<7@8)4%{Q6t`pL z5cLsY6bSmY{3xHN!muiaf`spd!a4BuLvsk5imzGG_BFI;O>->2W{UbWZ~!>=A^5{FzOsfdETN~8*y#76&{rAsbLB?r z?LY^>jAs8RcLTjZ8W;@lGt`Mq4mb|X^YwM&vKF7$)&jl2007@wc&Opvh0Ak4p(ldTm*HLeGpAQe@^h-poe5t1mfUeLP%h@mA@YNb@U%NT; z1)GfC8royO%EA#n^3{~=d_18Fs0L`?jrBki&>Zu947rbu0%Q7}0!QFW49L{g0JQ*eb;#8P zaxo74hFD)+7j@cFM?ch!1^9)?d>kJ>-U)Qa_)pA4<`ek(i6g*K;21Cm90%qB0Ab%6`Hz9vh8Bh+S zfC`{8GL0j^SY(ijYf*)Rt|0F)%OgnDI_nWJLdH@?Y zw*x_*-b|cso&?Z+^Fe?(-FzZ$*UiM}7W}#85U{{kA`FlMYJj?!uNivt5nvuT8RKv5 zh|H&u`BV}hwx7bMPZ3*%c8=YVxea}{;pc6{__k`GHkQ9_jQTh*0pRCt)4=}7wA2I0 zw+sN#T24gf)8Ibc44nE1@~4vv`qSI}G`2n+;6F1Ona|+UXR!GheEAIY&k*b1!P45*Y0rkSnEqMf^;z2bS#*Dncz&)7 zNCA~V4NwQP1pN3W{FWZzy^a=Wvyu6HJwO{i-w6cc@N=~9a|ZzY{oKJ=-rN3sH(&E8 ziSf5%@Af0WaUh7>7x1^$07U>XX)OiX0Bp9R`-@dT(C>GSM&`~j06ljG`E>6geuM}8 z_a2k?czb`J2jPN$#XzZVUHJ}1}l|XfX_qZuy-wBW} zAKpK)oPJw?{P@WHweXsM8h>Y#=a22)ho1ZD0Q%s*4bYGC!YaA?Kl|AABRCIRy2!D?V5&=L}!hH191Rzj#dv+A6`$POyBU6cC$)_6 zg&p1>&B8x22mf(k9-u!SIT6qo(U8Zc>IwFX-J`suIL3RH^x@-&0sMQMI6RL0zR^8q0sJ^P};7 zoj81b4mc5+K6Lce0_j-K*AGL(&ez4xZ{ri%07ND;00)6t;1Gb0eqz{9A8juO zDtK{%;|@87_MD#d26+D$=-Eyjx0lE5NfVcJ7tjj~1^5gOyTteO{s;WDC5^A?1>h9? z21v&A{v`DxpcqI6_!RXjpa!T5@W-jo1L)cw>?3v(x1HG9c`V}R82w*lcB6ZD2~Y}j z1bAXL*aox%+hY9S4D~~id5+_ACj&e-2cyUgl>>D^6VL*rfeBy|m;x3e^8)r>Af7J- zdG=3|3&!^l?O$Xs80SO7&~xk$1@q9eqmg+Q-=3wt&+Z2f00-lCy@pBdi5QfZhY$jdI4g?i!JUiO03|A+E?&{<7IU~QCkmnsq$ zO#laDxr-L4M*u%Azq%>LpWd&Sz52>nq^#NcIAl9!B1LWQ7qrez24om=(z!Y#0m;q*i!@v>X7;qvo zV`V@q0DkOfWZv-R4fKy_XAD2a4tPQ2a_p-9bWDGv96KqX5~u=NfMC9QW1ji~5Jl#j zWwG2iK8~M^%(wCF+rhl?ZS;J*8mI$WWB$Fhk=YAwZx^utL-4}^p1ABK278Ik-Z=pK zdx_DT6#zEg#Md{wV*c+HMdo|OKnXy5z6am;;Q3w+fbH+q15H3Pupy8eq&@@;10%pB zFa=Bl2Y>}23i!vUj{_5c@Z#5GJJ11i@`Kye05;y*0BnrqCX1lA{uX+mLw@jEf6+eZ zr_csJYw!Nh3GXDnzC}CUB35r5=l8=?KqY{^x6%9dHUK_;-91~5Hc!&#N!sz2z|nt# z`~Y%8z!)%r+(~Sd0ctn4^EUe5CSGr&|Lw!T5#U4)9UV%a;dlt}e8*!xY2)OAv;n}* zz7&AYec<;U&f(h+??GTDz|)tCo8?H1K2#q2llbU<>D(y*cht#sK%+g2>qffP^)Q~}MA`BP%^r!_zw&3k+0A2V~2K=-A{4Ms6liOe68FMrqykOO}htS^gc(2vCW|B!b6aVhz?AHdE>%}0^@BVuOdVts#9 z3%(Ah2ii_U9|1oKj5)i+?4#uW50i`s{IugEwkN(X9;X4l9C`|<1c;%G;r;ag{#F40 zen|ezz%x?;R0H_`qY|JD0RN*JU?TwUkAi$zY!ltxf!%KO7k^a!f!xsloZNomBliB? zD1M6n>UXR+L!UoAeTE$RchXL6cPuwUyJtE8iPOkw=!d}{0gfV{jOE0aFwVL0Q@X@A zC$6E)pP=JM#N$U3v0lObYkd9DRAhckzy7!qs1E40k@=H4fc*QDrU1X;cgUqfdMx*^ z@$UeB{usSKru<`K@#CJD{to`UQv#F%WdOYIR0MQS!_RlBot|Ld_6~l&(*zLvcUpnX zz+@nQocaO~0jFZT_;g@D`tbY5W55J32h2xib_0N}*+F19GXH)Q7>~?PngQ@XLFOmW zelh|e`xnsuViK4F(D@fLz#)Ks{flG3abO`bhl2i9`$O16*Z(i}>u5i*JJ1Bst^;jA zM-ZPyH0Ya&2W|f6$Ky11I-Gv`;dkl(NklwP8}AR-`|pdb-bMX~y`LOFpY)p?wclbr zv(RVB3)}xOUVRvc{}^yQ#%uo6A=3&B#`xJ1>eWCEP#fbV2M>@ZhoB#-$>0;KIR{=n z3vgby`Ur3oI0kUOnQ8^vfo;E=KgIcChJSO+pBe-|1PlXH0Ulc^Y^AW3I+?+nLnrX> zRAl}`5(xbNkHqyqmI7r!D&~)I;Hv_Bn)(1R2#mz|qv$ZO@)G!8mj!arkAXjS6qw7w({IP<*JIPbeqa`$AG7!}vVomLr?C?u zcLKn_cfA=ynYO%3Ti(U5cT0g3Pyti{)j%y!2QbdwZ30?=jX*2V26O`G)%G1+Y&WAf zS6?@BBfuCy8?C%|44n7J%VqJ$e1DDnUrz&vBJ-c|_dnz3f8G|Ezez>rco%@&@u8Ss z=^LPL6ncz5ev&$|`CH=gx1}-uZ}(F_5t;uo6PbD9Fi#BT4+68mVc;k*2h2z2=LSIj z=k-7{fSrYs$o#T7(1)JCU2ytpk^ATBqurwK@9^#KhW{7oJAzKy^|!~+HwX}e+;&R4 z{-0FPF7YFj8$%`-2VQ=ml9;r|a$2tjSCfN3OdWj-#CBmJ=KrtQ{ja4!1rX0e=I>f) zzxXQgl;bRLIF_4-KEDCj2>dR38$9j87t8;AC^Emm_Akl+`u7*~?=MCG+WGg`{Co8O z{h@&W0R4Xun1Lr(t`i(S{34iFetsBU+WT|j{_|j-{`oxh2wt%poEQ9Zl)OUsFHc5B z{`+s}{BPYrFM#e7$ejq{mf5W(YvTE9^#2+kem#d=2hasz!?J|2ycxx-M<_-G0UTviK)ItQ`UWp+Ns4{(x^G;H#ia zyMJ93(|uFq%V`IOgKP{dx>Q|A`=ve>F@Tq5bL@K-_t#8R0xEcaVjD2X zllRp?6OYjM07Jk8aDa!-XW(;x31X9nd>-<7bwE9U9etDdIL8Ixgk$EA7vS=XV|?;3 zx{m>Kz&wCl0eTD2TTlhm0)buiyA*kNLf?5<(Z2jK$T7lRiM5}1inb(y3UrSH=qi{3 z_5+82BLKEDf0M|IZAbTb!6n+!IbijAyu7)VPmJ?hfFWQQ7y%?^H30Nvz30xxCEEf# zerODib6fyugT^4mu?j$!_#OWh^Q!Z%v zvH{B+%Y*=Kn8UQ?O`C?kgrJ@8MXD#Li@eBrdYW>5P^UAsot{qcOfBI2T1uyxjs|Ue zA4TuO(q76NKdJa!AC?}0CUQ>aQfYftTwf+MI@i;ei4U9O`tlmeQ-Jefx%gDqaBjPe zLPoAQ1wIKlJH-{Q?CaIk2Lk$j%7=hTfHdNz=~6K;915 zzs`rV>JVvZisRsHoF)2OfD!JSCIhMBdluDT`iTKjrGKf6o?OwKnFN z*ha^MoeQT#LSpEw~g{)>*scJla84NKW3b7rB(1qpE+MjH&E`d zF-{xji)(l3G_=jumwwZjPBgfNJ73QeJ+(pqIGyK-A0MLgyn{kJjZP-e3c!W;doh*0$+FfF}p&1tO1;k6+@Iy)0P#p;M;v(IDcF$%cRdG zo{~HCQQ1ZgWiAh$-m)%mRaRbo^RgpM$OoXg`bv=%eNJv=kH`gcQ#o~PteoJm+2ndG}lg@OMQ+z*;Og%gFgR~4SfaFov*7VDYpiB z;No#n5`3+ThsV`{tIi&)7fFnI0O!j^^OQ$}Hu`zp#cFjLy2L645R=tnzsK6&ZW>OT z_bK6*+;V=TS}50N`<5C6*OEQ&r;dV~_3f6Kin?p}#bcCfgS->{_;azy3|pB2)377a zusyG_KfkY_A)OQs@AoBLluuc{2AK&P(}j&{0KAL)rJa=BT9BESios#$(nHLpqA_Lb z6^A*xx%H+UXEbgLu4)&U#6^| zJD3OZKiQYup6Jh7YcHRLXT-*$-`o`ErR&o*?a$biV-a)uSx8 z#WwaYnwy@_Z+I@*@N7ZDU}59#B@MfZ8g?#i*k0U_KC_|kteam*4CM_h+p)a=3^A1H z^K}!H>w-RaaakuZck`pL`?0Y;ML8$d>+8Y!@#6YyeJ?oX1lgnMoZ;sp*UoFn(?qgK zW3kIL>`XMu68}lb^rm#7OY|Ca(9Rm-md9Ez`;F&K!*hw<$(wf->?~{=ShAz2Y5UUt zWsT|O4SmIp&*ly0i-_|g{M}= zQ;o~5l*82{m&)Y)_C!N}9+}@K!%a5rB6njuJ|D6?gQj73qG4BF!_NGMfn>vuf`;vd z4gE_R(nSq@ONHIVysnCJPcUb=cGO899r5EM7(Y(#<2}&By=sa&K74$P!;JOertSF+ z{mF)OL1SN`Q2o5{FFR-p^S;FPrXBfAHOw-NvhjkaP8cKeiGys^@k?^@Mbq#?qG2en zA(L&IXN?2Png4<~8nkF7MXX56yYjX_FSA*#)%O`XIls(~ z;URO=v-u5!$%fqp4Z8{(b}nfcC~DZTw5fl2y11$DjHc%k&*g1jhFpb}{VZ)w8Xs%T zg1)7n+?hX+>|c^Dg2&A-zb`SFw0W6Xi(MRke-@fsS46AN9bQgn3|bi}X7Kftdn{h( zw-j~a!ta-w{NtHE*-q}~H})m%#O-W-aST=$TaohqeQ}QRwD-@Q@1($?mme%;k8k^F z(R%Cpnx83UzPIwq)8q!G8*^=A(ES|aV%K(%JY{bqdAgJRN#V@{i5+>{^ZS!&*=^YU z8ussG{3SXqA9Ka-WWz3&R+$}Io=eF5u(MER4Vg4l%*Scd2-W5we$MWuIq-hn9AJE) zZAsIPWPf3w^jIdx+mTO{+Pt`FdqHD=VPkrUWAV9q*ChO-uK)X&H>8Uj`*b#T{eE{d z^xmAfy1uwu`aPVdoyP3f~5`y_@==AH@4<-wTo_!;n>!Jf?FJ7oTuTa3TA z7<`ypHPngqy^OIl-MsMGzLhT)zi`ITna`i~T*?_!j*q+y)Z#QzTt^90=S$fj0=ePA;^la(idArZwwPI)4zy&)l+`h8EJiSVk zW&GJONFKRvKPP;{4rJ$9&gq{rzO$nQ6^0aN_Ua6!Um{ zFpoc<-}qdz@!5h#-7z%D)ZN&3R`XEauA-ewWwVezQzZTT^&+{IKhbDoc~kn9=A8`# zjXRpQf3pAPzGmS|$v^g?V1FLZo=~=fI=Kkd^Src~cChb~@jSp@DEUbnJUw@in4@Rp zAoFEc5~O-)9$?+`t#X&+fx>w6a0LDG4z@Ew%s)KC;H%# zHGuYuU$4v2pUZh%Wq`BxxDaYgQES7wQ<8hPrfYYt-+Apo&5rA~U*CU2-;Kf#h`xFb zwK?Oy*3q^Rry;i=e13VubHxqMp3yLPX2b5Y8g`X5?mT{OrPJ_x1wP{ zc8Jwh_6^2OKKs69ptxbj84cUdY)F?h_MfGv5#H|JS?nHl?Y?PuWy7v38g^dUIB-=% z|JugB>YJavd~nT&uR(W83`FL;V;o%Hus3E;MauN&**%q;Z@$OaNU{%abSJ}=B1}@yOa(j7NuO4P}?>ma$2YtWal1>Jx=H^N+ zSYyA&jw?!;81kzE=E6~z^9}tq4e9Gz`mTTOs%NVPuim|O*EKt<2iEOazx`U3DV2Za zf;WenU@b{G`~i+L){h;Wi^`^vHCMMm?p&XXjg{?!n3 z-%#cpLe~G5zGAy2*qxNK3E38;?POYOb^mpW^{u+$+bZ-by=3sx-4(ko+j;rGn(bGluj<1Q`Ez6Mmm9Fh7?50TNT2uV=a)UV{Mq8cGj^Z3 z>#Ut61846zXZyMRrG4kCOu78a%@pYam!~)NpTUWn8-Xrv@6SWWA30yqy5?7#CW)h=k^-%54$>T zQ+?V5>}$G4i8}->&gyCwB_``#-A!*&Q@Xa(*0e6yMlyfM+p}+np?+?LNP&83PW`-` zy6tU;gnva2UGv@JpkF}QEnyPe4}L|x*!Pd4t)QNCGQxW)^^-yUTIxrFdIR-iLH)Cl zksCq!C-VHTWTD29vefTY3ja9!59ieT{QVh{L-_x|-=DGdyc_+!7)Rej9T!Zitrz~0 zzt`gEulai{uFjhP_Wp{i|EtK@dn&H}4)redmAU%Ar7rnV@9O`a`V94yt8?SJ=s5LS zS3epVdr!sHe?h$$`bJm(N9q#4a$7IBj=K0?W$TG0d~{0UH{t4MM|qz}QBM*K@+*;w z5_`p-)XBfZmGFx{n;rl9DDPi(2mBwWzAdQVOnq}u|19+$>SInnKc!;t&p3T|Q5So4 zuD+FzTct$a)pt^_pkD0i{9HzHHT3~kpQ65>`XN{UH~zkitG^c|zC8!M$hGI^)MZ}s z_1|#MrH*=wf_WaUA>3;A?hwa^0>Ku_ClaW$=Ml6s!)zx)l*r>HkMI{9PonYj7`e8ejS z-Q`n$H}y8^HIDuq^&#rcpZsr;pY_yT|K#(-XZAjcS=doRV-lT0RA^>cFS7v?LoYK0-JSIDPfpM-l&Aek7Zz_XPa+ z`ui-7pZU+;S8??>sCU5c@-4~uvG-3LorfRyN!Aj$l*Dn;G(Pm%{U>^&39Ur-bo zd#}XRS5dEnzuMK;Q50m)2d@Nvou=hV4 z{RQfS&|6&nRq98n&$>GE^TlJ-UH=y_AKQBzj{eh}`g@VF_ck2;zekBblXW>^=ZC^& z)Medv^@2I>Wpq+^`CQ0+Vef5N`NDs}$HERn-|y=5*JT6LU3>~#smpxU?&$aXdls(# zH1%2NBd)%kkA}5VPrEwpUvr$gYkwj0qrKnY=(N|~YjAb)xpFi7ZayjeE9x>nHaL1j zeU7^8uO&%7^wlQwqoprlJ-7D|T>TpME6wn`@wDV){yu`E-{S8Xxccw;`vR^``|UM; zSHBy5MNS`aUqU|EYyFP?1p7N#kFKCUKrQ(i^=j%(uD+WOTBWGF_AOyOUtdqX-pP+g zi57`BKg6l>%#Z7Psk{7MauB+VuQMI}FZlpgG3`$}`TrYw4fJA1XFS;J|Bn9O-N&xR zZM}$mX-UC^Vjtq{qiVr+mYB_Q4Qly>TdiMecWH;cl@_Pm;CnhFF>!yKiA%( zPV`BCczdj`H@4H%Lr(sA=(NX_Ie*yC*z5X^&Umrc^IiQg*Xd<`sc`kb^VjWN{r@HY zW6;GPP)nKb>@|B!U%Jv?pLg~3tj7`j5|CjQBOJg ze(DEls@v}^`*VMd+R^{7$k=PouFib7X%2ZepDp`UWbCzNNB~&&S zzngf`pFUp8H*;NB^1t5EANSXZZ9VZE`FYs!lb_3bsmpkC`^V)ne(I>ZcrJg9{Xnau z(;v$xqr~`r;wj@xaApK}e^ z)i0wy2i?~{!FApi>TbR%zMcM-cr3N~RovmP16%nL9)9e=zr1?uUorFNtzxgl@$-Vh zfkV_?eigqS@k7RPY0>e2$DN<%Q>VSfKj5P-^yku(&c8orKYbvO|3CRy$RP1>{agGu zQQ{A3`Av!;r|-W-iEl~!Q?`Ca5&j&c?#AmGj1PNF+3G)I4IkAY{(0T5&i;FFO0FBb zdK3NA8_0j2k4ltq_B-L|_Yi;D@7sIEqyBoZqkkRxsesP<`qF0nckAOBuMl6_95y1`mNNr;s21UvtHQiuC9JJFYOb5-@Y>+!2db)Iseam!oIZc z=Z7GX3K%i*v^iY&W#d%Js8#3k-dLI*;++?|xf zP#Mk6%RUI>5zt^u{zkcuao1W1Dd7H@JV4rI*V}3Lq_wU31 zLhujX0KQrIOJ5)8ePgKSFpjS0 z`VPT=UIpg(>_a@=ei!g|mhYjzYxIxMAO6+p|0~EB?)wyQ3e5FG z-x=hmeMW!ekJ~YS?O%O=2K>B%U&4H`o*jL@0ef8p*7Nx`=qG>&SYOnyw;cjz|JY3X z&yB#l6n*o1f&07so3TGnlm43j0OEBgFvsWS!|jZH7BtKq%+g61NX5!)E_4< z0WUKh_1Y6(0-j-v{BrnZ;1kRbdz>K5_S*a;^2Y_nSeMO+r-$w{=+A*p@s~q?qF+Kh zL7%JlGsgUOTie^V8S{zTd#jcIE--Fa4SLmylm+zCVrr(0|K^+Zlg~PUl$O z$J&{Xfd5*Je_NlsDu3Sc8DKd+TVOwb7?{?Z#z#E*n}PNG zF9L4>ru~BGUk3*4^oM=xuLA4-ue37_;@9K-E9l=c_`eH$(cu3t;HQE0c&HcaXMlOU zts8+)0kghae**YEU>i*ag=8uZKP~9_zC;3p)9`?q38h82vv8ywB)= z5O^3^kADPslhGgXU%PDd|0Q6uzaGB|{HoC(>s@=v=)Va3lz~42{4g-vW9zR0-)G?8 z0c=#K%<0Be2E0@M8Td_NDo*WmwS;C^7O@0Z(|>Kg|CS5dE&fjK_6{uA(% zz+9hi{ZHWgf%hu^*!C{$*W~ZazYXVyXZCgZw-tdm8T`l>rw#eru>YPmi1*N4SD_WrzbXb_3Ov}`M4p!e*)N$-;ezE zxFNqE>wC(O-~TbtP5Gz~Xn)oA>i;9~oAQyrPnq(+32e&0+|K--A%FXOKsV%Xe;=?R ze|ri1hWzbEfDQTEU0_50_Iuiy$4vPj2i=taIbc)%3*a~9BOg3w%Ex~Fm?3|MXlEWZ z&N~*a2@vhDPW2Rm`Tpc>_rK>I_W$TR?EmZUu>WV?VSoHjO4JYA@9knd&%FB#Bplv) zg}@RIz<Z&OB@2@3k}UKLsp?l)N|4 z|6-TE^9uBTnXr<-6ZPx4{{UwBJKw9{C*u?!`s^HQXZBqJo#pNPAoyuN;qiAOzg|!B zH2oO*Zvgx-_Yc5N{;c_b74P74DBTY!{dS^0Ro{Uy|EJ{tcpUGQ8K1}amks$}Z1elp z%}PJya}AGwKjvQmo!4U*_Orbw z0XMO{-@$ra0M_&~ZIL;F`mfFUKGn`_!TN1{L;2$_?B5@t@iqSi_-h;L^fR6O^AyON zcz%Ba`|Jn4p!B;M`|Gp|d;>5_#$9+`IQKL#`@^p9K%Y~0)NlI71;9uV4m+DoVTkVrQaU-yZSx>@-TloZ=c=^jwy_f z_1SYT=0p9jVgBEM{8xarKA!-77Fdt}S&Wwg>+w#5UIhFQ&*$^N|6uU{3G&$);9;K6 z%b>qNbmsqO`0sR*WVYAf)^=tu`Qss`532rGE-U*EUJw40 zpzl-i2eY7){aF4W>aFvbYDeBd_%p3H)8CDFQuYE9>@`UK`CX8C{)2a7{x^5|2R-yR z;$yH0{x1_hkB@wP?n}Vzzk|pxXJ04G^iRS*CxO{MgV@ime;Qcp`vr{mnt`8#zY^5) zzlQk`=Jgu~ ztD%1APx86{5bS^UPpQB1-=Tf5$E(1s|Ii5ZKVe{;2mb)}$V{pA8p8Vnik}YuZEf+5 z2eJMSDt(9M5YKIcj(qZ$F9EZ?hEn9SIxy*jd^Yq^%;!nQSihm))ZY_rmi|8UY0wLx zD}BROdQ;uA-E1i8QNyvkW*V=E*h{>W?}z=wYJ^QYcIuWBwZw4Jh%Da?JSzypNI`Ge zPZ?H{MBQcm&~>cXOU0rWCw|z>I>K>6*Bc$F26mbavuPtjn`I?Sc4c(La>8bk+Raoz zr$G44Kt!!H@td{4t9#1?_~KYe8VmdeUQ;x@hSP}X0+p#Tb)pr~Yz4u5Z2JMa&qcQ5 ziOBJ3gsNYIPPSVSso(HoD+xR=5>>zHT2btWVj>LFFm}CoGHgMW4ivWQS`}|m9I_X^ zLsQf)CJr1|T-0{3(EYYxyS+xsa;i1UZP->C+s&lvk?vt^*F2cfv!He> z60YA2Ez&Uw!qlq4`hI-3R66!*FrH-xeywRXB&~*oaxA}z1&E;(CP(a8GEb6m!8*Fc zNw+X?oWi!?#%%?Q$f^j(4jd~Yr4s)hPml&q7=)y&yI8ZW#n^6Gv7N$31pQ`3M0V^a zjzzH1;C8HCMKa)KN%ytWG`5yvKlL!rB=Y47@U3bN;1yOHN(Y0J(JeK}3G%8*M)*YU zItHR)FL;(T0IGsk#^PJ9m)cHU1YWVQW`JVB6ekB*5|QsO8w+EMCmAqp zFcho^#*`~(JD3nq#ZEloJN0o3>)%S43U^eqr5iO@*Q?sCAcen$j)!OoqpY9Ac6L-y zbXbj+T9_#IXq}|P&9<5|VPbewvfxKTyOr0Zm2_c=AP8v@>B2I{u?DuY5FucgjHs*o zwYr8uxTJ5*=4#^AbUS(&TtFg1WH;@GCs(=>MS7v5z(%5gad7pr@Q*ZGAPuAkxi(uM zDjlOr`P{f@qRCz{8}lX6TH81-5SA))P{0Uymj{uF7yEX=6E>xc7KKyyoCONj zPAVWjRlFl(GJhdqAvhc1qKC{&7t1S;p@kmrP^kM_}(tt7c&^&$=kvRzjzqP+p@6VGr@J)6~*Br>rWr23IA~ zT6G!mOM6p`+^n*QO{AGtVR@JDq{e=;8nW&cyV=AJaQwjR-1N~SV&d5J;i>5(2alr5 zk{vg#W+=l~?l*4i!zC=M+G;wMl^xCJb81+)^D0^?KUxM2j))~9=jrq+=gT94nk;N# z%I%Q%%m9(@)a4%;D~Jk$NR|TB$&gh578qb zKbnJbwA#F{Iq(lSm#RBDO5{h!awVa{O0TZ=AQUHID|S3c00V->a4EOdXsoQWkII~$ z*j5FxLR*~7+@uALfCAGQPy~LBg1m>ZbN9Hm@iO45Lj}F<=Pm5I6f}bl2wG7fk7l6jlv}_ zZbg>8WFuoVQN2`>6)_k2%~o^(q0>>nlrNTr;zADVk%C$2NfyUP3d{uyN?8eVl+22h z*dt_sPH9CAa#$C4GVc=^3DoK|$c!Yb5h;dxVDx6HbCTLmEkCT-aaW6cu2jT+1b_9K zGM=SvP|qxgdVrdWs@)*0!5f1>g+>+ir;L_a4@LDn3NVyROC7?qR{Eq>*BG_>p3+vxQS=(AI14jvHwzUn=F`IYvo|0v0K_ z8aC5BcKTW+ODrW(x103v!I}5?!~v^{(iHnbl`3mgO^|_tka81EQj1g?Bi2J00PR*i zvaM>hT6S_6*Rl>CJ2E+sjEp>+FXl%}Du=24T`c-B3SX-dEKs&b%%}?5M`2{-XLv{{ zuM%{(L)RGjLa|f=8MUe9*IZ6Q9WO^H=iufryNb*X0cjvF+gTY-wUa8^`{A@?&>`wiH|MR^w2W2MkNKQ1Px)Kg}6jB?3{v2wXgT}=NSD;J6?1?eiGmkKXk-Jv|bx@kN| zgY(%Y_^D;jmi&?-c}S+RK>i$ihwMD2UfM>@}5+JI3)3L z*oNyn*(erp27odzNwfK}QhAiLSE>TR3qn_BOQMafntw4rmZM5s9$qL%CnU3vbbCSz z7364&0ZwOSRQWYb(+<2e^+t6w_FT2QIDA!gF0;YR-rX$=fh?btaK*DsK)4pel(;H7 zo+9Z<3L(xNH32)iBp}Dgjs@yPV+sFpjeh6rw5D`IpVEvn^CYmbOdD|udTP^=d0k`imCXS5oExpl3Gv2{gsT6;vu z*0mxK>Fa3GY3&gqTi1%fp1+QWPHT?{*}7K5$hsmrtvw=S>sk?obwzYqdql|AwIawd zRy&-V>$LWWkge;8$ge9xxAuyl)>R^GsIXQGv$ZQix2_UFlUpmoZ0(BBt*b=H2w5`` zv$ZQix2_UVtzvd-M3}8z5xRAah)Q)m5#3f(glb(QqD*S6Ues#0)fAyxE!SV1#!-4a znwJN;B8hYArV-=e5J$U$SdM`Ol~RLP=_)bWpiJChFXM@F0uP;sy_)T;@NmGlbvh+gJ)1&qdE9YS2u`mn=N`$oDOaRD`y$qmc{fbu3XE*r<(Wdu(n3OM-u1 zatFQ`ouZ?%qpcKYQ!}J73oM|XJkV&thO}B*OU~iYy#k;YqAjwW@(2f3o=GlpY1tkrWkO+UsC# zRMj|iQ>Kiy##FA+K~pSiCg~JdLrB0$Kq41dR)08fNOf0oqHa7WUzYBu=Buj0;bA&# zoz}BPrLF9WGDDu|=WWZunI1oGP0h?7&R3~00Q;C^m#6bvan~n+f%rs3Wh{Upz;=E{WgiRhja&Y=qF-=dGQ+UUM(`Nq&jGhpXFhCns7lkq=0KiNVb_#vH7I`Wm<+PTfm+@hs*v?{S()T7bl z)GVGi>1i*4V@s!WLm7%lbd>!f5AR3j8a~B6n@23;F&B>xIOT%>&_NH<0Y%b`AIoPo zO0-L1yg*T_CzI1Qz*)5PpJVDWEmMaaQM2OR(waOte_(FjjJe7(wij4HB~Z)bfKp37 zb#zvUY_igTyW)yBoAO%Mcha4*+$B46%k1>rWVY2@qIV%#uda?oL{?fOOQDj*>6wQH zd4^7>+WMYKPJM4zDluMjG8b}Gvj&G_h@k~e7#a;Yu5N?X^=&V+JeI+W=C|>)2fP{l zUM*jE(?=@&trpAJ%U8T=mwfmZ?S{?Z!Ta*zhnPl}O?*$^{gAwgHvLVF%#mSy<`FTC z+Bfj8!H2)Kq5j?lUYE_RsJm$i6x&{W*S{+Ec%(l zufE6KA42cx!;+%@qiI$z-}h(470-Qh9lnJgz71c<;N>#;^X-e2<_(&k3KL-203WKYmCv8MMzC_xN=0 z-dlyZ>09gYeX*DC{62hNni_oC4`@t$d&NIjy$C&qPXQtRGhfA3``Np2k3ZAGKUe+R a&G??>l!mx!-SO#*!FTnBSAbt!&G)}YO;TF` literal 0 HcmV?d00001 diff --git a/roms/seabios-hppa b/roms/seabios-hppa new file mode 160000 index 0000000000..8fa4ca9935 --- /dev/null +++ b/roms/seabios-hppa @@ -0,0 +1 @@ +Subproject commit 8fa4ca9935669414a824ecda24f6e70c36e8dc94 From patchwork Mon Jan 22 03:42:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125333 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp954569ljf; Sun, 21 Jan 2018 20:22:29 -0800 (PST) X-Google-Smtp-Source: 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:17 -0800 Message-Id: <20180122034217.19593-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 43/43] hw/hppa: Add MAINTAINERS entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) -- 2.14.3 diff --git a/MAINTAINERS b/MAINTAINERS index 753e7996ce..bee6b2bec7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -133,6 +133,7 @@ HPPA (PA-RISC) M: Richard Henderson S: Maintained F: target/hppa/ +F: hw/hppa/ F: disas/hppa.c LM32