From patchwork Fri Nov 27 12:11:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 333618 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp965514ejs; Fri, 27 Nov 2020 04:12:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJwdyn8nSlo4BgYPYvzHX3wbHBzW3xtkFFaySJiVBosKqznXZbsyc8r5D466nojMRC8csTOS X-Received: by 2002:a17:906:dc4:: with SMTP id p4mr7347150eji.56.1606479154853; Fri, 27 Nov 2020 04:12:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606479154; cv=none; d=google.com; s=arc-20160816; b=b6GR2nOAn2+iG9dlbT5JEvTO0PyYb4sFqx3gpOvAqtDVFnm5QteKrWeIbsMDrQlkhu PWSllq3Q4/+qdIyyLOwbwJFmkt3/+D/hxP+AWoenL43amj379T9EeNyyBex0v+1rjLB5 RbWFYGGfuMqjhjMTKgoj0KICEbcF36T/Fn3X4HqEnZXWG80+uqpyRlUgpjIpzjI+ZTHL y885ytyikSlXaBzAtsEqD6xZMd5Fqi17nOGXhG8hO1OlCztld9Na7J+pbz749U9DkmHZ uYPo5CKqPUdrtZHnUb6b+ZOBg6DR28Bypv392+2R5AnfLRetNWeSbRZplmHBzpXoH1UA W19Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jLxCd/F4fxI6lLKUfeAQgTwipZuT/u/XIJSTRbWtMDg=; b=HRSZ60jj8n9xYIjCSQzgJ8+ibgS0Sr3vbn9b8N45+Q+xOKGh7Hiq1e8FlsivMG85v+ 7M88DH8DVfFFmDwzlp2+zcTw3QjiaXvs649WbHrD07wYhMuLqyfBJVEHYfFbN83MK0Hc B7/l1D9Za/cpQtRGkbFeHUrHKErINKb6u3nPyYP6CD/o5QZ6zb35lgqHOsu5J3hmaWfO w2qdHU6uROomyCvOV1UQTRVaCIMu8EzNMNtxPQ7gf4+92hInEfjAFjRzpslXrl7/pnuq TOOK6zD1lF6wmnVHV42kfXeWW3jqsG5rWQmTJsHPnkvKlakLa3R8A68lJagzzyZ6I21w tkpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CPNWCzWs; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This LLCC is used to provide common cache memory pool for the cores in the SM8250 SoC thereby minimizing the percore caches. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.25.1 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..118b6bb29ebc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1758,6 +1758,12 @@ usb_1_dwc3: dwc3@a600000 { }; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8250-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + usb_2: usb@a8f8800 { compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; From patchwork Fri Nov 27 12:11:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 333619 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp965799ejs; Fri, 27 Nov 2020 04:12:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJx4EL6a5F/EtZF/fgYK+PpnOhuvPzP4PKqm23S9YnNUXSumC2okOm8GQ4Lv7/p8a97sWikG X-Received: by 2002:aa7:d48d:: with SMTP id b13mr7406952edr.264.1606479171836; Fri, 27 Nov 2020 04:12:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606479171; cv=none; d=google.com; s=arc-20160816; b=r7RMb5xG5hz86SA+BBDylJ6U1uuCIpt21G/CqYQg3xsq2bP/MJYS9jAXu9gEkTn36w upiOrdFJzTB4Y2fUEx2fIlvjK5kB0zm5BQKwzB/HaIcX9phMpf7HAoYIReelctS8JHHM dDuXhYbgLyLw74MVu1XqcBd2xCCm+jbl/vWCdRQpjzWtdLWaj6dkrGZGNsvLsRzWew0y gInyt5zoTyUC+tdSITiWzASwlacJo15w6ocZjr7vjy/owyRxIzNuPmWByvrIMbcCbdTq JFl4viq9AcD+QLFH0EaRzwpP+F7Ph/226IGl2oDDDuLEStL8WFpHydK0hr8aN+pQ9LZe TSuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kzKkCt4qLiDzrU3pEP907cfAa2/fONI8wtqu9xL5mS0=; b=p8VO//tvVter0j4WCSJEhbj6kYF/ezDWfUnMk7ApUUxrI2u3emi5vExtJwQlC/U7GA KT/yxH79b9T/cl6kzV2Hnp+QGWiWsU3hvRTQG8oXTJmTgYmK9giWjRqc7kCH44RAu16C e0hJsm5CL6iJUtirkY0IDOKQ+2F8jYkJlfPNmO4Wid5Hw5LJRUiKUz+bqRsGZIdzSIos 0fCYkarUAgQQL05Q5i1n9BGEHIppNsZo5fRvNwMsnj65nysyqmk0FgbAHiB6WfyjUno5 G1PzIODiSrGkkgckkoacBb4PXNTlmksVpW9mmLKhdDOEWWYH6XzDqQILt0Eu/RH5m0Um 6jdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="P7i2Ll/V"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In this version, the WRSC_EN register needs to be written to enable the Write Sub Cache for each SCID. Hence, use a dedicated "write_scid_en" member with predefined values and write them for SoCs enabling the "llcc_v2" flag. Signed-off-by: Manivannan Sadhasivam --- drivers/soc/qcom/llcc-qcom.c | 40 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 1 + 2 files changed, 41 insertions(+) -- 2.25.1 diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 16b421608e9c..3ec4cdffa852 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -47,6 +47,7 @@ #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 #define LLCC_TRP_PCB_ACT 0x21f04 +#define LLCC_TRP_WRSC_EN 0x21f20 #define BANK_OFFSET_STRIDE 0x80000 @@ -73,6 +74,7 @@ * then the ways assigned to this client are not flushed on power * collapse. * @activate_on_init: Activate the slice immediately after it is programmed + * @write_scid_en: Bit enables write cache support for a given scid. */ struct llcc_slice_config { u32 usecase_id; @@ -87,12 +89,14 @@ struct llcc_slice_config { bool dis_cap_alloc; bool retain_on_pc; bool activate_on_init; + bool write_scid_en; }; struct qcom_llcc_config { const struct llcc_slice_config *sct_data; int size; bool need_llcc_cfg; + bool llcc_v2; }; static const struct llcc_slice_config sc7180_data[] = { @@ -147,6 +151,25 @@ static const struct llcc_slice_config sm8150_data[] = { { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, }; +static const struct llcc_slice_config sm8250_data[] = { + { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, + { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, + { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, +}; + static const struct qcom_llcc_config sc7180_cfg = { .sct_data = sc7180_data, .size = ARRAY_SIZE(sc7180_data), @@ -164,6 +187,12 @@ static const struct qcom_llcc_config sm8150_cfg = { .size = ARRAY_SIZE(sm8150_data), }; +static const struct qcom_llcc_config sm8250_cfg = { + .sct_data = sm8250_data, + .size = ARRAY_SIZE(sm8250_data), + .llcc_v2 = true, +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -413,6 +442,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, return ret; } + if (cfg->llcc_v2) { + u32 wren; + + wren = config->write_scid_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, + BIT(config->slice_id), wren); + if (ret) + return ret; + } + if (config->activate_on_init) { desc.slice_id = config->slice_id; ret = llcc_slice_activate(&desc); @@ -559,6 +598,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, + { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { } }; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 3db6797ba6ff..85f18ae7692f 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -29,6 +29,7 @@ #define LLCC_AUDHW 22 #define LLCC_NPU 23 #define LLCC_WLHW 24 +#define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30 #define LLCC_WRCACHE 31