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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:41 -0800 Message-Id: <20180124232625.30105-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 01/45] target/hppa: Skeleton support for hppa-softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller With the addition of default-configs/hppa-softmmu.mak, this will compile. It is not enabled with this patch, however. Signed-off-by: Helge Deller Signed-off-by: Richard Henderson --- include/sysemu/arch_init.h | 1 + target/hppa/cpu.h | 1 + arch_init.c | 2 ++ hw/hppa/machine.c | 38 ++++++++++++++++++++++++++++++++ target/hppa/cpu.c | 5 +++++ target/hppa/helper.c | 10 --------- target/hppa/mem_helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/op_helper.c | 13 +++++++++-- hw/hppa/Makefile.objs | 1 + target/hppa/Makefile.objs | 2 +- 10 files changed, 114 insertions(+), 13 deletions(-) create mode 100644 hw/hppa/machine.c create mode 100644 target/hppa/mem_helper.c create mode 100644 hw/hppa/Makefile.objs -- 2.14.3 diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 8751c468ed..f999bfd3be 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -24,6 +24,7 @@ enum { QEMU_ARCH_MOXIE = (1 << 15), QEMU_ARCH_TRICORE = (1 << 16), QEMU_ARCH_NIOS2 = (1 << 17), + QEMU_ARCH_HPPA = (1 << 18), }; extern const uint32_t arch_type; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8d14077763..7fad92144c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -133,6 +133,7 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env); int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); diff --git a/arch_init.c b/arch_init.c index a0b8ed6167..4c36f2b076 100644 --- a/arch_init.c +++ b/arch_init.c @@ -53,6 +53,8 @@ int graphic_depth = 32; #define QEMU_ARCH QEMU_ARCH_CRIS #elif defined(TARGET_I386) #define QEMU_ARCH QEMU_ARCH_I386 +#elif defined(TARGET_HPPA) +#define QEMU_ARCH QEMU_ARCH_HPPA #elif defined(TARGET_M68K) #define QEMU_ARCH QEMU_ARCH_M68K #elif defined(TARGET_LM32) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c new file mode 100644 index 0000000000..79958da18f --- /dev/null +++ b/hw/hppa/machine.c @@ -0,0 +1,38 @@ +/* + * QEMU HPPA hardware system emulator. + * Copyright 2018 Helge Deller + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "elf.h" +#include "hw/loader.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "sysemu/sysemu.h" +#include "hw/timer/mc146818rtc.h" +#include "hw/ide.h" +#include "hw/timer/i8254.h" +#include "hw/char/serial.h" +#include "qemu/cutils.h" +#include "qapi/error.h" + + +static void machine_hppa_init(MachineState *machine) +{ +} + +static void machine_hppa_machine_init(MachineClass *mc) +{ + mc->desc = "HPPA generic machine"; + mc->init = machine_hppa_init; + mc->block_default_type = IF_SCSI; + mc->max_cpus = 1; + mc->is_default = 1; + mc->default_ram_size = 512 * M_BYTE; + mc->default_boot_order = "cd"; +} + +DEFINE_MACHINE("hppa", machine_hppa_machine_init) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9e7b0d4ccb..f6d92de972 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -132,7 +132,12 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; cc->gdb_read_register = hppa_cpu_gdb_read_register; cc->gdb_write_register = hppa_cpu_gdb_write_register; +#ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; +#else + cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; +#endif + cc->disas_set_info = hppa_cpu_disas_set_info; cc->tcg_initialize = hppa_translate_init; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index ba04a9a52b..d6d6f06cb0 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -65,16 +65,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) env->psw_cb = cb; } -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, - int rw, int mmu_idx) -{ - HPPACPU *cpu = HPPA_CPU(cs); - - cs->exception_index = EXCP_SIGSEGV; - cpu->env.ior = address; - return 1; -} - void hppa_cpu_do_interrupt(CPUState *cs) { HPPACPU *cpu = HPPA_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c new file mode 100644 index 0000000000..e0802bc935 --- /dev/null +++ b/target/hppa/mem_helper.c @@ -0,0 +1,54 @@ +/* + * HPPA memory access helper routines + * + * Copyright (c) 2017 Helge Deller + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qom/cpu.h" + +#ifdef CONFIG_USER_ONLY +int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, + int rw, int mmu_idx) +{ + HPPACPU *cpu = HPPA_CPU(cs); + + cs->exception_index = EXCP_SIGSEGV; + cpu->env.ior = address; + return 1; +} +#else +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + /* Stub */ + return addr; +} + +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, + int mmu_idx, uintptr_t retaddr) +{ + /* Stub */ + int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + hwaddr phys = addr; + + /* Success! Store the translation into the QEMU TLB. */ + tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); +} +#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 3104404e8d..9c7603588f 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -58,9 +58,9 @@ void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY uint32_t old, new, cmp; -#ifdef CONFIG_USER_ONLY uint32_t *haddr = g2h(addr - 1); old = *haddr; while (1) { @@ -72,7 +72,8 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val, old = cmp; } #else -#error "Not implemented." + /* FIXME -- we can do better. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #endif } @@ -158,12 +159,20 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, target_ulong HELPER(probe_r)(target_ulong addr) { +#ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_READ); +#else + return 1; /* FIXME */ +#endif } target_ulong HELPER(probe_w)(target_ulong addr) { +#ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_WRITE); +#else + return 1; /* FIXME */ +#endif } void HELPER(loaded_fr0)(CPUHPPAState *env) diff --git a/hw/hppa/Makefile.objs b/hw/hppa/Makefile.objs new file mode 100644 index 0000000000..46b2ae18de --- /dev/null +++ b/hw/hppa/Makefile.objs @@ -0,0 +1 @@ +obj-y += machine.o diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index 263446fa0b..d89285307b 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1 @@ -obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o +obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o From patchwork Wed Jan 24 23:25:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125723 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp733588ljf; Wed, 24 Jan 2018 15:32:46 -0800 (PST) X-Google-Smtp-Source: AH8x2276U4w5bApeHogp7bgeQmlH+ef3ZVYAeA0BJg57vsAJ0ZX/rlu0jKy9N3FBGPlGvFeimr6s X-Received: by 10.37.183.134 with SMTP id n6mr6981177ybh.216.1516836766437; Wed, 24 Jan 2018 15:32:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836766; cv=none; d=google.com; s=arc-20160816; b=PVM8LuigSxXQeDceblMxZ0yFK6KUebcWHQKNewlTlQ8Y6wBdAjV3XSG9KegeRgjVVP KFfCJm35teCIVRSrAkNxJoaIQhByVBlxKiXZ1TFVBTyzwwRJcjUREIIc+CM3aZ+fbAZT izD/oyVMUEX/DFhcldgavjpydp0zuCp+pCltqL8n70ooDDZTm3xCptHt3YvZYpwqGkvk UM66HNl0Qt5tKJFEKJWtLLNVBbybSymzqpe3y0TBvFdXxSYY9GqNL8sJch5krz3481Ru uZuMxTc7Kv6DftCExc6M87R0snKsE9IOsB9sFcj2SYq7DqNhqvyJ2TR7IRcHeMQ5fudi eVLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/D3ilS4wflTksMAoF+YKaff+lQbvvqDLvk8pG7D1+9Y=; b=NeLlyRkIXDefd3r4sc7DVS9VMuu33iFaUNTR9uJK23oVKtDQl5nzTcaCh5wZ4N2gNO vu7Mb92LvUYqlb0fEBYUypNFNWjjgKNJywplgukMNnMYHPRD0yKFLdRSakBrzZcY9vI8 ewNBJ30h07peDjd9U4iY0MnERNpDsDl5CDNtsRzq0m4QqmDk3cMKlIowedrCvfcH9Rrt fXU+1pHONGTeFDxFwmK2jR1M1z4VUbZB2WmoHCCuRBie0CSZc3wZKB2j/d6FBoRinFjK TQsd1ZxZVD26ioE+l6LJwQeN3gYS39BEi4BcZOx8hx7Q0Aes3VmoMMLsku1uETOrw2lc zMaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MOaeRiPw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:42 -0800 Message-Id: <20180124232625.30105-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 02/45] target/hppa: Define the rest of the PSW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We don't actually do anything with most of the bits yet, but at least they have names and we have somewhere to store them. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/helper.c | 53 ++++++++++++++++++++++++++++++++++++++-------------- 2 files changed, 86 insertions(+), 14 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7fad92144c..ea7e495408 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -46,6 +46,52 @@ #define EXCP_SIGILL 4 #define EXCP_SIGFPE 5 +/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ +#define PSW_I 0x00000001 +#define PSW_D 0x00000002 +#define PSW_P 0x00000004 +#define PSW_Q 0x00000008 +#define PSW_R 0x00000010 +#define PSW_F 0x00000020 +#define PSW_G 0x00000040 /* PA1.x only */ +#define PSW_O 0x00000080 /* PA2.0 only */ +#define PSW_CB 0x0000ff00 +#define PSW_M 0x00010000 +#define PSW_V 0x00020000 +#define PSW_C 0x00040000 +#define PSW_B 0x00080000 +#define PSW_X 0x00100000 +#define PSW_N 0x00200000 +#define PSW_L 0x00400000 +#define PSW_H 0x00800000 +#define PSW_T 0x01000000 +#define PSW_S 0x02000000 +#define PSW_E 0x04000000 +#ifdef TARGET_HPPA64 +#define PSW_W 0x08000000 /* PA2.0 only */ +#else +#define PSW_W 0 +#endif +#define PSW_Z 0x40000000 /* PA1.x only */ +#define PSW_Y 0x80000000 /* PA1.x only */ + +#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ + | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) + +/* ssm/rsm instructions number PSW_W and PSW_E differently */ +#define PSW_SM_I PSW_I /* Enable External Interrupts */ +#define PSW_SM_D PSW_D +#define PSW_SM_P PSW_P +#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ +#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ +#ifdef TARGET_HPPA64 +#define PSW_SM_E 0x100 +#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ +#else +#define PSW_SM_E 0 +#define PSW_SM_W 0 +#endif + typedef struct CPUHPPAState CPUHPPAState; struct CPUHPPAState { @@ -56,6 +102,7 @@ struct CPUHPPAState { target_ulong cr26; target_ulong cr27; + target_long psw; /* All psw bits except the following: */ target_ulong psw_n; /* boolean */ target_long psw_v; /* in most significant bit */ diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d6d6f06cb0..4231ef3bff 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -39,10 +39,11 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) /* .........................bcdefgh */ psw |= (psw >> 12) & 0xf; psw |= env->psw_cb_msb << 7; - psw <<= 8; + psw = (psw & 0xff) << 8; - psw |= env->psw_n << 21; - psw |= (env->psw_v < 0) << 17; + psw |= env->psw_n * PSW_N; + psw |= (env->psw_v < 0) * PSW_V; + psw |= env->psw; return psw; } @@ -51,8 +52,9 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { target_ulong cb = 0; - env->psw_n = (psw >> 21) & 1; - env->psw_v = -((psw >> 17) & 1); + env->psw = psw & ~(PSW_N | PSW_V | PSW_CB); + env->psw_n = (psw / PSW_N) & 1; + env->psw_v = -((psw / PSW_V) & 1); env->psw_cb_msb = (psw >> 15) & 1; cb |= ((psw >> 14) & 1) << 28; @@ -106,22 +108,45 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; + target_ulong psw = cpu_hppa_get_psw(env); + target_ulong psw_cb; + char psw_c[20]; int i; - cpu_fprintf(f, "IA_F " TARGET_FMT_lx - " IA_B " TARGET_FMT_lx - " PSW " TARGET_FMT_lx - " [N:" TARGET_FMT_ld " V:%d" - " CB:" TARGET_FMT_lx "]\n ", - env->iaoq_f, env->iaoq_b, cpu_hppa_get_psw(env), - env->psw_n, env->psw_v < 0, - ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28)); - for (i = 1; i < 32; i++) { + cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", + env->iaoq_f, env->iaoq_b); + + psw_c[0] = (psw & PSW_W ? 'W' : '-'); + psw_c[1] = (psw & PSW_E ? 'E' : '-'); + psw_c[2] = (psw & PSW_S ? 'S' : '-'); + psw_c[3] = (psw & PSW_T ? 'T' : '-'); + psw_c[4] = (psw & PSW_H ? 'H' : '-'); + psw_c[5] = (psw & PSW_L ? 'L' : '-'); + psw_c[6] = (psw & PSW_N ? 'N' : '-'); + psw_c[7] = (psw & PSW_X ? 'X' : '-'); + psw_c[8] = (psw & PSW_B ? 'B' : '-'); + psw_c[9] = (psw & PSW_C ? 'C' : '-'); + psw_c[10] = (psw & PSW_V ? 'V' : '-'); + psw_c[11] = (psw & PSW_M ? 'M' : '-'); + psw_c[12] = (psw & PSW_F ? 'F' : '-'); + psw_c[13] = (psw & PSW_R ? 'R' : '-'); + psw_c[14] = (psw & PSW_Q ? 'Q' : '-'); + psw_c[15] = (psw & PSW_P ? 'P' : '-'); + psw_c[16] = (psw & PSW_D ? 'D' : '-'); + psw_c[17] = (psw & PSW_I ? 'I' : '-'); + psw_c[18] = '\0'; + psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); + + cpu_fprintf(f, "PSW " TARGET_FMT_lx " CB " TARGET_FMT_lx " %s\n", + psw, psw_cb, psw_c); + + for (i = 0; i < 32; i++) { cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); if ((i % 4) == 3) { cpu_fprintf(f, "\n"); } } + cpu_fprintf(f, "\n"); /* ??? FR */ } From patchwork Wed Jan 24 23:25:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125724 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp733864ljf; Wed, 24 Jan 2018 15:33:22 -0800 (PST) X-Google-Smtp-Source: AH8x2272mJhOh5pfxEGCFE/THjchwwREU47hCaB+93pf7S4oBhtsy1iisM1Jb479meAn43G3x8qw X-Received: by 10.37.130.8 with SMTP id q8mr6936752ybk.339.1516836802099; Wed, 24 Jan 2018 15:33:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836802; cv=none; d=google.com; s=arc-20160816; b=J7gMseuVaDRrvYXa3rzsCSrXs47JG2Wyv814a4YiWINMVNlvxT6+ibh78onu5ic3gV uHNfDlqGCsCPuGjc2uSa7qNRv0eEvrJ3o6jZZe78ivUw8e3/bJefTplj/7c1C//0VKe2 gm74Eb5rPqTJCByWTV0zwB1h+/aMV31Zy50ahZQrqV97nh9oGSoWkiC/VTC9QqoqYe18 wGfIk7RdL/9o1zYOFh6TCfhZm6w9lYNlrOVT59n96ZShETIczNVmMQ3NDEmrU5iXIA/P fpUSFhPVZkI1bt8d/K0f5bUXw5pa/zBvuQAg2EHK/myJrUmldQllc3hEUYL5H8T1+4dG l2PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=jWlXGhyGzuQklKuZM0jR3HHQ8HHbSqFzQDbbpF04MmY=; b=b1W03KHa2DDNK5WGSupD2B6cxa0+WB16VSXIRDKL+b/NytgfCmWE8MvMToPIXoCgc9 sJ477iiEKV45o1S+hRVzrT3lh4ndDpLEJoZa96DV7WaowJCbtkzCa0btM3Ligql5/gMx Ib0PvHz534VthQuOYkhc3+oP7CGSLpi9YUgqzwyDzpvAQwflIUqKpwe5Ti9Wxj2vr+Pn yDB66ed/Y3HLIhr29Sw1jFQk0SbW4YanhHvIU3nVPogSYOlgTOi2LSOJGkp/z7GHv4C+ L7zxqu1cxgQlad/fYv4WnWYi3I3zlE1hMmSNbzVO8sjKSC9kvVjumqeOW7IruLL5gs7e XenA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kJW73X6E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:43 -0800 Message-Id: <20180124232625.30105-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 03/45] target/hppa: Disable gateway page emulation for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 31d9a2a31b..8e357cc60c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1543,6 +1543,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, return DISAS_NEXT; } +#ifdef CONFIG_USER_ONLY /* On Linux, page zero is normally marked execute only + gateway. Therefore normal read or write is supposed to fail, but specific offsets have kernel code mapped to raise permissions to implement @@ -1600,6 +1601,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; } } +#endif static DisasJumpType trans_nop(DisasContext *ctx, uint32_t insn, const DisasInsn *di) @@ -3787,10 +3789,13 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) int i, n; /* Execute one insn. */ +#ifdef CONFIG_USER_ONLY if (ctx->iaoq_f < TARGET_PAGE_SIZE) { ret = do_page_zero(ctx); assert(ret != DISAS_NEXT); - } else { + } else +#endif + { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f); @@ -3885,25 +3890,27 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { TranslationBlock *tb = dcbase->tb; + target_ulong pc = tb->pc; - switch (tb->pc) { +#ifdef CONFIG_USER_ONLY + switch (pc) { case 0x00: qemu_log("IN:\n0x00000000: (null)\n"); - break; + return; case 0xb0: qemu_log("IN:\n0x000000b0: light-weight-syscall\n"); - break; + return; case 0xe0: qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n"); - break; + return; case 0x100: qemu_log("IN:\n0x00000100: syscall\n"); - break; - default: - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, tb->size); - break; + return; } +#endif + + qemu_log("IN: %s\n", lookup_symbol(pc)); + log_target_disas(cs, pc, tb->size); } static const TranslatorOps hppa_tr_ops = { From patchwork Wed Jan 24 23:25:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125721 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp732328ljf; Wed, 24 Jan 2018 15:30:09 -0800 (PST) X-Google-Smtp-Source: AH8x2275SG+3tve5c8D6KvKrK93Mxd6KQ8tavdNLLcCVqLbb9oKiA+hl5ZoIw3zSDNRMaWGfAaeo X-Received: by 10.129.41.81 with SMTP id p78mr6860954ywp.368.1516836609862; Wed, 24 Jan 2018 15:30:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836609; cv=none; d=google.com; s=arc-20160816; b=bpWxxn833tyTWcBioJb2+4YpfcZDcUMJnSj9mZUij0zmkoOEEp+Ggg5IAlpZdrSKnS DQG2UUpN0zM6D0ahZBMp4DJGMgLHl3FarT2+LB8gOqIdF1cjIHsAV8KhQcyyvMV52K4n 0mTUCqiQW4tUK1zNLiW3S00Ex/ucy7IXoi5nf0p/zsFATeOHxUd8pocjUMr5/u64PJOD j3wJNkZ6h1rIevx2LmYwEflSlVoqH+X2RkxMPSoYYDprhW3puOYPnAjgm3FChDWMLjVP XRypTPBKrAUoWzWO1b5EAGKU1jSe8IuFfBzEgqOLm1sN2R/9ML3TelOCBquLcVzWRBVw GkAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=d85lqCspBYOiEahvyujgf0zWY50v14bxlk08GHck46o=; b=xAAF5FCD9IyVvQ5umiMAUeNAfQZMetohXSVIe8r9GxJlEOhHfbBlwNU4MidTAruBex tAN4hwPvEkw0zlH7/4OKrFDJi1i5AauP5oeDw5Wzp0LWo6OtWssDFCLEQFiwCA3V8H41 Tk4P7IQ+KbdiWOZT7wvZ7tkqhecx5+oA5bguPd5ll3ElC2afj539A0mkE7fz17a1wg5c JlgNDcsUEtE08xFI+GWj5H/p7NG0GJ1k/AXx+QhvavLFGk5W9O3RU+LjeIvYiLZ/ZSxU 6aZ67FxhVVaNcR6VjWaSuQUiqXFnQX4xhGgoDVIBFEUUlDTun1EDzL5nE4SAtqfaZugU esHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iLpRfCLh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:44 -0800 Message-Id: <20180124232625.30105-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 04/45] target/hppa: Define hardware exception types X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 39 +++++++++++++++++++++++++++---- linux-user/main.c | 26 ++++++++++++++++++--- target/hppa/helper.c | 61 ++++++++++++++++++++++++++++++++++-------------- target/hppa/mem_helper.c | 4 +++- target/hppa/op_helper.c | 6 ++--- target/hppa/translate.c | 8 +++---- 6 files changed, 111 insertions(+), 33 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index ea7e495408..d84af91860 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -40,11 +40,40 @@ #define MMU_USER_IDX 0 #define TARGET_INSN_START_EXTRA_WORDS 1 -#define EXCP_SYSCALL 1 -#define EXCP_SYSCALL_LWS 2 -#define EXCP_SIGSEGV 3 -#define EXCP_SIGILL 4 -#define EXCP_SIGFPE 5 +/* Hardware exceptions, interupts, faults, and traps. */ +#define EXCP_HPMC 1 /* high priority machine check */ +#define EXCP_POWER_FAIL 2 +#define EXCP_RC 3 /* recovery counter */ +#define EXCP_EXT_INTERRUPT 4 /* external interrupt */ +#define EXCP_LPMC 5 /* low priority machine check */ +#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ +#define EXCP_IMP 7 /* instruction memory protection trap */ +#define EXCP_ILL 8 /* illegal instruction trap */ +#define EXCP_BREAK 9 /* break instruction */ +#define EXCP_PRIV_OPR 10 /* privileged operation trap */ +#define EXCP_PRIV_REG 11 /* privileged register trap */ +#define EXCP_OVERFLOW 12 /* signed overflow trap */ +#define EXCP_COND 13 /* trap-on-condition */ +#define EXCP_ASSIST 14 /* assist exception trap */ +#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ +#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ +#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ +#define EXCP_DMP 18 /* data memory protection trap */ +#define EXCP_DMB 19 /* data memory break trap */ +#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ +#define EXCP_PAGE_REF 21 /* page reference trap */ +#define EXCP_ASSIST_EMU 22 /* assist emulation trap */ +#define EXCP_HPT 23 /* high-privilege transfer trap */ +#define EXCP_LPT 24 /* low-privilege transfer trap */ +#define EXCP_TB 25 /* taken branch trap */ +#define EXCP_DMAR 26 /* data memory access rights trap */ +#define EXCP_DMPI 27 /* data memory protection id trap */ +#define EXCP_UNALIGN 28 /* unaligned data reference trap */ +#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ + +/* Exceptions for linux-user emulation. */ +#define EXCP_SYSCALL 30 +#define EXCP_SYSCALL_LWS 31 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ #define PSW_I 0x00000001 diff --git a/linux-user/main.c b/linux-user/main.c index 450eb3ce65..42f4c66ce6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3768,21 +3768,41 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_SIGSEGV: + case EXCP_ITLB_MISS: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_IMP: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_PAGE_REF: + case EXCP_DMAR: + case EXCP_DMPI: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_ACCERR; info._sifields._sigfault._addr = env->ior; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_SIGILL: + case EXCP_UNALIGN: + info.si_signo = TARGET_SIGBUS; + info.si_errno = 0; + info.si_code = 0; + info._sifields._sigfault._addr = env->ior; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ILL: + case EXCP_PRIV_OPR: + case EXCP_PRIV_REG: info.si_signo = TARGET_SIGILL; info.si_errno = 0; info.si_code = TARGET_ILL_ILLOPN; info._sifields._sigfault._addr = env->iaoq_f; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_SIGFPE: + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; info.si_code = 0; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 4231ef3bff..6439179a0e 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -74,25 +74,52 @@ void hppa_cpu_do_interrupt(CPUState *cs) int i = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { + static const char * const names[] = { + [EXCP_HPMC] = "high priority machine check", + [EXCP_POWER_FAIL] = "power fail interrupt", + [EXCP_RC] = "recovery counter trap", + [EXCP_EXT_INTERRUPT] = "external interrupt", + [EXCP_LPMC] = "low priority machine check", + [EXCP_ITLB_MISS] = "instruction tlb miss fault", + [EXCP_IMP] = "instruction memory protection trap", + [EXCP_ILL] = "illegal instruction trap", + [EXCP_BREAK] = "break instruction trap", + [EXCP_PRIV_OPR] = "privileged operation trap", + [EXCP_PRIV_REG] = "privileged register trap", + [EXCP_OVERFLOW] = "overflow trap", + [EXCP_COND] = "conditional trap", + [EXCP_ASSIST] = "assist exception trap", + [EXCP_DTLB_MISS] = "data tlb miss fault", + [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss", + [EXCP_NA_DTLB_MISS] = "non-access data tlb miss", + [EXCP_DMP] = "data memory protection trap", + [EXCP_DMB] = "data memory break trap", + [EXCP_TLB_DIRTY] = "tlb dirty bit trap", + [EXCP_PAGE_REF] = "page reference trap", + [EXCP_ASSIST_EMU] = "assist emulation trap", + [EXCP_HPT] = "high-privilege transfer trap", + [EXCP_LPT] = "low-privilege transfer trap", + [EXCP_TB] = "taken branch trap", + [EXCP_DMAR] = "data memory access rights trap", + [EXCP_DMPI] = "data memory protection id trap", + [EXCP_UNALIGN] = "unaligned data reference trap", + [EXCP_PER_INTERRUPT] = "performance monitor interrupt", + [EXCP_SYSCALL] = "syscall", + [EXCP_SYSCALL_LWS] = "syscall-lws", + }; static int count; - const char *name = ""; - - switch (i) { - case EXCP_SYSCALL: - name = "syscall"; - break; - case EXCP_SIGSEGV: - name = "sigsegv"; - break; - case EXCP_SIGILL: - name = "sigill"; - break; - case EXCP_SIGFPE: - name = "sigfpe"; - break; + const char *name = NULL; + + if (i >= 0 && i < ARRAY_SIZE(names)) { + name = names[i]; + } + if (name) { + qemu_log("INT %6d: %s ia_f=" TARGET_FMT_lx "\n", + ++count, name, env->iaoq_f); + } else { + qemu_log("INT %6d: unknown %d ia_f=" TARGET_FMT_lx "\n", + ++count, i, env->iaoq_f); } - qemu_log("INT %6d: %s ia_f=" TARGET_FMT_lx "\n", - ++count, name, env->iaoq_f); } cs->exception_index = -1; } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index e0802bc935..2901f3e29c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,7 +29,9 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { HPPACPU *cpu = HPPA_CPU(cs); - cs->exception_index = EXCP_SIGSEGV; + /* ??? Test between data page fault and data memory protection trap, + which would affect si_code. */ + cs->exception_index = EXCP_DMP; cpu->env.ior = address; return 1; } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 9c7603588f..d6b86834c1 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -44,14 +44,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) { if (unlikely((target_long)cond < 0)) { - dynexcp(env, EXCP_SIGFPE, GETPC()); + dynexcp(env, EXCP_OVERFLOW, GETPC()); } } void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) { if (unlikely(cond)) { - dynexcp(env, EXCP_SIGFPE, GETPC()); + dynexcp(env, EXCP_COND, GETPC()); } } @@ -235,7 +235,7 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) env->fr[0] = (uint64_t)shadow << 32; if (hard_exp & shadow) { - dynexcp(env, EXCP_SIGFPE, ra); + dynexcp(env, EXCP_ASSIST, ra); } } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8e357cc60c..8d85ed9df3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -462,7 +462,7 @@ static DisasJumpType gen_excp(DisasContext *ctx, int exception) static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_SIGILL)); + return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -1578,7 +1578,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) switch (ctx->iaoq_f) { case 0x00: /* Null pointer call */ - gen_excp_1(EXCP_SIGSEGV); + gen_excp_1(EXCP_IMP); return DISAS_NORETURN; case 0xb0: /* LWS */ @@ -1597,7 +1597,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) default: do_sigill: - gen_excp_1(EXCP_SIGILL); + gen_excp_1(EXCP_ILL); return DISAS_NORETURN; } } @@ -1614,7 +1614,7 @@ static DisasJumpType trans_break(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_DEBUG)); + return nullify_end(ctx, gen_excp(ctx, EXCP_BREAK)); } static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, From patchwork Wed Jan 24 23:25:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125733 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp736367ljf; Wed, 24 Jan 2018 15:39:40 -0800 (PST) X-Google-Smtp-Source: AH8x225KTdFZs5SIPXJBWsj2Ch29OEjvKiWVJRj0r/uXeRTKALiFT9POLjTsAwFkUSvixeaofwSz X-Received: by 10.13.201.65 with SMTP id l62mr6702290ywd.331.1516837180366; Wed, 24 Jan 2018 15:39:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837180; cv=none; d=google.com; s=arc-20160816; b=F2rE0qjM8FZMHiGCCjzRGroHaJsTt3nkKqA3UfoR+wuqDU6qwJFwjefxU9DbIlShAf 0ZdeayF9pmKvqC1oCW5XZQOZ/1ZYsLpA+Wzt8AKa92PAHgIsRNDHZWlC6eKcb6+Dfu8X 3d76VpvmZlFkhOeo58BgmF5GFrgL/r3oq+EI4QI0yeOhljTj1yWy+XWEOxnGb3x9iRrb AYYKi4WCR4FTezo3DMx8q1gdsJWIfA9+8bB01f1nPpdU4vDBOqE6e7Z/fQvuoBJkoZXZ +QcpWBXOQcDG2eo18QO0VmIDF8V/JnCvOxITTIlkwXwDG6mzMlu9fETUucJEtdzxq2Xq Igng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=bZ7EKkQUfoBfunTKHhRsNTz16bT3SkwxXqAB/N1j7CA=; b=T8gzLLq/oh0mv6zCOYMFNpeEIPT1Yq/qjHzwvm+djnQdwbFKwmIi1Od6iOcWFnxxcf uISPQruOMo41BrSXqb7SAlrEiww4VFOyLzui+bBCLNud5BUzaET9eTLACumyJ8JlWm2D Ktcr7H4DcGf3nLCqDCDVVcrGDzokTuoIsFVycZSh6VOQDQxBA+lK0zHnvzjYBIm3Vmh1 7OtMlse93vftCD35NCQKmVN9cYpMeBOEzRX3xD7ibl7cbdIe55jDpeaaw0gHuMRrkupy j/rOntvn3ftNaAZTJIf7k92ODHULOWhQ14lYFDblnxuxplODJfVwtSrl5XFPVjslKEcW 7Spw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ji+u1oss; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.34 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:45 -0800 Message-Id: <20180124232625.30105-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22f Subject: [Qemu-devel] [PATCH v3 05/45] target/hppa: Split address size from register size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For system mode, we will need 64-bit virtual addresses even when we have 32-bit register sizes. Since the rest of QEMU equates TARGET_LONG_BITS with the address size, redefine everything related to register size in terms of a new TARGET_REGISTER_BITS. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 48 ++- target/hppa/helper.h | 26 +- target/hppa/gdbstub.c | 19 +- target/hppa/helper.c | 18 +- target/hppa/op_helper.c | 22 +- target/hppa/translate.c | 964 ++++++++++++++++++++++++++++++------------------ 6 files changed, 683 insertions(+), 414 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d84af91860..1524ef91b6 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,10 +23,10 @@ #include "qemu-common.h" #include "cpu-qom.h" -/* We only support hppa-linux-user at present, so 32-bit only. */ -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_LONG_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_REGISTER_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define CPUArchState struct CPUHPPAState @@ -123,17 +123,29 @@ typedef struct CPUHPPAState CPUHPPAState; +#if TARGET_REGISTER_BITS == 32 +typedef uint32_t target_ureg; +typedef int32_t target_sreg; +#define TREG_FMT_lx "%08"PRIx32 +#define TREG_FMT_ld "%"PRId32 +#else +typedef uint64_t target_ureg; +typedef int64_t target_sreg; +#define TREG_FMT_lx "%016"PRIx64 +#define TREG_FMT_ld "%"PRId64 +#endif + struct CPUHPPAState { - target_ulong gr[32]; + target_ureg gr[32]; uint64_t fr[32]; - target_ulong sar; - target_ulong cr26; - target_ulong cr27; + target_ureg sar; + target_ureg cr26; + target_ureg cr27; - target_long psw; /* All psw bits except the following: */ - target_ulong psw_n; /* boolean */ - target_long psw_v; /* in most significant bit */ + target_ureg psw; /* All psw bits except the following: */ + target_ureg psw_n; /* boolean */ + target_sreg psw_v; /* in most significant bit */ /* Splitting the carry-borrow field into the MSB and "the rest", allows * for "the rest" to be deleted when it is unused, but the MSB is in use. @@ -142,13 +154,13 @@ struct CPUHPPAState { * host has the appropriate add-with-carry insn to compute the msb). * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. */ - target_ulong psw_cb; /* in least significant bit of next nibble */ - target_ulong psw_cb_msb; /* boolean */ + target_ureg psw_cb; /* in least significant bit of next nibble */ + target_ureg psw_cb_msb; /* boolean */ - target_ulong iaoq_f; /* front */ - target_ulong iaoq_b; /* back, aka next instruction */ + target_ureg iaoq_f; /* front */ + target_ureg iaoq_b; /* back, aka next instruction */ - target_ulong ior; /* interrupt offset register */ + target_ureg ior; /* interrupt offset register */ uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; @@ -201,8 +213,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, *pflags = env->psw_n; } -target_ulong cpu_hppa_get_psw(CPUHPPAState *env); -void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); +target_ureg cpu_hppa_get_psw(CPUHPPAState *env); +void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); void cpu_hppa_loaded_fr0(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 0a6b900555..c720de523b 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,14 +1,24 @@ +#if TARGET_REGISTER_BITS == 64 +# define dh_alias_tr i64 +# define dh_is_64bit_tr 1 +#else +# define dh_alias_tr i32 +# define dh_is_64bit_tr 0 +#endif +#define dh_ctype_tr target_ureg +#define dh_is_signed_tr 0 + DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr) +DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tr) -DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tr, tl) +DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tr, tl) DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index c37a56f238..228d282fe9 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -26,7 +26,7 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - target_ulong val; + target_ureg val; switch (n) { case 0: @@ -61,14 +61,25 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) } break; } - return gdb_get_regl(mem_buf, val); + + if (TARGET_REGISTER_BITS == 64) { + return gdb_get_reg64(mem_buf, val); + } else { + return gdb_get_reg32(mem_buf, val); + } } int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - target_ulong val = ldtul_p(mem_buf); + target_ureg val; + + if (TARGET_REGISTER_BITS == 64) { + val = ldq_p(mem_buf); + } else { + val = ldl_p(mem_buf); + } switch (n) { case 0: @@ -108,5 +119,5 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } break; } - return sizeof(target_ulong); + return sizeof(target_ureg); } diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 6439179a0e..b6521f61fc 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -24,9 +24,9 @@ #include "fpu/softfloat.h" #include "exec/helper-proto.h" -target_ulong cpu_hppa_get_psw(CPUHPPAState *env) +target_ureg cpu_hppa_get_psw(CPUHPPAState *env) { - target_ulong psw; + target_ureg psw; /* Fold carry bits down to 8 consecutive bits. */ /* ??? Needs tweaking for hppa64. */ @@ -48,9 +48,9 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) return psw; } -void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) +void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) { - target_ulong cb = 0; + target_ureg cb = 0; env->psw = psw & ~(PSW_N | PSW_V | PSW_CB); env->psw_n = (psw / PSW_N) & 1; @@ -135,13 +135,13 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - target_ulong psw = cpu_hppa_get_psw(env); - target_ulong psw_cb; + target_ureg psw = cpu_hppa_get_psw(env); + target_ureg psw_cb; char psw_c[20]; int i; cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", - env->iaoq_f, env->iaoq_b); + (target_ulong)env->iaoq_f, (target_ulong)env->iaoq_b); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); @@ -164,11 +164,11 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, psw_c[18] = '\0'; psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); - cpu_fprintf(f, "PSW " TARGET_FMT_lx " CB " TARGET_FMT_lx " %s\n", + cpu_fprintf(f, "PSW " TREG_FMT_lx " CB " TREG_FMT_lx " %s\n", psw, psw_cb, psw_c); for (i = 0; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); + cpu_fprintf(f, "GR%02d " TREG_FMT_lx " ", i, env->gr[i]); if ((i % 4) == 3) { cpu_fprintf(f, "\n"); } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index d6b86834c1..479bfc0fdf 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -41,14 +41,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } -void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) +void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) { - if (unlikely((target_long)cond < 0)) { + if (unlikely((target_sreg)cond < 0)) { dynexcp(env, EXCP_OVERFLOW, GETPC()); } } -void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) +void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) { if (unlikely(cond)) { dynexcp(env, EXCP_COND, GETPC()); @@ -77,7 +77,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val, #endif } -static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val, +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val, bool parallel) { uintptr_t ra = GETPC(); @@ -104,18 +104,18 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val, } } -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_b(env, addr, val, false); } void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, - target_ulong val) + target_ureg val) { do_stby_b(env, addr, val, true); } -static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val, +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val, bool parallel) { uintptr_t ra = GETPC(); @@ -146,18 +146,18 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val, } } -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_e(env, addr, val, false); } void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, - target_ulong val) + target_ureg val) { do_stby_e(env, addr, val, true); } -target_ulong HELPER(probe_r)(target_ulong addr) +target_ureg HELPER(probe_r)(target_ulong addr) { #ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_READ); @@ -166,7 +166,7 @@ target_ulong HELPER(probe_r)(target_ulong addr) #endif } -target_ulong HELPER(probe_w)(target_ulong addr) +target_ureg HELPER(probe_w)(target_ulong addr) { #ifdef CONFIG_USER_ONLY return page_check_range(addr, 1, PAGE_WRITE); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8d85ed9df3..dd96147bf1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -30,9 +30,239 @@ #include "trace-tcg.h" #include "exec/log.h" +/* Since we have a distinction between register size and address size, + we need to redefine all of these. */ + +#undef TCGv +#undef tcg_temp_new +#undef tcg_global_reg_new +#undef tcg_global_mem_new +#undef tcg_temp_local_new +#undef tcg_temp_free + +#if TARGET_LONG_BITS == 64 +#define TCGv_tl TCGv_i64 +#define tcg_temp_new_tl tcg_temp_new_i64 +#define tcg_temp_free_tl tcg_temp_free_i64 +#if TARGET_REGISTER_BITS == 64 +#define tcg_gen_extu_reg_tl tcg_gen_mov_i64 +#else +#define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 +#endif +#else +#define TCGv_tl TCGv_i32 +#define tcg_temp_new_tl tcg_temp_new_i32 +#define tcg_temp_free_tl tcg_temp_free_i32 +#define tcg_gen_extu_reg_tl tcg_gen_mov_i32 +#endif + +#if TARGET_REGISTER_BITS == 64 +#define TCGv_reg TCGv_i64 + +#define tcg_temp_new tcg_temp_new_i64 +#define tcg_global_reg_new tcg_global_reg_new_i64 +#define tcg_global_mem_new tcg_global_mem_new_i64 +#define tcg_temp_local_new tcg_temp_local_new_i64 +#define tcg_temp_free tcg_temp_free_i64 + +#define tcg_gen_movi_reg tcg_gen_movi_i64 +#define tcg_gen_mov_reg tcg_gen_mov_i64 +#define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 +#define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 +#define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 +#define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 +#define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 +#define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 +#define tcg_gen_ld_reg tcg_gen_ld_i64 +#define tcg_gen_st8_reg tcg_gen_st8_i64 +#define tcg_gen_st16_reg tcg_gen_st16_i64 +#define tcg_gen_st32_reg tcg_gen_st32_i64 +#define tcg_gen_st_reg tcg_gen_st_i64 +#define tcg_gen_add_reg tcg_gen_add_i64 +#define tcg_gen_addi_reg tcg_gen_addi_i64 +#define tcg_gen_sub_reg tcg_gen_sub_i64 +#define tcg_gen_neg_reg tcg_gen_neg_i64 +#define tcg_gen_subfi_reg tcg_gen_subfi_i64 +#define tcg_gen_subi_reg tcg_gen_subi_i64 +#define tcg_gen_and_reg tcg_gen_and_i64 +#define tcg_gen_andi_reg tcg_gen_andi_i64 +#define tcg_gen_or_reg tcg_gen_or_i64 +#define tcg_gen_ori_reg tcg_gen_ori_i64 +#define tcg_gen_xor_reg tcg_gen_xor_i64 +#define tcg_gen_xori_reg tcg_gen_xori_i64 +#define tcg_gen_not_reg tcg_gen_not_i64 +#define tcg_gen_shl_reg tcg_gen_shl_i64 +#define tcg_gen_shli_reg tcg_gen_shli_i64 +#define tcg_gen_shr_reg tcg_gen_shr_i64 +#define tcg_gen_shri_reg tcg_gen_shri_i64 +#define tcg_gen_sar_reg tcg_gen_sar_i64 +#define tcg_gen_sari_reg tcg_gen_sari_i64 +#define tcg_gen_brcond_reg tcg_gen_brcond_i64 +#define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 +#define tcg_gen_setcond_reg tcg_gen_setcond_i64 +#define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 +#define tcg_gen_mul_reg tcg_gen_mul_i64 +#define tcg_gen_muli_reg tcg_gen_muli_i64 +#define tcg_gen_div_reg tcg_gen_div_i64 +#define tcg_gen_rem_reg tcg_gen_rem_i64 +#define tcg_gen_divu_reg tcg_gen_divu_i64 +#define tcg_gen_remu_reg tcg_gen_remu_i64 +#define tcg_gen_discard_reg tcg_gen_discard_i64 +#define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 +#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 +#define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 +#define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 +#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 +#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 +#define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 +#define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 +#define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 +#define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 +#define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 +#define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 +#define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 +#define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 +#define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 +#define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 +#define tcg_gen_andc_reg tcg_gen_andc_i64 +#define tcg_gen_eqv_reg tcg_gen_eqv_i64 +#define tcg_gen_nand_reg tcg_gen_nand_i64 +#define tcg_gen_nor_reg tcg_gen_nor_i64 +#define tcg_gen_orc_reg tcg_gen_orc_i64 +#define tcg_gen_clz_reg tcg_gen_clz_i64 +#define tcg_gen_ctz_reg tcg_gen_ctz_i64 +#define tcg_gen_clzi_reg tcg_gen_clzi_i64 +#define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 +#define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 +#define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 +#define tcg_gen_rotl_reg tcg_gen_rotl_i64 +#define tcg_gen_rotli_reg tcg_gen_rotli_i64 +#define tcg_gen_rotr_reg tcg_gen_rotr_i64 +#define tcg_gen_rotri_reg tcg_gen_rotri_i64 +#define tcg_gen_deposit_reg tcg_gen_deposit_i64 +#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 +#define tcg_gen_extract_reg tcg_gen_extract_i64 +#define tcg_gen_sextract_reg tcg_gen_sextract_i64 +#define tcg_const_reg tcg_const_i64 +#define tcg_const_local_reg tcg_const_local_i64 +#define tcg_gen_movcond_reg tcg_gen_movcond_i64 +#define tcg_gen_add2_reg tcg_gen_add2_i64 +#define tcg_gen_sub2_reg tcg_gen_sub2_i64 +#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 +#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 +#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 +#if UINTPTR_MAX == UINT32_MAX +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_trunc_i64_i32(TCGV_PTR_TO_NAT(p), r) +#else +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_mov_i64(TCGV_PTR_TO_NAT(p), r) +#endif +#else +#define TCGv_reg TCGv_i32 +#define tcg_temp_new tcg_temp_new_i32 +#define tcg_global_reg_new tcg_global_reg_new_i32 +#define tcg_global_mem_new tcg_global_mem_new_i32 +#define tcg_temp_local_new tcg_temp_local_new_i32 +#define tcg_temp_free tcg_temp_free_i32 + +#define tcg_gen_movi_reg tcg_gen_movi_i32 +#define tcg_gen_mov_reg tcg_gen_mov_i32 +#define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 +#define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 +#define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 +#define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 +#define tcg_gen_ld32u_reg tcg_gen_ld_i32 +#define tcg_gen_ld32s_reg tcg_gen_ld_i32 +#define tcg_gen_ld_reg tcg_gen_ld_i32 +#define tcg_gen_st8_reg tcg_gen_st8_i32 +#define tcg_gen_st16_reg tcg_gen_st16_i32 +#define tcg_gen_st32_reg tcg_gen_st32_i32 +#define tcg_gen_st_reg tcg_gen_st_i32 +#define tcg_gen_add_reg tcg_gen_add_i32 +#define tcg_gen_addi_reg tcg_gen_addi_i32 +#define tcg_gen_sub_reg tcg_gen_sub_i32 +#define tcg_gen_neg_reg tcg_gen_neg_i32 +#define tcg_gen_subfi_reg tcg_gen_subfi_i32 +#define tcg_gen_subi_reg tcg_gen_subi_i32 +#define tcg_gen_and_reg tcg_gen_and_i32 +#define tcg_gen_andi_reg tcg_gen_andi_i32 +#define tcg_gen_or_reg tcg_gen_or_i32 +#define tcg_gen_ori_reg tcg_gen_ori_i32 +#define tcg_gen_xor_reg tcg_gen_xor_i32 +#define tcg_gen_xori_reg tcg_gen_xori_i32 +#define tcg_gen_not_reg tcg_gen_not_i32 +#define tcg_gen_shl_reg tcg_gen_shl_i32 +#define tcg_gen_shli_reg tcg_gen_shli_i32 +#define tcg_gen_shr_reg tcg_gen_shr_i32 +#define tcg_gen_shri_reg tcg_gen_shri_i32 +#define tcg_gen_sar_reg tcg_gen_sar_i32 +#define tcg_gen_sari_reg tcg_gen_sari_i32 +#define tcg_gen_brcond_reg tcg_gen_brcond_i32 +#define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 +#define tcg_gen_setcond_reg tcg_gen_setcond_i32 +#define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 +#define tcg_gen_mul_reg tcg_gen_mul_i32 +#define tcg_gen_muli_reg tcg_gen_muli_i32 +#define tcg_gen_div_reg tcg_gen_div_i32 +#define tcg_gen_rem_reg tcg_gen_rem_i32 +#define tcg_gen_divu_reg tcg_gen_divu_i32 +#define tcg_gen_remu_reg tcg_gen_remu_i32 +#define tcg_gen_discard_reg tcg_gen_discard_i32 +#define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 +#define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 +#define tcg_gen_extu_i32_reg tcg_gen_mov_i32 +#define tcg_gen_ext_i32_reg tcg_gen_mov_i32 +#define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 +#define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 +#define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 +#define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 +#define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 +#define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 +#define tcg_gen_ext32u_reg tcg_gen_mov_i32 +#define tcg_gen_ext32s_reg tcg_gen_mov_i32 +#define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 +#define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 +#define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 +#define tcg_gen_andc_reg tcg_gen_andc_i32 +#define tcg_gen_eqv_reg tcg_gen_eqv_i32 +#define tcg_gen_nand_reg tcg_gen_nand_i32 +#define tcg_gen_nor_reg tcg_gen_nor_i32 +#define tcg_gen_orc_reg tcg_gen_orc_i32 +#define tcg_gen_clz_reg tcg_gen_clz_i32 +#define tcg_gen_ctz_reg tcg_gen_ctz_i32 +#define tcg_gen_clzi_reg tcg_gen_clzi_i32 +#define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 +#define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 +#define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 +#define tcg_gen_rotl_reg tcg_gen_rotl_i32 +#define tcg_gen_rotli_reg tcg_gen_rotli_i32 +#define tcg_gen_rotr_reg tcg_gen_rotr_i32 +#define tcg_gen_rotri_reg tcg_gen_rotri_i32 +#define tcg_gen_deposit_reg tcg_gen_deposit_i32 +#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 +#define tcg_gen_extract_reg tcg_gen_extract_i32 +#define tcg_gen_sextract_reg tcg_gen_sextract_i32 +#define tcg_const_reg tcg_const_i32 +#define tcg_const_local_reg tcg_const_local_i32 +#define tcg_gen_movcond_reg tcg_gen_movcond_i32 +#define tcg_gen_add2_reg tcg_gen_add2_i32 +#define tcg_gen_sub2_reg tcg_gen_sub2_i32 +#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 +#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 +#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 +#if UINTPTR_MAX == UINT32_MAX +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_mov_i32(TCGV_PTR_TO_NAT(p), r) +#else +# define tcg_gen_trunc_reg_ptr(p, r) \ + tcg_gen_extu_i32_i64(TCGV_PTR_TO_NAT(p), r) +#endif +#endif /* TARGET_REGISTER_BITS */ + typedef struct DisasCond { TCGCond c; - TCGv a0, a1; + TCGv_reg a0, a1; bool a0_is_n; bool a1_is_0; } DisasCond; @@ -41,13 +271,13 @@ typedef struct DisasContext { DisasContextBase base; CPUState *cs; - target_ulong iaoq_f; - target_ulong iaoq_b; - target_ulong iaoq_n; - TCGv iaoq_n_var; + target_ureg iaoq_f; + target_ureg iaoq_b; + target_ureg iaoq_n; + TCGv_reg iaoq_n_var; int ntemps; - TCGv temps[8]; + TCGv_reg temps[8]; DisasCond null_cond; TCGLabel *null_lab; @@ -72,7 +302,7 @@ typedef struct DisasInsn { DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, const struct DisasInsn *f); union { - void (*ttt)(TCGv, TCGv, TCGv); + void (*ttt)(TCGv_reg, TCGv_reg, TCGv_reg); void (*weww)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32); void (*dedd)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64); void (*wew)(TCGv_i32, TCGv_env, TCGv_i32); @@ -83,16 +313,16 @@ typedef struct DisasInsn { } DisasInsn; /* global register indexes */ -static TCGv cpu_gr[32]; -static TCGv cpu_iaoq_f; -static TCGv cpu_iaoq_b; -static TCGv cpu_sar; -static TCGv cpu_psw_n; -static TCGv cpu_psw_v; -static TCGv cpu_psw_cb; -static TCGv cpu_psw_cb_msb; -static TCGv cpu_cr26; -static TCGv cpu_cr27; +static TCGv_reg cpu_gr[32]; +static TCGv_reg cpu_iaoq_f; +static TCGv_reg cpu_iaoq_b; +static TCGv_reg cpu_sar; +static TCGv_reg cpu_psw_n; +static TCGv_reg cpu_psw_v; +static TCGv_reg cpu_psw_cb; +static TCGv_reg cpu_psw_cb_msb; +static TCGv_reg cpu_cr26; +static TCGv_reg cpu_cr27; #include "exec/gen-icount.h" @@ -100,7 +330,7 @@ void hppa_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } - typedef struct { TCGv *var; const char *name; int ofs; } GlobalVar; + typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] = { DEF_VAR(sar), DEF_VAR(cr26), @@ -158,26 +388,26 @@ static DisasCond cond_make_n(void) }; } -static DisasCond cond_make_0(TCGCond c, TCGv a0) +static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) { DisasCond r = { .c = c, .a1 = NULL, .a1_is_0 = true }; assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); r.a0 = tcg_temp_new(); - tcg_gen_mov_tl(r.a0, a0); + tcg_gen_mov_reg(r.a0, a0); return r; } -static DisasCond cond_make(TCGCond c, TCGv a0, TCGv a1) +static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) { DisasCond r = { .c = c }; assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); r.a0 = tcg_temp_new(); - tcg_gen_mov_tl(r.a0, a0); + tcg_gen_mov_reg(r.a0, a0); r.a1 = tcg_temp_new(); - tcg_gen_mov_tl(r.a1, a1); + tcg_gen_mov_reg(r.a1, a1); return r; } @@ -186,7 +416,7 @@ static void cond_prep(DisasCond *cond) { if (cond->a1_is_0) { cond->a1_is_0 = false; - cond->a1 = tcg_const_tl(0); + cond->a1 = tcg_const_reg(0); } } @@ -213,32 +443,32 @@ static void cond_free(DisasCond *cond) } } -static TCGv get_temp(DisasContext *ctx) +static TCGv_reg get_temp(DisasContext *ctx) { unsigned i = ctx->ntemps++; g_assert(i < ARRAY_SIZE(ctx->temps)); return ctx->temps[i] = tcg_temp_new(); } -static TCGv load_const(DisasContext *ctx, target_long v) +static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { - TCGv t = get_temp(ctx); - tcg_gen_movi_tl(t, v); + TCGv_reg t = get_temp(ctx); + tcg_gen_movi_reg(t, v); return t; } -static TCGv load_gpr(DisasContext *ctx, unsigned reg) +static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) { if (reg == 0) { - TCGv t = get_temp(ctx); - tcg_gen_movi_tl(t, 0); + TCGv_reg t = get_temp(ctx); + tcg_gen_movi_reg(t, 0); return t; } else { return cpu_gr[reg]; } } -static TCGv dest_gpr(DisasContext *ctx, unsigned reg) +static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) { if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { return get_temp(ctx); @@ -247,18 +477,18 @@ static TCGv dest_gpr(DisasContext *ctx, unsigned reg) } } -static void save_or_nullify(DisasContext *ctx, TCGv dest, TCGv t) +static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) { if (ctx->null_cond.c != TCG_COND_NEVER) { cond_prep(&ctx->null_cond); - tcg_gen_movcond_tl(ctx->null_cond.c, dest, ctx->null_cond.a0, + tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, ctx->null_cond.a1, dest, t); } else { - tcg_gen_mov_tl(dest, t); + tcg_gen_mov_reg(dest, t); } } -static void save_gpr(DisasContext *ctx, unsigned reg, TCGv t) +static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) { if (reg != 0) { save_or_nullify(ctx, cpu_gr[reg], t); @@ -350,17 +580,17 @@ static void nullify_over(DisasContext *ctx) if (ctx->null_cond.a0_is_n) { ctx->null_cond.a0_is_n = false; ctx->null_cond.a0 = tcg_temp_new(); - tcg_gen_mov_tl(ctx->null_cond.a0, cpu_psw_n); + tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); } /* ... we clear it before branching over the implementation, so that (1) it's clear after nullifying this insn and (2) if this insn nullifies the next, PSW[N] is valid. */ if (ctx->psw_n_nonzero) { ctx->psw_n_nonzero = false; - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); } - tcg_gen_brcond_tl(ctx->null_cond.c, ctx->null_cond.a0, + tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); cond_free(&ctx->null_cond); } @@ -371,13 +601,13 @@ static void nullify_save(DisasContext *ctx) { if (ctx->null_cond.c == TCG_COND_NEVER) { if (ctx->psw_n_nonzero) { - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); } return; } if (!ctx->null_cond.a0_is_n) { cond_prep(&ctx->null_cond); - tcg_gen_setcond_tl(ctx->null_cond.c, cpu_psw_n, + tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero = true; } @@ -390,7 +620,7 @@ static void nullify_save(DisasContext *ctx) static void nullify_set(DisasContext *ctx, bool x) { if (ctx->psw_n_nonzero || x) { - tcg_gen_movi_tl(cpu_psw_n, x); + tcg_gen_movi_reg(cpu_psw_n, x); } } @@ -429,16 +659,16 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) return status; } -static void copy_iaoq_entry(TCGv dest, target_ulong ival, TCGv vval) +static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) { if (unlikely(ival == -1)) { - tcg_gen_mov_tl(dest, vval); + tcg_gen_mov_reg(dest, vval); } else { - tcg_gen_movi_tl(dest, ival); + tcg_gen_movi_reg(dest, ival); } } -static inline target_ulong iaoq_dest(DisasContext *ctx, target_long disp) +static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) { return ctx->iaoq_f + disp + 8; } @@ -465,7 +695,7 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } -static bool use_goto_tb(DisasContext *ctx, target_ulong dest) +static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ if ((tb_cflags(ctx->base.tb) & CF_LAST_IO) || ctx->base.singlestep_enabled) { @@ -485,12 +715,12 @@ static bool use_nullify_skip(DisasContext *ctx) } static void gen_goto_tb(DisasContext *ctx, int which, - target_ulong f, target_ulong b) + target_ureg f, target_ureg b) { if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { tcg_gen_goto_tb(which); - tcg_gen_movi_tl(cpu_iaoq_f, f); - tcg_gen_movi_tl(cpu_iaoq_b, b); + tcg_gen_movi_reg(cpu_iaoq_f, f); + tcg_gen_movi_reg(cpu_iaoq_b, b); tcg_gen_exit_tb((uintptr_t)ctx->base.tb + which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); @@ -505,9 +735,9 @@ static void gen_goto_tb(DisasContext *ctx, int which, /* PA has a habit of taking the LSB of a field and using that as the sign, with the rest of the field becoming the least significant bits. */ -static target_long low_sextract(uint32_t val, int pos, int len) +static target_sreg low_sextract(uint32_t val, int pos, int len) { - target_ulong x = -(target_ulong)extract32(val, pos, 1); + target_ureg x = -(target_ureg)extract32(val, pos, 1); x = (x << (len - 1)) | extract32(val, pos + 1, len - 1); return x; } @@ -541,15 +771,15 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } -static target_long assemble_12(uint32_t insn) +static target_sreg assemble_12(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 1) | extract32(insn, 2, 1); x = (x << 10) | extract32(insn, 3, 10); return x; } -static target_long assemble_16(uint32_t insn) +static target_sreg assemble_16(uint32_t insn) { /* Take the name from PA2.0, which produces a 16-bit number only with wide mode; otherwise a 14-bit number. Since we don't @@ -557,28 +787,28 @@ static target_long assemble_16(uint32_t insn) return low_sextract(insn, 0, 14); } -static target_long assemble_16a(uint32_t insn) +static target_sreg assemble_16a(uint32_t insn) { /* Take the name from PA2.0, which produces a 14-bit shifted number only with wide mode; otherwise a 12-bit shifted number. Since we don't implement wide mode, this is always the 12-bit number. */ - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 11) | extract32(insn, 2, 11); return x << 2; } -static target_long assemble_17(uint32_t insn) +static target_sreg assemble_17(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 5) | extract32(insn, 16, 5); x = (x << 1) | extract32(insn, 2, 1); x = (x << 10) | extract32(insn, 3, 10); return x << 2; } -static target_long assemble_21(uint32_t insn) +static target_sreg assemble_21(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 11) | extract32(insn, 1, 11); x = (x << 2) | extract32(insn, 14, 2); x = (x << 5) | extract32(insn, 16, 5); @@ -586,9 +816,9 @@ static target_long assemble_21(uint32_t insn) return x << 11; } -static target_long assemble_22(uint32_t insn) +static target_sreg assemble_22(uint32_t insn) { - target_ulong x = -(target_ulong)(insn & 1); + target_ureg x = -(target_ureg)(insn & 1); x = (x << 10) | extract32(insn, 16, 10); x = (x << 1) | extract32(insn, 2, 1); x = (x << 10) | extract32(insn, 3, 10); @@ -602,10 +832,11 @@ static target_long assemble_22(uint32_t insn) as a whole it would appear that these relations are similar to what a traditional NZCV set of flags would produce. */ -static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) +static DisasCond do_cond(unsigned cf, TCGv_reg res, + TCGv_reg cb_msb, TCGv_reg sv) { DisasCond cond; - TCGv tmp; + TCGv_reg tmp; switch (cf >> 1) { case 0: /* Never / TR */ @@ -625,8 +856,8 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp = tcg_temp_new(); - tcg_gen_neg_tl(tmp, cb_msb); - tcg_gen_and_tl(tmp, tmp, res); + tcg_gen_neg_reg(tmp, cb_msb); + tcg_gen_and_reg(tmp, tmp, res); cond = cond_make_0(TCG_COND_EQ, tmp); tcg_temp_free(tmp); break; @@ -635,7 +866,7 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) break; case 7: /* OD / EV */ tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, res, 1); + tcg_gen_andi_reg(tmp, res, 1); cond = cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; @@ -653,7 +884,8 @@ static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv) can use the inputs directly. This can allow other computation to be deleted as unused. */ -static DisasCond do_sub_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2, TCGv sv) +static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) { DisasCond cond; @@ -686,7 +918,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2, TCGv sv) /* Similar, but for logicals, where the carry and overflow bits are not computed, and use of them is undefined. */ -static DisasCond do_log_cond(unsigned cf, TCGv res) +static DisasCond do_log_cond(unsigned cf, TCGv_reg res) { switch (cf >> 1) { case 4: case 5: case 6: @@ -698,7 +930,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv res) /* Similar, but for shift/extract/deposit conditions. */ -static DisasCond do_sed_cond(unsigned orig, TCGv res) +static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) { unsigned c, f; @@ -716,10 +948,11 @@ static DisasCond do_sed_cond(unsigned orig, TCGv res) /* Similar, but for unit conditions. */ -static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) +static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2) { DisasCond cond; - TCGv tmp, cb = NULL; + TCGv_reg tmp, cb = NULL; if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not @@ -728,10 +961,10 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) */ cb = tcg_temp_new(); tmp = tcg_temp_new(); - tcg_gen_or_tl(cb, in1, in2); - tcg_gen_and_tl(tmp, in1, in2); - tcg_gen_andc_tl(cb, cb, res); - tcg_gen_or_tl(cb, cb, tmp); + tcg_gen_or_reg(cb, in1, in2); + tcg_gen_and_reg(tmp, in1, in2); + tcg_gen_andc_reg(cb, cb, res); + tcg_gen_or_reg(cb, cb, tmp); tcg_temp_free(tmp); } @@ -747,34 +980,34 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ tmp = tcg_temp_new(); - tcg_gen_subi_tl(tmp, res, 0x01010101u); - tcg_gen_andc_tl(tmp, tmp, res); - tcg_gen_andi_tl(tmp, tmp, 0x80808080u); + tcg_gen_subi_reg(tmp, res, 0x01010101u); + tcg_gen_andc_reg(tmp, tmp, res); + tcg_gen_andi_reg(tmp, tmp, 0x80808080u); cond = cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; case 3: /* SHZ / NHZ */ tmp = tcg_temp_new(); - tcg_gen_subi_tl(tmp, res, 0x00010001u); - tcg_gen_andc_tl(tmp, tmp, res); - tcg_gen_andi_tl(tmp, tmp, 0x80008000u); + tcg_gen_subi_reg(tmp, res, 0x00010001u); + tcg_gen_andc_reg(tmp, tmp, res); + tcg_gen_andi_reg(tmp, tmp, 0x80008000u); cond = cond_make_0(TCG_COND_NE, tmp); tcg_temp_free(tmp); break; case 4: /* SDC / NDC */ - tcg_gen_andi_tl(cb, cb, 0x88888888u); + tcg_gen_andi_reg(cb, cb, 0x88888888u); cond = cond_make_0(TCG_COND_NE, cb); break; case 6: /* SBC / NBC */ - tcg_gen_andi_tl(cb, cb, 0x80808080u); + tcg_gen_andi_reg(cb, cb, 0x80808080u); cond = cond_make_0(TCG_COND_NE, cb); break; case 7: /* SHC / NHC */ - tcg_gen_andi_tl(cb, cb, 0x80008000u); + tcg_gen_andi_reg(cb, cb, 0x80008000u); cond = cond_make_0(TCG_COND_NE, cb); break; @@ -792,38 +1025,40 @@ static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) } /* Compute signed overflow for addition. */ -static TCGv do_add_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2) +static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2) { - TCGv sv = get_temp(ctx); - TCGv tmp = tcg_temp_new(); + TCGv_reg sv = get_temp(ctx); + TCGv_reg tmp = tcg_temp_new(); - tcg_gen_xor_tl(sv, res, in1); - tcg_gen_xor_tl(tmp, in1, in2); - tcg_gen_andc_tl(sv, sv, tmp); + tcg_gen_xor_reg(sv, res, in1); + tcg_gen_xor_reg(tmp, in1, in2); + tcg_gen_andc_reg(sv, sv, tmp); tcg_temp_free(tmp); return sv; } /* Compute signed overflow for subtraction. */ -static TCGv do_sub_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2) +static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, + TCGv_reg in1, TCGv_reg in2) { - TCGv sv = get_temp(ctx); - TCGv tmp = tcg_temp_new(); + TCGv_reg sv = get_temp(ctx); + TCGv_reg tmp = tcg_temp_new(); - tcg_gen_xor_tl(sv, res, in1); - tcg_gen_xor_tl(tmp, in1, in2); - tcg_gen_and_tl(sv, sv, tmp); + tcg_gen_xor_reg(sv, res, in1); + tcg_gen_xor_reg(tmp, in1, in2); + tcg_gen_and_reg(sv, sv, tmp); tcg_temp_free(tmp); return sv; } -static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, - unsigned shift, bool is_l, bool is_tsv, bool is_tc, - bool is_c, unsigned cf) +static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned shift, bool is_l, + bool is_tsv, bool is_tc, bool is_c, unsigned cf) { - TCGv dest, cb, cb_msb, sv, tmp; + TCGv_reg dest, cb, cb_msb, sv, tmp; unsigned c = cf >> 1; DisasCond cond; @@ -833,27 +1068,27 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, if (shift) { tmp = get_temp(ctx); - tcg_gen_shli_tl(tmp, in1, shift); + tcg_gen_shli_reg(tmp, in1, shift); in1 = tmp; } if (!is_l || c == 4 || c == 5) { - TCGv zero = tcg_const_tl(0); + TCGv_reg zero = tcg_const_reg(0); cb_msb = get_temp(ctx); - tcg_gen_add2_tl(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { - tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); } tcg_temp_free(zero); if (!is_l) { cb = get_temp(ctx); - tcg_gen_xor_tl(cb, in1, in2); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_xor_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); } } else { - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); if (is_c) { - tcg_gen_add_tl(dest, dest, cpu_psw_cb_msb); + tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); } } @@ -872,7 +1107,7 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, if (is_tc) { cond_prep(&cond); tmp = tcg_temp_new(); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -891,10 +1126,11 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } -static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, - bool is_tsv, bool is_b, bool is_tc, unsigned cf) +static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, bool is_tsv, bool is_b, + bool is_tc, unsigned cf) { - TCGv dest, sv, cb, cb_msb, zero, tmp; + TCGv_reg dest, sv, cb, cb_msb, zero, tmp; unsigned c = cf >> 1; DisasCond cond; @@ -902,21 +1138,21 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, cb = tcg_temp_new(); cb_msb = tcg_temp_new(); - zero = tcg_const_tl(0); + zero = tcg_const_reg(0); if (is_b) { /* DEST,C = IN1 + ~IN2 + C. */ - tcg_gen_not_tl(cb, in2); - tcg_gen_add2_tl(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); - tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cb, zero); - tcg_gen_xor_tl(cb, cb, in1); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_not_reg(cb, in2); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_xor_reg(cb, cb, in1); + tcg_gen_xor_reg(cb, cb, dest); } else { /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer operations by seeding the high word with 1 and subtracting. */ - tcg_gen_movi_tl(cb_msb, 1); - tcg_gen_sub2_tl(dest, cb_msb, in1, cb_msb, in2, zero); - tcg_gen_eqv_tl(cb, in1, in2); - tcg_gen_xor_tl(cb, cb, dest); + tcg_gen_movi_reg(cb_msb, 1); + tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); + tcg_gen_eqv_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); } tcg_temp_free(zero); @@ -940,7 +1176,7 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, if (is_tc) { cond_prep(&cond); tmp = tcg_temp_new(); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -957,14 +1193,14 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } -static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf) +static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned cf) { - TCGv dest, sv; + TCGv_reg dest, sv; DisasCond cond; dest = tcg_temp_new(); - tcg_gen_sub_tl(dest, in1, in2); + tcg_gen_sub_reg(dest, in1, in2); /* Compute signed overflow if required. */ sv = NULL; @@ -976,7 +1212,7 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, cond = do_sub_cond(cf, dest, in1, in2, sv); /* Clear. */ - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); tcg_temp_free(dest); @@ -986,10 +1222,11 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, return DISAS_NEXT; } -static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, - unsigned cf, void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned cf, + void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { - TCGv dest = dest_gpr(ctx, rt); + TCGv_reg dest = dest_gpr(ctx, rt); /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1003,11 +1240,11 @@ static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, return DISAS_NEXT; } -static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf, bool is_tc, - void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, + TCGv_reg in2, unsigned cf, bool is_tc, + void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { - TCGv dest; + TCGv_reg dest; DisasCond cond; if (cf == 0) { @@ -1022,9 +1259,9 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, cond = do_unit_cond(cf, dest, in1, in2); if (is_tc) { - TCGv tmp = tcg_temp_new(); + TCGv_reg tmp = tcg_temp_new(); cond_prep(&cond); - tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); } @@ -1042,10 +1279,10 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, * = 0 for no base register update. */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1055,10 +1292,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } if (modify == 0) { @@ -1072,10 +1309,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, } static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1085,10 +1322,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } if (modify == 0) { @@ -1102,10 +1339,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, } static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1115,10 +1352,10 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); @@ -1130,10 +1367,10 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, } static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv addr, base; + TCGv_reg addr, base; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); @@ -1143,10 +1380,10 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, /* Note that RX is mutually exclusive with DISP. */ if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); @@ -1157,19 +1394,19 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, tcg_temp_free(addr); } -#if TARGET_LONG_BITS == 64 -#define do_load_tl do_load_64 -#define do_store_tl do_store_64 +#if TARGET_REGISTER_BITS == 64 +#define do_load_reg do_load_64 +#define do_store_reg do_store_64 #else -#define do_load_tl do_load_32 -#define do_store_tl do_store_32 +#define do_load_reg do_load_32 +#define do_store_reg do_store_32 #endif static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify, TCGMemOp mop) { - TCGv dest; + TCGv_reg dest; nullify_over(ctx); @@ -1180,14 +1417,14 @@ static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, /* Make sure if RT == RB, we see the result of the load. */ dest = get_temp(ctx); } - do_load_tl(ctx, dest, rb, rx, scale, disp, modify, mop); + do_load_reg(ctx, dest, rb, rx, scale, disp, modify, mop); save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i32 tmp; @@ -1207,7 +1444,7 @@ static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i64 tmp; @@ -1227,15 +1464,15 @@ static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_long disp, int modify, TCGMemOp mop) + target_sreg disp, int modify, TCGMemOp mop) { nullify_over(ctx); - do_store_tl(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); + do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i32 tmp; @@ -1250,7 +1487,7 @@ static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, + unsigned rx, int scale, target_sreg disp, int modify) { TCGv_i64 tmp; @@ -1370,7 +1607,7 @@ static DisasJumpType do_fop_dedd(DisasContext *ctx, unsigned rt, /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static DisasJumpType do_dbranch(DisasContext *ctx, target_ulong dest, +static DisasJumpType do_dbranch(DisasContext *ctx, target_ureg dest, unsigned link, bool is_n) { if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { @@ -1407,10 +1644,10 @@ static DisasJumpType do_dbranch(DisasContext *ctx, target_ulong dest, /* Emit a conditional branch to a direct target. If the branch itself is nullified, we should have already used nullify_over. */ -static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool is_n, +static DisasJumpType do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, DisasCond *cond) { - target_ulong dest = iaoq_dest(ctx, disp); + target_ureg dest = iaoq_dest(ctx, disp); TCGLabel *taken = NULL; TCGCond c = cond->c; bool n; @@ -1427,7 +1664,7 @@ static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool is_n, taken = gen_new_label(); cond_prep(cond); - tcg_gen_brcond_tl(c, cond->a0, cond->a1, taken); + tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); cond_free(cond); /* Not taken: Condition not satisfied; nullify on backward branches. */ @@ -1468,10 +1705,10 @@ static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool is_n, /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, +static DisasJumpType do_ibranch(DisasContext *ctx, TCGv_reg dest, unsigned link, bool is_n) { - TCGv a0, a1, next, tmp; + TCGv_reg a0, a1, next, tmp; TCGCond c; assert(ctx->null_lab == NULL); @@ -1481,7 +1718,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } next = get_temp(ctx); - tcg_gen_mov_tl(next, dest); + tcg_gen_mov_reg(next, dest); ctx->iaoq_n = -1; ctx->iaoq_n_var = next; if (is_n) { @@ -1500,12 +1737,12 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, /* We do have to handle the non-local temporary, DEST, before branching. Since IOAQ_F is not really live at this point, we can simply store DEST optimistically. Similarly with IAOQ_B. */ - tcg_gen_mov_tl(cpu_iaoq_f, dest); - tcg_gen_addi_tl(cpu_iaoq_b, dest, 4); + tcg_gen_mov_reg(cpu_iaoq_f, dest); + tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); nullify_over(ctx); if (link != 0) { - tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); + tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); } tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, DISAS_NEXT); @@ -1519,19 +1756,19 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, next = get_temp(ctx); copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_tl(c, next, a0, a1, tmp, dest); + tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); ctx->iaoq_n = -1; ctx->iaoq_n_var = next; if (link != 0) { - tcg_gen_movcond_tl(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); + tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); } if (is_n) { /* The branch nullifies the next insn, which means the state of N after the branch is the inverse of the state of N that applied to the branch. */ - tcg_gen_setcond_tl(tcg_invert_cond(c), cpu_psw_n, a0, a1); + tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); cond_free(&ctx->null_cond); ctx->null_cond = cond_make_n(); ctx->psw_n_nonzero = true; @@ -1560,7 +1797,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) case TCG_COND_NEVER: break; case TCG_COND_ALWAYS: - tcg_gen_movi_tl(cpu_psw_n, 0); + tcg_gen_movi_reg(cpu_psw_n, 0); goto do_sigill; default: /* Since this is always the first (and only) insn within the @@ -1586,9 +1823,9 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_mov_tl(cpu_cr27, cpu_gr[26]); - tcg_gen_mov_tl(cpu_iaoq_f, cpu_gr[31]); - tcg_gen_addi_tl(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_reg(cpu_cr27, cpu_gr[26]); + tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); + tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; case 0x100: /* SYSCALL */ @@ -1631,8 +1868,8 @@ static DisasJumpType trans_mfia(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv tmp = dest_gpr(ctx, rt); - tcg_gen_movi_tl(tmp, ctx->iaoq_f); + TCGv_reg tmp = dest_gpr(ctx, rt); + tcg_gen_movi_reg(tmp, ctx->iaoq_f); save_gpr(ctx, rt, tmp); cond_free(&ctx->null_cond); @@ -1643,10 +1880,10 @@ static DisasJumpType trans_mfsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv tmp = dest_gpr(ctx, rt); + TCGv_reg tmp = dest_gpr(ctx, rt); /* ??? We don't implement space registers. */ - tcg_gen_movi_tl(tmp, 0); + tcg_gen_movi_reg(tmp, 0); save_gpr(ctx, rt, tmp); cond_free(&ctx->null_cond); @@ -1658,7 +1895,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, { unsigned rt = extract32(insn, 0, 5); unsigned ctl = extract32(insn, 21, 5); - TCGv tmp; + TCGv_reg tmp; switch (ctl) { case 11: /* SAR */ @@ -1666,7 +1903,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, if (extract32(insn, 14, 1) == 0) { /* MFSAR without ,W masks low 5 bits. */ tmp = dest_gpr(ctx, rt); - tcg_gen_andi_tl(tmp, cpu_sar, 31); + tcg_gen_andi_reg(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); break; } @@ -1698,11 +1935,11 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, { unsigned rin = extract32(insn, 16, 5); unsigned ctl = extract32(insn, 21, 5); - TCGv tmp; + TCGv_reg tmp; if (ctl == 11) { /* SAR */ tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, load_gpr(ctx, rin), TARGET_LONG_BITS - 1); + tcg_gen_andi_reg(tmp, load_gpr(ctx, rin), TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); } else { @@ -1718,10 +1955,10 @@ static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rin = extract32(insn, 16, 5); - TCGv tmp = tcg_temp_new(); + TCGv_reg tmp = tcg_temp_new(); - tcg_gen_not_tl(tmp, load_gpr(ctx, rin)); - tcg_gen_andi_tl(tmp, tmp, TARGET_LONG_BITS - 1); + tcg_gen_not_reg(tmp, load_gpr(ctx, rin)); + tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); @@ -1733,10 +1970,10 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv dest = dest_gpr(ctx, rt); + TCGv_reg dest = dest_gpr(ctx, rt); /* Since we don't implement space registers, this returns zero. */ - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); cond_free(&ctx->null_cond); @@ -1761,12 +1998,12 @@ static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rx = extract32(insn, 16, 5); - TCGv dest = dest_gpr(ctx, rb); - TCGv src1 = load_gpr(ctx, rb); - TCGv src2 = load_gpr(ctx, rx); + TCGv_reg dest = dest_gpr(ctx, rb); + TCGv_reg src1 = load_gpr(ctx, rb); + TCGv_reg src2 = load_gpr(ctx, rx); /* The only thing we need to do is the base register modification. */ - tcg_gen_add_tl(dest, src1, src2); + tcg_gen_add_reg(dest, src1, src2); save_gpr(ctx, rb, dest); cond_free(&ctx->null_cond); @@ -1779,7 +2016,7 @@ static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); unsigned rb = extract32(insn, 21, 5); unsigned is_write = extract32(insn, 6, 1); - TCGv dest; + TCGv_reg dest; nullify_over(ctx); @@ -1821,7 +2058,7 @@ static DisasJumpType trans_add(DisasContext *ctx, uint32_t insn, unsigned ext = extract32(insn, 8, 4); unsigned shift = extract32(insn, 6, 2); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; bool is_c = false; bool is_l = false; bool is_tc = false; @@ -1864,7 +2101,7 @@ static DisasJumpType trans_sub(DisasContext *ctx, uint32_t insn, unsigned cf = extract32(insn, 12, 4); unsigned ext = extract32(insn, 6, 6); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; bool is_b = false; bool is_tc = false; bool is_tsv = false; @@ -1908,7 +2145,7 @@ static DisasJumpType trans_log(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; if (cf) { @@ -1928,8 +2165,8 @@ static DisasJumpType trans_copy(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); if (r1 == 0) { - TCGv dest = dest_gpr(ctx, rt); - tcg_gen_movi_tl(dest, 0); + TCGv_reg dest = dest_gpr(ctx, rt); + tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); } else { save_gpr(ctx, rt, cpu_gr[r1]); @@ -1945,7 +2182,7 @@ static DisasJumpType trans_cmpclr(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; if (cf) { @@ -1964,7 +2201,7 @@ static DisasJumpType trans_uxor(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2; + TCGv_reg tcg_r1, tcg_r2; DisasJumpType ret; if (cf) { @@ -1972,7 +2209,7 @@ static DisasJumpType trans_uxor(DisasContext *ctx, uint32_t insn, } tcg_r1 = load_gpr(ctx, r1); tcg_r2 = load_gpr(ctx, r2); - ret = do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_tl); + ret = do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_reg); return nullify_end(ctx, ret); } @@ -1984,7 +2221,7 @@ static DisasJumpType trans_uaddcm(DisasContext *ctx, uint32_t insn, unsigned cf = extract32(insn, 12, 4); unsigned is_tc = extract32(insn, 6, 1); unsigned rt = extract32(insn, 0, 5); - TCGv tcg_r1, tcg_r2, tmp; + TCGv_reg tcg_r1, tcg_r2, tmp; DisasJumpType ret; if (cf) { @@ -1993,8 +2230,8 @@ static DisasJumpType trans_uaddcm(DisasContext *ctx, uint32_t insn, tcg_r1 = load_gpr(ctx, r1); tcg_r2 = load_gpr(ctx, r2); tmp = get_temp(ctx); - tcg_gen_not_tl(tmp, tcg_r2); - ret = do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_tl); + tcg_gen_not_reg(tmp, tcg_r2); + ret = do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_reg); return nullify_end(ctx, ret); } @@ -2005,20 +2242,20 @@ static DisasJumpType trans_dcor(DisasContext *ctx, uint32_t insn, unsigned cf = extract32(insn, 12, 4); unsigned is_i = extract32(insn, 6, 1); unsigned rt = extract32(insn, 0, 5); - TCGv tmp; + TCGv_reg tmp; DisasJumpType ret; nullify_over(ctx); tmp = get_temp(ctx); - tcg_gen_shri_tl(tmp, cpu_psw_cb, 3); + tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); if (!is_i) { - tcg_gen_not_tl(tmp, tmp); + tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_tl(tmp, tmp, 0x11111111); - tcg_gen_muli_tl(tmp, tmp, 6); + tcg_gen_andi_reg(tmp, tmp, 0x11111111); + tcg_gen_muli_reg(tmp, tmp, 6); ret = do_unit(ctx, rt, tmp, load_gpr(ctx, r2), cf, false, - is_i ? tcg_gen_add_tl : tcg_gen_sub_tl); + is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); return nullify_end(ctx, ret); } @@ -2030,7 +2267,7 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); - TCGv dest, add1, add2, addc, zero, in1, in2; + TCGv_reg dest, add1, add2, addc, zero, in1, in2; nullify_over(ctx); @@ -2041,19 +2278,19 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, add2 = tcg_temp_new(); addc = tcg_temp_new(); dest = tcg_temp_new(); - zero = tcg_const_tl(0); + zero = tcg_const_reg(0); /* Form R1 << 1 | PSW[CB]{8}. */ - tcg_gen_add_tl(add1, in1, in1); - tcg_gen_add_tl(add1, add1, cpu_psw_cb_msb); + tcg_gen_add_reg(add1, in1, in1); + tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); /* Add or subtract R2, depending on PSW[V]. Proper computation of carry{8} requires that we subtract via + ~R2 + 1, as described in the manual. By extracting and masking V, we can produce the proper inputs to the addition without movcond. */ - tcg_gen_sari_tl(addc, cpu_psw_v, TARGET_LONG_BITS - 1); - tcg_gen_xor_tl(add2, in2, addc); - tcg_gen_andi_tl(addc, addc, 1); + tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); + tcg_gen_xor_reg(add2, in2, addc); + tcg_gen_andi_reg(addc, addc, 1); /* ??? This is only correct for 32-bit. */ tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); @@ -2065,16 +2302,16 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, save_gpr(ctx, rt, dest); /* Write back PSW[CB]. */ - tcg_gen_xor_tl(cpu_psw_cb, add1, add2); - tcg_gen_xor_tl(cpu_psw_cb, cpu_psw_cb, dest); + tcg_gen_xor_reg(cpu_psw_cb, add1, add2); + tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); /* Write back PSW[V] for the division step. */ - tcg_gen_neg_tl(cpu_psw_v, cpu_psw_cb_msb); - tcg_gen_xor_tl(cpu_psw_v, cpu_psw_v, in2); + tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); + tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); /* Install the new nullification. */ if (cf) { - TCGv sv = NULL; + TCGv_reg sv = NULL; if (cf >> 1 == 6) { /* ??? The lshift is supposed to contribute to overflow. */ sv = do_add_sv(ctx, dest, add1, add2); @@ -2092,10 +2329,10 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, static const DisasInsn table_arith_log[] = { { 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */ { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */ - { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_tl }, - { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_tl }, - { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_tl }, - { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_xor_tl }, + { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_reg }, + { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_reg }, + { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_reg }, + { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_xor_reg }, { 0x08000880u, 0xfc000fe0u, trans_cmpclr }, { 0x08000380u, 0xfc000fe0u, trans_uxor }, { 0x08000980u, 0xfc000fa0u, trans_uaddcm }, @@ -2109,13 +2346,13 @@ static const DisasInsn table_arith_log[] = { static DisasJumpType trans_addi(DisasContext *ctx, uint32_t insn) { - target_long im = low_sextract(insn, 0, 11); + target_sreg im = low_sextract(insn, 0, 11); unsigned e1 = extract32(insn, 11, 1); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); unsigned o1 = extract32(insn, 26, 1); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; if (cf) { @@ -2131,12 +2368,12 @@ static DisasJumpType trans_addi(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_subi(DisasContext *ctx, uint32_t insn) { - target_long im = low_sextract(insn, 0, 11); + target_sreg im = low_sextract(insn, 0, 11); unsigned e1 = extract32(insn, 11, 1); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; if (cf) { @@ -2152,11 +2389,11 @@ static DisasJumpType trans_subi(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_cmpiclr(DisasContext *ctx, uint32_t insn) { - target_long im = low_sextract(insn, 0, 11); + target_sreg im = low_sextract(insn, 0, 11); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); - TCGv tcg_im, tcg_r2; + TCGv_reg tcg_im, tcg_r2; DisasJumpType ret; if (cf) { @@ -2224,7 +2461,7 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); TCGMemOp mop = MO_TEUL | MO_ALIGN_16; - TCGv zero, addr, base, dest; + TCGv_reg zero, addr, base, dest; int modify, disp = 0, scale = 0; nullify_over(ctx); @@ -2252,15 +2489,15 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, addr = tcg_temp_new(); base = load_gpr(ctx, rb); if (rx) { - tcg_gen_shli_tl(addr, cpu_gr[rx], scale); - tcg_gen_add_tl(addr, addr, base); + tcg_gen_shli_reg(addr, cpu_gr[rx], scale); + tcg_gen_add_reg(addr, addr, base); } else { - tcg_gen_addi_tl(addr, base, disp); + tcg_gen_addi_reg(addr, base, disp); } - zero = tcg_const_tl(0); - tcg_gen_atomic_xchg_tl(dest, (modify <= 0 ? addr : base), - zero, MMU_USER_IDX, mop); + zero = tcg_const_reg(0); + tcg_gen_atomic_xchg_reg(dest, (modify <= 0 ? addr : base), + zero, MMU_USER_IDX, mop); if (modify) { save_gpr(ctx, rb, addr); } @@ -2272,20 +2509,20 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { - target_long disp = low_sextract(insn, 0, 5); + target_sreg disp = low_sextract(insn, 0, 5); unsigned m = extract32(insn, 5, 1); unsigned a = extract32(insn, 13, 1); unsigned rt = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); - TCGv addr, val; + TCGv_reg addr, val; nullify_over(ctx); addr = tcg_temp_new(); if (m || disp == 0) { - tcg_gen_mov_tl(addr, load_gpr(ctx, rb)); + tcg_gen_mov_reg(addr, load_gpr(ctx, rb)); } else { - tcg_gen_addi_tl(addr, load_gpr(ctx, rb), disp); + tcg_gen_addi_reg(addr, load_gpr(ctx, rb), disp); } val = load_gpr(ctx, rt); @@ -2304,8 +2541,8 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, } if (m) { - tcg_gen_addi_tl(addr, addr, disp); - tcg_gen_andi_tl(addr, addr, ~3); + tcg_gen_addi_reg(addr, addr, disp); + tcg_gen_andi_reg(addr, addr, ~3); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -2324,10 +2561,10 @@ static const DisasInsn table_index_mem[] = { static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) { unsigned rt = extract32(insn, 21, 5); - target_long i = assemble_21(insn); - TCGv tcg_rt = dest_gpr(ctx, rt); + target_sreg i = assemble_21(insn); + TCGv_reg tcg_rt = dest_gpr(ctx, rt); - tcg_gen_movi_tl(tcg_rt, i); + tcg_gen_movi_reg(tcg_rt, i); save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); @@ -2337,11 +2574,11 @@ static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_addil(DisasContext *ctx, uint32_t insn) { unsigned rt = extract32(insn, 21, 5); - target_long i = assemble_21(insn); - TCGv tcg_rt = load_gpr(ctx, rt); - TCGv tcg_r1 = dest_gpr(ctx, 1); + target_sreg i = assemble_21(insn); + TCGv_reg tcg_rt = load_gpr(ctx, rt); + TCGv_reg tcg_r1 = dest_gpr(ctx, 1); - tcg_gen_addi_tl(tcg_r1, tcg_rt, i); + tcg_gen_addi_reg(tcg_r1, tcg_rt, i); save_gpr(ctx, 1, tcg_r1); cond_free(&ctx->null_cond); @@ -2352,15 +2589,15 @@ static DisasJumpType trans_ldo(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16(insn); - TCGv tcg_rt = dest_gpr(ctx, rt); + target_sreg i = assemble_16(insn); + TCGv_reg tcg_rt = dest_gpr(ctx, rt); /* Special case rb == 0, for the LDI pseudo-op. The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ if (rb == 0) { - tcg_gen_movi_tl(tcg_rt, i); + tcg_gen_movi_reg(tcg_rt, i); } else { - tcg_gen_addi_tl(tcg_rt, cpu_gr[rb], i); + tcg_gen_addi_reg(tcg_rt, cpu_gr[rb], i); } save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); @@ -2373,7 +2610,7 @@ static DisasJumpType trans_load(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16(insn); + target_sreg i = assemble_16(insn); return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } @@ -2382,7 +2619,7 @@ static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); switch (ext2) { @@ -2401,7 +2638,7 @@ static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_fload_mod(DisasContext *ctx, uint32_t insn) { - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); unsigned t0 = extract32(insn, 16, 5); @@ -2416,7 +2653,7 @@ static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16(insn); + target_sreg i = assemble_16(insn); return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } @@ -2425,7 +2662,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); switch (ext2) { @@ -2443,7 +2680,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_fstore_mod(DisasContext *ctx, uint32_t insn) { - target_long i = assemble_16a(insn); + target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); unsigned t0 = extract32(insn, 16, 5); @@ -2525,12 +2762,12 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, bool is_true, bool is_imm, bool is_dw) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 13, 3); unsigned r = extract32(insn, 21, 5); unsigned cf = c * 2 + !is_true; - TCGv dest, in1, in2, sv; + TCGv_reg dest, in1, in2, sv; DisasCond cond; nullify_over(ctx); @@ -2543,7 +2780,7 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, in2 = load_gpr(ctx, r); dest = get_temp(ctx); - tcg_gen_sub_tl(dest, in1, in2); + tcg_gen_sub_reg(dest, in1, in2); sv = NULL; if (c == 6) { @@ -2557,12 +2794,12 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, bool is_true, bool is_imm) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 13, 3); unsigned r = extract32(insn, 21, 5); unsigned cf = c * 2 + !is_true; - TCGv dest, in1, in2, sv, cb_msb; + TCGv_reg dest, in1, in2, sv, cb_msb; DisasCond cond; nullify_over(ctx); @@ -2579,15 +2816,15 @@ static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, switch (c) { default: - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); break; case 4: case 5: cb_msb = get_temp(ctx); - tcg_gen_movi_tl(cb_msb, 0); - tcg_gen_add2_tl(dest, cb_msb, in1, cb_msb, in2, cb_msb); + tcg_gen_movi_reg(cb_msb, 0); + tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); break; case 6: - tcg_gen_add_tl(dest, in1, in2); + tcg_gen_add_reg(dest, in1, in2); sv = do_add_sv(ctx, dest, in1, in2); break; } @@ -2598,13 +2835,13 @@ static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 15, 1); unsigned r = extract32(insn, 16, 5); unsigned p = extract32(insn, 21, 5); unsigned i = extract32(insn, 26, 1); - TCGv tmp, tcg_r; + TCGv_reg tmp, tcg_r; DisasCond cond; nullify_over(ctx); @@ -2612,9 +2849,9 @@ static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) tmp = tcg_temp_new(); tcg_r = load_gpr(ctx, r); if (i) { - tcg_gen_shli_tl(tmp, tcg_r, p); + tcg_gen_shli_reg(tmp, tcg_r, p); } else { - tcg_gen_shl_tl(tmp, tcg_r, cpu_sar); + tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); } cond = cond_make_0(c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -2624,23 +2861,23 @@ static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) static DisasJumpType trans_movb(DisasContext *ctx, uint32_t insn, bool is_imm) { - target_long disp = assemble_12(insn) * 4; + target_sreg disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); unsigned c = extract32(insn, 13, 3); unsigned t = extract32(insn, 16, 5); unsigned r = extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; DisasCond cond; nullify_over(ctx); dest = dest_gpr(ctx, r); if (is_imm) { - tcg_gen_movi_tl(dest, low_sextract(t, 0, 5)); + tcg_gen_movi_reg(dest, low_sextract(t, 0, 5)); } else if (t == 0) { - tcg_gen_movi_tl(dest, 0); + tcg_gen_movi_reg(dest, 0); } else { - tcg_gen_mov_tl(dest, cpu_gr[t]); + tcg_gen_mov_reg(dest, cpu_gr[t]); } cond = do_sed_cond(c, dest); @@ -2654,7 +2891,7 @@ static DisasJumpType trans_shrpw_sar(DisasContext *ctx, uint32_t insn, unsigned c = extract32(insn, 13, 3); unsigned r1 = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; if (c) { nullify_over(ctx); @@ -2662,22 +2899,22 @@ static DisasJumpType trans_shrpw_sar(DisasContext *ctx, uint32_t insn, dest = dest_gpr(ctx, rt); if (r1 == 0) { - tcg_gen_ext32u_tl(dest, load_gpr(ctx, r2)); - tcg_gen_shr_tl(dest, dest, cpu_sar); + tcg_gen_ext32u_reg(dest, load_gpr(ctx, r2)); + tcg_gen_shr_reg(dest, dest, cpu_sar); } else if (r1 == r2) { TCGv_i32 t32 = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t32, load_gpr(ctx, r2)); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, r2)); tcg_gen_rotr_i32(t32, t32, cpu_sar); - tcg_gen_extu_i32_tl(dest, t32); + tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); } else { TCGv_i64 t = tcg_temp_new_i64(); TCGv_i64 s = tcg_temp_new_i64(); - tcg_gen_concat_tl_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); - tcg_gen_extu_tl_i64(s, cpu_sar); + tcg_gen_concat_reg_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); + tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_shr_i64(t, t, s); - tcg_gen_trunc_i64_tl(dest, t); + tcg_gen_trunc_i64_reg(dest, t); tcg_temp_free_i64(t); tcg_temp_free_i64(s); @@ -2701,7 +2938,7 @@ static DisasJumpType trans_shrpw_imm(DisasContext *ctx, uint32_t insn, unsigned r1 = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); unsigned sa = 31 - cpos; - TCGv dest, t2; + TCGv_reg dest, t2; if (c) { nullify_over(ctx); @@ -2711,16 +2948,16 @@ static DisasJumpType trans_shrpw_imm(DisasContext *ctx, uint32_t insn, t2 = load_gpr(ctx, r2); if (r1 == r2) { TCGv_i32 t32 = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t32, t2); + tcg_gen_trunc_reg_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_tl(dest, t32); + tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); } else if (r1 == 0) { - tcg_gen_extract_tl(dest, t2, sa, 32 - sa); + tcg_gen_extract_reg(dest, t2, sa, 32 - sa); } else { - TCGv t0 = tcg_temp_new(); - tcg_gen_extract_tl(t0, t2, sa, 32 - sa); - tcg_gen_deposit_tl(dest, t0, cpu_gr[r1], 32 - sa, sa); + TCGv_reg t0 = tcg_temp_new(); + tcg_gen_extract_reg(t0, t2, sa, 32 - sa); + tcg_gen_deposit_reg(dest, t0, cpu_gr[r1], 32 - sa, sa); tcg_temp_free(t0); } save_gpr(ctx, rt, dest); @@ -2742,7 +2979,7 @@ static DisasJumpType trans_extrw_sar(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 16, 5); unsigned rr = extract32(insn, 21, 5); unsigned len = 32 - clen; - TCGv dest, src, tmp; + TCGv_reg dest, src, tmp; if (c) { nullify_over(ctx); @@ -2753,13 +2990,13 @@ static DisasJumpType trans_extrw_sar(DisasContext *ctx, uint32_t insn, tmp = tcg_temp_new(); /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_xori_tl(tmp, cpu_sar, TARGET_LONG_BITS - 1); + tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); if (is_se) { - tcg_gen_sar_tl(dest, src, tmp); - tcg_gen_sextract_tl(dest, dest, 0, len); + tcg_gen_sar_reg(dest, src, tmp); + tcg_gen_sextract_reg(dest, dest, 0, len); } else { - tcg_gen_shr_tl(dest, src, tmp); - tcg_gen_extract_tl(dest, dest, 0, len); + tcg_gen_shr_reg(dest, src, tmp); + tcg_gen_extract_reg(dest, dest, 0, len); } tcg_temp_free(tmp); save_gpr(ctx, rt, dest); @@ -2783,7 +3020,7 @@ static DisasJumpType trans_extrw_imm(DisasContext *ctx, uint32_t insn, unsigned rr = extract32(insn, 21, 5); unsigned len = 32 - clen; unsigned cpos = 31 - pos; - TCGv dest, src; + TCGv_reg dest, src; if (c) { nullify_over(ctx); @@ -2792,9 +3029,9 @@ static DisasJumpType trans_extrw_imm(DisasContext *ctx, uint32_t insn, dest = dest_gpr(ctx, rt); src = load_gpr(ctx, rr); if (is_se) { - tcg_gen_sextract_tl(dest, src, cpos, len); + tcg_gen_sextract_reg(dest, src, cpos, len); } else { - tcg_gen_extract_tl(dest, src, cpos, len); + tcg_gen_extract_reg(dest, src, cpos, len); } save_gpr(ctx, rt, dest); @@ -2820,11 +3057,11 @@ static DisasJumpType trans_depw_imm_c(DisasContext *ctx, uint32_t insn, unsigned cpos = extract32(insn, 5, 5); unsigned nz = extract32(insn, 10, 1); unsigned c = extract32(insn, 13, 3); - target_long val = low_sextract(insn, 16, 5); + target_sreg val = low_sextract(insn, 16, 5); unsigned rt = extract32(insn, 21, 5); unsigned len = 32 - clen; - target_long mask0, mask1; - TCGv dest; + target_sreg mask0, mask1; + TCGv_reg dest; if (c) { nullify_over(ctx); @@ -2838,14 +3075,14 @@ static DisasJumpType trans_depw_imm_c(DisasContext *ctx, uint32_t insn, mask1 = deposit64(-1, cpos, len, val); if (nz) { - TCGv src = load_gpr(ctx, rt); + TCGv_reg src = load_gpr(ctx, rt); if (mask1 != -1) { - tcg_gen_andi_tl(dest, src, mask1); + tcg_gen_andi_reg(dest, src, mask1); src = dest; } - tcg_gen_ori_tl(dest, src, mask0); + tcg_gen_ori_reg(dest, src, mask0); } else { - tcg_gen_movi_tl(dest, mask0); + tcg_gen_movi_reg(dest, mask0); } save_gpr(ctx, rt, dest); @@ -2868,7 +3105,7 @@ static DisasJumpType trans_depw_imm(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 21, 5); unsigned rs = nz ? rt : 0; unsigned len = 32 - clen; - TCGv dest, val; + TCGv_reg dest, val; if (c) { nullify_over(ctx); @@ -2880,9 +3117,9 @@ static DisasJumpType trans_depw_imm(DisasContext *ctx, uint32_t insn, dest = dest_gpr(ctx, rt); val = load_gpr(ctx, rr); if (rs == 0) { - tcg_gen_deposit_z_tl(dest, val, cpos, len); + tcg_gen_deposit_z_reg(dest, val, cpos, len); } else { - tcg_gen_deposit_tl(dest, cpu_gr[rs], val, cpos, len); + tcg_gen_deposit_reg(dest, cpu_gr[rs], val, cpos, len); } save_gpr(ctx, rt, dest); @@ -2904,7 +3141,7 @@ static DisasJumpType trans_depw_sar(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 21, 5); unsigned rs = nz ? rt : 0; unsigned len = 32 - clen; - TCGv val, mask, tmp, shift, dest; + TCGv_reg val, mask, tmp, shift, dest; unsigned msb = 1U << (len - 1); if (c) { @@ -2921,17 +3158,17 @@ static DisasJumpType trans_depw_sar(DisasContext *ctx, uint32_t insn, tmp = tcg_temp_new(); /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_xori_tl(shift, cpu_sar, TARGET_LONG_BITS - 1); + tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); - mask = tcg_const_tl(msb + (msb - 1)); - tcg_gen_and_tl(tmp, val, mask); + mask = tcg_const_reg(msb + (msb - 1)); + tcg_gen_and_reg(tmp, val, mask); if (rs) { - tcg_gen_shl_tl(mask, mask, shift); - tcg_gen_shl_tl(tmp, tmp, shift); - tcg_gen_andc_tl(dest, cpu_gr[rs], mask); - tcg_gen_or_tl(dest, dest, tmp); + tcg_gen_shl_reg(mask, mask, shift); + tcg_gen_shl_reg(tmp, tmp, shift); + tcg_gen_andc_reg(dest, cpu_gr[rs], mask); + tcg_gen_or_reg(dest, dest, tmp); } else { - tcg_gen_shl_tl(dest, tmp, shift); + tcg_gen_shl_reg(dest, tmp, shift); } tcg_temp_free(shift); tcg_temp_free(mask); @@ -2956,7 +3193,7 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) { unsigned n = extract32(insn, 1, 1); unsigned b = extract32(insn, 21, 5); - target_long disp = assemble_17(insn); + target_sreg disp = assemble_17(insn); /* unsigned s = low_uextract(insn, 13, 3); */ /* ??? It seems like there should be a good way of using @@ -2971,8 +3208,8 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) if (b == 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); } else { - TCGv tmp = get_temp(ctx); - tcg_gen_addi_tl(tmp, load_gpr(ctx, b), disp); + TCGv_reg tmp = get_temp(ctx); + tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } } @@ -2982,7 +3219,7 @@ static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, { unsigned n = extract32(insn, 1, 1); unsigned link = extract32(insn, 21, 5); - target_long disp = assemble_17(insn); + target_sreg disp = assemble_17(insn); return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } @@ -2991,7 +3228,7 @@ static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned n = extract32(insn, 1, 1); - target_long disp = assemble_22(insn); + target_sreg disp = assemble_22(insn); return do_dbranch(ctx, iaoq_dest(ctx, disp), 2, n); } @@ -3002,10 +3239,10 @@ static DisasJumpType trans_blr(DisasContext *ctx, uint32_t insn, unsigned n = extract32(insn, 1, 1); unsigned rx = extract32(insn, 16, 5); unsigned link = extract32(insn, 21, 5); - TCGv tmp = get_temp(ctx); + TCGv_reg tmp = get_temp(ctx); - tcg_gen_shli_tl(tmp, load_gpr(ctx, rx), 3); - tcg_gen_addi_tl(tmp, tmp, ctx->iaoq_f + 8); + tcg_gen_shli_reg(tmp, load_gpr(ctx, rx), 3); + tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); return do_ibranch(ctx, tmp, link, n); } @@ -3015,14 +3252,14 @@ static DisasJumpType trans_bv(DisasContext *ctx, uint32_t insn, unsigned n = extract32(insn, 1, 1); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); - TCGv dest; + TCGv_reg dest; if (rx == 0) { dest = load_gpr(ctx, rb); } else { dest = get_temp(ctx); - tcg_gen_shli_tl(dest, load_gpr(ctx, rx), 3); - tcg_gen_add_tl(dest, dest, load_gpr(ctx, rb)); + tcg_gen_shli_reg(dest, load_gpr(ctx, rx), 3); + tcg_gen_add_reg(dest, dest, load_gpr(ctx, rb)); } return do_ibranch(ctx, dest, 0, n); } @@ -3242,13 +3479,13 @@ static DisasJumpType trans_ftest_t(DisasContext *ctx, uint32_t insn, { unsigned y = extract32(insn, 13, 3); unsigned cbit = (y ^ 1) - 1; - TCGv t; + TCGv_reg t; nullify_over(ctx); t = tcg_temp_new(); - tcg_gen_ld32u_tl(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); - tcg_gen_extract_tl(t, t, 21 - cbit, 1); + tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_extract_reg(t, t, 21 - cbit, 1); ctx->null_cond = cond_make_0(TCG_COND_NE, t); tcg_temp_free(t); @@ -3261,16 +3498,16 @@ static DisasJumpType trans_ftest_q(DisasContext *ctx, uint32_t insn, unsigned c = extract32(insn, 0, 5); int mask; bool inv = false; - TCGv t; + TCGv_reg t; nullify_over(ctx); t = tcg_temp_new(); - tcg_gen_ld32u_tl(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); switch (c) { case 0: /* simple */ - tcg_gen_andi_tl(t, t, 0x4000000); + tcg_gen_andi_reg(t, t, 0x4000000); ctx->null_cond = cond_make_0(TCG_COND_NE, t); goto done; case 2: /* rej */ @@ -3298,11 +3535,11 @@ static DisasJumpType trans_ftest_q(DisasContext *ctx, uint32_t insn, return gen_illegal(ctx); } if (inv) { - TCGv c = load_const(ctx, mask); - tcg_gen_or_tl(t, t, c); + TCGv_reg c = load_const(ctx, mask); + tcg_gen_or_reg(t, t, c); ctx->null_cond = cond_make(TCG_COND_EQ, t, c); } else { - tcg_gen_andi_tl(t, t, mask); + tcg_gen_andi_reg(t, t, mask); ctx->null_cond = cond_make_0(TCG_COND_EQ, t); } done: @@ -3805,7 +4042,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) if (ctx->iaoq_b == -1) { ctx->iaoq_n = -1; ctx->iaoq_n_var = get_temp(ctx); - tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4); + tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n = ctx->iaoq_b + 4; ctx->iaoq_n_var = NULL; @@ -3849,12 +4086,12 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } if (ctx->iaoq_f == -1) { - tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); + tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); nullify_save(ctx); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; } else if (ctx->iaoq_b == -1) { - tcg_gen_mov_tl(cpu_iaoq_b, ctx->iaoq_n_var); + tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); } } @@ -3889,8 +4126,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { - TranslationBlock *tb = dcbase->tb; - target_ulong pc = tb->pc; + target_ureg pc = dcbase->pc_first; #ifdef CONFIG_USER_ONLY switch (pc) { @@ -3910,7 +4146,7 @@ static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) #endif qemu_log("IN: %s\n", lookup_symbol(pc)); - log_target_disas(cs, pc, tb->size); + log_target_disas(cs, pc, dcbase->tb->size); } static const TranslatorOps hppa_tr_ops = { From patchwork Wed Jan 24 23:25:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125729 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp735254ljf; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:46 -0800 Message-Id: <20180124232625.30105-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 06/45] target/hppa: Implement mmu_idx from IA privilege level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most aspects of privilege are not yet handled. But this gives us the start from which to begin checking. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 19 +++++++++++++---- target/hppa/cpu.c | 2 +- target/hppa/translate.c | 55 ++++++++++++++++++++++++++++++------------------- 3 files changed, 50 insertions(+), 26 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1524ef91b6..805c93db9c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -36,8 +36,10 @@ #define TARGET_PAGE_BITS 12 #define ALIGNED_ONLY -#define NB_MMU_MODES 1 -#define MMU_USER_IDX 0 +#define NB_MMU_MODES 5 +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 3 +#define MMU_PHYS_IDX 4 #define TARGET_INSN_START_EXTRA_WORDS 1 /* Hardware exceptions, interupts, faults, and traps. */ @@ -195,7 +197,14 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { - return 0; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return env->iaoq_f & 3; + } + return MMU_PHYS_IDX; /* mmu disabled */ +#endif } void hppa_translate_init(void); @@ -210,7 +219,9 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, { *pc = env->iaoq_f; *cs_base = env->iaoq_b; - *pflags = env->psw_n; + /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ + *pflags = (env->psw & (PSW_W | PSW_C | PSW_D)) + | env->psw_n * PSW_N; } target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index f6d92de972..9962ab71ee 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -39,7 +39,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.iaoq_f = tb->pc; cpu->env.iaoq_b = tb->cs_base; - cpu->env.psw_n = tb->flags & 1; + cpu->env.psw_n = (tb->flags & PSW_N) != 0; } static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dd96147bf1..33605a2d15 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -282,6 +282,8 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; + int mmu_idx; + int privilege; bool psw_n_nonzero; } DisasContext; @@ -1299,10 +1301,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, } if (modify == 0) { - tcg_gen_qemu_ld_i32(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i32(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1329,10 +1331,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, } if (modify == 0) { - tcg_gen_qemu_ld_i64(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i64(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1358,7 +1360,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } - tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); + tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); if (modify != 0) { save_gpr(ctx, rb, addr); @@ -1386,7 +1388,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } - tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), MMU_USER_IDX, mop); + tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); if (modify != 0) { save_gpr(ctx, rb, addr); @@ -2497,7 +2499,7 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, zero = tcg_const_reg(0); tcg_gen_atomic_xchg_reg(dest, (modify <= 0 ? addr : base), - zero, MMU_USER_IDX, mop); + zero, ctx->mmu_idx, mop); if (modify) { save_gpr(ctx, rb, addr); } @@ -3971,30 +3973,43 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs, int max_insns) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - TranslationBlock *tb = ctx->base.tb; int bound; ctx->cs = cs; - ctx->iaoq_f = tb->pc; - ctx->iaoq_b = tb->cs_base; + +#ifdef CONFIG_USER_ONLY + ctx->privilege = MMU_USER_IDX; + ctx->mmu_idx = MMU_USER_IDX; +#else + ctx->privilege = ctx->base.pc_first & 3; + ctx->mmu_idx = (ctx->base.tb->flags & PSW_D + ? ctx->privilege : MMU_PHYS_IDX); +#endif + ctx->iaoq_f = ctx->base.pc_first; + ctx->iaoq_b = ctx->base.tb->cs_base; + ctx->base.pc_first &= -4; + ctx->iaoq_n = -1; ctx->iaoq_n_var = NULL; + /* Bound the number of instructions by those left on the page. */ + bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; + bound = MIN(max_insns, bound); + ctx->ntemps = 0; memset(ctx->temps, 0, sizeof(ctx->temps)); - bound = -(tb->pc | TARGET_PAGE_MASK) / 4; - return MIN(max_insns, bound); + return bound; } static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - /* Seed the nullification status from PSW[N], as shown in TB->FLAGS. */ + /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ ctx->null_cond = cond_make_f(); ctx->psw_n_nonzero = false; - if (ctx->base.tb->flags & 1) { + if (ctx->base.tb->flags & PSW_N) { ctx->null_cond.c = TCG_COND_ALWAYS; ctx->psw_n_nonzero = true; } @@ -4014,7 +4029,7 @@ static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next = ctx->iaoq_f + 4; + ctx->base.pc_next = (ctx->iaoq_f & -4) + 4; return true; } @@ -4035,7 +4050,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f); + uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f & -4); /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ @@ -4064,10 +4079,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } ctx->ntemps = 0; - /* Advance the insn queue. */ - /* ??? The non-linear instruction restriction is purely due to - the debugging dump. Otherwise we *could* follow unconditional - branches within the same page. */ + /* Advance the insn queue. Note that this check also detects + a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { if (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS) { @@ -4121,7 +4134,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* We don't actually use this during normal translation, but we should interact with the generic main loop. */ - ctx->base.pc_next = ctx->base.tb->pc + 4 * ctx->base.num_insns; + ctx->base.pc_next = ctx->base.pc_first + 4 * ctx->base.num_insns; } static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) From patchwork Wed Jan 24 23:25:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125732 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp736292ljf; Wed, 24 Jan 2018 15:39:28 -0800 (PST) X-Google-Smtp-Source: AH8x2256qd42CHvVZtye/A1bKaNW6LdWM/tqpXfCaGZRoUzWeOFzlQdgbNEeJLLuf3RuKp3xhuUn X-Received: by 10.129.55.209 with SMTP id e200mr6681317ywa.306.1516837168594; Wed, 24 Jan 2018 15:39:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837168; cv=none; d=google.com; s=arc-20160816; b=ibqci36WRPUCceYBMtuPDJ3xRw6Rxdb6KlIPK9SArmZmNoq5hbNk2pfbdYdPIpBJ7M avo5lnrpb3V/X9myP+JtXDoNrdpUA/+Qyi1q11WdJUAhXCwT5q4jVUae9OEfg/NZ2WlQ ypafF4rOGFvPHDUMk1cSHN5x9w2jHYqBTT9rkEOsiVViBFk386fANNKc0bBXeKgGdFHZ 3EH/6VypVcpNh05EkPjSLhsq2r68YMzwuRgBWZKdFHGL3W4mbvOm67b41jeFeaATBtR6 poDdz+RUNqeYMoY2sFQBI99E3YIsDR421G79CAa1MIkaUGmuKmhqZ+ZLsqtTjCKt318N L3Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+6dDGlU5G4pqOu3+fCXuYTnali05S0or37iI2x6SAAg=; b=g6S8ezHwUkxYTTE526sZ3dy2VsSp4CBOYT/qu3AEV6j+WhpZoAFdPhZ+QLMoLkDVsI ta6y8CbyqKCczBQtl3aMcj8S/Rm7HiGEsRsd4UDwQeVFXiNfNeAhzr70lnfzrsdELxnA f4yPQo6/KEXVc2puBY3zkYFC6NBPKErw9043Y+t0lr6SOy1iD7KdQE2dbZDS7aGREWzr X4I6D12M3bCpTgZ3HJ6twHQCzHYEE6x/09yGI6YK5/Fs/t/O8B0zA51XLXfKaDfYoVT9 D121G8wNkS6cmGiXPgdpEPVP0anhPq6/vzSamGpJSuplZkm91UcQKQrKJhxmJnAiX6NV 5oiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ATR8z3xj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:47 -0800 Message-Id: <20180124232625.30105-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 07/45] target/hppa: Implement the system mask instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 4 +++ target/hppa/op_helper.c | 14 ++++++++ target/hppa/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 113 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c720de523b..254a4da133 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -76,3 +76,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) + +#ifndef CONFIG_USER_ONLY +DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +#endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 479bfc0fdf..1c3e043cc0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -601,3 +601,17 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c) update_fr0_op(env, GETPC()); return ret; } + +#ifndef CONFIG_USER_ONLY +target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) +{ + target_ulong psw = env->psw; + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (nsm & ~psw & PSW_Q) { + dynexcp(env, EXCP_ILL, GETPC()); + } + env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); + return psw & PSW_SM; +} +#endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 33605a2d15..088031e7f3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -299,6 +299,10 @@ typedef struct DisasContext { updated the iaq for the next instruction to be executed. */ #define DISAS_IAQ_N_STALE DISAS_TARGET_1 +/* Similarly, but we want to return to the main loop immediately + to recognize unmasked interrupts. */ +#define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 + typedef struct DisasInsn { uint32_t insn, mask; DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, @@ -697,6 +701,14 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } +#define CHECK_MOST_PRIVILEGED(EXCP) \ + do { \ + if (ctx->privilege != 0) { \ + nullify_over(ctx); \ + return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + } \ + } while (0) + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ @@ -1982,6 +1994,79 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, return DISAS_NEXT; } +#ifndef CONFIG_USER_ONLY +/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ +static target_ureg extract_sm_imm(uint32_t insn) +{ + target_ureg val = extract32(insn, 16, 10); + + if (val & PSW_SM_E) { + val = (val & ~PSW_SM_E) | PSW_E; + } + if (val & PSW_SM_W) { + val = (val & ~PSW_SM_W) | PSW_W; + } + return val; +} + +static DisasJumpType trans_rsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_andi_reg(tmp, tmp, ~sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_ssm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ori_reg(tmp, tmp, sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr = extract32(insn, 16, 5); + TCGv_reg tmp, reg; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + reg = load_gpr(ctx, rr); + tmp = get_temp(ctx); + gen_helper_swap_system_mask(tmp, cpu_env, reg); + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_system[] = { { 0x00000000u, 0xfc001fe0u, trans_break }, /* We don't implement space register, so MTSP is a nop. */ @@ -1993,6 +2078,11 @@ static const DisasInsn table_system[] = { { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, +#ifndef CONFIG_USER_ONLY + { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, + { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, + { 0x00001860u, 0xffe0ffffu, trans_mtsm }, +#endif }; static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, @@ -4111,12 +4201,14 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + DisasJumpType is_jmp = ctx->base.is_jmp; - switch (ctx->base.is_jmp) { + switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: + case DISAS_IAQ_N_STALE_EXIT: copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); @@ -4124,6 +4216,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_IAQ_N_UPDATED: if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); + } else if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(0); } else { tcg_gen_lookup_and_goto_ptr(); } From patchwork Wed Jan 24 23:25:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125736 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp737443ljf; Wed, 24 Jan 2018 15:42:17 -0800 (PST) X-Google-Smtp-Source: AH8x224hd94vEHOAiAD/15Txktac2UCtY20ThTbhkvbZTFmTLttmfDnkcRdlnYP5koLOVyU+2Wam X-Received: by 10.37.107.6 with SMTP id g6mr6930515ybc.395.1516837337868; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:48 -0800 Message-Id: <20180124232625.30105-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 08/45] target/hppa: Add space registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not used where they should be yet, but we can copy them. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.c | 14 ++++++---- target/hppa/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 77 insertions(+), 11 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 805c93db9c..24c728c0d2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -140,6 +140,7 @@ typedef int64_t target_sreg; struct CPUHPPAState { target_ureg gr[32]; uint64_t fr[32]; + uint64_t sr[8]; /* stored shifted into place for gva */ target_ureg sar; target_ureg cr26; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index b6521f61fc..48ac80cb2d 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -168,12 +168,16 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, psw, psw_cb, psw_c); for (i = 0; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TREG_FMT_lx " ", i, env->gr[i]); - if ((i % 4) == 3) { - cpu_fprintf(f, "\n"); - } + cpu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i], + (i & 3) == 3 ? '\n' : ' '); + } +#ifndef CONFIG_USER_ONLY + for (i = 0; i < 8; i++) { + cpu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), + (i & 3) == 3 ? '\n' : ' '); } - cpu_fprintf(f, "\n"); +#endif + cpu_fprintf(f, "\n"); /* ??? FR */ } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 088031e7f3..50d41b0c63 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -320,6 +320,7 @@ typedef struct DisasInsn { /* global register indexes */ static TCGv_reg cpu_gr[32]; +static TCGv_i64 cpu_sr[4]; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_reg cpu_sar; @@ -358,6 +359,10 @@ void hppa_translate_init(void) "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; + /* SR[4-7] are not global registers so that we can index them. */ + static const char sr_names[4][4] = { + "sr0", "sr1", "sr2", "sr3" + }; int i; @@ -367,6 +372,11 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, gr[i]), gr_names[i]); } + for (i = 0; i < 4; i++) { + cpu_sr[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[i]), + sr_names[i]); + } for (i = 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v = &vars[i]; @@ -571,6 +581,19 @@ static void save_frd(unsigned rt, TCGv_i64 val) tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); } +static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) +{ +#ifdef CONFIG_USER_ONLY + tcg_gen_movi_i64(dest, 0); +#else + if (reg < 4) { + tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else { + tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); + } +#endif +} + /* Skip over the implementation of an insn that has been nullified. Use this when the insn is too complex for a conditional move. */ static void nullify_over(DisasContext *ctx) @@ -785,6 +808,13 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } +static unsigned assemble_sr3(uint32_t insn) +{ + unsigned s2 = extract32(insn, 13, 1); + unsigned s0 = extract32(insn, 14, 2); + return s2 * 4 + s0; +} + static target_sreg assemble_12(uint32_t insn) { target_ureg x = -(target_ureg)(insn & 1); @@ -1894,11 +1924,17 @@ static DisasJumpType trans_mfsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); - TCGv_reg tmp = dest_gpr(ctx, rt); + unsigned rs = assemble_sr3(insn); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_reg t1 = tcg_temp_new(); - /* ??? We don't implement space registers. */ - tcg_gen_movi_reg(tmp, 0); - save_gpr(ctx, rt, tmp); + load_spr(ctx, t0, rs); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_reg(t1, t0); + + save_gpr(ctx, rt, t1); + tcg_temp_free(t1); + tcg_temp_free_i64(t0); cond_free(&ctx->null_cond); return DISAS_NEXT; @@ -1944,6 +1980,32 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, return DISAS_NEXT; } +static DisasJumpType trans_mtsp(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr = extract32(insn, 16, 5); + unsigned rs = assemble_sr3(insn); + TCGv_i64 t64; + + if (rs >= 5) { + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + } + nullify_over(ctx); + + t64 = tcg_temp_new_i64(); + tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); + tcg_gen_shli_i64(t64, t64, 32); + + if (rs >= 4) { + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + } else { + tcg_gen_mov_i64(cpu_sr[rs], t64); + } + tcg_temp_free_i64(t64); + + return nullify_end(ctx, DISAS_NEXT); +} + static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -2069,8 +2131,7 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, static const DisasInsn table_system[] = { { 0x00000000u, 0xfc001fe0u, trans_break }, - /* We don't implement space register, so MTSP is a nop. */ - { 0x00001820u, 0xffe01fffu, trans_nop }, + { 0x00001820u, 0xffe01fffu, trans_mtsp }, { 0x00001840u, 0xfc00ffffu, trans_mtctl }, { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, { 0x000014a0u, 0xffffffe0u, trans_mfia }, From patchwork Wed Jan 24 23:25:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125743 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp739401ljf; Wed, 24 Jan 2018 15:47:24 -0800 (PST) X-Google-Smtp-Source: AH8x2274lAuVgH5WIzKgaUyPszRI+SzhadRTX1bGw2YyIPYspGdCmVMtPGXNi2n+LP0UKWKHUZUE X-Received: by 10.37.224.9 with SMTP id x9mr6627909ybg.461.1516837644517; Wed, 24 Jan 2018 15:47:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837644; cv=none; d=google.com; s=arc-20160816; b=NvUBH45X4MptWz0E4P96DZw2xtkYbx8p/d7JJQ5jD8Y1Zui+0qucXI+ol2g+wrFuW6 OEbKq/a9QjZhA1QzHBfxHpq1MRgzoo5tFz8tYAzFO3XWL5SSEyRvtj9Z7eMjD8lQJl8+ 220/06lThpyBVEmwfPGZvj4Zinnjl3gpvL81xb/tqc34DiNGBC3T9AIyJfyEx/jrrZ1M wp8G+/fxzXRhV27ENVHZC8rsw9A0YM/rA+xWZfKP2tHoq0YnahS/197TJF5wpYn0GOhJ tJLXE2Ev3KxH+ejp5RHSPDhh7noBKUZTeBCgifouX5vRzMxJLsnv8SrvhYL2nGmVG0aS yFQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=zEJIyNNEFcvSLly3Po8WRqqswnEmq+LgGLaXt/hERiA=; b=fLbtskluwYPshCPcKO2wY2sqq+olVYYjdNT+e+4kLF7AdOg7dv5fFtvjm0VWJKHd3b RLdJCnbGqE/a+a5+T18mWeSbEyK+Xvfyl4qZf4A37wVpx3ez4ykMQ9WExu1JBBBGQCJq X5jsOsHDlT7L5XCHgo6NWYCoiX2fKpt2eUWRljXQNyN4sUdagkHqSUdvGTcH6jJM33+Q dLHiU9pwZ/fHXPOcWDga0o7CypevOxpTMbU7AuDZRlMc9ZkjC4/VF8lPhUIvskpawPZx i0wmnekMaVJzLv/tBlVA459lQeDZ3Fba39RigKrvIL5HvYu1mhLuXGsRmyqN5jgVt4GN tXCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iVxK7pVS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:49 -0800 Message-Id: <20180124232625.30105-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 09/45] target/hppa: Add control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/hppa/target_cpu.h | 2 +- target/hppa/cpu.h | 23 +++++++++++---- linux-user/main.c | 4 +-- linux-user/signal.c | 4 +-- target/hppa/gdbstub.c | 12 ++++---- target/hppa/mem_helper.c | 2 +- target/hppa/translate.c | 70 ++++++++++++++++++++++++++++++-------------- 7 files changed, 77 insertions(+), 40 deletions(-) -- 2.14.3 diff --git a/linux-user/hppa/target_cpu.h b/linux-user/hppa/target_cpu.h index e50522eae9..7b78bbea80 100644 --- a/linux-user/hppa/target_cpu.h +++ b/linux-user/hppa/target_cpu.h @@ -33,7 +33,7 @@ static inline void cpu_clone_regs(CPUHPPAState *env, target_ulong newsp) static inline void cpu_set_tls(CPUHPPAState *env, target_ulong newtls) { - env->cr27 = newtls; + env->cr[27] = newtls; } #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 24c728c0d2..c92c564a7f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -123,6 +123,20 @@ #define PSW_SM_W 0 #endif +#define CR_RC 0 +#define CR_SCRCCR 10 +#define CR_SAR 11 +#define CR_IVA 14 +#define CR_EIEM 15 +#define CR_IT 16 +#define CR_IIASQ 17 +#define CR_IIAOQ 18 +#define CR_IIR 19 +#define CR_ISR 20 +#define CR_IOR 21 +#define CR_IPSW 22 +#define CR_EIRR 23 + typedef struct CPUHPPAState CPUHPPAState; #if TARGET_REGISTER_BITS == 32 @@ -142,10 +156,6 @@ struct CPUHPPAState { uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ - target_ureg sar; - target_ureg cr26; - target_ureg cr27; - target_ureg psw; /* All psw bits except the following: */ target_ureg psw_n; /* boolean */ target_sreg psw_v; /* in most significant bit */ @@ -163,11 +173,12 @@ struct CPUHPPAState { target_ureg iaoq_f; /* front */ target_ureg iaoq_b; /* back, aka next instruction */ - target_ureg ior; /* interrupt offset register */ - uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; + target_ureg cr[32]; /* control registers */ + target_ureg cr_back[2]; /* back of cr17/cr18 */ + /* Those resources are used only in QEMU core */ CPU_COMMON }; diff --git a/linux-user/main.c b/linux-user/main.c index 42f4c66ce6..90ae447368 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3781,14 +3781,14 @@ void cpu_loop(CPUHPPAState *env) info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->ior; + info._sifields._sigfault._addr = env->cr[CR_IOR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; info.si_code = 0; - info._sifields._sigfault._addr = env->ior; + info._sifields._sigfault._addr = env->cr[CR_IOR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_ILL: diff --git a/linux-user/signal.c b/linux-user/signal.c index f85f0dd780..40d5d849f0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -6440,7 +6440,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUArchState *env) __put_user(env->fr[i], &sc->sc_fr[i]); } - __put_user(env->sar, &sc->sc_sar); + __put_user(env->cr[CR_SAR], &sc->sc_sar); } static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc) @@ -6461,7 +6461,7 @@ static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc) __get_user(env->iaoq_f, &sc->sc_iaoq[0]); __get_user(env->iaoq_b, &sc->sc_iaoq[1]); - __get_user(env->sar, &sc->sc_sar); + __get_user(env->cr[CR_SAR], &sc->sc_sar); } /* No, this doesn't look right, but it's copied straight from the kernel. */ diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 228d282fe9..fc27aec073 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -36,7 +36,7 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) val = env->gr[n]; break; case 32: - val = env->sar; + val = env->cr[CR_SAR]; break; case 33: val = env->iaoq_f; @@ -45,10 +45,10 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) val = env->iaoq_b; break; case 59: - val = env->cr26; + val = env->cr[26]; break; case 60: - val = env->cr27; + val = env->cr[27]; break; case 64 ... 127: val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32); @@ -89,7 +89,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->gr[n] = val; break; case 32: - env->sar = val; + env->cr[CR_SAR] = val; break; case 33: env->iaoq_f = val; @@ -98,10 +98,10 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->iaoq_b = val; break; case 59: - env->cr26 = val; + env->cr[26] = val; break; case 60: - env->cr27 = val; + env->cr[27] = val; break; case 64: env->fr[0] = deposit64(env->fr[0], 32, 32, val); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2901f3e29c..1afaf89539 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -32,7 +32,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, /* ??? Test between data page fault and data memory protection trap, which would affect si_code. */ cs->exception_index = EXCP_DMP; - cpu->env.ior = address; + cpu->env.cr[CR_IOR] = address; return 1; } #else diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 50d41b0c63..89b336c2c4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -328,8 +328,6 @@ static TCGv_reg cpu_psw_n; static TCGv_reg cpu_psw_v; static TCGv_reg cpu_psw_cb; static TCGv_reg cpu_psw_cb_msb; -static TCGv_reg cpu_cr26; -static TCGv_reg cpu_cr27; #include "exec/gen-icount.h" @@ -339,9 +337,7 @@ void hppa_translate_init(void) typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] = { - DEF_VAR(sar), - DEF_VAR(cr26), - DEF_VAR(cr27), + { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, DEF_VAR(psw_n), DEF_VAR(psw_v), DEF_VAR(psw_cb), @@ -1867,7 +1863,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) return DISAS_NORETURN; case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_mov_reg(cpu_cr27, cpu_gr[26]); + tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])); tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; @@ -1948,34 +1944,39 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, TCGv_reg tmp; switch (ctl) { - case 11: /* SAR */ + case CR_SAR: #ifdef TARGET_HPPA64 if (extract32(insn, 14, 1) == 0) { /* MFSAR without ,W masks low 5 bits. */ tmp = dest_gpr(ctx, rt); tcg_gen_andi_reg(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); - break; + goto done; } #endif save_gpr(ctx, rt, cpu_sar); - break; - case 16: /* Interval Timer */ + goto done; + case CR_IT: /* Interval Timer */ + /* FIXME: Respect PSW_S bit. */ + nullify_over(ctx); tmp = dest_gpr(ctx, rt); - tcg_gen_movi_tl(tmp, 0); /* FIXME */ + tcg_gen_movi_reg(tmp, 0); /* FIXME */ save_gpr(ctx, rt, tmp); break; case 26: - save_gpr(ctx, rt, cpu_cr26); - break; case 27: - save_gpr(ctx, rt, cpu_cr27); break; default: /* All other control registers are privileged. */ - return gen_illegal(ctx); + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + break; } + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + save_gpr(ctx, rt, tmp); + + done: cond_free(&ctx->null_cond); return DISAS_NEXT; } @@ -2011,20 +2012,45 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, { unsigned rin = extract32(insn, 16, 5); unsigned ctl = extract32(insn, 21, 5); + TCGv_reg reg = load_gpr(ctx, rin); TCGv_reg tmp; - if (ctl == 11) { /* SAR */ + if (ctl == CR_SAR) { tmp = tcg_temp_new(); - tcg_gen_andi_reg(tmp, load_gpr(ctx, rin), TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); - } else { - /* All other control registers are privileged or read-only. */ - return gen_illegal(ctx); + + cond_free(&ctx->null_cond); + return DISAS_NEXT; } - cond_free(&ctx->null_cond); - return DISAS_NEXT; + /* All other control registers are privileged or read-only. */ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + + nullify_over(ctx); + switch (ctl) { + case CR_IT: + /* ??? modify interval timer offset */ + break; + + case CR_IIASQ: + case CR_IIAOQ: + /* FIXME: Respect PSW_Q bit */ + /* The write advances the queue and stores to the back element. */ + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, + offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); + tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_reg(reg, cpu_env, + offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); + break; + + default: + tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + break; + } + return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, From patchwork Wed Jan 24 23:25:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125727 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp735090ljf; Wed, 24 Jan 2018 15:36:04 -0800 (PST) X-Google-Smtp-Source: AH8x224xhk6ZqI/xN3QPJcG5ao7DKwEQVqn7CbyPxEf4/JaObsPyBl+bKsr8pl0oAh+C5XH7+rr8 X-Received: by 10.129.120.216 with SMTP id t207mr6550851ywc.8.1516836964458; Wed, 24 Jan 2018 15:36:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836964; cv=none; d=google.com; s=arc-20160816; b=xNkQy/BT74pmFm7UnSJSPHmwUByVhdFfvn9iChFC911YdJgSu4MiQHaOZPjmhF0Qc2 lUBPwFGUyDi2hCNh66tL1xHFM4FwIqAhXn917qBe7KrKiNfTsPVh9ezU6BOBEZ509lap trdrtt3MoWK0GZkHS9Rvo7unU6wPf4Svds+J1Z7BLg9/Xs2O502o1ZXT90FxTBGL40L4 zzb6XsFnFOzIAyAUhw7+T/SxPHmkFR8XSMSMGOEG1bvgiO9x02QcqnoO1tdhnakOc0sF S26+iuSm4h7G6KaT8uPqUYksixMg30OUEGZo0ZbAU93+lF6MWAFSxiAaZcOi4byv3gRX 76CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=4cqttb91gExKzUzwYTJJ0VdaDdFF9NoJxDPY3zpOHAU=; b=mKvC7A/QeYvUD3jSY8pYKC0rxBqNbusHSHbSj4Mh0lnlD1/J2Cax2bWMs1JNfiFM8Y TynS8XlOHV1ZsYt8vKqUMte+7uuw/CJRZx1Rhu76pxHeggiPNMyjxCqkf0yte9rPcR0k okdVfwrZ9gpAYXio+S+7iP+UuLjc1jGIR6rGk7VApjF8xDeVLtiJBFjMRmAUrVgrODBr ZhKZUIa06Sk8AC66kTwC3cZvR1sxDBD4XN4zEAyUm3egBi6t2ZPzgM30Fsmhx0PPkn9O oa6huLVGiEi7SXAC4c8HSiYVOoj850uo3MF+sVuq0mhAgRJa0cgTOnW9SPHpTSiRQb7B 8jSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=brH+ZW3K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 10/45] target/hppa: Adjust insn mask for mfctl, w X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While the E bit is only used for pa2.0 mfctl,w from sar, the otherwise reserved bit does not appear to be decoded. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 89b336c2c4..8ca58f3df3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2162,7 +2162,7 @@ static const DisasInsn table_system[] = { { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, { 0x000014a0u, 0xffffffe0u, trans_mfia }, { 0x000004a0u, 0xffff1fe0u, trans_mfsp }, - { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, + { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, #ifndef CONFIG_USER_ONLY From patchwork Wed Jan 24 23:25:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125718 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp731312ljf; Wed, 24 Jan 2018 15:27:18 -0800 (PST) X-Google-Smtp-Source: AH8x225uL4XNPzPpm5Ak7+0HPNJPKCKcsQkF/9/znkRHjlQUlkVtwzck3sYAFUWjkvmPffhFMGtT X-Received: by 10.37.43.130 with SMTP id r124mr5867712ybr.210.1516836437985; Wed, 24 Jan 2018 15:27:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836437; cv=none; d=google.com; s=arc-20160816; b=Pwv2Y6QS12octucf/8nLc5CB9bY4CKjRaMJKldOflizpr8achNAw7frPOVrNPBg1rG dfjfNQiYuE5ccAL17bIgA5QjuNDXev0LJGKWUSe5JTQB899Mr3Nrc0fNw12ZqQP+VcXC p/TsSk25tMAFMFZZ6dv2nrC0iCVwwQU3qjOYTixEzvZjD8dtigevNvwqPIaJt9tEPgJg x+h3d32pKBRXbOIKHKzFFYMjNUxSn9KxzoJWojSDgCiMJCt8tkd0DQIhjmSrmGzMCg4w cjdzGH79urRSASgNxUrZ0R4+yJJA2APdL1EGaN+ybQEsQwcLrJ+NCox0vfKay45BDEM6 VRRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=PebevTPJ54h7rXLum6cMnnkXuvReOv6VdVnhmLEjzeE=; b=t+PF5fx9jrSRrf39nRL4tIXBdAwD4ypnnvQHV1JQRuzcpRi95QVghRxtyZKhUX+kOv dD4A5ncKzK63B9lsu4Ef1EovlUaJPuVvGkjMlR2e1PLudh6EWSuxHbAhlp1KSdp1aDbD 3BcHaviuCuFXQtCx0Z6hnFaLKFmPUqkdkZiM45Vd1ts2iielMpmKpNkaHpWA6vDmZJxb 0+oTKz+Jzecpvheu/Jnnb98JuyLJ1QDhHb8qv3dTh37tKIdoZMKMWtz0XnQPF8vuGlod c3V5Si7Ipy/ReCy7vC6A58GM1NXy2ynL5o+NiTWaU+0qvu4j+nBGG0avTVX3ZPs6lvba FV8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cTmXzzGx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 11/45] target/hppa: Implement rfi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 24 ++++++++++++++++++++++++ target/hppa/translate.c | 30 ++++++++++++++++++++++++++++-- 4 files changed, 55 insertions(+), 2 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c92c564a7f..6ec3430ae3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -178,6 +178,7 @@ struct CPUHPPAState { target_ureg cr[32]; /* control registers */ target_ureg cr_back[2]; /* back of cr17/cr18 */ + target_ureg shadow[7]; /* shadow registers */ /* Those resources are used only in QEMU core */ CPU_COMMON diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 254a4da133..79d22ae486 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -78,5 +78,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) #ifndef CONFIG_USER_ONLY +DEF_HELPER_1(rfi, void, env) +DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) #endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 1c3e043cc0..3f5dcbbca0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -614,4 +614,28 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; } + +void HELPER(rfi)(CPUHPPAState *env) +{ + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (env->psw & (PSW_I | PSW_R | PSW_Q)) { + helper_excp(env, EXCP_ILL); + } + env->iaoq_f = env->cr[CR_IIAOQ]; + env->iaoq_b = env->cr_back[1]; + cpu_hppa_put_psw(env, env->cr[CR_IPSW]); +} + +void HELPER(rfi_r)(CPUHPPAState *env) +{ + env->gr[1] = env->shadow[0]; + env->gr[8] = env->shadow[1]; + env->gr[9] = env->shadow[2]; + env->gr[16] = env->shadow[3]; + env->gr[17] = env->shadow[4]; + env->gr[24] = env->shadow[5]; + env->gr[25] = env->shadow[6]; + helper_rfi(env); +} #endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8ca58f3df3..df0bb04907 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -655,6 +655,10 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) { TCGLabel *null_lab = ctx->null_lab; + /* For NEXT, NORETURN, STALE, we can easily continue (or exit). + For UPDATED, we cannot update on the nullified path. */ + assert(status != DISAS_IAQ_N_UPDATED); + if (likely(null_lab == NULL)) { /* The current insn wasn't conditional or handled the condition applied to it without a branch, so the (new) setting of @@ -676,8 +680,6 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) gen_set_label(null_lab); ctx->null_cond = cond_make_n(); } - - assert(status != DISAS_NORETURN && status != DISAS_IAQ_N_UPDATED); if (status == DISAS_NORETURN) { status = DISAS_NEXT; } @@ -2153,6 +2155,29 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, /* Exit the TB to recognize new interrupts. */ return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); } + +static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned comp = extract32(insn, 5, 4); + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + if (comp == 5) { + gen_helper_rfi_r(cpu_env); + } else { + gen_helper_rfi(cpu_env); + } + if (ctx->base.singlestep_enabled) { + gen_excp_1(EXCP_DEBUG); + } else { + tcg_gen_exit_tb(0); + } + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_NORETURN); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_system[] = { @@ -2169,6 +2194,7 @@ static const DisasInsn table_system[] = { { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, { 0x00001860u, 0xffe0ffffu, trans_mtsm }, + { 0x00000c00u, 0xfffffe1fu, trans_rfi }, #endif }; From patchwork Wed Jan 24 23:25:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125730 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp735281ljf; Wed, 24 Jan 2018 15:36:37 -0800 (PST) X-Google-Smtp-Source: AH8x224bDE54N/1B9/5fiUcvvbtrMAijWV1pYy1EHMr8naVLvul0OuRL+UQdF0m1qVEVszWB2dVd X-Received: by 10.37.128.69 with SMTP id a5mr6534353ybn.153.1516836997055; Wed, 24 Jan 2018 15:36:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836997; cv=none; d=google.com; s=arc-20160816; b=lyTRFHeSifv1Xds8mHWMu8ur/jEemoF+1EqMpJA2s+0XgIOWwXmQz+2RlPE9gLFxgq i26F+hd8ApOJdv5o4aE4Tn3ZlYuVL5OEV+FG8/pnZ2BEBbjaKnGKtfi7ZDIXdRFdiJdi kHGvhMonD/sZwSmIlyHY9Bf/SIZeVMsTc+Gc610DOUveSnIPlYZ4WAY/wWiiGHp7ezXL DKfBDryZ/SBG8yvOEyyvVKYTOUJpk/5UTuWpx2Mh26GNwXj0Z4wy8738qpSPOCknA/zc kK22EjY3Gi+pAHddDUF3nBFnKPGXgenvnZ7wsdiFQctQ5sQdtaEGTY8QLqZXniDnqC5U LlWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ehRh7IpYE9aUdFX+lvwLZUNe4Qev1gs40Bf4m1i72VM=; b=C/I5p4u8POWJ1ladyufEuA50XyKjwOFRf8B9cv8zV5Q+rnCmIITM/mVeOIuU1hdYjq oXiZkTkBoYNxaocl8CZwerKyyUGVWPBnBdCfbl6UjCrfyvltqcZUjnoCj9CQ/fYvik4D L+1QeKE4YfmVyr1ypV5cNzwnwAgZhaRNtVibB3tuv62b8ej5Do3TXGvESGNwfanqoqoA tgSlA5vPjSOv8DbLS3XTKkzJx03pKPbGTnuSDzBN47T+JeCKw8WF2P4X8+xLxriuFyAA +txqm6NilZqsGHFJED5fSVXgsu6PnMEX0sAJhlYH5+d0zojhgCeMX/v1Duk+R73hXGpa tVMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B69WmBR9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 12/45] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 2 + target/hppa/helper.c | 63 ----------------- target/hppa/int_helper.c | 176 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++- target/hppa/Makefile.objs | 1 + 5 files changed, 192 insertions(+), 66 deletions(-) create mode 100644 target/hppa/int_helper.c -- 2.14.3 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9962ab71ee..ca619578dd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -106,8 +106,10 @@ static void hppa_cpu_initfn(Object *obj) CPUHPPAState *env = &cpu->env; cs->env_ptr = env; + cs->exception_index = -1; cpu_hppa_loaded_fr0(env); set_snan_bit_is_one(true, &env->fp_status); + cpu_hppa_put_psw(env, PSW_W); } static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 48ac80cb2d..6e8758f82c 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -67,69 +67,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) env->psw_cb = cb; } -void hppa_cpu_do_interrupt(CPUState *cs) -{ - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; - int i = cs->exception_index; - - if (qemu_loglevel_mask(CPU_LOG_INT)) { - static const char * const names[] = { - [EXCP_HPMC] = "high priority machine check", - [EXCP_POWER_FAIL] = "power fail interrupt", - [EXCP_RC] = "recovery counter trap", - [EXCP_EXT_INTERRUPT] = "external interrupt", - [EXCP_LPMC] = "low priority machine check", - [EXCP_ITLB_MISS] = "instruction tlb miss fault", - [EXCP_IMP] = "instruction memory protection trap", - [EXCP_ILL] = "illegal instruction trap", - [EXCP_BREAK] = "break instruction trap", - [EXCP_PRIV_OPR] = "privileged operation trap", - [EXCP_PRIV_REG] = "privileged register trap", - [EXCP_OVERFLOW] = "overflow trap", - [EXCP_COND] = "conditional trap", - [EXCP_ASSIST] = "assist exception trap", - [EXCP_DTLB_MISS] = "data tlb miss fault", - [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss", - [EXCP_NA_DTLB_MISS] = "non-access data tlb miss", - [EXCP_DMP] = "data memory protection trap", - [EXCP_DMB] = "data memory break trap", - [EXCP_TLB_DIRTY] = "tlb dirty bit trap", - [EXCP_PAGE_REF] = "page reference trap", - [EXCP_ASSIST_EMU] = "assist emulation trap", - [EXCP_HPT] = "high-privilege transfer trap", - [EXCP_LPT] = "low-privilege transfer trap", - [EXCP_TB] = "taken branch trap", - [EXCP_DMAR] = "data memory access rights trap", - [EXCP_DMPI] = "data memory protection id trap", - [EXCP_UNALIGN] = "unaligned data reference trap", - [EXCP_PER_INTERRUPT] = "performance monitor interrupt", - [EXCP_SYSCALL] = "syscall", - [EXCP_SYSCALL_LWS] = "syscall-lws", - }; - static int count; - const char *name = NULL; - - if (i >= 0 && i < ARRAY_SIZE(names)) { - name = names[i]; - } - if (name) { - qemu_log("INT %6d: %s ia_f=" TARGET_FMT_lx "\n", - ++count, name, env->iaoq_f); - } else { - qemu_log("INT %6d: unknown %d ia_f=" TARGET_FMT_lx "\n", - ++count, i, env->iaoq_f); - } - } - cs->exception_index = -1; -} - -bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - abort(); - return false; -} - void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c new file mode 100644 index 0000000000..a59aae1189 --- /dev/null +++ b/target/hppa/int_helper.c @@ -0,0 +1,176 @@ +/* + * HPPA interrupt helper routines + * + * Copyright (c) 2017 Richard Henderson + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qom/cpu.h" + + +void hppa_cpu_do_interrupt(CPUState *cs) +{ + HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = &cpu->env; + int i = cs->exception_index; + target_ureg iaoq_f = env->iaoq_f; + target_ureg iaoq_b = env->iaoq_b; + +#ifndef CONFIG_USER_ONLY + target_ureg old_psw; + + /* As documented in pa2.0 -- interruption handling. */ + /* step 1 */ + env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); + + /* step 2 -- note PSW_W == 0 for !HPPA64. */ + cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0)); + + /* step 3 */ + env->cr[CR_IIAOQ] = iaoq_f; + env->cr_back[1] = iaoq_b; + + if (old_psw & PSW_Q) { + /* step 5 */ + /* ISR and IOR will be set elsewhere. */ + switch (i) { + case EXCP_ILL: + case EXCP_BREAK: + case EXCP_PRIV_REG: + case EXCP_PRIV_OPR: + /* IIR set via translate.c. */ + break; + + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_DMAR: + case EXCP_DMPI: + case EXCP_UNALIGN: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_TLB_DIRTY: + case EXCP_PAGE_REF: + case EXCP_ASSIST_EMU: + { + /* Avoid reading directly from the virtual address, lest we + raise another exception from some sort of TLB issue. */ + vaddr vaddr; + hwaddr paddr; + + paddr = vaddr = iaoq_f & -4; + env->cr[CR_IIR] = ldl_phys(cs->as, paddr); + } + break; + + default: + /* Other exceptions do not set IIR. */ + break; + } + + /* step 6 */ + env->shadow[0] = env->gr[1]; + env->shadow[1] = env->gr[8]; + env->shadow[2] = env->gr[9]; + env->shadow[3] = env->gr[16]; + env->shadow[4] = env->gr[17]; + env->shadow[5] = env->gr[24]; + env->shadow[6] = env->gr[25]; + } + + /* step 7 */ + env->iaoq_f = env->cr[CR_IVA] + 32 * i; + env->iaoq_b = env->iaoq_f + 4; +#endif + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + static const char * const names[] = { + [EXCP_HPMC] = "high priority machine check", + [EXCP_POWER_FAIL] = "power fail interrupt", + [EXCP_RC] = "recovery counter trap", + [EXCP_EXT_INTERRUPT] = "external interrupt", + [EXCP_LPMC] = "low priority machine check", + [EXCP_ITLB_MISS] = "instruction tlb miss fault", + [EXCP_IMP] = "instruction memory protection trap", + [EXCP_ILL] = "illegal instruction trap", + [EXCP_BREAK] = "break instruction trap", + [EXCP_PRIV_OPR] = "privileged operation trap", + [EXCP_PRIV_REG] = "privileged register trap", + [EXCP_OVERFLOW] = "overflow trap", + [EXCP_COND] = "conditional trap", + [EXCP_ASSIST] = "assist exception trap", + [EXCP_DTLB_MISS] = "data tlb miss fault", + [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss", + [EXCP_NA_DTLB_MISS] = "non-access data tlb miss", + [EXCP_DMP] = "data memory protection trap", + [EXCP_DMB] = "data memory break trap", + [EXCP_TLB_DIRTY] = "tlb dirty bit trap", + [EXCP_PAGE_REF] = "page reference trap", + [EXCP_ASSIST_EMU] = "assist emulation trap", + [EXCP_HPT] = "high-privilege transfer trap", + [EXCP_LPT] = "low-privilege transfer trap", + [EXCP_TB] = "taken branch trap", + [EXCP_DMAR] = "data memory access rights trap", + [EXCP_DMPI] = "data memory protection id trap", + [EXCP_UNALIGN] = "unaligned data reference trap", + [EXCP_PER_INTERRUPT] = "performance monitor interrupt", + [EXCP_SYSCALL] = "syscall", + [EXCP_SYSCALL_LWS] = "syscall-lws", + }; + static int count; + const char *name = NULL; + char unknown[16]; + + if (i >= 0 && i < ARRAY_SIZE(names)) { + name = names[i]; + } + if (!name) { + snprintf(unknown, sizeof(unknown), "unknown %d", i); + name = unknown; + } + qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx + " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", + ++count, name, + (target_ulong)iaoq_f, + (target_ulong)iaoq_b, + env->iaoq_f, + (target_ulong)env->cr[CR_IOR]); + } + cs->exception_index = -1; +} + +bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ +#ifndef CONFIG_USER_ONLY + HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = &cpu->env; + + /* If interrupts are requested and enabled, raise them. */ + if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { + cs->exception_index = EXCP_EXT_INTERRUPT; + hppa_cpu_do_interrupt(cs); + return true; + } +#endif + return false; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index df0bb04907..34b999fb2c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -282,6 +282,7 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; + uint32_t insn; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -716,17 +717,25 @@ static DisasJumpType gen_excp(DisasContext *ctx, int exception) return DISAS_NORETURN; } +static DisasJumpType gen_excp_iir(DisasContext *ctx, int exc) +{ + TCGv_reg tmp = tcg_const_reg(ctx->insn); + tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); + tcg_temp_free(tmp); + return gen_excp(ctx, exc); +} + static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_ILL)); } #define CHECK_MOST_PRIVILEGED(EXCP) \ do { \ if (ctx->privilege != 0) { \ nullify_over(ctx); \ - return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + return nullify_end(ctx, gen_excp_iir(ctx, EXCP)); \ } \ } while (0) @@ -1893,7 +1902,7 @@ static DisasJumpType trans_break(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_BREAK)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_BREAK)); } static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, @@ -4270,6 +4279,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->null_cond.c = TCG_COND_NEVER; ret = DISAS_NEXT; } else { + ctx->insn = insn; ret = translate_one(ctx, insn); assert(ctx->null_lab == NULL); } diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index d89285307b..dcd60a6839 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1,2 @@ obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o +obj-y += int_helper.o From patchwork Wed Jan 24 23:25:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125719 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp731642ljf; Wed, 24 Jan 2018 15:28:15 -0800 (PST) X-Google-Smtp-Source: AH8x227sOiznMmfylNbNGS+uDRZWCX0TRhHnomgwlXtPvabGHhk3nZ2pZvOXPMcRcfwPDtlCWhKa X-Received: by 10.129.155.78 with SMTP id s75mr6833597ywg.358.1516836495484; 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:53 -0800 Message-Id: <20180124232625.30105-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 13/45] target/hppa: Implement unaligned access trap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ca619578dd..4d0b760baa 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -48,6 +48,23 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) info->print_insn = print_insn_hppa; } +static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = &cpu->env; + + cs->exception_index = EXCP_UNALIGN; + if (env->psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + env->cr[CR_IOR] = addr; + env->cr[CR_ISR] = addr >> 32; + } + + cpu_loop_exit_restore(cs, retaddr); +} + static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -139,7 +156,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) #else cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; #endif - + cc->do_unaligned_access = hppa_cpu_do_unaligned_access; cc->disas_set_info = hppa_cpu_disas_set_info; cc->tcg_initialize = hppa_translate_init; From patchwork Wed Jan 24 23:25:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125745 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp739987ljf; Wed, 24 Jan 2018 15:47:55 -0800 (PST) X-Google-Smtp-Source: AH8x2246EwHVg2E1MpnwUexRA32LT9tNyPHLSp5mrXgnkNZpVcLUhF6wK5+6kw+E0vYoc1LxFhNo X-Received: by 10.37.221.195 with SMTP id u186mr6707737ybg.154.1516837675423; Wed, 24 Jan 2018 15:47:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837675; cv=none; d=google.com; s=arc-20160816; b=znvkZavRX+jalt/y81l6NkbDWTw2z+h104+k7MzT26Yf8RY+yrVt4E7OyfCLmJgG6V 6mFGN//ngd5rPBd0piQu9juEcI0Z1oljNvyUDhziH/ZHahiBXExGnyzL4Jva2H1Tm1vV oxg0ckACRQN8l6X/Hmqj4/AvtUZCK3Hbguj2gfVybcBGOPUnZBACItFP2Nv+XW58UXAK bCH0VoXYoSJRA1rU/IiBMc9zZhLAXhsro/++VrpWDDhVN/pauvbpf8O28TnVYwS4XEhP fYDjxjn5EEu0S+mjyrcSUPQUdifmIfdmT5ETfo4pZKtmQ8GGxKp/LftWzLC7P7HpWBdU 4u1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=CJugC0HTqccstHjqeSWo1FHBhIo7Tmfaw+q9yecCg08=; b=N7v+ZAlOILhpZosfq7L0dMW7cu7vI0uYXrNQGfRERYbGPYfC+a2ybODNjnPLh078e+ 7wTXZLp9iIqquGzYVpxo4x5OjbAc+x/2ENjEtPNfSkIPnJ2MdrUYEyk9sdm9Xh5ZvJaq aI0ePeOsP0UxAdm7xJcoESYsTgdhE6CDyDTs7l7WDyZ45nn9NZIc58p30t3iSB5hhJbf lsuKm9DkjWeO6CRL7Q+5N4kre05H84dxP2PdP9nRNADLvXRyG07DFtPCw0cC2o+wviSh WL1wpV23q8hujnYXjFVeQQCAHpq+6LZYBnddMamSUfoGdGP9Utx/2LQeSpMmM3H9LI6l ocVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZFZQbIOJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:54 -0800 Message-Id: <20180124232625.30105-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 14/45] target/hppa: Use space registers in data operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This changes the system virtual address width to 64-bit and incorporates the space registers into load/store operations. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 14 ++ target/hppa/translate.c | 334 +++++++++++++++++++++++++++--------------------- 2 files changed, 201 insertions(+), 147 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6ec3430ae3..94f9c8ca2b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,10 +23,24 @@ #include "qemu-common.h" #include "cpu-qom.h" +#ifdef TARGET_HPPA64 +#define TARGET_LONG_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define TARGET_REGISTER_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#elif defined(CONFIG_USER_ONLY) #define TARGET_LONG_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #define TARGET_REGISTER_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32 +#else +/* In order to form the GVA from space:offset, + we need a 64-bit virtual address space. */ +#define TARGET_LONG_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define TARGET_REGISTER_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#endif #define CPUArchState struct CPUHPPAState diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 34b999fb2c..6be9e0c3ff 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -276,8 +276,9 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; - int ntemps; - TCGv_reg temps[8]; + int ntempr, ntempl; + TCGv_reg tempr[4]; + TCGv_tl templ[4]; DisasCond null_cond; TCGLabel *null_lab; @@ -458,11 +459,20 @@ static void cond_free(DisasCond *cond) static TCGv_reg get_temp(DisasContext *ctx) { - unsigned i = ctx->ntemps++; - g_assert(i < ARRAY_SIZE(ctx->temps)); - return ctx->temps[i] = tcg_temp_new(); + unsigned i = ctx->ntempr++; + g_assert(i < ARRAY_SIZE(ctx->tempr)); + return ctx->tempr[i] = tcg_temp_new(); } +#ifndef CONFIG_USER_ONLY +static TCGv_tl get_temp_tl(DisasContext *ctx) +{ + unsigned i = ctx->ntempl++; + g_assert(i < ARRAY_SIZE(ctx->templ)); + return ctx->templ[i] = tcg_temp_new_tl(); +} +#endif + static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { TCGv_reg t = get_temp(ctx); @@ -1324,6 +1334,70 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, return DISAS_NEXT; } +#ifndef CONFIG_USER_ONLY +/* Top 2 bits of the base register select sp[4-7]. */ +static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) +{ + TCGv_ptr ptr; + TCGv_reg tmp; + TCGv_i64 spc; + + if (sp != 0) { + return cpu_sr[sp]; + } + + ptr = tcg_temp_new_ptr(); + tmp = tcg_temp_new(); + spc = get_temp_tl(ctx); + + tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + tcg_gen_andi_reg(tmp, tmp, 030); + tcg_gen_trunc_reg_ptr(ptr, tmp); + tcg_temp_free(tmp); + + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); + tcg_temp_free_ptr(ptr); + + return spc; +} +#endif + +static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, + unsigned rb, unsigned rx, int scale, target_sreg disp, + unsigned sp, int modify, bool is_phys) +{ + TCGv_reg base = load_gpr(ctx, rb); + TCGv_reg ofs; + + /* Note that RX is mutually exclusive with DISP. */ + if (rx) { + ofs = get_temp(ctx); + tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); + tcg_gen_add_reg(ofs, ofs, base); + } else if (disp || modify) { + ofs = get_temp(ctx); + tcg_gen_addi_reg(ofs, base, disp); + } else { + ofs = base; + } + + *pofs = ofs; +#ifdef CONFIG_USER_ONLY + *pgva = (modify <= 0 ? ofs : base); +#else + TCGv_tl addr = get_temp_tl(ctx); + tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); + if (ctx->base.tb->flags & PSW_W) { + tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); + } + if (!is_phys) { + tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); + } + *pgva = addr; +#endif +} + /* Emit a memory load. The modify parameter should be * < 0 for pre-modify, * > 0 for post-modify, @@ -1331,118 +1405,74 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - if (modify == 0) { - tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop); - } else { - tcg_gen_qemu_ld_i32(dest, (modify < 0 ? addr : base), - ctx->mmu_idx, mop); - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - if (modify == 0) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); - } else { - tcg_gen_qemu_ld_i64(dest, (modify < 0 ? addr : base), - ctx->mmu_idx, mop); - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - tcg_gen_qemu_st_i32(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); - - if (modify != 0) { - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { - TCGv_reg addr, base; + TCGv_reg ofs; + TCGv_tl addr; /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c == TCG_COND_NEVER); - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - - /* Note that RX is mutually exclusive with DISP. */ - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - - tcg_gen_qemu_st_i64(src, (modify <= 0 ? addr : base), ctx->mmu_idx, mop); - - if (modify != 0) { - save_gpr(ctx, rb, addr); + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + if (modify) { + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); } #if TARGET_REGISTER_BITS == 64 @@ -1455,7 +1485,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify, TCGMemOp mop) + unsigned sp, int modify, TCGMemOp mop) { TCGv_reg dest; @@ -1468,7 +1498,7 @@ static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, /* Make sure if RT == RB, we see the result of the load. */ dest = get_temp(ctx); } - do_load_reg(ctx, dest, rb, rx, scale, disp, modify, mop); + do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); @@ -1476,14 +1506,14 @@ static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i32 tmp; nullify_over(ctx); tmp = tcg_temp_new_i32(); - do_load_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); + do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); save_frw_i32(rt, tmp); tcg_temp_free_i32(tmp); @@ -1496,14 +1526,14 @@ static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i64 tmp; nullify_over(ctx); tmp = tcg_temp_new_i64(); - do_load_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); + do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); save_frd(rt, tmp); tcg_temp_free_i64(tmp); @@ -1515,23 +1545,24 @@ static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, } static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_sreg disp, int modify, TCGMemOp mop) + target_sreg disp, unsigned sp, + int modify, TCGMemOp mop) { nullify_over(ctx); - do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); + do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); return nullify_end(ctx, DISAS_NEXT); } static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i32 tmp; nullify_over(ctx); tmp = load_frw_i32(rt); - do_store_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); + do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); tcg_temp_free_i32(tmp); return nullify_end(ctx, DISAS_NEXT); @@ -1539,14 +1570,14 @@ static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - int modify) + unsigned sp, int modify) { TCGv_i64 tmp; nullify_over(ctx); tmp = load_frd(rt); - do_store_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); + do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); tcg_temp_free_i64(tmp); return nullify_end(ctx, DISAS_NEXT); @@ -2228,18 +2259,21 @@ static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); + unsigned sp = extract32(insn, 14, 2); unsigned rb = extract32(insn, 21, 5); unsigned is_write = extract32(insn, 6, 1); - TCGv_reg dest; + TCGv_reg dest, ofs; + TCGv_tl addr; nullify_over(ctx); /* ??? Do something with priv level operand. */ dest = dest_gpr(ctx, rt); + form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); if (is_write) { - gen_helper_probe_w(dest, load_gpr(ctx, rb)); + gen_helper_probe_w(dest, addr); } else { - gen_helper_probe_r(dest, load_gpr(ctx, rb)); + gen_helper_probe_r(dest, addr); } save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); @@ -2628,12 +2662,13 @@ static DisasJumpType trans_ld_idx_i(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned sz = extract32(insn, 6, 2); unsigned a = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); int disp = low_sextract(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); int modify = (m ? (a ? -1 : 1) : 0); TCGMemOp mop = MO_TE | sz; - return do_load(ctx, rt, rb, 0, 0, disp, modify, mop); + return do_load(ctx, rt, rb, 0, 0, disp, sp, modify, mop); } static DisasJumpType trans_ld_idx_x(DisasContext *ctx, uint32_t insn, @@ -2643,11 +2678,12 @@ static DisasJumpType trans_ld_idx_x(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned sz = extract32(insn, 6, 2); unsigned u = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); TCGMemOp mop = MO_TE | sz; - return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, m, mop); + return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, sp, m, mop); } static DisasJumpType trans_st_idx_i(DisasContext *ctx, uint32_t insn, @@ -2657,12 +2693,13 @@ static DisasJumpType trans_st_idx_i(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned sz = extract32(insn, 6, 2); unsigned a = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rr = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); int modify = (m ? (a ? -1 : 1) : 0); TCGMemOp mop = MO_TE | sz; - return do_store(ctx, rr, rb, disp, modify, mop); + return do_store(ctx, rr, rb, disp, sp, modify, mop); } static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, @@ -2672,16 +2709,16 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, unsigned m = extract32(insn, 5, 1); unsigned i = extract32(insn, 12, 1); unsigned au = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); TCGMemOp mop = MO_TEUL | MO_ALIGN_16; - TCGv_reg zero, addr, base, dest; + TCGv_reg zero, dest, ofs; + TCGv_tl addr; int modify, disp = 0, scale = 0; nullify_over(ctx); - /* ??? Share more code with do_load and do_load_{32,64}. */ - if (i) { modify = (m ? (au ? -1 : 1) : 0); disp = low_sextract(rx, 0, 5); @@ -2693,27 +2730,19 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, } } if (modify) { - /* Base register modification. Make sure if RT == RB, we see - the result of the load. */ + /* Base register modification. Make sure if RT == RB, + we see the result of the load. */ dest = get_temp(ctx); } else { dest = dest_gpr(ctx, rt); } - addr = tcg_temp_new(); - base = load_gpr(ctx, rb); - if (rx) { - tcg_gen_shli_reg(addr, cpu_gr[rx], scale); - tcg_gen_add_reg(addr, addr, base); - } else { - tcg_gen_addi_reg(addr, base, disp); - } - + form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, + ctx->mmu_idx == MMU_PHYS_IDX); zero = tcg_const_reg(0); - tcg_gen_atomic_xchg_reg(dest, (modify <= 0 ? addr : base), - zero, ctx->mmu_idx, mop); + tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); if (modify) { - save_gpr(ctx, rb, addr); + save_gpr(ctx, rb, ofs); } save_gpr(ctx, rt, dest); @@ -2726,20 +2755,17 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, target_sreg disp = low_sextract(insn, 0, 5); unsigned m = extract32(insn, 5, 1); unsigned a = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rt = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); - TCGv_reg addr, val; + TCGv_reg ofs, val; + TCGv_tl addr; nullify_over(ctx); - addr = tcg_temp_new(); - if (m || disp == 0) { - tcg_gen_mov_reg(addr, load_gpr(ctx, rb)); - } else { - tcg_gen_addi_reg(addr, load_gpr(ctx, rb), disp); - } + form_gva(ctx, &addr, &ofs, rb, 0, 0, disp, sp, m, + ctx->mmu_idx == MMU_PHYS_IDX); val = load_gpr(ctx, rt); - if (a) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { gen_helper_stby_e_parallel(cpu_env, addr, val); @@ -2755,11 +2781,9 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, } if (m) { - tcg_gen_addi_reg(addr, addr, disp); - tcg_gen_andi_reg(addr, addr, ~3); - save_gpr(ctx, rb, addr); + tcg_gen_andi_reg(ofs, ofs, ~3); + save_gpr(ctx, rb, ofs); } - tcg_temp_free(addr); return nullify_end(ctx, DISAS_NEXT); } @@ -2824,15 +2848,18 @@ static DisasJumpType trans_load(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16(insn); - return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); + return do_load(ctx, rt, rb, 0, 0, i, sp, + is_mod ? (i < 0 ? -1 : 1) : 0, mop); } static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); @@ -2840,11 +2867,11 @@ static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) case 0: case 1: /* FLDW without modification. */ - return do_floadw(ctx, ext2 * 32 + rt, rb, 0, 0, i, 0); + return do_floadw(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: /* LDW with modification. Note that the sign of I selects post-dec vs pre-inc. */ - return do_load(ctx, rt, rb, 0, 0, i, (i < 0 ? 1 : -1), MO_TEUL); + return do_load(ctx, rt, rb, 0, 0, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); } @@ -2855,11 +2882,12 @@ static DisasJumpType trans_fload_mod(DisasContext *ctx, uint32_t insn) target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); + unsigned sp = extract32(insn, 14, 2); unsigned t0 = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); /* FLDW with modification. */ - return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); + return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1)); } static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, @@ -2867,15 +2895,17 @@ static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16(insn); - return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); + return do_store(ctx, rt, rb, i, sp, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); + unsigned sp = extract32(insn, 14, 2); target_sreg i = assemble_16a(insn); unsigned ext2 = extract32(insn, 1, 2); @@ -2883,10 +2913,10 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) case 0: case 1: /* FSTW without modification. */ - return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, 0); + return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: /* LDW with modification. */ - return do_store(ctx, rt, rb, i, (i < 0 ? 1 : -1), MO_TEUL); + return do_store(ctx, rt, rb, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); } @@ -2897,11 +2927,12 @@ static DisasJumpType trans_fstore_mod(DisasContext *ctx, uint32_t insn) target_sreg i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); unsigned a = extract32(insn, 2, 1); + unsigned sp = extract32(insn, 14, 2); unsigned t0 = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); /* FSTW with modification. */ - return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); + return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1)); } static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) @@ -2913,6 +2944,7 @@ static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) /* unsigned cc = extract32(insn, 10, 2); */ unsigned i = extract32(insn, 12, 1); unsigned ua = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); unsigned rt = t1 * 32 + t0; @@ -2932,9 +2964,9 @@ static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) switch (ext3) { case 0: /* FLDW */ - return do_floadw(ctx, rt, rb, rx, scale, disp, modify); + return do_floadw(ctx, rt, rb, rx, scale, disp, sp, modify); case 4: /* FSTW */ - return do_fstorew(ctx, rt, rb, rx, scale, disp, modify); + return do_fstorew(ctx, rt, rb, rx, scale, disp, sp, modify); } return gen_illegal(ctx); } @@ -2947,6 +2979,7 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) /* unsigned cc = extract32(insn, 10, 2); */ unsigned i = extract32(insn, 12, 1); unsigned ua = extract32(insn, 13, 1); + unsigned sp = extract32(insn, 14, 2); unsigned rx = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); int modify = (m ? (ua ? -1 : 1) : 0); @@ -2965,9 +2998,9 @@ static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) switch (ext4) { case 0: /* FLDD */ - return do_floadd(ctx, rt, rb, rx, scale, disp, modify); + return do_floadd(ctx, rt, rb, rx, scale, disp, sp, modify); case 8: /* FSTD */ - return do_fstored(ctx, rt, rb, rx, scale, disp, modify); + return do_fstored(ctx, rt, rb, rx, scale, disp, sp, modify); default: return gen_illegal(ctx); } @@ -4208,8 +4241,10 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; bound = MIN(max_insns, bound); - ctx->ntemps = 0; - memset(ctx->temps, 0, sizeof(ctx->temps)); + ctx->ntempr = 0; + ctx->ntempl = 0; + memset(ctx->tempr, 0, sizeof(ctx->tempr)); + memset(ctx->templ, 0, sizeof(ctx->templ)); return bound; } @@ -4286,11 +4321,16 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } /* Free any temporaries allocated. */ - for (i = 0, n = ctx->ntemps; i < n; ++i) { - tcg_temp_free(ctx->temps[i]); - ctx->temps[i] = NULL; + for (i = 0, n = ctx->ntempr; i < n; ++i) { + tcg_temp_free(ctx->tempr[i]); + ctx->tempr[i] = NULL; + } + for (i = 0, n = ctx->ntempl; i < n; ++i) { + tcg_temp_free_tl(ctx->templ[i]); + ctx->templ[i] = NULL; } - ctx->ntemps = 0; + ctx->ntempr = 0; + ctx->ntempl = 0; /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ @@ -4400,7 +4440,7 @@ void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb, target_ulong *data) { env->iaoq_f = data[0]; - if (data[1] != -1) { + if (data[1] != (target_ureg)-1) { env->iaoq_b = data[1]; } /* Since we were executing the instruction at IAOQ_F, and took some From patchwork Wed Jan 24 23:25:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125738 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp737660ljf; Wed, 24 Jan 2018 15:42:46 -0800 (PST) X-Google-Smtp-Source: AH8x224oYVL7Gg5X86m28aiP/BvgNtd1jLZcLqMRcVxEPIFBCbTAj14L2/pTexyjiN1O6VIpGBYf X-Received: by 10.129.161.202 with SMTP id y193mr7141034ywg.228.1516837366264; Wed, 24 Jan 2018 15:42:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837366; cv=none; d=google.com; s=arc-20160816; b=F6teW/0dClJl9zzyVhewy3gOrN+QnUs81sxfaRZpV2auKK82IHKOXLWXEmHFPFYvzR 1f4n38RNjoWueBZYcMvtC43ZFzbnc3GL+n01d82yqeW+WlM/s4wqR3K1MlQd93ufz+RN bFvjtfGqoFpJ7wlQ+QEKMo7lKsqn43gbrwyVo0aOFdXPKvllUL44I9oLsgS3X1qqlQjK 4hTdpUv/kl15SRhmj64gCwCK8Q12bGvGblbCVkf9CSvuYs2PaGS1HmN87Qw01/Gbzov0 cwFA+yoiL+gm9Wd+GB/fMJMKVFVKjRx/gRHw5ue0hNTbiX3i8r1kkgCwTc5wO9JhYBwE Yfzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=R7Enyxbsmc64EfsW5JScMt9UKiAW8/F8PsYnC3AJCUE=; b=rA8y2oGW3VTTUVJn6rFaFHGwWQkm4HRmlR35lLDpI60SboXa617sy64LLXMiot79aj VLNVEjTrcL/blD2LK3VHHcRDPAGC6LMwSGXjcUMVOn4bhQr+OUbzqF/JKvjx8q6gOtK4 pLBEaDdDixTuIVZKfo9ZEtZhvx9uXv2BwgTLGhXIJ6joT4+TBFV6f6ISKuUnk0YZxF3K R+fQR/G2OOjj/Lr97YGjpj2131gqH5kK8CftG+ngGKDIRBC7MsGJztNOVfgK63W65mTm aRr8Q2uY73ljDuqH9DD4QeTgR4stxjQEtoz/IQ4dntxhtLx1+XDaPWzJa0LAypCdlwCD H04A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=K1oZ4V/k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:55 -0800 Message-Id: <20180124232625.30105-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 15/45] target/hppa: Avoid privilege level decrease during branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These instructions force the destination privilege level of the branch destination to be no higher than current. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 5 deletions(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6be9e0c3ff..4a69f05a91 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1862,6 +1862,40 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv_reg dest, return DISAS_NEXT; } +/* Implement + * if (IAOQ_Front{30..31} < GR[b]{30..31}) + * IAOQ_Next{30..31} ← GR[b]{30..31}; + * else + * IAOQ_Next{30..31} ← IAOQ_Front{30..31}; + * which keeps the privilege level from being increased. + */ +static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) +{ +#ifdef CONFIG_USER_ONLY + return offset; +#else + TCGv_reg dest; + switch (ctx->privilege) { + case 0: + /* Privilege 0 is maximum and is allowed to decrease. */ + return offset; + case 3: + /* Privilege 3 is minimum and is never allowed increase. */ + dest = get_temp(ctx); + tcg_gen_ori_reg(dest, offset, 3); + break; + default: + dest = tcg_temp_new(); + tcg_gen_andi_reg(dest, offset, -4); + tcg_gen_ori_reg(dest, dest, ctx->privilege); + tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset); + tcg_temp_free(dest); + break; + } + return dest; +#endif +} + #ifdef CONFIG_USER_ONLY /* On Linux, page zero is normally marked execute only + gateway. Therefore normal read or write is supposed to fail, but specific @@ -3441,6 +3475,7 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) unsigned n = extract32(insn, 1, 1); unsigned b = extract32(insn, 21, 5); target_sreg disp = assemble_17(insn); + TCGv_reg tmp; /* unsigned s = low_uextract(insn, 13, 3); */ /* ??? It seems like there should be a good way of using @@ -3449,16 +3484,19 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) manage along side branch delay slots. Therefore we handle entry into the gateway page via absolute address. */ +#ifdef CONFIG_USER_ONLY /* Since we don't implement spaces, just branch. Do notice the special case of "be disp(*,r0)" using a direct branch to disp, so that we can goto_tb to the TB containing the syscall. */ if (b == 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); - } else { - TCGv_reg tmp = get_temp(ctx); - tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); - return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } +#endif + + tmp = get_temp(ctx); + tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); + tmp = do_ibranch_priv(ctx, tmp); + return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); } static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, @@ -3490,6 +3528,7 @@ static DisasJumpType trans_blr(DisasContext *ctx, uint32_t insn, tcg_gen_shli_reg(tmp, load_gpr(ctx, rx), 3); tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); + /* The computation here never changes privilege level. */ return do_ibranch(ctx, tmp, link, n); } @@ -3508,6 +3547,7 @@ static DisasJumpType trans_bv(DisasContext *ctx, uint32_t insn, tcg_gen_shli_reg(dest, load_gpr(ctx, rx), 3); tcg_gen_add_reg(dest, dest, load_gpr(ctx, rb)); } + dest = do_ibranch_priv(ctx, dest); return do_ibranch(ctx, dest, 0, n); } @@ -3517,8 +3557,10 @@ static DisasJumpType trans_bve(DisasContext *ctx, uint32_t insn, unsigned n = extract32(insn, 1, 1); unsigned rb = extract32(insn, 21, 5); unsigned link = extract32(insn, 13, 1) ? 2 : 0; + TCGv_reg dest; - return do_ibranch(ctx, load_gpr(ctx, rb), link, n); + dest = do_ibranch_priv(ctx, load_gpr(ctx, rb)); + return do_ibranch(ctx, dest, link, n); } static const DisasInsn table_branch[] = { From patchwork Wed Jan 24 23:25:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125722 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp732424ljf; Wed, 24 Jan 2018 15:30:20 -0800 (PST) X-Google-Smtp-Source: AH8x225Et3YKvqD9Xkk9wF7HBrv49EGeY4IOiA9bO9cgWaTnz/CvHQz6O4+bgmci+RdqHDURbUiy X-Received: by 10.37.211.11 with SMTP id e11mr7067168ybf.243.1516836620470; Wed, 24 Jan 2018 15:30:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836620; cv=none; d=google.com; s=arc-20160816; b=YHlcR2dNX2mqwNXYJc/ggS7Rqk8pwDa9AYsjXvKdIGzzAZ9Giuc1HdvZ8xRvLIZr9Y TdHO2tUJlVqsY3BXf8/66bMq16z+kwasejNhxhIwjJG5fXu8mHOvTrecUAX0kZgVaWFe 2ll5OzGlPd+o8/yasKcYGbs2hnb94uEIkOotIatby8fANX/mFv2qNfBV8QT4l2l/hShj o67PO0mKWsnQArBlmIVWwSyQ9LS2tOYFBrBg1eTytKCPKyz+a5buOi4sfuh3Y06gNg5o rnakbJojXST14jajwSPocUtel26DpKmyHXLYhmSlfDOgDYYEnQFz2zhtsaeZ9AOcT2Km 1mXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=p+QD+b6Cw+XW39YAD69NZNQ9QvIBR9apORbL4Kd/U/Y=; b=0iLWxRZCWGM6dlnXeGvanJBvR+C4N/N3CsSUEZcFC7nGfO1uu/wn9B21Zfnha+AUdq Vz+ugsgG6eVQtxMb2NTkkd3EtCVQ3vAsv/iwC69slmYDA0RejJR7p/XEN5+kQSc76yE+ Z/30/axjURTEFPiuapOjo3VgOgUjNXDyYC8p92YmYi6hN0lBsWYo1vE0pVWk/4nE7I+D XPLCBIIrogqCmkD66ur6ysL9Q+oyTiQ4JQdV+e6uk75Yv1As1YMSdkvmmKi/uZ/AnW7I jCadMQ7qMyDCbkUizuG6RYDZf0Fb8e7mrmPBqIJ1vtQFZwA909bHOFUxPhLSN2YAWEJk cFOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HI1pPunD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:56 -0800 Message-Id: <20180124232625.30105-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: [Qemu-devel] [PATCH v3 16/45] target/hppa: Implement IASQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Any one TB will have only one space value. If we change spaces, we change TBs. Thus BE and BEV must exit the TB immediately. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 53 ++++++++++++++++++++- target/hppa/cpu.c | 15 ++++++ target/hppa/helper.c | 3 +- target/hppa/int_helper.c | 16 +++++-- target/hppa/op_helper.c | 2 + target/hppa/translate.c | 117 ++++++++++++++++++++++++++++++++++++++--------- 6 files changed, 179 insertions(+), 27 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 94f9c8ca2b..d583ea43dd 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -186,6 +186,8 @@ struct CPUHPPAState { target_ureg iaoq_f; /* front */ target_ureg iaoq_b; /* back, aka next instruction */ + uint64_t iasq_f; + uint64_t iasq_b; uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; @@ -240,15 +242,62 @@ void hppa_translate_init(void); void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf); +static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, + target_ureg off) +{ +#ifdef CONFIG_USER_ONLY + return off; +#else + off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + return spc | off; +#endif +} + +static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, + target_ureg off) +{ + return hppa_form_gva_psw(env->psw, spc, off); +} + +/* Since PSW_CB will never need to be in tb->flags, reuse them. */ +#define TB_FLAG_PRIV_SHIFT 8 + static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { + uint32_t flags = env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu priviledge from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY *pc = env->iaoq_f; *cs_base = env->iaoq_b; +#else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ - *pflags = (env->psw & (PSW_W | PSW_C | PSW_D)) - | env->psw_n * PSW_N; + flags |= env->psw & (PSW_W | PSW_C | PSW_D); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc = (env->psw & PSW_C + ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) + : env->iaoq_f & -4); + *cs_base = env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a page. + Failure is indicated by a zero difference. */ + if (env->iasq_f == env->iasq_b) { + target_sreg diff = env->iaoq_b - env->iaoq_f; + if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { + *cs_base |= (uint32_t)diff; + } + } +#endif + + *pflags = flags; } target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4d0b760baa..2970afd58d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -37,8 +37,23 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) { HPPACPU *cpu = HPPA_CPU(cs); +#ifdef CONFIG_USER_ONLY cpu->env.iaoq_f = tb->pc; cpu->env.iaoq_b = tb->cs_base; +#else + /* Recover the IAOQ values from the GVA + PRIV. */ + uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; + target_ulong cs_base = tb->cs_base; + target_ulong iasq_f = cs_base & ~0xffffffffull; + int32_t diff = cs_base; + + cpu->env.iasq_f = iasq_f; + cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; + if (diff) { + cpu->env.iaoq_b = cpu->env.iaoq_f + diff; + } +#endif + cpu->env.psw_n = (tb->flags & PSW_N) != 0; } diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 6e8758f82c..858ec205b6 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -78,7 +78,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int i; cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n", - (target_ulong)env->iaoq_f, (target_ulong)env->iaoq_b); + hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), + hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index a59aae1189..02963b80c6 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -32,6 +32,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) int i = cs->exception_index; target_ureg iaoq_f = env->iaoq_f; target_ureg iaoq_b = env->iaoq_b; + uint64_t iasq_f = env->iasq_f; + uint64_t iasq_b = env->iasq_b; #ifndef CONFIG_USER_ONLY target_ureg old_psw; @@ -44,6 +46,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0)); /* step 3 */ + env->cr[CR_IIASQ] = iasq_f >> 32; + env->cr_back[0] = iasq_b >> 32; env->cr[CR_IIAOQ] = iaoq_f; env->cr_back[1] = iaoq_b; @@ -79,6 +83,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) hwaddr paddr; paddr = vaddr = iaoq_f & -4; + if (old_psw & PSW_C) { + vaddr = hppa_form_gva_psw(old_psw, iasq_f, iaoq_f & -4); + } env->cr[CR_IIR] = ldl_phys(cs->as, paddr); } break; @@ -101,6 +108,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 7 */ env->iaoq_f = env->cr[CR_IVA] + 32 * i; env->iaoq_b = env->iaoq_f + 4; + env->iasq_f = 0; + env->iasq_b = 0; #endif if (qemu_loglevel_mask(CPU_LOG_INT)) { @@ -151,10 +160,11 @@ void hppa_cpu_do_interrupt(CPUState *cs) qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", ++count, name, - (target_ulong)iaoq_f, - (target_ulong)iaoq_b, + hppa_form_gva(env, iasq_f, iaoq_f), + hppa_form_gva(env, iasq_b, iaoq_b), env->iaoq_f, - (target_ulong)env->cr[CR_IOR]); + hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32, + env->cr[CR_IOR])); } cs->exception_index = -1; } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 3f5dcbbca0..1963b2439b 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -622,6 +622,8 @@ void HELPER(rfi)(CPUHPPAState *env) if (env->psw & (PSW_I | PSW_R | PSW_Q)) { helper_excp(env, EXCP_ILL); } + env->iasq_f = (uint64_t)env->cr[CR_IIASQ] << 32; + env->iasq_b = (uint64_t)env->cr_back[0] << 32; env->iaoq_f = env->cr[CR_IIAOQ]; env->iaoq_b = env->cr_back[1]; cpu_hppa_put_psw(env, env->cr[CR_IPSW]); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4a69f05a91..44abc9006b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -325,6 +325,8 @@ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; +static TCGv_i64 cpu_iasq_f; +static TCGv_i64 cpu_iasq_b; static TCGv_reg cpu_sar; static TCGv_reg cpu_psw_n; static TCGv_reg cpu_psw_v; @@ -380,6 +382,13 @@ void hppa_translate_init(void) const GlobalVar *v = &vars[i]; *v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name); } + + cpu_iasq_f = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, iasq_f), + "iasq_f"); + cpu_iasq_b = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, iasq_b), + "iasq_b"); } static DisasCond cond_make_f(void) @@ -1760,6 +1769,11 @@ static DisasJumpType do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); + if (ctx->iaoq_n == -1) { + /* The temporary iaoq_n_var died at the branch above. + Regenerate it here instead of saving it. */ + tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); + } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } @@ -1801,11 +1815,17 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv_reg dest, } next = get_temp(ctx); tcg_gen_mov_reg(next, dest); - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; if (is_n) { + if (use_nullify_skip(ctx)) { + tcg_gen_mov_reg(cpu_iaoq_f, next); + tcg_gen_addi_reg(cpu_iaoq_b, next, 4); + nullify_set(ctx, 0); + return DISAS_IAQ_N_UPDATED; + } ctx->null_cond.c = TCG_COND_ALWAYS; } + ctx->iaoq_n = -1; + ctx->iaoq_n_var = next; } else if (is_n && use_nullify_skip(ctx)) { /* The (conditional) branch, B, nullifies the next insn, N, and we're allowed to skip execution N (no single-step or @@ -3477,26 +3497,55 @@ static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) target_sreg disp = assemble_17(insn); TCGv_reg tmp; - /* unsigned s = low_uextract(insn, 13, 3); */ +#ifdef CONFIG_USER_ONLY /* ??? It seems like there should be a good way of using "be disp(sr2, r0)", the canonical gateway entry mechanism to our advantage. But that appears to be inconvenient to manage along side branch delay slots. Therefore we handle entry into the gateway page via absolute address. */ - -#ifdef CONFIG_USER_ONLY /* Since we don't implement spaces, just branch. Do notice the special case of "be disp(*,r0)" using a direct branch to disp, so that we can goto_tb to the TB containing the syscall. */ if (b == 0) { return do_dbranch(ctx, disp, is_l ? 31 : 0, n); } +#else + int sp = assemble_sr3(insn); + nullify_over(ctx); #endif tmp = get_temp(ctx); tcg_gen_addi_reg(tmp, load_gpr(ctx, b), disp); tmp = do_ibranch_priv(ctx, tmp); + +#ifdef CONFIG_USER_ONLY return do_ibranch(ctx, tmp, is_l ? 31 : 0, n); +#else + TCGv_i64 new_spc = tcg_temp_new_i64(); + + load_spr(ctx, new_spc, sp); + if (is_l) { + copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); + tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); + } + if (n && use_nullify_skip(ctx)) { + tcg_gen_mov_reg(cpu_iaoq_f, tmp); + tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_i64(cpu_iasq_f, new_spc); + tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + } else { + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + if (ctx->iaoq_b == -1) { + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + } + tcg_gen_mov_reg(cpu_iaoq_b, tmp); + tcg_gen_mov_i64(cpu_iasq_b, new_spc); + nullify_set(ctx, n); + } + tcg_temp_free_i64(new_spc); + tcg_gen_lookup_and_goto_ptr(); + return nullify_end(ctx, DISAS_NORETURN); +#endif } static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, @@ -3559,8 +3608,26 @@ static DisasJumpType trans_bve(DisasContext *ctx, uint32_t insn, unsigned link = extract32(insn, 13, 1) ? 2 : 0; TCGv_reg dest; +#ifdef CONFIG_USER_ONLY dest = do_ibranch_priv(ctx, load_gpr(ctx, rb)); return do_ibranch(ctx, dest, link, n); +#else + nullify_over(ctx); + dest = do_ibranch_priv(ctx, load_gpr(ctx, rb)); + + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + if (ctx->iaoq_b == -1) { + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + } + copy_iaoq_entry(cpu_iaoq_b, -1, dest); + tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); + if (link) { + copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); + } + nullify_set(ctx, n); + tcg_gen_lookup_and_goto_ptr(); + return nullify_end(ctx, DISAS_NORETURN); +#endif } static const DisasInsn table_branch[] = { @@ -4267,15 +4334,21 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_USER_IDX; ctx->mmu_idx = MMU_USER_IDX; + ctx->iaoq_f = ctx->base.pc_first; + ctx->iaoq_b = ctx->base.tb->cs_base; #else - ctx->privilege = ctx->base.pc_first & 3; + ctx->privilege = (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->base.tb->flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); -#endif - ctx->iaoq_f = ctx->base.pc_first; - ctx->iaoq_b = ctx->base.tb->cs_base; - ctx->base.pc_first &= -4; + /* Recover the IAOQ values from the GVA + PRIV. */ + uint64_t cs_base = ctx->base.tb->cs_base; + uint64_t iasq_f = cs_base & ~0xffffffffull; + int32_t diff = cs_base; + + ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); +#endif ctx->iaoq_n = -1; ctx->iaoq_n_var = NULL; @@ -4318,7 +4391,7 @@ static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next = (ctx->iaoq_f & -4) + 4; + ctx->base.pc_next += 4; return true; } @@ -4331,7 +4404,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Execute one insn. */ #ifdef CONFIG_USER_ONLY - if (ctx->iaoq_f < TARGET_PAGE_SIZE) { + if (ctx->base.pc_next < TARGET_PAGE_SIZE) { ret = do_page_zero(ctx); assert(ret != DISAS_NEXT); } else @@ -4339,7 +4412,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f & -4); + uint32_t insn = cpu_ldl_code(env, ctx->base.pc_next); /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ @@ -4377,18 +4450,21 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (ctx->null_cond.c == TCG_COND_NEVER - || ctx->null_cond.c == TCG_COND_ALWAYS) { + if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 + && use_goto_tb(ctx, ctx->iaoq_b) + && (ctx->null_cond.c == TCG_COND_NEVER + || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); ret = DISAS_NORETURN; } else { ret = DISAS_IAQ_N_STALE; - } + } } ctx->iaoq_f = ctx->iaoq_b; ctx->iaoq_b = ctx->iaoq_n; ctx->base.is_jmp = ret; + ctx->base.pc_next += 4; if (ret == DISAS_NORETURN || ret == DISAS_IAQ_N_UPDATED) { return; @@ -4396,6 +4472,9 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) if (ctx->iaoq_f == -1) { tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); +#ifndef CONFIG_USER_ONLY + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); +#endif nullify_save(ctx); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; } else if (ctx->iaoq_b == -1) { @@ -4430,15 +4509,11 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) default: g_assert_not_reached(); } - - /* We don't actually use this during normal translation, - but we should interact with the generic main loop. */ - ctx->base.pc_next = ctx->base.pc_first + 4 * ctx->base.num_insns; } static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) { - target_ureg pc = dcbase->pc_first; + target_ulong pc = dcbase->pc_first; #ifdef CONFIG_USER_ONLY switch (pc) { From patchwork Wed Jan 24 23:25:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125744 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp739953ljf; Wed, 24 Jan 2018 15:47:53 -0800 (PST) X-Google-Smtp-Source: AH8x226FiJcu8wSVaVBRUsNSDMBhyTC7iC5L8SQdp2IUoyUft2QpTyD9MLsLKSUjlOWtztLgcyNe X-Received: by 10.37.204.6 with SMTP id l6mr6788038ybf.490.1516837673145; Wed, 24 Jan 2018 15:47:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837673; cv=none; d=google.com; s=arc-20160816; b=AxbCJ158kS68iAw4dDwqLmcxaTOGcZFLA5CpuR9X9mmnHqF2hrjAXq8BMbeEWMUBG1 BSx14SZGwvJo9i+NdY1sWDav0xYs2kzDK/mvIo5SRFNLmWJU2ULPiQtr9PVXMMuhYAgb tRyfyvII2QgvrLEaS3I+/9kHiOfDl8YmpB8slMmenO/ARQ6OTfyUY3pD5Xhh0/0Rq31b CuQBjCqEuJhhCGRp+UG4hwIvGKhyFr4TFU7ZVuKm5MyqbPtFN31Fnso3aStNrdoWkN7B 4LyOnrDnI779gCOEFW11mH9cJHJRv8H6febf+Av1ivNEiiIugYlfZUqQaT7VjIvwhfSD 747A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=cNMWduwd/imEbozb8k3aw4xPmG54EEtG552lqHT79mQ=; b=yWMfDQv7WMUojMtI/I5B2uKkEIBxdGfU+ZDp419TzfZIKQhuzckExVyxmHGnZ81v1R YZYxFaXd4ZjZbsuVBu6IqfblEG8HOTN9KwtfyQm4lORAVgGzFnDUxMbdgit2Vz9bavdl 58b2bxJTG2+YtaD4B3F2HN30SN33QNVSH/gDUPcdhVak2fNZCehvZsbRuAQidMig5KL6 aFRfyu+g3f0IEWDx7u4Y2WBUZ7hMrXyowCrbnMEWEtaCkR4uH1mVnJq8rsPiNut6kxvQ 8TwJ7jtSFG2gdtWLsVPwMlVqY75slRs8cZh1G3dCtFZFJFdJ8069grL4mC8gYVRkwlgb /9VA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=K/Kd1IwD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:57 -0800 Message-Id: <20180124232625.30105-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 17/45] target/hppa: Implement tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 29 ++++++++- target/hppa/int_helper.c | 15 ++++- target/hppa/mem_helper.c | 151 +++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 188 insertions(+), 7 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d583ea43dd..c7a2fb5b20 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -165,6 +165,22 @@ typedef int64_t target_sreg; #define TREG_FMT_ld "%"PRId64 #endif +typedef struct { + uint64_t va_b; + uint64_t va_e; + target_ureg pa; + unsigned u : 1; + unsigned t : 1; + unsigned d : 1; + unsigned b : 1; + unsigned page_size : 4; + unsigned ar_type : 3; + unsigned ar_pl1 : 2; + unsigned ar_pl2 : 2; + unsigned entry_valid : 1; + unsigned access_id : 16; +} hppa_tlb_entry; + struct CPUHPPAState { target_ureg gr[32]; uint64_t fr[32]; @@ -198,6 +214,12 @@ struct CPUHPPAState { /* Those resources are used only in QEMU core */ CPU_COMMON + + /* ??? The number of entries isn't specified by the architecture. */ + /* ??? Implement a unified itlb/dtlb for the moment. */ + /* ??? We should use a more intelligent data structure. */ + hppa_tlb_entry tlb[256]; + uint32_t tlb_last; }; /** @@ -307,12 +329,17 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int); +#ifdef CONFIG_USER_ONLY +int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); +#else +int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, + MMUAccessType type, hwaddr *pphys, int *pprot); +#endif #endif /* HPPA_CPU_H */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 02963b80c6..5ae5233a96 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -79,12 +79,25 @@ void hppa_cpu_do_interrupt(CPUState *cs) { /* Avoid reading directly from the virtual address, lest we raise another exception from some sort of TLB issue. */ + /* ??? An alternate fool-proof method would be to store the + instruction data into the unwind info. That's probably + a bit too much in the way of extra storage required. */ vaddr vaddr; hwaddr paddr; paddr = vaddr = iaoq_f & -4; if (old_psw & PSW_C) { - vaddr = hppa_form_gva_psw(old_psw, iasq_f, iaoq_f & -4); + int prot, t; + + vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr); + t = hppa_get_physical_address(env, vaddr, 0, + MMU_INST_FETCH, + &paddr, &prot); + if (t >= 0) { + /* We can't re-load the instruction. */ + env->cr[CR_IIR] = 0; + break; + } } env->cr[CR_IIR] = ldl_phys(cs->as, paddr); } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 1afaf89539..08ab19aacf 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -36,18 +36,159 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, return 1; } #else +static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) { + hppa_tlb_entry *ent = &env->tlb[i]; + if (ent->va_b <= addr && addr <= ent->va_e && ent->entry_valid) { + return ent; + } + } + return NULL; +} + +int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, + MMUAccessType type, hwaddr *pphys, int *pprot) +{ + hwaddr phys; + int prot, ret, r_prot, w_prot, x_prot, a_prot; + bool ifetch = type == MMU_INST_FETCH; + hppa_tlb_entry *ent; + + /* Virtual translation disabled. Direct map virtual to physical. */ + if (mmu_idx == MMU_PHYS_IDX) { + phys = addr; + prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + ret = -1; + goto egress; + } + + /* Find a valid tlb entry that matches the virtual address. */ + ent = hppa_find_tlb(env, addr); + if (ent == NULL) { + phys = 0; + prot = 0; + ret = (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); + goto egress; + } + + /* We now know the physical address. */ + phys = ent->pa + (addr & ~TARGET_PAGE_MASK); + + /* Map TLB access_rights field to QEMU protection. */ + r_prot = (mmu_idx <= ent->ar_pl1 ? PROT_READ : 0); + w_prot = (mmu_idx <= ent->ar_pl2 ? PROT_WRITE : 0); + x_prot = (ent->ar_pl2 <= mmu_idx && mmu_idx <= ent->ar_pl1 ? PROT_EXEC : 0); + switch (ent->ar_type) { + case 0: /* read-only: data page */ + prot = r_prot; + break; + case 1: /* read/write: dynamic data page */ + prot = r_prot | w_prot; + break; + case 2: /* read/execute: normal code page */ + prot = r_prot | x_prot; + break; + case 3: /* read/write/execute: dynamic code page */ + prot = r_prot | w_prot | x_prot; + break; + default: /* execute: promote to privilege level type & 3 */ + prot = x_prot; + } + + /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. */ + + /* Map MMUAccessType to QEMU protection. */ + if (ifetch) { + a_prot = PROT_EXEC; + } else if (type == MMU_DATA_STORE) { + a_prot = PROT_WRITE; + } else { + a_prot = PROT_READ; + } + + if (unlikely(!(prot & a_prot))) { + /* The access isn't allowed -- Inst/Data Memory Protection Fault. */ + ret = (ifetch ? EXCP_IMP : EXCP_DMP); + goto egress; + } + + /* In reverse priority order, check for conditions which raise faults. + As we go, remove PROT bits that cover the condition we want to check. + In this way, the resulting PROT will force a re-check of the + architectural TLB entry for the next access. */ + ret = -1; + if (unlikely(!ent->d)) { + if (type == MMU_DATA_STORE) { + /* The D bit is not set -- TLB Dirty Bit Fault. */ + ret = EXCP_TLB_DIRTY; + } + prot &= PROT_READ | PROT_EXEC; + } + if (unlikely(ent->b)) { + if (type == MMU_DATA_STORE) { + /* The B bit is set -- Data Memory Break Fault. */ + ret = EXCP_DMB; + } + prot &= PROT_READ | PROT_EXEC; + } + if (unlikely(ent->t)) { + if (!ifetch) { + /* The T bit is set -- Page Reference Fault. */ + ret = EXCP_PAGE_REF; + } + prot &= PROT_EXEC; + } + + egress: + *pphys = phys; + *pprot = prot; + return ret; +} + hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - /* Stub */ - return addr; + HPPACPU *cpu = HPPA_CPU(cs); + hwaddr phys; + int prot, excp; + + /* If the (data) mmu is disabled, bypass translation. */ + /* ??? We really ought to know if the code mmu is disabled too, + in order to get the correct debugging dumps. */ + if (!(cpu->env.psw & PSW_D)) { + return addr; + } + + excp = hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, + MMU_DATA_LOAD, &phys, &prot); + + /* Since we're translating for debugging, the only error that is a + hard error is no translation at all. Otherwise, while a real cpu + access might not have permission, the debugger does. */ + return excp == EXCP_DTLB_MISS ? -1 : phys; } void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, int mmu_idx, uintptr_t retaddr) { - /* Stub */ - int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - hwaddr phys = addr; + HPPACPU *cpu = HPPA_CPU(cs); + int prot, excp; + hwaddr phys; + + excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, + type, &phys, &prot); + if (unlikely(excp >= 0)) { + /* Failure. Raise the indicated exception. */ + cs->exception_index = excp; + if (cpu->env.psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + cpu->env.cr[CR_IOR] = addr; + cpu->env.cr[CR_ISR] = addr >> 32; + } + cpu_loop_exit_restore(cs, retaddr); + } /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, From patchwork Wed Jan 24 23:25:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125725 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp734772ljf; Wed, 24 Jan 2018 15:35:25 -0800 (PST) X-Google-Smtp-Source: AH8x227nBmObwM5qsa/NV7+lB4UGObkNvHI2idtoebKjBdZ6SYohiImwE4vazxVbdxoEq6u+CaRB X-Received: by 10.129.122.73 with SMTP id v70mr6702385ywc.156.1516836925292; Wed, 24 Jan 2018 15:35:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836925; cv=none; d=google.com; s=arc-20160816; b=bo5Cb7HG0ik7u3FLP7Q0P5VzJaCbTxTACen5GEuByjwx8iOsN/DwKHFVAjDWw11MFb jBIp4kI8YMm17gRJOM+GbmqEqJkmlGI3sbTqXSXLrz4MnXJscbOWoC8i3dHcPd3bzHXP 7ybgYhJQ4GGiuon62z1HwLvwarAifwOXFmS7kevBIqqpTLOvoEZCYkY96jLr31yZNHsw 7SYRfOyFVT3mBRkdVxuen8sceOzlmbUgWyqvWLHlmgrBnsdn50JNBtHgDHhJ7WpHCax+ LSt9dzzrA8flC4mQgWZO3kFdo6N0ixVQfN8ntSUb0r4aeIrC1biQb9MEQag2qW4VYVTC 9crQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=CUfgcA2foVF68I+6bbQG+I5P6I+RV/GKq3qFtasSazM=; b=wpOfugul3Fg4h+jJA337icFQ15G0M04rId9fhlHPDDDxDHrAm6JZi0i/Y9cnZa0+qi lYHiFjiKMTNlwNsRuEhg4U8qY7JlZ+ezAYQcdL4WuyafU9h+WuYC7eTyzWageIQT1Elw 6cVGIld9XZUuDtU4pBYC6SKyftpJNQTZfUre6hc+kFSLIjhG6vIolCxGRLEl3mND0fzv hcHfimUMU2TlVHGO5qGxwX5Qd7mtQCd7eKUK8Qje9BdqD15deHAZcEF/JlzxA7eTFY4q O+TV9BJTssASNVNLLFYxxm+U653ZTpmAEUxkomaNKzR1E8O9sm5XJBwp/BXWRzdT1Hei fmEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XxCZ1mVu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 18/45] target/hppa: Implement external interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 2 ++ target/hppa/cpu.c | 6 +++++ target/hppa/int_helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++++++++++- 5 files changed, 83 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c7a2fb5b20..fc3e62c0af 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -340,6 +340,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); #else int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot); +extern const MemoryRegionOps hppa_io_eir_ops; #endif #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 79d22ae486..535f086ab4 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -80,5 +80,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) +DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2970afd58d..888a48f16d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -57,6 +57,11 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) cpu->env.psw_n = (tb->flags & PSW_N) != 0; } +static bool hppa_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach = bfd_mach_hppa20; @@ -159,6 +164,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) dc->realize = hppa_cpu_realizefn; cc->class_by_name = hppa_cpu_class_by_name; + cc->has_work = hppa_cpu_has_work; cc->do_interrupt = hppa_cpu_do_interrupt; cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt; cc->dump_state = hppa_cpu_dump_state; diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 5ae5233a96..249e14a2a1 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -24,6 +24,65 @@ #include "exec/helper-proto.h" #include "qom/cpu.h" +#ifndef CONFIG_USER_ONLY +static void eval_interrupt(HPPACPU *cpu) +{ + CPUState *cs = CPU(cpu); + if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus + * can write to this word to raise an external interrupt on the target CPU. + * This includes the system controler (DINO) for regular devices, or + * another CPU for SMP interprocessor interrupts. + */ +static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size) +{ + HPPACPU *cpu = opaque; + + /* ??? What does a read of this register over the GSC bus do? */ + return cpu->env.cr[CR_EIRR]; +} + +static void io_eir_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + HPPACPU *cpu = opaque; + int le_bit = ~data & (TARGET_REGISTER_BITS - 1); + + cpu->env.cr[CR_EIRR] |= (target_ureg)1 << le_bit; + eval_interrupt(cpu); +} + +const MemoryRegionOps hppa_io_eir_ops = { + .read = io_eir_read, + .write = io_eir_write, + .valid.min_access_size = 4, + .valid.max_access_size = 4, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + +void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIRR] &= ~val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} + +void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIEM] = val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} +#endif /* !CONFIG_USER_ONLY */ void hppa_cpu_do_interrupt(CPUState *cs) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 44abc9006b..d6c65f314b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2124,12 +2124,25 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, /* All other control registers are privileged or read-only. */ CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + DisasJumpType ret = DISAS_NEXT; + nullify_over(ctx); switch (ctl) { case CR_IT: /* ??? modify interval timer offset */ break; + case CR_EIRR: + gen_helper_write_eirr(cpu_env, reg); + break; + case CR_EIEM: + gen_helper_write_eiem(cpu_env, reg); + ret = DISAS_IAQ_N_STALE_EXIT; + break; + case CR_IIASQ: case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ @@ -2146,7 +2159,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); break; } - return nullify_end(ctx, DISAS_NEXT); + return nullify_end(ctx, ret); +#endif } static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, From patchwork Wed Jan 24 23:25:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125748 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp741292ljf; Wed, 24 Jan 2018 15:50:51 -0800 (PST) X-Google-Smtp-Source: AH8x226i9JdFQssUufykfBmm1Mj/7BBIQVE6c9wrWv8sCcROhVkTBBuskhWeZ02ZiVzW+fzdVrJg X-Received: by 10.37.160.98 with SMTP id x89mr7026402ybh.448.1516837850966; Wed, 24 Jan 2018 15:50:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837850; cv=none; d=google.com; s=arc-20160816; b=nBy9c8c1sN5yk37FaK7hnh69uHD0ZqNy/Zv6Yqjq/bno4LvV3omVdo5rEaIVtI2SHj Glolfkmgm3oGBaz/Jvdit3SJkJEDlPxPibOghb7nO6fvO6mq5XI8x10ISey2FkwaxJry fNpLskaLLSG4lOTk49TYteLL4CO4DjfsgSiIy28k1b9mR5sqyuoWzhcUuONfztaCB0Nw 1orpZjpcsQWNCTHUbxHzJaUIjXoe0SPRyT1dDgdRSjTJerLG7WXD8DsWe8aBjYTIpHKk i/vMt1PA7oyii0BTd3gN4DTZFdEvPH4N0FPw2IJLmz+UbR1ywWxNW39HgynXwx0vnV9P QMkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=3QgQ3aTosAcrqniuf2FzQ9ncn1tfTZjIHIuTzT3AMPw=; b=sY6HjrWzRb+Q4BLHh65AQlwEKQ6s6+r6fL6zTRPlHCh6stxjWRM7YvHGMnTLre2e+x ZI6Ex0ExbbJM+ZgakYuJ4eyCV1w1gKsdOMWix+TY0OpxfJXKnRYRvNR2B5f6L/knQxs6 pd5n7/WZ78IDhlzqfsBwJTLTFAW4/0SaUbzMkjdoZiWT3UaLJwIK7IUS57G76WvK4Q/m JSrKkBMScFc6lTOKBbDUbZHwuTWPLGTAopqX6R8JzQDRmdErKSfO0kLAv6Sl5GgfURsd h+gTyoOanmnHOER6nzmyrBGEPljmDaKgPMStNcOSRl841uswx2fCYs+xavn383ud/Dpc 04dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B3Ud02GC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:59 -0800 Message-Id: <20180124232625.30105-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 19/45] target/hppa: Implement the interval timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/helper.h | 3 +++ target/hppa/cpu.c | 8 ++++++++ target/hppa/int_helper.c | 6 ++++++ target/hppa/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++++++++++---- 6 files changed, 67 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fc3e62c0af..31a3702684 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -234,6 +234,7 @@ struct HPPACPU { /*< public >*/ CPUHPPAState env; + QEMUTimer *alarm_timer; }; static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) @@ -341,6 +342,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; +void hppa_cpu_alarm_timer(void *); #endif #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 535f086ab4..744b11cb66 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -77,9 +77,12 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) + #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 888a48f16d..6be6eb0a7b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -99,6 +99,14 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); acc->parent_realize(dev, errp); + +#ifndef CONFIG_USER_ONLY + { + HPPACPU *cpu = HPPA_CPU(cs); + cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + hppa_cpu_alarm_timer, cpu); + } +#endif } /* Sort hppabetically by type name. */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 249e14a2a1..d54d830196 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -67,6 +67,12 @@ const MemoryRegionOps hppa_io_eir_ops = { .impl.max_access_size = 4, }; +void hppa_cpu_alarm_timer(void *opaque) +{ + /* Raise interrupt 0. */ + io_eir_write(opaque, 0, 0, 4); +} + void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) { env->cr[CR_EIRR] &= ~val; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 1963b2439b..6d19cab6c9 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,8 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include "qemu/timer.h" + void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { @@ -602,7 +604,41 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c) return ret; } +target_ureg HELPER(read_interval_timer)(void) +{ +#ifdef CONFIG_USER_ONLY + /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. + Just pass through the host cpu clock ticks. */ + return cpu_get_host_ticks(); +#else + /* In system mode we have access to a decent high-resolution clock. + In order to make OS-level time accounting work with the cr16, + present it with a well-timed clock fixed at 250MHz. */ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2; +#endif +} + #ifndef CONFIG_USER_ONLY +void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) +{ + HPPACPU *cpu = hppa_env_get_cpu(env); + uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t timeout; + + /* Even in 64-bit mode, the comparator is always 32-bit. But the + value we expose to the guest is 1/4 of the speed of the clock, + so moosh in 34 bits. */ + timeout = deposit64(current, 0, 34, (uint64_t)val << 2); + + /* If the mooshing puts the clock in the past, advance to next round. */ + if (timeout < current + 1000) { + timeout += 1ULL << 34; + } + + cpu->env.cr[CR_IT] = timeout; + timer_mod(cpu->alarm_timer, timeout); +} + target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw = env->psw; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d6c65f314b..1cd57f5a90 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2038,6 +2038,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); unsigned ctl = extract32(insn, 21, 5); TCGv_reg tmp; + DisasJumpType ret; switch (ctl) { case CR_SAR: @@ -2056,9 +2057,17 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp = dest_gpr(ctx, rt); - tcg_gen_movi_reg(tmp, 0); /* FIXME */ + if (ctx->base.tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + gen_helper_read_interval_timer(tmp); + gen_io_end(); + ret = DISAS_IAQ_N_STALE; + } else { + gen_helper_read_interval_timer(tmp); + ret = DISAS_NEXT; + } save_gpr(ctx, rt, tmp); - break; + return nullify_end(ctx, ret); case 26: case 27: break; @@ -2132,9 +2141,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, nullify_over(ctx); switch (ctl) { case CR_IT: - /* ??? modify interval timer offset */ + gen_helper_write_interval_timer(cpu_env, reg); break; - case CR_EIRR: gen_helper_write_eirr(cpu_env, reg); break; From patchwork Wed Jan 24 23:26:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125751 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp742812ljf; Wed, 24 Jan 2018 15:54:44 -0800 (PST) X-Google-Smtp-Source: AH8x227Dsxsj3okVsZT+2c3rvzKAujLVDyewIS641GVvnt7CaXkjEfzv+H4dXICjBMSc+/mt4nhH X-Received: by 10.129.52.151 with SMTP id b145mr6894288ywa.487.1516838084852; Wed, 24 Jan 2018 15:54:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838084; cv=none; d=google.com; s=arc-20160816; b=pRcLzrZzbVnf0PO9kRLTVm48uATDJqqro/wCAf4pOrW+DYnt2aVbnxLENaVp/0m2ii zkzLkEFRvRQLIovDgGoVJF1zigEob1Vt91xH78kvDXwHbMsqCzY3PEk5w5zz3sUTJauQ 5SUsvl7/c9Mix89ZDAjzpjM6NwxWaadXfrvCk5kgV6xfO8Wi4ATcfeHoBf7uzAHYcAY0 UwIHucZ6XNfGFXXTLuAUzWuavHOjf/1J6XozTEGMtha02/oMfJ3JDpMzfg/PEqy9lXhR KIU2QTaI86Ohu9ylDiNtkp6LFhPE7ehxRZMpVrlv2qwsgaPa8nILskw3rMskevWMDnwh /hdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8fZcIG/WtHjKUCwfLG506MBVjMxOcPO/hwapVk47rEc=; b=iOiv6gbK9rqceAdOGcDtUnnxV76qmiTbfQHU9A6s1YHuYA3dRWbLbKsPzTMMv/ux+A b+E5r9o1A8FG0jrqPZQsrrJnWWIaVTNwtm4n/+nBLk46XYfy1tfqZcPQNDu3xzhrLU1G DygdTwmYKWSZJ2YwmViAALuOgLo+Ik7VKoDBDBd4tf01cr9xJHyZxz3tbgHSK9iyVOBC nvsrLOH3WyaupkXcC52TrcWw7qupA9WSL9ufgSBlAvgxKJhCzk0BpWzXj/6cZmrzSiP7 PbtEQvGo0Ij7ktPuurfk+59K6sJN7FY/L39dZ9Pzk4Id6LGIdy7uCqeizBP8ZShRMskl sjow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JvXpamxV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:00 -0800 Message-Id: <20180124232625.30105-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 20/45] target/hppa: Log unimplemented instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1cd57f5a90..6288bb9f67 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4218,6 +4218,8 @@ static DisasJumpType translate_table_int(DisasContext *ctx, uint32_t insn, return table[i].trans(ctx, insn, &table[i]); } } + qemu_log_mask(LOG_UNIMP, "UNIMP insn %08x @ " TARGET_FMT_lx "\n", + insn, ctx->base.pc_next); return gen_illegal(ctx); } From patchwork Wed Jan 24 23:26:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125752 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp742892ljf; Wed, 24 Jan 2018 15:55:02 -0800 (PST) X-Google-Smtp-Source: AH8x225OPN7SugOrSFzqSUzg/caxSgp8y3XC8yTC8TKUGc08Y1M+HBOfkutKYmq6IJtY2ORD8Eev X-Received: by 10.37.97.75 with SMTP id v72mr6722187ybb.14.1516838102501; Wed, 24 Jan 2018 15:55:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838102; cv=none; d=google.com; s=arc-20160816; b=x75FQSl4Q1FgsHPgewmDQG63uORfecaYbWeyyN1PXj+1LSnh7JPNVQgSo4v7O8pgXY U6Q9gDGDRBLU2vickymqChGsMkBPNg33Muw04BiCjyueM/EgfyNoEx6+LCab2IKZJlyC a7dYFkLMQH4kkwwidA+KLeuQVDywg3YPgksrUZSSvJKX0bxPj4CkTcAPMlJLjgTDQRXH FnC71awiIX0kH0rakP+3PgJyVu+QW0M7ddYo7B796QaSi8/UWcjqNQjD2aru/+TbSlP/ 5g1npSMWr2oj/9D6CCDhXY6OAgw7TFEeQHJ2p9HrHH20R3EDyzyvZaf6SuBn470EvD35 PYDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=35pGJnCLY/5W72jYPTV6lM+5a5u4ZQxV/aLV82wAQ+M=; b=kfcScxYR7AH9nIayV2eoya0SJEuC9Zg64Z6CSVBtAzkacAz72ruzg27LdjcpqP/6bY On5KjhJ+jkBmB1cSKMBqSNOxhzmtY0Lh7aCFUSw0ugNitRObsijFm9Evyi/IDwhDhevV W5Wra8IsXs7BriOH9n5Fe01c+ESV4XdNfPTZbW24fT018eSDJASHZINpwP5+T6Dswdtt lVtp3WeXPAQ83LaRl8EY8Pm21aBPYf+cCaYNORbt/BCBDPuSGBUSe5eIsTBKdiO9gdOZ C7JHM2K17lFcz453pAn4U78unlP+a7jCkmzwC3jAO2BnIob4fKZZhHNuJiUisJCuSzPI rq1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Mbnq2Jn0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:01 -0800 Message-Id: <20180124232625.30105-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 21/45] target/hppa: Implement I*TLBA and I*TLBP insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/mem_helper.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++-- target/hppa/translate.c | 54 ++++++++++++++++++++++++++++++-- 3 files changed, 132 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 744b11cb66..d412093914 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -86,4 +86,6 @@ DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 08ab19aacf..7c3c7d1415 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -42,13 +42,40 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) { hppa_tlb_entry *ent = &env->tlb[i]; - if (ent->va_b <= addr && addr <= ent->va_e && ent->entry_valid) { + if (ent->va_b <= addr && addr <= ent->va_e) { return ent; } } return NULL; } +static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) +{ + CPUState *cs = CPU(hppa_env_get_cpu(env)); + unsigned i, n = 1 << (2 * ent->page_size); + uint64_t addr = ent->va_b; + + for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) { + /* Do not flush MMU_PHYS_IDX. */ + tlb_flush_page_by_mmuidx(cs, addr, 0xf); + } + + memset(ent, 0, sizeof(*ent)); + ent->va_b = -1; +} + +static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env) +{ + hppa_tlb_entry *ent; + uint32_t i = env->tlb_last; + + env->tlb_last = (i == ARRAY_SIZE(env->tlb) - 1 ? 0 : i + 1); + ent = &env->tlb[i]; + + hppa_flush_tlb_ent(env, ent); + return ent; +} + int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot) { @@ -67,7 +94,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* Find a valid tlb entry that matches the virtual address. */ ent = hppa_find_tlb(env, addr); - if (ent == NULL) { + if (ent == NULL || !ent->entry_valid) { phys = 0; prot = 0; ret = (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); @@ -194,4 +221,53 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType type, tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); } + +/* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ +void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +{ + hppa_tlb_entry *empty = NULL; + int i; + + /* Zap any old entries covering ADDR; notice empty entries on the way. */ + for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) { + hppa_tlb_entry *ent = &env->tlb[i]; + if (!ent->entry_valid) { + empty = ent; + } else if (ent->va_b <= addr && addr <= ent->va_e) { + hppa_flush_tlb_ent(env, ent); + empty = ent; + } + } + + /* If we didn't see an empty entry, evict one. */ + if (empty == NULL) { + empty = hppa_alloc_tlb_ent(env); + } + + /* Note that empty->entry_valid == 0 already. */ + empty->va_b = addr & TARGET_PAGE_MASK; + empty->va_e = empty->va_b + TARGET_PAGE_SIZE - 1; + empty->pa = extract32(reg, 5, 20) << TARGET_PAGE_BITS; +} + +/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ +void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +{ + hppa_tlb_entry *ent = hppa_find_tlb(env, addr); + + if (unlikely(ent == NULL || ent->entry_valid)) { + qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); + return; + } + + ent->access_id = extract32(reg, 1, 18); + ent->u = extract32(reg, 19, 1); + ent->ar_pl2 = extract32(reg, 20, 2); + ent->ar_pl1 = extract32(reg, 22, 2); + ent->ar_type = extract32(reg, 24, 3); + ent->b = extract32(reg, 27, 1); + ent->d = extract32(reg, 28, 1); + ent->t = extract32(reg, 29, 1); + ent->entry_valid = 1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6288bb9f67..c02d107041 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1344,7 +1344,10 @@ static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, } #ifndef CONFIG_USER_ONLY -/* Top 2 bits of the base register select sp[4-7]. */ +/* The "normal" usage is SP >= 0, wherein SP == 0 selects the space + from the top 2 bits of the base register. There are a few system + instructions that have a 3-bit space specifier, for which SR0 is + not special. To handle this, pass ~SP. */ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) { TCGv_ptr ptr; @@ -1352,7 +1355,12 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) TCGv_i64 spc; if (sp != 0) { - return cpu_sr[sp]; + if (sp < 0) { + sp = ~sp; + } + spc = get_temp_tl(ctx); + load_spr(ctx, spc, sp); + return spc; } ptr = tcg_temp_new_ptr(); @@ -2355,6 +2363,42 @@ static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } +#ifndef CONFIG_USER_ONLY +static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned sp; + unsigned rr = extract32(insn, 16, 5); + unsigned rb = extract32(insn, 21, 5); + unsigned is_data = insn & 0x1000; + unsigned is_addr = insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs, reg; + + if (is_data) { + sp = extract32(insn, 14, 2); + } else { + sp = ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); + reg = load_gpr(ctx, rr); + if (is_addr) { + gen_helper_itlba(cpu_env, addr, reg); + } else { + gen_helper_itlbp(cpu_env, addr, reg); + } + + /* Exit TB for ITLB change if mmu is enabled. This *should* not be + the case, since the OS TLB fill handler runs with mmu disabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_mem_mgmt[] = { { 0x04003280u, 0xfc003fffu, trans_nop }, /* fdc, disp */ { 0x04001280u, 0xfc003fffu, trans_nop }, /* fdc, index */ @@ -2371,6 +2415,12 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04002720u, 0xfc003fffu, trans_base_idx_mod }, /* pdc, base mod */ { 0x04001180u, 0xfc003fa0u, trans_probe }, /* probe */ { 0x04003180u, 0xfc003fa0u, trans_probe }, /* probei */ +#ifndef CONFIG_USER_ONLY + { 0x04000000u, 0xfc001fffu, trans_ixtlbx }, /* iitlbp */ + { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ + { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ + { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ +#endif }; static DisasJumpType trans_add(DisasContext *ctx, uint32_t insn, From patchwork Wed Jan 24 23:26:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125728 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp735166ljf; Wed, 24 Jan 2018 15:36:17 -0800 (PST) X-Google-Smtp-Source: AH8x224rfDOIdU6p1+VFl2cYi78WcDxb1130VWH5osH5JVwt9T2nj1oMe1ZE31GnOzEpuQYAhXAz X-Received: by 10.37.74.134 with SMTP id x128mr1330409yba.91.1516836977304; Wed, 24 Jan 2018 15:36:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836977; cv=none; d=google.com; s=arc-20160816; b=ge3Pqc+AllAE12oOj37y1demGFO2MBG9NvkyU2bZwfKWX0oQyYI9L4hBHTHlbokEQa PNLoLyu4EfCqL0kXZcZHiQXqJSUw4JgT0/wu1zP8oB1GIa5Uzdp1Lo2QI26MmXXrggXx JcjyUUDAhxtU09JwRFT38Pfri1PpBEnPIFDo/9bslI8KXSkdwkx72PJjwzB2wRBCxIfx UlHEf889cEw/14StYxmQZRs+Od+u2SvvHS9PEizSJIUSlTyUD3Zn6V4UvwJ5BFEGEhPf rFQQ8KZs2seWxgLA7vtNvAVOu3niomxLQBWs5pWo0wFIJ2Cp2ZAjExSnNQD8wGIBOBRu 4qMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=syJ0GoJ+f8WMWrwcEiicvHb0HU1xqjyXCwDF8fegEPk=; b=x5RXCTO06pODAJ11XDfKmpW5p7Z4zgLNFISpmCCC4mn/MuOj5r0Zxz34g5JSaM3yOH KcKGbswupo44HQyVwLdnQsLJlPqDohaKRaq456ufYjPxk9FolU6AukAURaSp+p3Pt832 IFKcM/4QiDrPdUYPAf5MRNXqZiL3oZKD6vKKXV4Q91IYtsprPLP5w9I7JfajZMWRnYul GfF3LerJAip/VbhlnEQjAGdXq4LSlYE0/iSIeO2nQp/fRarLtJxqw8oRdrBMI9S3SFWt fPebSrwqp0YOir82cdzeA99ErWmCbSt4e1XxgZlN6fxunAWaupkgHwzbN/SWBsYAldgK n+dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RRSdKFHJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:02 -0800 Message-Id: <20180124232625.30105-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 22/45] target/hppa: Implement P*TLB and P*TLBE insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/mem_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index d412093914..f059ddf3b9 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -88,4 +88,6 @@ DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 7c3c7d1415..2835d890f2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -270,4 +270,41 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) ent->t = extract32(reg, 29, 1); ent->entry_valid = 1; } + +/* Purge (Insn/Data) TLB. This is explicitly page-based, and is + synchronous across all processors. */ +static void ptlb_work(CPUState *cpu, run_on_cpu_data data) +{ + CPUHPPAState *env = cpu->env_ptr; + target_ulong addr = (target_ulong) data.target_ptr; + hppa_tlb_entry *ent = hppa_find_tlb(env, addr); + + if (ent && ent->entry_valid) { + hppa_flush_tlb_ent(env, ent); + } +} + +void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) +{ + CPUState *src = CPU(hppa_env_get_cpu(env)); + CPUState *cpu; + run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr); + + CPU_FOREACH(cpu) { + if (cpu != src) { + async_run_on_cpu(cpu, ptlb_work, data); + } + } + async_safe_run_on_cpu(src, ptlb_work, data); +} + +/* Purge (Insn/Data) TLB entry. This affects an implementation-defined + number of pages/entries (we choose all), and is local to the cpu. */ +void HELPER(ptlbe)(CPUHPPAState *env) +{ + CPUState *src = CPU(hppa_env_get_cpu(env)); + + memset(env->tlb, 0, sizeof(env->tlb)); + tlb_flush_by_mmuidx(src, 0xf); +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c02d107041..5b77688fc0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2397,6 +2397,42 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned m = extract32(insn, 5, 1); + unsigned sp; + unsigned rx = extract32(insn, 16, 5); + unsigned rb = extract32(insn, 21, 5); + unsigned is_data = insn & 0x1000; + unsigned is_local = insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs; + + if (is_data) { + sp = extract32(insn, 14, 2); + } else { + sp = ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, rx, 0, 0, sp, m, false); + if (m) { + save_gpr(ctx, rb, ofs); + } + if (is_local) { + gen_helper_ptlbe(cpu_env); + } else { + gen_helper_ptlb(cpu_env, addr); + } + + /* Exit TB for TLB change if mmu is enabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2420,6 +2456,10 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ + { 0x04000200u, 0xfc001fdfu, trans_pxtlbx }, /* pitlb */ + { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ + { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ + { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ #endif }; From patchwork Wed Jan 24 23:26:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125747 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp740212ljf; Wed, 24 Jan 2018 15:48:22 -0800 (PST) X-Google-Smtp-Source: AH8x227QcCmXcJRtsb/FMq01JfmTdvGSOFENDRpiLdYllJi/VuupK9SRvJvvb2oHcYySp0AAOMt1 X-Received: by 10.129.60.9 with SMTP id j9mr6707747ywa.315.1516837702835; Wed, 24 Jan 2018 15:48:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837702; cv=none; d=google.com; s=arc-20160816; b=tlC79A726hFx4vlYZmvjv3tZ3IJF6RG8YKDp4qgxFOz37uf1Kvuj1eQ05M8nifZYHJ PHFus1tgrgHqqYWa+Ei0pr2Z+f8LBDggROFA+HtOYv5rFhyJBlOigPlH35I1owxedCXs RUYXlWceW1BzhxhcjnbVJSIU9UHYHNIGmn7QDz5iUMpe6OLIFwfPszEigPW4z0r5nAOr laoWGZRoXn22O3k7SFHWSfK4Zu5Fr40C9AZ96jeG4WzdF3yhCTO6cywD6bZrPT0ND5h4 0fLtkAqmeuXEFupbpazrxa5V8Lo024PmixOgtXghmNPlZ3rlvFQt8le/f0EgkKf1OcSv O91w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=TlXxIZoHiIplbDXZZDFycXiOKS9HrTW99ifnkcnfjHA=; b=vDX36Q/ODLKkrChapYkDj8jaF0aSCJKABWHnw3gLLD7JBSabLIb/ATFAjao/BxhtI2 gFncE/kkl3ZC4Zj5YRek6X4QQpTc/G9sambsaDs2GzNUXARkyvxIWHqVYAf3hQthYVio JJIIauBkR4FAyIre8Cu9+x6A140YHXR5tBgl/G5HdlHASBpITK9XrOQ6K+F5u+rIVVp4 oH44+S+077ZBEC+Gr0jXmDp0yw3L/PgoVk1ZVQ0xX9oM18VZf3bLAHewiq8AYsahCrkE KMk1XZabO3dwteS7W/vbw/tUjZ0+IHEKvvnSzW8dHTnptgGnjEUtr7tCoR0mr5a00Vyb e6uA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NHSKrktJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:03 -0800 Message-Id: <20180124232625.30105-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 23/45] target/hppa: Implement LDWA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5b77688fc0..3d441ef4ac 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2954,12 +2954,50 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } +#ifndef CONFIG_USER_ONLY +static DisasJumpType trans_ldwa_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx = ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx = MMU_PHYS_IDX; + ret = trans_ld_idx_i(ctx, insn, di); + ctx->mmu_idx = hold_mmu_idx; + return ret; +} + +static DisasJumpType trans_ldwa_idx_x(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx = ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx = MMU_PHYS_IDX; + ret = trans_ld_idx_x(ctx, insn, di); + ctx->mmu_idx = hold_mmu_idx; + return ret; +} +#endif + static const DisasInsn table_index_mem[] = { { 0x0c001000u, 0xfc001300, trans_ld_idx_i }, /* LD[BHWD], im */ { 0x0c000000u, 0xfc001300, trans_ld_idx_x }, /* LD[BHWD], rx */ { 0x0c001200u, 0xfc001300, trans_st_idx_i }, /* ST[BHWD] */ { 0x0c0001c0u, 0xfc0003c0, trans_ldcw }, { 0x0c001300u, 0xfc0013c0, trans_stby }, +#ifndef CONFIG_USER_ONLY + { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ + { 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */ +#endif }; static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) From patchwork Wed Jan 24 23:26:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125726 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp735033ljf; Wed, 24 Jan 2018 15:35:56 -0800 (PST) X-Google-Smtp-Source: AH8x225TyLRY7s1HsKmNL72ngf2SrS6uOPzxOJrhG6s+hiekJUGw5ynJ6hC9M5W1N7TAo3FxmUPr X-Received: by 10.129.80.10 with SMTP id e10mr6795233ywb.429.1516836956494; Wed, 24 Jan 2018 15:35:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516836956; cv=none; d=google.com; s=arc-20160816; b=sl5RGLJAzS51C7tN+reOOrpx9MJXbhe7fQivaGf8eFeCIVqKv7/WAPXPgL3khOQ82J /IFCqcvvpW7Ysg0qOvCKcKAMXtTXhDXXrSaneMH4k9FlU7tX223XFjXPdjEHs8aLkiD2 mNZLYJ13c2wCT0DBuWFxQl2ax0sTYRPxJhCSdSnW2CYz1qH17LJ/EeFOwfA7RrrW5kDo ADj9uPzkCrM6F2/yFGUuBFkDF+a/Qw0KRPaH6N4j7enyQ39gSUGy8tX4EV94b5Ut8K3b 2OwHDWH0IIyl7A4lLe2CAyetOgEHDl7T2XIuVeq9lWCmN4EzK6lxHaOFyzzeUy55hME8 8XTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=l90A/DY5v8SNLXxNLjiu4jsgTj01n2M44ta48kw+zYE=; b=EK7RoQrNN4cSYKn1n+vFkmAnsWtIdKUz1/8Ge6TEoTsLWGk4HqfLb2sucPBEOyMj91 qKFB+GQTPHJ2XzubaEbkD2yzaBDXbH/00u5ef10H9fkN5GtPIyDCN7W+/BNlN3WX2yG1 pxZk1qpuFGAlIsY6exNKGxUf8v0eIwMXY35qoBmQjU4ZK8RYAZ6mcznRAaF/yg2iyeUU FLC0uwyllT1kX6t4HhRUPKF+XrQEAz1hpVhwsgbl9+JyCWyk5heYtLJR3FnwbuEDX37A flse1CWXmVEAwPGOpPwGuICsDVZcOVFkCFZzydTJUGFODr7Rr7fz4rqJgWCQ/OQzygRM zKEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UchfsvBq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:04 -0800 Message-Id: <20180124232625.30105-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 24/45] target/hppa: Implement LPA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 1 + target/hppa/mem_helper.c | 21 +++++++++++++++++++++ target/hppa/op_helper.c | 10 +++++----- target/hppa/translate.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 58 insertions(+), 5 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 31a3702684..a6e4091b6a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -344,5 +344,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; void hppa_cpu_alarm_timer(void *); #endif +void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index f059ddf3b9..1e733b7926 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -90,4 +90,5 @@ DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2835d890f2..fbe2e19d5d 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -307,4 +307,25 @@ void HELPER(ptlbe)(CPUHPPAState *env) memset(env->tlb, 0, sizeof(env->tlb)); tlb_flush_by_mmuidx(src, 0xf); } + +target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) +{ + hwaddr phys; + int prot, excp; + + excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, + MMU_DATA_LOAD, &phys, &prot); + if (excp >= 0) { + if (env->psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + env->cr[CR_IOR] = addr; + env->cr[CR_ISR] = addr >> 32; + } + if (excp == EXCP_DTLB_MISS) { + excp = EXCP_NA_DTLB_MISS; + } + hppa_dynamic_excp(env, excp, GETPC()); + } + return phys; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 6d19cab6c9..d270f94e31 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -34,7 +34,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) cpu_loop_exit(cs); } -static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) +void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra) { HPPACPU *cpu = hppa_env_get_cpu(env); CPUState *cs = CPU(cpu); @@ -46,14 +46,14 @@ static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra) void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) { if (unlikely((target_sreg)cond < 0)) { - dynexcp(env, EXCP_OVERFLOW, GETPC()); + hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); } } void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) { if (unlikely(cond)) { - dynexcp(env, EXCP_COND, GETPC()); + hppa_dynamic_excp(env, EXCP_COND, GETPC()); } } @@ -237,7 +237,7 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) env->fr[0] = (uint64_t)shadow << 32; if (hard_exp & shadow) { - dynexcp(env, EXCP_ASSIST, ra); + hppa_dynamic_excp(env, EXCP_ASSIST, ra); } } @@ -645,7 +645,7 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) /* ??? On second reading this condition simply seems to be undefined rather than a diagnosed trap. */ if (nsm & ~psw & PSW_Q) { - dynexcp(env, EXCP_ILL, GETPC()); + hppa_dynamic_excp(env, EXCP_ILL, GETPC()); } env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3d441ef4ac..082221f450 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2433,6 +2433,35 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_lpa(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + unsigned m = extract32(insn, 5, 1); + unsigned sp = extract32(insn, 14, 2); + unsigned rx = extract32(insn, 16, 5); + unsigned rb = extract32(insn, 21, 5); + TCGv_tl vaddr; + TCGv_reg ofs, paddr; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &vaddr, &ofs, rb, rx, 0, 0, sp, m, false); + + paddr = tcg_temp_new(); + gen_helper_lpa(paddr, cpu_env, vaddr); + + /* Note that physical address result overrides base modification. */ + if (m) { + save_gpr(ctx, rb, ofs); + } + save_gpr(ctx, rt, paddr); + tcg_temp_free(paddr); + + return nullify_end(ctx, DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2460,6 +2489,7 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ + { 0x04001340u, 0xfc003fc0u, trans_lpa }, #endif }; From patchwork Wed Jan 24 23:26:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125735 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp737013ljf; Wed, 24 Jan 2018 15:41:13 -0800 (PST) X-Google-Smtp-Source: AH8x225AGHKr4s51OaqL/Rdeebg5nespvkaWQO8FKr8f8KTpH1aC50YtdqDF/CsjVWm0SkSLtn0b X-Received: by 10.37.223.202 with SMTP id w193mr6697608ybg.68.1516837273718; Wed, 24 Jan 2018 15:41:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837273; cv=none; d=google.com; s=arc-20160816; b=mfZDLPaE4AVxdUS3DL/rvO/M/vaqQGofimJEqQmfwsG6Nmndyc8ZkeRcQBwu0b+MO+ fQ5Kdptgx22ytIUFOPyVchfAiPe25Ks3Qqc17BbBxAdGTT/LxBShQDkCrVYRhSrmMDCH TW/v+sKv67xnun1pp9G0u5vjytxeyNkJ5oJ98GhPcnDRW9fAbxosOOFJZFf405953Ji4 DUCPwqIAXgvQYCQRtu5Kkz+ZwpOaVozowqKwOMyfY1rvDDg8e5m4gYq7e+wZ8Tm3BL1B R58C9y2c/GIqleMNkIPNmInlvwJA6YX9j11IbQQgKBvrA5P2dGJ2v9JSq4cvzVLthaEp 3J0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8xzSBqTDqbAsaks2scycjrLsfLpa0BF7CTKM2I7mUds=; b=FN5eVR0j1v8pZT6x3r2FHyXcWKA/80tJ0rRu4iVNLQhf7tMYk6MI0ERuw+RzYOmxP8 9eVvvzhldg5lYm8ymmALf0aTMtjT4S3YGkeUt/E7Pxg1DH5JF/ndCkZm1gLLUJfNrP6o yyzJBk2lLySozaDTW01UOXowBcNuMQschHZmKUtAYYLW9P6Ic/+v+b6RdcLpfI+9qP0R G7tgCvHW/PW5+7c0+m3IhMETq+VWwU/QzK0wOjOX3qtFcoy3yKo+PyZ21cUTxN7CjU4j VIB94TuIokUhBNG3IlJHct7KsxydHpF0OJujCtXpG3tmhkoWqou0DHrm3goSCgAUHMZu /Uxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FJEllaNA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 25/45] target/hppa: Implement LCI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 082221f450..41e28ff64c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2462,6 +2462,25 @@ static DisasJumpType trans_lpa(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } + +static DisasJumpType trans_lci(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + TCGv_reg ci; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* The Coherence Index is an implementation-defined function of the + physical address. Two addresses with the same CI have a coherent + view of the cache. Our implementation is to return 0 for all, + since the entire address space is coherent. */ + ci = tcg_const_reg(0); + save_gpr(ctx, rt, ci); + tcg_temp_free(ci); + + return DISAS_NEXT; +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2490,6 +2509,7 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ { 0x04001340u, 0xfc003fc0u, trans_lpa }, + { 0x04001300u, 0xfc003fe0u, trans_lci }, #endif }; From patchwork Wed Jan 24 23:26:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125749 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp741423ljf; Wed, 24 Jan 2018 15:51:07 -0800 (PST) X-Google-Smtp-Source: AH8x224VZaEdmjqdhKHAM+R8KxQv0neTV2kKeQx8iysdvtOTg4R6AWubTcfYfjrKDnojBhxo2RAY X-Received: by 10.37.224.6 with SMTP id x6mr1376134ybg.82.1516837867017; Wed, 24 Jan 2018 15:51:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837867; cv=none; d=google.com; s=arc-20160816; b=dMNtrgZoauu4Qw+ZsMut1O4ZEZYwhE20jqyP+Sj28Xq7KBOa6SdzG/+7gokP5Q6Crg HyptfHAfZqzb+rkb0riXP+QiWIDggUiRa+WVOlIaTj2AMAitp2Bl4jWQ/wbJl3DdZhkL ztONp/XLRr3t1b/VSzUs2+2YJraSAnjTstf1wvpDY1PWHzrP0XmYTXK9wXFoNoZeHTU2 yUCFy+k9KthgK3bxCUTyTgR8a8VWP+m3gtl16YJgkw7ayMNtx6IMhniwEniUhwZyZSB6 jlQ2cWt+873SmitOgawu93DgwufWjNjiwJv1PqEisoeeUuN0bv+hywstuTMw5a2YR5JW PIMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xTWn9N9mXuKmrdgjJWIw2xv4sCHNU3rpymThFVTj1ak=; b=GbnB8yvEw4HxoThqQdIIMk2n1QKlW2dw60G9uLdqyGqTlUWNeb7xcIeLKP7PHq5F31 GoibD/zl9MkQfNx3cgHPZ5LwmwBxJOFyPR/5YMeODhJOadVZab1tVxO0/S/HfES1/6n1 AU/Ly2Ja/GZ3nxhjSBxoU0lVDd/MjhT6NwcBEIbEDewQAiV/6HmzjZalZeAA3AUcAwxQ svfX5kJb9P2qG90QRpMRqsudCcgYmp9ywHeyVm62zMqp7soW6eWljlx7drAdF3e1a3xb rCDaKaP/ALoBu+55cTzLTxrJrB2VYF7ThfNliTyND3p2vvd/2ZUZy9nPXRbX+KVvH0we QFOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=avyGF9xZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:06 -0800 Message-Id: <20180124232625.30105-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 26/45] target/hppa: Implement SYNCDMA insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 41e28ff64c..f3942b1baf 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2312,7 +2312,8 @@ static const DisasInsn table_system[] = { { 0x000014a0u, 0xffffffe0u, trans_mfia }, { 0x000004a0u, 0xffff1fe0u, trans_mfsp }, { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl }, - { 0x00000400u, 0xffffffffu, trans_sync }, + { 0x00000400u, 0xffffffffu, trans_sync }, /* sync */ + { 0x00100400u, 0xffffffffu, trans_sync }, /* syncdma */ { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, #ifndef CONFIG_USER_ONLY { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, From patchwork Wed Jan 24 23:26:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125731 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp736220ljf; Wed, 24 Jan 2018 15:39:13 -0800 (PST) X-Google-Smtp-Source: AH8x225OLxGTPjtqtY52NBJMuMDNEjE5pNQQk0Ph2I0t6Sps16RbuMfKhp/13TJZMTf6+UmnLCO7 X-Received: by 10.37.60.7 with SMTP id j7mr5400502yba.39.1516837153292; Wed, 24 Jan 2018 15:39:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837153; cv=none; d=google.com; s=arc-20160816; b=xMxi0qbsQrvnNEcQEw7/me3iAF/b4HNWCgBBBrQwRTuWBe+9UVUd9DN+pPU126d8Ku Elc7xlLFoWZEWz4ZuFH08NfqFExG9KxrtInyNJNhFpWPg08iUwD3d/TvpRpgPa2d9LCF +dlGPWy3svTr9CwOLdKvjj+f3LZbCE3MeIItYCQGExG5YebKJYAMgiaJTgieB3Y8x9k5 S9TUBiBLW6pr6n8F1LUShtRT0pcXHeaP99LWFSQmuDiDqv57W2/KuHQosn/KnQIHBL8J EF/uQGOzAXSDTMjAo9KDtz7h6SwWcXOIsUVyABR/UFvJ6Jq7G4rVLaWAdCvI+iO26+WE IVxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Jz9a0SHM1j6sy0TDh85R+Hbc1trXnrF4FvsYuaL1xsE=; b=FHKoA/KKdOQUWQx6zzigoCWoci0vbcL3z+Cq8txbWSKKLzSwNi8vageh9x0LPD5kxE g4bmpovwGq4aLyCyHgP18kMZAo3JkRnlLuB/L1JQFh6f7M6sfp0eHxjtv9NOysdLz5hv TXRJM1RRqi0nTe8/fLL5vT7tmKu+h+TetbjlGqdC4AtHO3437ZllRs3tShjTzaVFIheZ pZWlfqFycR6yWYdj+vgWcHA/aRsPhU7k1bIhJM24agOHlrr9zfvrIWAjej2XqN5A3v/p UUDIZdeneKr6SxfCquhVO07EZQNRAFoYrXpMxPaSLUFqRTPdxnexOPhdXJPcyJrPOS/N 24lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EmBIVCO8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:07 -0800 Message-Id: <20180124232625.30105-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 27/45] target/hppa: Implement halt and reset instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 13 +++++++++++++ target/hppa/translate.c | 25 ++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 1e733b7926..31320740da 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -80,6 +80,8 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) #ifndef CONFIG_USER_ONLY +DEF_HELPER_1(shutdown, noreturn, env) +DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index d270f94e31..c2eeced0e9 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include "sysemu/sysemu.h" #include "qemu/timer.h" @@ -639,6 +640,18 @@ void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) timer_mod(cpu->alarm_timer, timeout); } +void HELPER(shutdown)(CPUHPPAState *env) +{ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + helper_excp(env, EXCP_HLT); +} + +void HELPER(reset)(CPUHPPAState *env) +{ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + helper_excp(env, EXCP_HLT); +} + target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw = env->psw; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f3942b1baf..8c1ae4db78 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2302,6 +2302,18 @@ static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn, /* Exit the TB to recognize new interrupts. */ return nullify_end(ctx, DISAS_NORETURN); } + +static DisasJumpType gen_hlt(DisasContext *ctx, int reset) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + if (reset) { + gen_helper_reset(cpu_env); + } else { + gen_helper_shutdown(cpu_env); + } + return nullify_end(ctx, DISAS_NORETURN); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_system[] = { @@ -4519,7 +4531,18 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) case 0x15: /* unassigned */ case 0x1D: /* unassigned */ case 0x37: /* unassigned */ - case 0x3F: /* unassigned */ + break; + case 0x3F: +#ifndef CONFIG_USER_ONLY + /* Unassigned, but use as system-halt. */ + if (insn == 0xfffdead0) { + return gen_hlt(ctx, 0); /* halt system */ + } + if (insn == 0xfffdead1) { + return gen_hlt(ctx, 1); /* reset system */ + } +#endif + break; default: break; } From patchwork Wed Jan 24 23:26:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125753 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp743570ljf; Wed, 24 Jan 2018 15:56:58 -0800 (PST) X-Google-Smtp-Source: AH8x2272LOMpLIXu4s9M22SCybBlKb9xvVWaVYh8EkPafuUZhNLayvDCRiT2AQsL3HmE0O/R/k3j X-Received: by 10.37.142.14 with SMTP id p14mr6911992ybl.145.1516838218117; Wed, 24 Jan 2018 15:56:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838218; cv=none; d=google.com; s=arc-20160816; b=YxcaR15iYNGnZWbQVwBFGFxRP2YYVhV8xqLCulBbgpqcrf8w43TK3DbzR53acknQDS svCOdxcLzTGasdQmZpbdiLwzsfSL4dIaHKVlre07qmS7DxtbB6kSgsWITudgnfwq4JA/ CRUxYc567YIO41TpyNoWEUX7ts5y193GFW1EShOazQ8VhPyLFO8fQE2PS/xc9eciVBxE yi2W1XldNx1Xa2BfkxMF/RdwBi88B/9QpWLPduuEQ0N6GdO9aUk1UrYZdyV1Gv3sKPJx n1YNapluVDfzONAyJtI3BSXk7r2RIc5/JgGnkk2J0DGXKsDRaUoiM0Wc08x9jNPsX9eq oW4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=W1Ymh+4pKR0f40mVJ3TI2zd9pktGvqRjYsVLc8R5trk=; b=jc0Ud4UBx7nFxmnd69HPkXwooImuI2hQdALB7G9BZAoBiDPbX3O99XVLv2x3yrLS2o DWsUZSBs57Vc6nIVy0SFVJq7ITOg2X+lB9FWT5azkA5M2ERxI2eqCUIHRjOqvOfRr6fn UZSPQQOmWDZ3glLrR0w/fbqaVSXsVKjk9nzuHzjiC+0ej6YNN0stxdzMutcA7bPdnPD1 F2YwSOfBAHrzarqLikt3apa4MZ0tAIgOcs6m730OkIjpVLrt1ngesP+cVLD0PdKxagIE IalpnwKQouA7Rr8mQ0e2I0YNiLUZqcuz9qo1YEyiu3FGNEhI1Ce6BpYIwGPCbdNd+HSs 7SbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bFA0dOtj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.09 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:08 -0800 Message-Id: <20180124232625.30105-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 28/45] target/hppa: Optimize for flat addressing space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 11 ++++++++++- target/hppa/translate.c | 29 ++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a6e4091b6a..57e0bd6f0e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -282,7 +282,11 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } -/* Since PSW_CB will never need to be in tb->flags, reuse them. */ +/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. + * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the + * same value. + */ +#define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, @@ -318,6 +322,11 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, *cs_base |= (uint32_t)diff; } } + if ((env->sr[4] == env->sr[5]) + & (env->sr[4] == env->sr[6]) + & (env->sr[4] == env->sr[7])) { + flags |= TB_FLAG_SR_SAME; + } #endif *pflags = flags; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8c1ae4db78..24d357889e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -284,6 +284,7 @@ typedef struct DisasContext { TCGLabel *null_lab; uint32_t insn; + uint32_t tb_flags; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -323,6 +324,7 @@ typedef struct DisasInsn { /* global register indexes */ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; +static TCGv_i64 cpu_srH; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_i64 cpu_iasq_f; @@ -360,8 +362,8 @@ void hppa_translate_init(void) "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; /* SR[4-7] are not global registers so that we can index them. */ - static const char sr_names[4][4] = { - "sr0", "sr1", "sr2", "sr3" + static const char sr_names[5][4] = { + "sr0", "sr1", "sr2", "sr3", "srH" }; int i; @@ -377,6 +379,9 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, sr[i]), sr_names[i]); } + cpu_srH = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[4]), + sr_names[4]); for (i = 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v = &vars[i]; @@ -604,6 +609,8 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) #else if (reg < 4) { tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { + tcg_gen_mov_i64(dest, cpu_srH); } else { tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); } @@ -1362,6 +1369,9 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) load_spr(ctx, spc, sp); return spc; } + if (ctx->tb_flags & TB_FLAG_SR_SAME) { + return cpu_srH; + } ptr = tcg_temp_new_ptr(); tmp = tcg_temp_new(); @@ -1405,7 +1415,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, #else TCGv_tl addr = get_temp_tl(ctx); tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); - if (ctx->base.tb->flags & PSW_W) { + if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); } if (!is_phys) { @@ -2112,6 +2122,7 @@ static DisasJumpType trans_mtsp(DisasContext *ctx, uint32_t insn, if (rs >= 4) { tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + ctx->tb_flags &= ~TB_FLAG_SR_SAME; } else { tcg_gen_mov_i64(cpu_sr[rs], t64); } @@ -2407,7 +2418,7 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, /* Exit TB for ITLB change if mmu is enabled. This *should* not be the case, since the OS TLB fill handler runs with mmu disabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } @@ -2443,7 +2454,7 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, } /* Exit TB for TLB change if mmu is enabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } @@ -4556,6 +4567,7 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, int bound; ctx->cs = cs; + ctx->tb_flags = ctx->base.tb->flags; #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_USER_IDX; @@ -4563,9 +4575,8 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, ctx->iaoq_f = ctx->base.pc_first; ctx->iaoq_b = ctx->base.tb->cs_base; #else - ctx->privilege = (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - ctx->mmu_idx = (ctx->base.tb->flags & PSW_D - ? ctx->privilege : MMU_PHYS_IDX); + ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; + ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); /* Recover the IAOQ values from the GVA + PRIV. */ uint64_t cs_base = ctx->base.tb->cs_base; @@ -4597,7 +4608,7 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ ctx->null_cond = cond_make_f(); ctx->psw_n_nonzero = false; - if (ctx->base.tb->flags & PSW_N) { + if (ctx->tb_flags & PSW_N) { ctx->null_cond.c = TCG_COND_ALWAYS; ctx->psw_n_nonzero = true; } From patchwork Wed Jan 24 23:26:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125757 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp745198ljf; Wed, 24 Jan 2018 16:00:44 -0800 (PST) X-Google-Smtp-Source: AH8x224oGKIaOWizHTN/hMdOM3UHtUtfI7saj3B76vvNse4zeDq9CsLqvF3WCZJhKFIHK99R6mhB X-Received: by 10.129.84.139 with SMTP id i133mr6706977ywb.43.1516838444500; Wed, 24 Jan 2018 16:00:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838444; cv=none; d=google.com; s=arc-20160816; b=L17pEJ04WU0Ttgi22EgEuivbp/C9NsdeqO42hnWoTwQG6uNG9Ny8ZJnlES//p6tOMl 2lMMjmThXKIisdtImtZW6W3rxxvGnAVUTc2jkyDoTa6wQcUnatRBhcVdhpQrRcT/RsCP Cba04cxYVf4ta7OLGfbeWfEfeTGwvoy4lSzbMOwe9AF5jwjAWRgWeixYi8h8SgohvNPc HxYAosH6wdY9EzYtmVEX31Gh+GIn3Bi3RdbCIEK+NKssTEK9unEe/4EFv1hraXXHYTMW doZJ5h9wJwe+aWyFECgl+xDjCAuDrMTB+M2oW96nySHg/hjZLswX2+jrn0/kjx+FObMP nhOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mOdt0qcyMnQWoblkB3DI4JREleHkAHQJdcCTlXCiOnM=; b=WZ5ItOtbMgQSY3qSc5Jvjml/ZFoBQuTiA6yImbq1erwRYQzuixaGH0w9EVDP6BegB4 mcybjDhsVrOU7dXJLsc7o9d+YoGdfUgzmzLxGVINOOabGmkZ68JHr6uCpl4deZDR04EE gUPzEQKaBKVjMQGORHytrNYEXpQecS52/LU3bluhhL4dWQUkRmdo7/or9LOGD8SGo0iL LaLYICBd/pkirNyZOUVz8LN8W0nUtPhu3tsTrLeQONS6K77r2y3bJ94jF1ezLIk5hqm7 Adxb/66p9lqjoJavY46bYFK7fzneDYVZRbVkc7Iy4DIFwcWu3BmUaI4p24QzgDnXO4MN Rz1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=E43S/vqs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 29/45] target/hppa: Add system registers to gdbstub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/gdbstub.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) -- 2.14.3 diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index fc27aec073..e2e9c4d77f 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -41,15 +41,93 @@ int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) case 33: val = env->iaoq_f; break; + case 34: + val = env->iasq_f >> 32; + break; case 35: val = env->iaoq_b; break; + case 36: + val = env->iasq_b >> 32; + break; + case 37: + val = env->cr[CR_EIEM]; + break; + case 38: + val = env->cr[CR_IIR]; + break; + case 39: + val = env->cr[CR_ISR]; + break; + case 40: + val = env->cr[CR_IOR]; + break; + case 41: + val = env->cr[CR_IPSW]; + break; + case 43: + val = env->sr[4] >> 32; + break; + case 44: + val = env->sr[0] >> 32; + break; + case 45: + val = env->sr[1] >> 32; + break; + case 46: + val = env->sr[2] >> 32; + break; + case 47: + val = env->sr[3] >> 32; + break; + case 48: + val = env->sr[5] >> 32; + break; + case 49: + val = env->sr[6] >> 32; + break; + case 50: + val = env->sr[7] >> 32; + break; + case 51: + val = env->cr[CR_RC]; + break; + case 52: + val = env->cr[8]; + break; + case 53: + val = env->cr[9]; + break; + case 54: + val = env->cr[CR_SCRCCR]; + break; + case 55: + val = env->cr[12]; + break; + case 56: + val = env->cr[13]; + break; + case 57: + val = env->cr[24]; + break; + case 58: + val = env->cr[25]; + break; case 59: val = env->cr[26]; break; case 60: val = env->cr[27]; break; + case 61: + val = env->cr[28]; + break; + case 62: + val = env->cr[29]; + break; + case 63: + val = env->cr[30]; + break; case 64 ... 127: val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32); break; @@ -94,15 +172,93 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) case 33: env->iaoq_f = val; break; + case 34: + env->iasq_f = (uint64_t)val << 32; + break; case 35: env->iaoq_b = val; break; + case 36: + env->iasq_b = (uint64_t)val << 32; + break; + case 37: + env->cr[CR_EIEM] = val; + break; + case 38: + env->cr[CR_IIR] = val; + break; + case 39: + env->cr[CR_ISR] = val; + break; + case 40: + env->cr[CR_IOR] = val; + break; + case 41: + env->cr[CR_IPSW] = val; + break; + case 43: + env->sr[4] = (uint64_t)val << 32; + break; + case 44: + env->sr[0] = (uint64_t)val << 32; + break; + case 45: + env->sr[1] = (uint64_t)val << 32; + break; + case 46: + env->sr[2] = (uint64_t)val << 32; + break; + case 47: + env->sr[3] = (uint64_t)val << 32; + break; + case 48: + env->sr[5] = (uint64_t)val << 32; + break; + case 49: + env->sr[6] = (uint64_t)val << 32; + break; + case 50: + env->sr[7] = (uint64_t)val << 32; + break; + case 51: + env->cr[CR_RC] = val; + break; + case 52: + env->cr[8] = val; + break; + case 53: + env->cr[9] = val; + break; + case 54: + env->cr[CR_SCRCCR] = val; + break; + case 55: + env->cr[12] = val; + break; + case 56: + env->cr[13] = val; + break; + case 57: + env->cr[24] = val; + break; + case 58: + env->cr[25] = val; + break; case 59: env->cr[26] = val; break; case 60: env->cr[27] = val; break; + case 61: + env->cr[28] = val; + break; + case 62: + env->cr[29] = val; + break; + case 63: + env->cr[30] = val; + break; case 64: env->fr[0] = deposit64(env->fr[0], 32, 32, val); cpu_hppa_loaded_fr0(env); From patchwork Wed Jan 24 23:26:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125750 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp742629ljf; Wed, 24 Jan 2018 15:54:07 -0800 (PST) X-Google-Smtp-Source: AH8x224Cn3/iauOShq5s0I/Uk3ECOLnN66jk3DsdHxQjhkguaiKUxhf8FBw7cX5nLSZf/qhsFSb5 X-Received: by 10.37.199.11 with SMTP id w11mr7013643ybe.285.1516838047635; Wed, 24 Jan 2018 15:54:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838047; cv=none; d=google.com; s=arc-20160816; b=RBk6ZG4VbVBZoemI5ZkDkJyPJ+mH2fbiROBTiTkmBG271QTzf6A2VcS6jL8DU0oeSh r7ejrdizvijBgJWiLnj/AtvInZuR4BNmUzeD1ZcTO8NdVQzYVNgu7cJGBy9PqF7+kdM5 lJxPfvetO71L9U27uM9N/hn45q3HFHeROJSpt0tjd91eS7fIedrEuqfsRPowAgkC0BWg DOH7MroJfCwvste3uKSElqMmA5UwiI0sSHaum0z7zhe1Au08R6sN8itgRZqWYCps9lSh OjS+qANUteDzX2EK6n1SCrflNF2anEFOVsvFCOOYochrAkAdSqEk3jnhvlJqY78PV9rV 8utg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=CGmoeVcqiAmOqDS89hTb5p7XLCN2XOrTKuUeMRPriRM=; b=r6v+pQ8nGhPofCnGFdgNX02i7zA2fv18hfNWA/QBajC2hjwp4xVPKAbkV9YTPcQSY7 oZPKU35mVDsi4oaElnNz/pX4JtZsh/jPYUN7dVIZbNlxXL4Fjm7mc/fWS1vl8w/ZgBap WVx79VwlTBwOYAAK5PwtRZp+Pksw8+GWmdnexjIbdh9J5zxXBoMIMjXZbFtm2n1RzYYe QEk1IEQcdRMPab4Bn+o6VIApWL25gbHgETJKuemD9ICmUZ5xqd+1swK6cwPtTjzf7vtM OcFGIoEW3vCR5sBl4zcmc6gU1hR/0xvS4kMftcASpVQyVVmB0GNWsVI0CfcP9kru3WQS ED3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LNL9Vl7H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.12 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:10 -0800 Message-Id: <20180124232625.30105-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 30/45] target/hppa: Add migration for the cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/cpu.c | 1 + target/hppa/machine.c | 181 ++++++++++++++++++++++++++++++++++++++++++++++ target/hppa/Makefile.objs | 1 + 4 files changed, 184 insertions(+) create mode 100644 target/hppa/machine.c -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 57e0bd6f0e..8a87b8a9b3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -351,6 +351,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int midx); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; +extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6be6eb0a7b..5213347720 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -184,6 +184,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; #else cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; + dc->vmsd = &vmstate_hppa_cpu; #endif cc->do_unaligned_access = hppa_cpu_do_unaligned_access; cc->disas_set_info = hppa_cpu_disas_set_info; diff --git a/target/hppa/machine.c b/target/hppa/machine.c new file mode 100644 index 0000000000..8e077788c3 --- /dev/null +++ b/target/hppa/machine.c @@ -0,0 +1,181 @@ +/* + * HPPA interrupt helper routines + * + * Copyright (c) 2017 Richard Henderson + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "migration/cpu.h" + +#if TARGET_REGISTER_BITS == 64 +#define qemu_put_betr qemu_put_be64 +#define qemu_get_betr qemu_get_be64 +#define VMSTATE_UINTTL_V(_f, _s, _v) \ + VMSTATE_UINT64_V(_f, _s, _v) +#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) +#else +#define qemu_put_betr qemu_put_be32 +#define qemu_get_betr qemu_get_be32 +#define VMSTATE_UINTTR_V(_f, _s, _v) \ + VMSTATE_UINT32_V(_f, _s, _v) +#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) +#endif + +#define VMSTATE_UINTTR(_f, _s) \ + VMSTATE_UINTTR_V(_f, _s, 0) +#define VMSTATE_UINTTR_ARRAY(_f, _s, _n) \ + VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, 0) + + +static int get_psw(QEMUFile *f, void *opaque, size_t size, VMStateField *field) +{ + CPUHPPAState *env = opaque; + cpu_hppa_put_psw(env, qemu_get_betr(f)); + return 0; +} + +static int put_psw(QEMUFile *f, void *opaque, size_t size, + VMStateField *field, QJSON *vmdesc) +{ + CPUHPPAState *env = opaque; + qemu_put_betr(f, cpu_hppa_get_psw(env)); + return 0; +} + +static const VMStateInfo vmstate_psw = { + .name = "psw", + .get = get_psw, + .put = put_psw, +}; + +/* FIXME: Use the PA2.0 format, which is a superset of the PA1.1 format. */ +static int get_tlb(QEMUFile *f, void *opaque, size_t size, VMStateField *field) +{ + hppa_tlb_entry *ent = opaque; + uint32_t val; + + memset(ent, 0, sizeof(*ent)); + + ent->va_b = qemu_get_be64(f); + ent->pa = qemu_get_betr(f); + val = qemu_get_be32(f); + + ent->entry_valid = extract32(val, 0, 1); + ent->access_id = extract32(val, 1, 18); + ent->u = extract32(val, 19, 1); + ent->ar_pl2 = extract32(val, 20, 2); + ent->ar_pl1 = extract32(val, 22, 2); + ent->ar_type = extract32(val, 24, 3); + ent->b = extract32(val, 27, 1); + ent->d = extract32(val, 28, 1); + ent->t = extract32(val, 29, 1); + + ent->va_e = ent->va_b + TARGET_PAGE_SIZE - 1; + return 0; +} + +static int put_tlb(QEMUFile *f, void *opaque, size_t size, + VMStateField *field, QJSON *vmdesc) +{ + hppa_tlb_entry *ent = opaque; + uint32_t val = 0; + + if (ent->entry_valid) { + val = 1; + val = deposit32(val, 1, 18, ent->access_id); + val = deposit32(val, 19, 1, ent->u); + val = deposit32(val, 20, 2, ent->ar_pl2); + val = deposit32(val, 22, 2, ent->ar_pl1); + val = deposit32(val, 24, 3, ent->ar_type); + val = deposit32(val, 27, 1, ent->b); + val = deposit32(val, 28, 1, ent->d); + val = deposit32(val, 29, 1, ent->t); + } + + qemu_put_be64(f, ent->va_b); + qemu_put_betr(f, ent->pa); + qemu_put_be32(f, val); + return 0; +} + +static const VMStateInfo vmstate_tlb = { + .name = "tlb entry", + .get = get_tlb, + .put = put_tlb, +}; + +static VMStateField vmstate_env_fields[] = { + VMSTATE_UINTTR_ARRAY(gr, CPUHPPAState, 32), + VMSTATE_UINT64_ARRAY(fr, CPUHPPAState, 32), + VMSTATE_UINT64_ARRAY(sr, CPUHPPAState, 8), + VMSTATE_UINTTR_ARRAY(cr, CPUHPPAState, 32), + VMSTATE_UINTTR_ARRAY(cr_back, CPUHPPAState, 2), + VMSTATE_UINTTR_ARRAY(shadow, CPUHPPAState, 7), + + /* Save the architecture value of the psw, not the internally + expanded version. Since this architecture value does not + exist in memory to be stored, this requires a but of hoop + jumping. We want OFFSET=0 so that we effectively pass ENV + to the helper functions, and we need to fill in the name by + hand since there's no field of that name. */ + { + .name = "psw", + .version_id = 0, + .size = sizeof(uint64_t), + .info = &vmstate_psw, + .flags = VMS_SINGLE, + .offset = 0 + }, + + VMSTATE_UINTTR(iaoq_f, CPUHPPAState), + VMSTATE_UINTTR(iaoq_b, CPUHPPAState), + VMSTATE_UINT64(iasq_f, CPUHPPAState), + VMSTATE_UINT64(iasq_b, CPUHPPAState), + + VMSTATE_UINT32(fr0_shadow, CPUHPPAState), + + VMSTATE_ARRAY(tlb, CPUHPPAState, ARRAY_SIZE(((CPUHPPAState *)0)->tlb), + 0, vmstate_tlb, hppa_tlb_entry), + VMSTATE_UINT32(tlb_last, CPUHPPAState), + + VMSTATE_END_OF_LIST() +}; + +static const VMStateDescription vmstate_env = { + .name = "env", + .version_id = 1, + .minimum_version_id = 1, + .fields = vmstate_env_fields, +}; + +static VMStateField vmstate_cpu_fields[] = { + VMSTATE_CPU(), + VMSTATE_STRUCT(env, HPPACPU, 1, vmstate_env, CPUHPPAState), + VMSTATE_END_OF_LIST() +}; + +const VMStateDescription vmstate_hppa_cpu = { + .name = "cpu", + .version_id = 1, + .minimum_version_id = 1, + .fields = vmstate_cpu_fields, +}; diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index dcd60a6839..3359da5341 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1,2 +1,3 @@ obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o obj-y += int_helper.o +obj-$(CONFIG_SOFTMMU) += machine.o From patchwork Wed Jan 24 23:26:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125739 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp738098ljf; Wed, 24 Jan 2018 15:44:02 -0800 (PST) X-Google-Smtp-Source: AH8x227MJxM1Hzy6550u6/ymmMsMLBvlw+gL6TEHeCuoNfePBSvoJdI/3vRri2P8LQYa4iUWlshm X-Received: by 10.129.157.17 with SMTP id u17mr6542744ywg.86.1516837442702; Wed, 24 Jan 2018 15:44:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837442; cv=none; d=google.com; s=arc-20160816; b=sQHOsppvlvCSIKG90GnbwHHdufFxLh2hSr4zxIlAEMz1G55nL8Uov8EDMn+b3ccMVG RupsWdAre70H+ACYEcftBpwi4UORzJUKcsauPWymGVhniNsneh7voos3efPAwzlZNMo8 919Vz7vrrEWbZmPMK80sGrqIEdksDfxparjLFth2r+mmaoQ3BNrLyDFy64sxzjMQeYcp ezjVjXeXsp1yqwPPidXpCJA3kdVFscxXR+LTqvJl0fM6NxH30HGsWeQTQZ2X7/Dxe/y0 D74UFSp/nLh17l0HHN9z7JcivIeXL0Wt8+LQRUe1r30shsXN/0vonAt+ygiZjHI59S+M 7xJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lvnCci7iV1I3qKNv3WOKkyQvm2uDS3zDbCwOpT7h1yY=; b=dP6+LvLa0HxfWI6NJNq3tj6iZ40dbdaPyOwAq5xxv173pPmwu+Ds9Bz0RnqGNYDor8 uA4UDUtJZ7zT7D44kOmvEF/ksKhj4GJElvTHR+eSDYsGq78QS419i+J5sWXWOMwxx1Tp XCy6RVoXNhvw1gXmHXAufWrp7y4n8vgzMcrnK2rShdwl5l+gu9y5KaYVGEl9Lx1yLHOw qEre4/pZWxdxDVR+4hQRHsIIEATsd00kXYIHUDjKhamlz1Ud6o7t8MZuvhCyn7P877Ci j4tW3205K+PwolO+pT4l5cTHGF88Z+2TgYmRFCnT0nLUvMfK8q51a5uls2ebQo9R52CS leMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dQmhO3Fb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:11 -0800 Message-Id: <20180124232625.30105-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 31/45] target/hppa: Implement B,GATE insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/mem_helper.c | 8 ++++++++ target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8a87b8a9b3..79763b254c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -353,6 +353,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index fbe2e19d5d..c14317ebef 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -123,6 +123,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, break; default: /* execute: promote to privilege level type & 3 */ prot = x_prot; + break; } /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. */ @@ -328,4 +329,11 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) } return phys; } + +/* Return the ar_type of the TLB at VADDR, or -1. */ +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) +{ + hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); + return ent ? ent->ar_type : -1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 24d357889e..5b7824f065 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3782,6 +3782,53 @@ static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } +static DisasJumpType trans_b_gate(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned n = extract32(insn, 1, 1); + unsigned link = extract32(insn, 21, 5); + target_sreg disp = assemble_17(insn); + target_ureg dest = iaoq_dest(ctx, disp); + + /* Make sure the caller hasn't done something weird with the queue. + * ??? This is not quite the same as the PSW[B] bit, which would be + * expensive to track. Real hardware will trap for + * b gateway + * b gateway+4 (in delay slot of first branch) + * However, checking for a non-sequential instruction queue *will* + * diagnose the security hole + * b gateway + * b evil + * in which instructions at evil would run with increased privs. + */ + if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { + return gen_illegal(ctx); + } + +#ifndef CONFIG_USER_ONLY + if (ctx->tb_flags & PSW_C) { + CPUHPPAState *env = ctx->cs->env_ptr; + int type = hppa_artype_for_page(env, ctx->base.pc_next); + /* If we could not find a TLB entry, then we need to generate an + ITLB miss exception so the kernel will provide it. + The resulting TLB fill operation will invalidate this TB and + we will re-translate, at which point we *will* be able to find + the TLB entry and determine if this is in fact a gateway page. */ + if (type < 0) { + return gen_excp(ctx, EXCP_ITLB_MISS); + } + /* No change for non-gateway pages or for priv decrease. */ + if (type >= 4 && type - 4 < ctx->privilege) { + dest = deposit32(dest, 0, 2, type - 4); + } + } else { + dest &= -4; /* priv = 0 */ + } +#endif + + return do_dbranch(ctx, dest, link, n); +} + static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -3860,6 +3907,7 @@ static const DisasInsn table_branch[] = { { 0xe8004000u, 0xfc00fffdu, trans_blr }, { 0xe800c000u, 0xfc00fffdu, trans_bv }, { 0xe800d000u, 0xfc00dffcu, trans_bve }, + { 0xe8002000u, 0xfc00e000u, trans_b_gate }, }; static DisasJumpType trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, From patchwork Wed Jan 24 23:26:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125741 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp739142ljf; Wed, 24 Jan 2018 15:46:48 -0800 (PST) X-Google-Smtp-Source: AH8x227ryqIK/AGF1bFSNSIoybw40gwm4aYRSYw/DoIPnyqHoznx+G8xnB/o/tSP5cWm24q+f+2U X-Received: by 10.37.6.69 with SMTP id 66mr4554756ybg.139.1516837608378; Wed, 24 Jan 2018 15:46:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837608; cv=none; d=google.com; s=arc-20160816; b=M8wwlO0bJxkGtp9jRrt/sr9j/D0iBGMoJTUnxejWK64VGydhaukEr7ap0xj0FHmraf 0jsXGWyPAigbA3X5TiEg0rOLsXRMQhaHf8CCmJyK5ISdJDDuQ18Eu9t1xRgTDIlAK+v4 keAWzBwszejo2MMPO/SxNFEmIKYnGhoVN+MtD/HVk5wSXMj2zxbF45KFoCv2r6rNQYzb 8b6y3p2cre0pMVcZEnWoEC+jWm2dPh4x26S5WkenKfNMihk9XQ5DGygOAqn3fG18LFhv Exnh/eNXVp+MnNaYybOVoQTuRpX79C2iualZ0RabBkQSaLb732TBJl/KqHmrnsJL9kC2 rf4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=LP9OHUOYoiZv6JPSNgAYHzOXuxtIZkBZc9DCBZ38R7g=; b=QbLDb8yIhuBFXGbEBLJP1RlJClRW+MMzMADE2w4YKhqj36KvN1Ge+8nGtrwXjC0ROd E8ljugv5x2Sx9vWA6kTB2q83ZDzitquuLVTFC8O2T6OM/7Spp1CFbgX5D1Gea3ZCt5Ex rbIXVOugdrCLdi1IDjeJTexfCIhtu0/XkwW6Ftluyi3bUY/Mz3O5SubQQPd+oSjZLCfd 0NzptDxrno+wlEN/sPXExfNGWiAkimGSVJQGZmtPCk6GSzE3hdhxniUN0XkATev5UFyc OOtEolxTxGmCVLQrmscVgFaRbx/d+UMNBLuaq7/SdpU57daJdR08IlET3tMFS/59r9mU b4Eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cczMHoAN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:12 -0800 Message-Id: <20180124232625.30105-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 32/45] target/hppa: Only use EXCP_DTLB_MISS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c14317ebef..81bcbe45db 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -97,7 +97,9 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, if (ent == NULL || !ent->entry_valid) { phys = 0; prot = 0; - ret = (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); + /* ??? Unconditionally report data tlb miss, + even if this is an instruction fetch. */ + ret = EXCP_DTLB_MISS; goto egress; } From patchwork Wed Jan 24 23:26:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125756 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp744283ljf; Wed, 24 Jan 2018 15:58:53 -0800 (PST) X-Google-Smtp-Source: AH8x22482u4A9bQDcFdrLkIeTs+X5uB0rmvqS71qOCXq6TDwiMJckeFBuTMJ4aR03zW4ljeaW3Px X-Received: by 10.37.79.195 with SMTP id d186mr6728259ybb.482.1516838333353; Wed, 24 Jan 2018 15:58:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838333; cv=none; d=google.com; s=arc-20160816; b=O5VaVquE6EdyX5Y6AV5lXKOPu6dzoTh6vMkoy0LxiAtD3uTfMGQrRSSRaz5jANNY0t 2jD3/WGRT2AMxFBOD4ZpqkJxxwJvUt704CtF6A8JGXv2D/nLSUzhXVo/Kw4FOT7OkFbn DoVKdr1CPpzPaurybcIWmj6IkQdTEcGYk69+IaNX4oByuPMJ976+i177Yfya8Z8Vf5zR kDrK/Qvuz/zmbuZQt+zv0dvjkthAtQtjnVuX36UlklfjhkaoxpsE+bsfapxtn0rkVENN BruhWfm7vCJd6dubW6Xol194VFWIrzBL30/XVFCVKZuacsAy88mBl5C3ZWO/moy6TcSN MBpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xn4bhEwKxjI4xsJWxskbh4FNSmb1M37z+WdKtA6veJo=; b=dSFlJLYScYLlf4DODFpbpdJOLlse0l1GLIXGC6TW5O1REBE0AnQZP7hITOF0++D7VT vm7LPfJVADritvCx1BU0CGSdgwEBLvDVa7VAT8Ji51t4xs7ZazdIij3fSGjkIfiS326j Hg2VJc189APp/AYdettWrx6EbaNJfKBG1h4Izk+dn0ZzcYLt7lCckHdLQTeVM9wuu5HQ zX+lmDYePaFg5rLNDv/dnZq2hWvW32MwhJj6UfDwl6hE5IXfJiwVeadFVWHdwirrZDdp AmNrfjcZqQa5MVZhrODYMiTWJ20L5pXj+Wc/PXpTCfxhqdRt+6j+2KJqSq+U+arnEDHN /+aA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DEghSbpF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:13 -0800 Message-Id: <20180124232625.30105-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 33/45] qom: Add MMU_DEBUG_LOAD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Andreas_F=C3=A4rber?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This lets us tell bottom levels of virtual memory translation routines that the access is from within QEMU itself and bypass certain tests. Cc: Andreas Färber Signed-off-by: Richard Henderson --- include/qom/cpu.h | 3 ++- target/sh4/op_helper.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 93bd546879..6367acca97 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -64,7 +64,8 @@ typedef uint64_t vaddr; typedef enum MMUAccessType { MMU_DATA_LOAD = 0, MMU_DATA_STORE = 1, - MMU_INST_FETCH = 2 + MMU_INST_FETCH = 2, + MMU_DEBUG_LOAD = 3 } MMUAccessType; typedef struct CPUWatchpoint CPUWatchpoint; diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index d798f239cf..8fa7cb6b42 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -36,6 +36,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, case MMU_DATA_STORE: cs->exception_index = 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } From patchwork Wed Jan 24 23:26:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125754 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp743790ljf; Wed, 24 Jan 2018 15:57:33 -0800 (PST) X-Google-Smtp-Source: AH8x224tT29LGY1CiJLVH3IMZx4GhiH8fOazh9IlHCYtFagLZpeM4qEocXbNnDDXmnG7SumzqUAU X-Received: by 10.13.247.2 with SMTP id h2mr6587701ywf.443.1516838253769; Wed, 24 Jan 2018 15:57:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838253; cv=none; d=google.com; s=arc-20160816; b=WXhkJUC5wFRGATvp8NNllvec5XJgJX62Did7Tc+10oIcUmmO/pPTBHh5PzLQiAMn6P RE8AodXH5uPBA0iyhYCm56WHUjhKrdnsy8lD9pnXGBF4GxAeaAL9erSAYd1p6zS+w0dR ekjli5zVtTif/V9uhZDjWHTRWOzML6fAR9JyQXrDPXdvHxyZR30nUByoXdCGcMZwT2rH Y/DlfaMUIxIZ5aESK2LtaFQLBoVxaWva6eo8j+3c4VmPNKPoRwsGX/V7UwvL27v3hS3n 4VXyhDw3ikpHpMN8ikjhFAvoBCRU753UT9KRxdzRrlAC4O/4k0C+FoAlqhg5gAocKQYT OCVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=N3yFY3KLuN7s5EJ+56CkqrbPrG+d6aGgbHxBlCsk0dI=; b=OaLL+Ad51e36osY0Bs0oF35MgAkSWruaQNgywct3oY4zbvPiJkoOZk7wpqTwo6no++ WFUlWbjo33acA8vikf9ab3E6+ENXe9oEx8GlVR575cUQUsFY5/3KV6E5K62sJSW96WYa BJcMHgyVdQxbbvHtWR+vcz98Zp4dAwqOwFnlTkW2Nsa0Y1UcsU/732LgJlSCQsHqSjwB ohYbTgRTiSIZEKGDku2bC2d9bRqTwiSVDw9UsBwvYJdvZyTOdjJuRQKWx0VGRHDTfMi/ 78N6iGdXmiCeSkThSoC9DmT1VHk2nOUqKO0tvG+Y6jxf7jUa0klZw3MHVSXo+YrnoM9Y XmwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Kwoc938a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.17 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:14 -0800 Message-Id: <20180124232625.30105-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 34/45] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Bypass any tlb protection checks, as this is not a "real" access to memory per the architecture. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 19 ++++++++++++++----- 2 files changed, 15 insertions(+), 6 deletions(-) -- 2.14.3 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index d54d830196..1a9bbe268a 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -156,7 +156,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, 0, - MMU_INST_FETCH, + MMU_DEBUG_LOAD, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 81bcbe45db..4decfca407 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -131,12 +131,21 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. */ /* Map MMUAccessType to QEMU protection. */ - if (ifetch) { - a_prot = PROT_EXEC; - } else if (type == MMU_DATA_STORE) { - a_prot = PROT_WRITE; - } else { + switch (type) { + case MMU_DATA_LOAD: a_prot = PROT_READ; + break; + case MMU_DATA_STORE: + a_prot = PROT_WRITE; + break; + case MMU_INST_FETCH: + a_prot = PROT_EXEC; + break; + case MMU_DEBUG_LOAD: + ret = -1; + goto egress; + default: + g_assert_not_reached(); } if (unlikely(!(prot & a_prot))) { From patchwork Wed Jan 24 23:26:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125734 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp736393ljf; Wed, 24 Jan 2018 15:39:44 -0800 (PST) X-Google-Smtp-Source: AH8x224oyaBSD3c8GW9ekeGWPHC9Ace1L6d4cTfbdsFNWPQFMJSUK4hnjimPxXjc6y6pZ28pv7X+ X-Received: by 10.37.44.85 with SMTP id s82mr6770492ybs.248.1516837184084; Wed, 24 Jan 2018 15:39:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837184; cv=none; d=google.com; s=arc-20160816; b=ERKScSQAdVrSWySwxKVfZQ8jwMQf4718O5pl3k85MiSOXQdaP46rDBL+IaysPwCMq0 fPIRlk6pC7+vxO/EtVprnt61JoIBKR4C0Ay1S4NIxFMCmqmdW8HAD6Ot/byz4e5KBhq/ GCnag+WvXxWZ40i5GkOlCdNtgxYhvaYxlr7RNkGOwAQevLm7E8Mh/GHN5EzjNkdp2Oca oR8nYCQTLjUR5hUkrc1YSNuX/QOi/us4A0pf2S4uES4xzAotl42FhRELvxJ6Ynj9VRXl OaljTXKkei/UkjCQzx0hZ5m0RrZzgp+cvLjsanRyI5LK+d1M7F5KpxTLOKU3ai5VbpLN XarA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=4VkiwsHNT0XZNGRGb4PuM6QAQn0VXnbiBb9LBE57JCc=; b=QVgzCERZHWHJ2e+82kGDu7Q3ijldSCzfkV8ML5z+OhsHqjOrt6X6OigksxJm5TtwQ/ ZOlw5jikARuGe13u7zjcr6/PQbYm+jRUNk4oPKFrkC03CASUPIsLh63fG9o/JGDXSviR uLcOSKQLrwMfg9tnE91FkCoKW6pk1+abeEDM1v5oZNHWeCmYWOukA9uBjrInVLJ7F2R7 +vz1CX3OF3RgEcJGKRLsU3Dv2AeDCJXlsjitKUy6ombjhGO2CGI+CfvYbEXCUSeoO15G TW2cnA6XUDC3C4wkCqRmlSzvg8bYQj+uVwQ0zJ6ZEgWq9QMI8NcpLbLqQV1HNDFiL/1d QuGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pgbr7gm6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:15 -0800 Message-Id: <20180124232625.30105-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 35/45] target/hppa: Increase number of temp regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5b7824f065..a93e86c9e3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -277,7 +277,7 @@ typedef struct DisasContext { TCGv_reg iaoq_n_var; int ntempr, ntempl; - TCGv_reg tempr[4]; + TCGv_reg tempr[8]; TCGv_tl templ[4]; DisasCond null_cond; From patchwork Wed Jan 24 23:26:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125760 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp746679ljf; Wed, 24 Jan 2018 16:03:03 -0800 (PST) X-Google-Smtp-Source: AH8x224JPy9jhmhbRaX6bRuwXMUiuD8e5VZ+VmoGlI8ecdfdEVI6zma7L7X3Zwyuk3D/1kelNUu7 X-Received: by 10.129.196.8 with SMTP id j8mr6770267ywi.260.1516838583803; Wed, 24 Jan 2018 16:03:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838583; cv=none; d=google.com; s=arc-20160816; b=S+YS32uk8V3JtkIYMRn9CakXj+q6J+MGD5WaL7YqBgVYxxaHmRqK2b+4hy7+bOfGXZ lALZbsy2LEIs/RTm7sU+gaDCj+p0OpU6Co6dIAch47BbzVlgsFUeO1K/rj3luwqeZB/x pBAhcg9zgX1DEKtNrGiwUccb6/WWzCyhuCmDKfF+rE7RwLOzT5ybM540l2MXkRZBZvXP KxfB+w9+1yy1wbu5DRTXm0IxzL2k3gZoYNZJmoDfI6Ms83QWvQ7E9GxwZjRkk5ODsDaT fG7jVbbiKSwSKRNd83nUCR4FJfAh1NRAxEvNCjf8V+OqWUh6mJ/r0A7wmAl0qPZ3/sZn ZHZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=yysuXyU8pp+OJW+iGbsJa3l0BlyzeKUmKw/ticbpINs=; b=0QCfBCwVVqmtu7YN6dv2OG6hMQoRQi/fPaqE4H4P/YlWZIihNo2ay3zKwBkvBNHXpv +rGQC+2iceIagJUO3tJrlvxFbSRKH15yI/61kXyJ4PXwRuU1bte7vnYO4GrmAZTn1TXf qUFfO0eAyPHWgmGMPDIIDEzc2DkelkYCKeB0P7pPlLCazzzN9Lfj1Mv5/WAs4U6I43DE xT15rWVzqNWSVoYwzjULvRlqJKzmuiXNZmmCY71DNSrD9CDIX75p0ElHqiXeE03wDKgj CeNea5nTRDkeRrdQINRd30FSi1KZC5bZeZS1++GRhCWdzdg/1criwHtcVJoAiAWG2yW8 oNpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NxO41voB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:16 -0800 Message-Id: <20180124232625.30105-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 36/45] target/hppa: Fix comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Signed-off-by: Helge Deller Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a93e86c9e3..3327c085ff 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3193,7 +3193,7 @@ static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) /* FSTW without modification. */ return do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0); case 2: - /* LDW with modification. */ + /* STW with modification. */ return do_store(ctx, rt, rb, i, sp, (i < 0 ? 1 : -1), MO_TEUL); default: return gen_illegal(ctx); From patchwork Wed Jan 24 23:26:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125758 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp745782ljf; Wed, 24 Jan 2018 16:01:30 -0800 (PST) X-Google-Smtp-Source: AH8x2250ycrnsahJCuCKuSgwbtX0NjvBDXLAUxhFOhTrzwo2F7VXNvQlO7bk9idUFY8kJDmlyK7t X-Received: by 10.13.225.69 with SMTP id k66mr6993183ywe.114.1516838490777; Wed, 24 Jan 2018 16:01:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838490; cv=none; d=google.com; s=arc-20160816; b=Ho96HppYczpQMwcxYm0B9+37B3qdh0udua5OFkDzlt6Dz3sCFfySAFtxiMKrtgqBNI cp7vF2SmmOCwCDcC0p6/DMRPpnf0ehILQtWQAMSScAIbn7GSj2cjlGNgPaCBEwXfRywp KU9YVsexBmkJiKyR52SIRs/YBlMV0QjKGvUBe36ZE1KOii5CmC2J5z7lRaJCELsJ72PE W91y8eYisMhgfZBUbV6iNI5quduWmp5PDDYq7ialvVR9cTzUXxX9JPFMiK5XcsoMXc8O dFdJa2e+v9cqyqdVbl5Rn7eF1619PO4EjWjVQzEvNHsRwndGxCH8phaglWRsTeKkCuXH 2tCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=riVkqWj2V4rUtQRTP3OOrzMkWn1EMy0FQkn8R9nvamI=; b=QWsXd3E3F2F1+0ZCl5Eim/EogAJNJWsw+6DQYYbg234M6IgEY6TsF9UPOjLeC6qudZ fgWDiWrNQDPQyVcguRqMjui0G7my0V/c/kJz2/afLFcrKnUYXzJ1OYb1Z56r2+wlrKQ9 ZfEJrECwmj6MqrkXGoK6x3vC7N57dtxVc9RRt5QxDkYDTgwu+dAqPlIa84oE1WYiGwnx N3YUcFyg/7ucjmvu8nTcCoVEO8wm29u1TwdX1inTpEQCe6xkCljCaqtqWRbWMFebW8JP gAUzdrsg9gFbKIxJR/hCW+S9T9e0yy8rJboZqP28Jq4Sxm7KQVlxxizbK4YnoEJOEBGr Irdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i+pKbjcc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:17 -0800 Message-Id: <20180124232625.30105-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 37/45] target/hppa: Implement LDSID for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Signed-off-by: Helge Deller Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3327c085ff..cf67ca026e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2211,8 +2211,20 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, unsigned rt = extract32(insn, 0, 5); TCGv_reg dest = dest_gpr(ctx, rt); - /* Since we don't implement space registers, this returns zero. */ +#ifdef CONFIG_USER_ONLY + /* We don't implement space registers in user mode. */ tcg_gen_movi_reg(dest, 0); +#else + unsigned rb = extract32(insn, 21, 5); + unsigned sp = extract32(insn, 14, 2); + TCGv_i64 t0 = tcg_temp_new_i64(); + + tcg_gen_mov_i64(t0, space_select(ctx, sp, load_gpr(ctx, rb))); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_reg(dest, t0); + + tcg_temp_free_i64(t0); +#endif save_gpr(ctx, rt, dest); cond_free(&ctx->null_cond); From patchwork Wed Jan 24 23:26:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125761 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp748290ljf; Wed, 24 Jan 2018 16:06:31 -0800 (PST) X-Google-Smtp-Source: AH8x225bn3n3iaiG23R4npro7bfgKUZSdwYKkNya6GPlLAEUyVTuGRG14xNMrKCKbrzNzOxXSHvM X-Received: by 10.37.208.210 with SMTP id h201mr6701438ybg.479.1516838791658; Wed, 24 Jan 2018 16:06:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838791; cv=none; d=google.com; s=arc-20160816; b=DpUDRHTFxyL7DgZFOxsMSmVrhEWhmrCqLPAcqA2lMcUV4JlDPOANSgGHQg/RuF+hXq c3BxVnK4Y3fMTT1NBSt0CuiEAACG6j4QbpMTq9yoGHArlP4uhfbZf3I/DJHKxVJmzHCM zvXO+hu9qtXOazDszhvuKozSPMuuIQy+9NNZf1eBajeLphqJW413uuTJ/KwzTWRwuWhD SXoS9FcH3L6O0FYJ6Up7QmgWr9MRS+aRmyXbX7DDlTAlNdSERhy8HA2kJanzVl6/bxE8 gzH774nnRg/7/2RVC6F7dbzlQ6/H8HrFlzSjzvMaGTILsAM3ZMmycw+1kzeqqq9jmpmX sTag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8Kg5OMBfw7BaLTAtWZSwfZCWdsar5dGHF70bimc73J4=; b=tcOdJrKUD4ejKaRNimdlWHtVuTfiP0iVyhcY9zUW4zlWBpyad9bntH+4EovIfOKniG UFztcnQzty59cP8q2EF6xBPSDeBB3c6AoogUqN4O4gLIJPnamBDzYh+/n9KU5ROIs2xf unJxoQM1J7aORASEf5OHVgCw2tDRJki6/3UAL3+r/Qe1FCfO8hTqCKTn+3SSlt0APDEQ 7s8iMl4yuhNbflWK1t0+S9WP621xMSGw/1hZTDOrGpimT+1mCEU83TiLD2OW9izR8Wl/ oII9U++tMr7EVEetqFa8u4ui1Jf9CKPmeDkgXIpqkMemUT8lUYDUF4IUO1S3rE5NMF8S zSSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=S0LFBqBB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.23 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:18 -0800 Message-Id: <20180124232625.30105-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 38/45] target/hppa: Implement a pause instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cf67ca026e..d84090d479 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2826,9 +2826,45 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } +#ifndef CONFIG_USER_ONLY +/* These are QEMU extensions and are nops in the real architecture: + * + * or %r10,%r10,%r10 -- idle loop; wait for interrupt + * or %r31,%r31,%r31 -- death loop; offline cpu + * currently implemented as idle. + */ +static DisasJumpType trans_pause(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + TCGv_i32 tmp; + + /* No need to check for supervisor, as userland can only pause + until the next timer interrupt. */ + nullify_over(ctx); + + /* Advance the instruction queue. */ + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + nullify_set(ctx, 0); + + /* Tell the qemu main loop to halt until this cpu has work. */ + tmp = tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + gen_excp_1(EXCP_HALTED); + + return nullify_end(ctx, DISAS_NORETURN); +} +#endif + static const DisasInsn table_arith_log[] = { { 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */ { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */ +#ifndef CONFIG_USER_ONLY + { 0x094a024au, 0xffffffffu, trans_pause }, /* or r10,r10,r10 */ + { 0x0bff025fu, 0xffffffffu, trans_pause }, /* or r31,r31,r31 */ +#endif { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_reg }, { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_reg }, { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_reg }, From patchwork Wed Jan 24 23:26:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125755 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp743914ljf; Wed, 24 Jan 2018 15:57:53 -0800 (PST) X-Google-Smtp-Source: AH8x226crSzu8Mk25CjGHbt2shnjGodEsBCryzFz0HsdzZ2+1mRhaMP48ua0O2gNDRjrutIrS66c X-Received: by 10.37.31.214 with SMTP id f205mr7148120ybf.236.1516838273255; Wed, 24 Jan 2018 15:57:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838273; cv=none; d=google.com; s=arc-20160816; b=XOd5ugZ58rHJ22XfxHAVWKsEg+UY7LCcBh/Tnkbg2JFYlDbpM3CJhLKGpRQyEWTrlS /58Vp0Lluc4NWQ0HZ+5Jbkxw3+4tlOvuFKmYifL0kJK5cOdZv/fTpinKEHvXJKjcl/d5 X/NhcFIseiXNVGpwIPyv4j1eab3U6AbCYRAFL50tW7acY40ogLZ993lg0QkK97KbNc0+ lFm1vFCF+AuSqCwc6+cKHF1n65F2KEoDpFiAUkUuWjfG7RzYCAuvXskkm96BNvpJ0yU9 dsMVf795QeGiQC4q1Sw5oeag0onbXbI5+umCqWk3uUopvSD6V2lNIRFsojxVCNdDSuxC EFjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mAVHaLoUOgItDvWDmsq3JGoLZftVOaugLdkVZOQP1t4=; b=pP3upNgLlCe5cS0hb2vHkf5CDTVSpFWQObeFb0oCh0s3iQhVNoSsagWdYj5xrAaswd Bo41n+Jb2PiXMDw+lJVKzUo9KYeFkef46xiI0K7XZoDYE/TGd3NtMw6aKgeWONYjkghM DDH/VVOVNfSgEeT08ysjnvTAoQuyEDkzpIOIS8jF2/aKHBezpAOiqiu71bJdXI8E993+ H1s/NtUu+SoSRpQMDkXIOqFEFhMJleQR+v9usMHpownMOvFGTvgwvHlwfzmOltMptsz9 8O2CSy1U/vH8jlppwu+9a8mUs1JSfYKZet9TdT8ecm+oBUHbPB3ujSA2B+RA7We+y+BZ qSKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z2pB/5Jq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.24 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:19 -0800 Message-Id: <20180124232625.30105-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 39/45] target/hppa: Implement STWA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d84090d479..b9b097acc9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3108,6 +3108,22 @@ static DisasJumpType trans_ldwa_idx_x(DisasContext *ctx, uint32_t insn, ctx->mmu_idx = hold_mmu_idx; return ret; } + +static DisasJumpType trans_stwa_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx = ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx = MMU_PHYS_IDX; + ret = trans_st_idx_i(ctx, insn, di); + ctx->mmu_idx = hold_mmu_idx; + return ret; +} #endif static const DisasInsn table_index_mem[] = { @@ -3117,8 +3133,9 @@ static const DisasInsn table_index_mem[] = { { 0x0c0001c0u, 0xfc0003c0, trans_ldcw }, { 0x0c001300u, 0xfc0013c0, trans_stby }, #ifndef CONFIG_USER_ONLY - { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ { 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */ + { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ + { 0x0c001380u, 0xfc00d3c0, trans_stwa_idx_i }, /* STWA, im */ #endif }; From patchwork Wed Jan 24 23:26:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125737 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp737572ljf; Wed, 24 Jan 2018 15:42:34 -0800 (PST) X-Google-Smtp-Source: AH8x227jJmlebksc4cUuzBtYbjxJ/VlC4eZtoI0J8M5DHhDtwiMAmBTnp9GDJWeKfAiQxz6gg4FU X-Received: by 10.129.76.68 with SMTP id z65mr7014018ywa.513.1516837354538; Wed, 24 Jan 2018 15:42:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837354; cv=none; d=google.com; s=arc-20160816; b=Zd8jFqX4vMwSK2tH0sdOfAYN+o3x0hgyn2N2qLZgtevwrFAD5F3aFhtn56Yp7whD8d U4oKGHU1dxJkjsUyijKuIC3BsakR8uejZdM/GQ1TQJCXh4ZqYenAjAyiz8MAYC8vJFB8 pAouZOSrndtvhdX70UPjtVb9tTocXNj0kncpPENBeX8fDKdspaUfhKklCD+cwHsMsCdd YzvRZvuf3TFX+vkhOTKBkJZwvPjlXyDSqZajhDiDkZjw7A66aNgehler6cikNCmVSxhb jZpwlpwNThUGjDlr+dm6U41ji0+TVLcjmEAr2cJfHEbnO1z2d8gR1+Nj92AV52zdOc50 FGMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=quBtnarmfehsLQSA0SyAoxzs5iPyto2pNccU5OZX0IY=; b=RF3tup1c/greXrepIFyAn4ZXpAB2lztXa8qW55fT9byHWd0cNwxAzHWqhPMeJL6V8j qBB8mpx0aq0hHujf8LU6kcINZd5s8boIQBY4gXdt0KwLuhT7IqslgViSw557O3oNDG3e 2Fh+C+qJCNwxIgMhk7JKW+YrrbcjYckwOH9m8g6tVowiocrMa52La2yLweKe9dbeiRIO GWqzL3LByBrLZToh5dupd+uRPzCJEtEKGTmcQF2zJHKWLlNVVn1zKXw9WZ2wHO6XEOJY Rf8QaqbnbRmmtG89qWIkSos1PZYGcyvR7Nul9d2kd2rYPFDPNndIGbxjOLDYQo04Wh2J GNZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RqkWvK6q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.26 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:20 -0800 Message-Id: <20180124232625.30105-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 40/45] target/hppa: Enable MTTCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 6 ++++++ configure | 1 + 2 files changed, 7 insertions(+) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 79763b254c..3df3ebd19d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif +/* PA-RISC 1.x processors have a strong memory model. */ +/* ??? While we do not yet implement PA-RISC 2.0, those processors have + a weak memory model, but with TLB bits that force ordering on a per-page + basis. It's probably easier to fall back to a strong memory model. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #define CPUArchState struct CPUHPPAState #include "exec/cpu-defs.h" diff --git a/configure b/configure index 044c6fafe2..0046135db6 100755 --- a/configure +++ b/configure @@ -6549,6 +6549,7 @@ case "$target_name" in cris) ;; hppa) + mttcg="yes" ;; lm32) ;; From patchwork Wed Jan 24 23:26:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125742 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp739375ljf; Wed, 24 Jan 2018 15:47:19 -0800 (PST) X-Google-Smtp-Source: AH8x227Ql0Qv3BSQA5bW5z2ToRs5/FGFvwoPw7vgqokvKleTnKbWBu8MN3uRKyKgnSfz77byBAdc X-Received: by 10.37.123.133 with SMTP id w127mr6826089ybc.274.1516837639079; Wed, 24 Jan 2018 15:47:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837639; cv=none; d=google.com; s=arc-20160816; b=PkOZjp4bF7dZiprG+KrMd+rzz/DGkGQDwTw5paN+fuGQP76QFJnNCtTK0F5txuiEZS oo2fcDW1laQJjmOwncmBPpMugPPpOvmnGutGNpWRNJ34Wm1+vun9Kg3iHK69ACQMEygN 9lV1utd69yEGYbBGWwCh9k371PM4m800ag2zQtjoWj2xPwhZfrufOTkYHdz4TA9d4MAx dBvZ7eZwtAfI5eNknlkpy+iBLAo8whdz9/k0CTkFd2MTOnE/GFmqyr+2sNmfVQq+j6h/ uTqiNDigYbA5trheQnIHZ+q+zc9mw809FnJRRCkSB3KnBQENMiAbiZY2/VZUXjVZYHtB sZNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=HAkWzbNyq/NWf9wH76fUmDkbv9xXj9EHzXbveFbQb2k=; b=V7BOVVDPivUt2iRyavWBMzvXsZMEHwIuBgfUYSk7p8LUYs68chPomtV3S7u3KzCw11 I3m1oB6Hbfs7v199hilBWRMMbfgpRmxZPOrjrnEt6RVKUrmbt1LlJafcMb/61z9/DU24 Zh8txcy1AQCLN/bzO1HoVGiZXXq5RLzaKSE+X6UgQJPCk83Bqj1uSpz9pKKFG7nLdRwn gg3ucTwZD1wgD+H4EcWfp2FqsJI8j/HV6L/ZbswCBgFNpLisSGeFt4QXJ69wgcz29a0a rkcr+2D8RQ/4+RBTgqRhYlBwIp32VW12ddcy0axE7Fb4zAI2rgK+lIbT/GNUjvCBRxNr X40Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QYYX3emk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:21 -0800 Message-Id: <20180124232625.30105-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 41/45] hw/hppa: Implement DINO system board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Helge Deller Now that we have the prerequisites in target/hppa/, implement the hardware for a PA7100LC. This also enables build for hppa-softmmu. Signed-off-by: Helge Deller [rth: Since it is all new code, squashed all branch development withing hw/hppa/ to a single patch.] Signed-off-by: Richard Henderson --- Makefile.objs | 1 + hw/hppa/hppa_hardware.h | 40 +++ hw/hppa/hppa_sys.h | 24 ++ hw/hppa/dino.c | 518 +++++++++++++++++++++++++++++++++++++++ hw/hppa/machine.c | 246 ++++++++++++++++++- hw/hppa/pci.c | 90 +++++++ default-configs/hppa-softmmu.mak | 14 ++ hw/hppa/Makefile.objs | 2 +- hw/hppa/trace-events | 4 + 9 files changed, 937 insertions(+), 2 deletions(-) create mode 100644 hw/hppa/hppa_hardware.h create mode 100644 hw/hppa/hppa_sys.h create mode 100644 hw/hppa/dino.c create mode 100644 hw/hppa/pci.c create mode 100644 default-configs/hppa-softmmu.mak create mode 100644 hw/hppa/trace-events -- 2.14.3 diff --git a/Makefile.objs b/Makefile.objs index 669d8d684d..c52925133a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -155,6 +155,7 @@ trace-events-subdirs += hw/vfio trace-events-subdirs += hw/acpi trace-events-subdirs += hw/arm trace-events-subdirs += hw/alpha +trace-events-subdirs += hw/hppa trace-events-subdirs += hw/xen trace-events-subdirs += hw/ide trace-events-subdirs += ui diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h new file mode 100644 index 0000000000..2c61b1f77c --- /dev/null +++ b/hw/hppa/hppa_hardware.h @@ -0,0 +1,40 @@ +/* HPPA cores and system support chips. */ + +#define FIRMWARE_START 0xf0000000 +#define FIRMWARE_END 0xf0800000 + +#define DEVICE_HPA_LEN 0x00100000 + +#define GSC_HPA 0xffc00000 +#define DINO_HPA 0xfff80000 +#define DINO_UART_HPA 0xfff83000 +#define DINO_UART_BASE 0xfff83800 +#define DINO_SCSI_HPA 0xfff8c000 +#define LASI_HPA 0xffd00000 +#define LASI_UART_HPA 0xffd05000 +#define LASI_SCSI_HPA 0xffd06000 +#define LASI_LAN_HPA 0xffd07000 +#define LASI_LPT_HPA 0xffd02000 +#define LASI_AUDIO_HPA 0xffd04000 +#define LASI_PS2KBD_HPA 0xffd08000 +#define LASI_PS2MOU_HPA 0xffd08100 +#define LASI_GFX_HPA 0xf8000000 +#define CPU_HPA 0xfff10000 +#define MEMORY_HPA 0xfffbf000 + +#define PCI_HPA DINO_HPA /* PCI bus */ +#define IDE_HPA 0xf9000000 /* Boot disc controller */ + +/* offsets to DINO HPA: */ +#define DINO_PCI_ADDR 0x064 +#define DINO_CONFIG_DATA 0x068 +#define DINO_IO_DATA 0x06c + +#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) +#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) + +#define PORT_SERIAL1 (DINO_UART_HPA + 0x800) +#define PORT_SERIAL2 (LASI_UART_HPA + 0x800) + +#define HPPA_MAX_CPUS 32 /* max. number of SMP CPUs */ +#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h new file mode 100644 index 0000000000..a182d1f34e --- /dev/null +++ b/hw/hppa/hppa_sys.h @@ -0,0 +1,24 @@ +/* HPPA cores and system support chips. */ + +#ifndef HW_HPPA_SYS_H +#define HW_HPPA_SYS_H + +#include "target/hppa/cpu-qom.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_host.h" +#include "hw/ide.h" +#include "hw/i386/pc.h" +#include "hw/irq.h" + +#include "hw/hppa/hppa_hardware.h" + +PCIBus *dino_init(MemoryRegion *, qemu_irq *, qemu_irq *); + +#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" + +/* hppa_pci.c. */ +extern const MemoryRegionOps hppa_pci_ignore_ops; +extern const MemoryRegionOps hppa_pci_conf1_ops; +extern const MemoryRegionOps hppa_pci_iack_ops; + +#endif diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c new file mode 100644 index 0000000000..15aefde09c --- /dev/null +++ b/hw/hppa/dino.c @@ -0,0 +1,518 @@ +/* + * HP-PARISC Dino PCI chipset emulation. + * + * (C) 2017 by Helge Deller + * + * This work is licensed under the GNU GPL license version 2 or later. + * + * Documentation available at: + * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf + * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/devices.h" +#include "sysemu/sysemu.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hppa_sys.h" +#include "exec/address-spaces.h" + + +#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" + +#define DINO_IAR0 0x004 +#define DINO_IODC 0x008 +#define DINO_IRR0 0x00C /* RO */ +#define DINO_IAR1 0x010 +#define DINO_IRR1 0x014 /* RO */ +#define DINO_IMR 0x018 +#define DINO_IPR 0x01C +#define DINO_TOC_ADDR 0x020 +#define DINO_ICR 0x024 +#define DINO_ILR 0x028 /* RO */ +#define DINO_IO_COMMAND 0x030 /* WO */ +#define DINO_IO_STATUS 0x034 /* RO */ +#define DINO_IO_CONTROL 0x038 +#define DINO_IO_GSC_ERR_RESP 0x040 /* RO */ +#define DINO_IO_ERR_INFO 0x044 /* RO */ +#define DINO_IO_PCI_ERR_RESP 0x048 /* RO */ +#define DINO_IO_FBB_EN 0x05c +#define DINO_IO_ADDR_EN 0x060 +#define DINO_PCI_CONFIG_ADDR 0x064 +#define DINO_PCI_CONFIG_DATA 0x068 +#define DINO_PCI_IO_DATA 0x06c +#define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */ +#define DINO_GSC2X_CONFIG 0x7b4 /* RO */ +#define DINO_GMASK 0x800 +#define DINO_PAMR 0x804 +#define DINO_PAPR 0x808 +#define DINO_DAMODE 0x80c +#define DINO_PCICMD 0x810 +#define DINO_PCISTS 0x814 /* R/WC */ +#define DINO_MLTIM 0x81c +#define DINO_BRDG_FEAT 0x820 +#define DINO_PCIROR 0x824 +#define DINO_PCIWOR 0x828 +#define DINO_TLTIM 0x830 + +#define DINO_IRQS 11 /* bits 0-10 are architected */ +#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ +#define DINO_LOCAL_IRQS (DINO_IRQS + 1) +#define DINO_MASK_IRQ(x) (1 << (x)) + +#define PCIINTA 0x001 +#define PCIINTB 0x002 +#define PCIINTC 0x004 +#define PCIINTD 0x008 +#define PCIINTE 0x010 +#define PCIINTF 0x020 +#define GSCEXTINT 0x040 +/* #define xxx 0x080 - bit 7 is "default" */ +/* #define xxx 0x100 - bit 8 not used */ +/* #define xxx 0x200 - bit 9 not used */ +#define RS232INT 0x400 + +#define DINO_MEM_CHUNK_SIZE (8 * 1024 * 1024) /* 8MB */ + +#define DINO_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE) + +typedef struct DinoState { + PCIHostState parent_obj; + + /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, + so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */ + + uint32_t iar0; + uint32_t iar1; + uint32_t imr; + uint32_t ipr; + uint32_t icr; + uint32_t ilr; + uint32_t io_addr_en; + uint32_t io_control; + + MemoryRegion this_mem; + MemoryRegion pci_mem; + MemoryRegion pci_mem_alias[32]; + + AddressSpace bm_as; + MemoryRegion bm; + MemoryRegion bm_ram_alias; + MemoryRegion bm_pci_alias; + + MemoryRegion cpu0_eir_mem; +} DinoState; + +/* + * Dino can forward memory accesses from the CPU in the range between + * 0xf0800000 and 0xff000000 to the PCI bus. + */ +static void gsc_to_pci_forwarding(DinoState *s) +{ + uint32_t io_addr_en, tmp; + int enabled, i; + + tmp = extract32(s->io_control, 7, 2); + enabled = (tmp == 0x01); + io_addr_en = s->io_addr_en; + + memory_region_transaction_begin(); + for (i = 1; i < 31; i++) { + MemoryRegion *mem = &s->pci_mem_alias[i]; + if (enabled && (io_addr_en & (1U << i))) { + if (!memory_region_is_mapped(mem)) { + uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; + memory_region_add_subregion(get_system_memory(), addr, mem); + } + } else if (memory_region_is_mapped(mem)) { + memory_region_del_subregion(get_system_memory(), mem); + } + } + memory_region_transaction_commit(); +} + +static bool dino_chip_mem_valid(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + switch (addr) { + case DINO_IAR0: + case DINO_IAR1: + case DINO_IRR0: + case DINO_IRR1: + case DINO_IMR: + case DINO_IPR: + case DINO_ICR: + case DINO_ILR: + case DINO_IO_CONTROL: + case DINO_IO_ADDR_EN: + case DINO_PCI_IO_DATA: + return true; + case DINO_PCI_IO_DATA + 2: + return size <= 2; + case DINO_PCI_IO_DATA + 1: + case DINO_PCI_IO_DATA + 3: + return size == 1; + } + return false; +} + +static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + DinoState *s = opaque; + MemTxResult ret = MEMTX_OK; + AddressSpace *io; + uint16_t ioaddr; + uint32_t val; + + switch (addr) { + case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3: + /* Read from PCI IO space. */ + io = &address_space_io; + ioaddr = s->parent_obj.config_reg; + switch (size) { + case 1: + val = address_space_ldub(io, ioaddr, attrs, &ret); + break; + case 2: + val = address_space_lduw_be(io, ioaddr, attrs, &ret); + break; + case 4: + val = address_space_ldl_be(io, ioaddr, attrs, &ret); + break; + default: + g_assert_not_reached(); + } + break; + + case DINO_IO_ADDR_EN: + val = s->io_addr_en; + break; + case DINO_IO_CONTROL: + val = s->io_control; + break; + + case DINO_IAR0: + val = s->iar0; + break; + case DINO_IAR1: + val = s->iar1; + break; + case DINO_IMR: + val = s->imr; + break; + case DINO_ICR: + val = s->icr; + break; + case DINO_IPR: + val = s->ipr; + /* Any read to IPR clears the register. */ + s->ipr = 0; + break; + case DINO_ILR: + val = s->ilr; + break; + case DINO_IRR0: + val = s->ilr & s->imr & ~s->icr; + break; + case DINO_IRR1: + val = s->ilr & s->imr & s->icr; + break; + + default: + /* Controlled by dino_chip_mem_valid above. */ + g_assert_not_reached(); + } + + *data = val; + return ret; +} + +static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + DinoState *s = opaque; + AddressSpace *io; + MemTxResult ret; + uint16_t ioaddr; + + switch (addr) { + case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3: + /* Write into PCI IO space. */ + io = &address_space_io; + ioaddr = s->parent_obj.config_reg; + switch (size) { + case 1: + address_space_stb(io, ioaddr, val, attrs, &ret); + break; + case 2: + address_space_stw_be(io, ioaddr, val, attrs, &ret); + break; + case 4: + address_space_stl_be(io, ioaddr, val, attrs, &ret); + break; + default: + g_assert_not_reached(); + } + return ret; + + case DINO_IO_ADDR_EN: + /* Never allow first (=firmware) and last (=Dino) areas. */ + s->io_addr_en = val & 0x7ffffffe; + gsc_to_pci_forwarding(s); + break; + case DINO_IO_CONTROL: + s->io_control = val; + gsc_to_pci_forwarding(s); + break; + + case DINO_IAR0: + s->iar0 = val; + break; + case DINO_IAR1: + s->iar1 = val; + break; + case DINO_IMR: + s->imr = val; + break; + case DINO_ICR: + s->icr = val; + break; + case DINO_IPR: + /* Any write to IPR clears the register. */ + s->ipr = 0; + break; + + case DINO_ILR: + case DINO_IRR0: + case DINO_IRR1: + /* These registers are read-only. */ + break; + + default: + /* Controlled by dino_chip_mem_valid above. */ + g_assert_not_reached(); + } + return MEMTX_OK; +} + +static const MemoryRegionOps dino_chip_ops = { + .read_with_attrs = dino_chip_read_with_attrs, + .write_with_attrs = dino_chip_write_with_attrs, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + .accepts = dino_chip_mem_valid, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static const VMStateDescription vmstate_dino = { + .name = "Dino", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(iar0, DinoState), + VMSTATE_UINT32(iar1, DinoState), + VMSTATE_UINT32(imr, DinoState), + VMSTATE_UINT32(ipr, DinoState), + VMSTATE_UINT32(icr, DinoState), + VMSTATE_UINT32(ilr, DinoState), + VMSTATE_UINT32(io_addr_en, DinoState), + VMSTATE_UINT32(io_control, DinoState), + VMSTATE_END_OF_LIST() + } +}; + + +/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */ + +static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len) +{ + PCIHostState *s = opaque; + return pci_data_read(s->bus, s->config_reg | (addr & 3), len); +} + +static void dino_config_data_write(void *opaque, hwaddr addr, + uint64_t val, unsigned len) +{ + PCIHostState *s = opaque; + pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); +} + +static const MemoryRegionOps dino_config_data_ops = { + .read = dino_config_data_read, + .write = dino_config_data_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, + int devfn) +{ + DinoState *s = opaque; + + return &s->bm_as; +} + +/* + * Dino interrupts are connected as shown on Page 78, Table 23 + * (Little-endian bit numbers) + * 0 PCI INTA + * 1 PCI INTB + * 2 PCI INTC + * 3 PCI INTD + * 4 PCI INTE + * 5 PCI INTF + * 6 GSC External Interrupt + * 7 Bus Error for "less than fatal" mode + * 8 PS2 + * 9 Unused + * 10 RS232 + */ + +static void dino_set_irq(void *opaque, int irq, int level) +{ + DinoState *s = opaque; + uint32_t bit = 1u << irq; + uint32_t old_ilr = s->ilr; + + if (level) { + uint32_t ena = bit & ~old_ilr; + s->ipr |= ena; + s->ilr = old_ilr | bit; + if (ena & s->imr) { + uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0); + stl_be_phys(&address_space_memory, iar & -32, iar & 31); + } + } else { + s->ilr = old_ilr & ~bit; + } +} + +static int dino_pci_map_irq(PCIDevice *d, int irq_num) +{ + int slot = d->devfn >> 3; + int local_irq; + + assert(irq_num >= 0 && irq_num <= 3); + + local_irq = slot & 0x03; + + return local_irq; +} + +static void dino_set_timer_irq(void *opaque, int irq, int level) +{ + /* ??? Not connected. */ +} + +static void dino_set_serial_irq(void *opaque, int irq, int level) +{ + dino_set_irq(opaque, 10, level); +} + +PCIBus *dino_init(MemoryRegion *addr_space, + qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq) +{ + DeviceState *dev; + DinoState *s; + PCIBus *b; + int i; + + dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE); + s = DINO_PCI_HOST_BRIDGE(dev); + + /* Dino PCI access from main memory. */ + memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops, + s, "dino", 4096); + memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem); + + /* Dino PCI config. */ + memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj), + &pci_host_conf_be_ops, dev, "pci-conf-idx", 4); + memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj), + &dino_config_data_ops, dev, "pci-conf-data", 4); + memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, + &s->parent_obj.conf_mem); + memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA, + &s->parent_obj.data_mem); + + /* Dino PCI bus memory. */ + memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32); + + b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s, + &s->pci_mem, get_system_io(), + PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS); + s->parent_obj.bus = b; + qdev_init_nofail(dev); + + /* Set up windows into PCI bus memory. */ + for (i = 1; i < 31; i++) { + uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; + char *name = g_strdup_printf("PCI Outbound Window %d", i); + memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s), + name, &s->pci_mem, addr, + DINO_MEM_CHUNK_SIZE); + } + + /* Set up PCI view of memory: Bus master address space. */ + memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32); + memory_region_init_alias(&s->bm_ram_alias, OBJECT(s), + "bm-system", addr_space, 0, + 0xf0000000 + DINO_MEM_CHUNK_SIZE); + memory_region_init_alias(&s->bm_pci_alias, OBJECT(s), + "bm-pci", &s->pci_mem, + 0xf0000000 + DINO_MEM_CHUNK_SIZE, + 31 * DINO_MEM_CHUNK_SIZE); + memory_region_add_subregion(&s->bm, 0, + &s->bm_ram_alias); + memory_region_add_subregion(&s->bm, + 0xf0000000 + DINO_MEM_CHUNK_SIZE, + &s->bm_pci_alias); + address_space_init(&s->bm_as, &s->bm, "pci-bm"); + pci_setup_iommu(b, dino_pcihost_set_iommu, s); + + *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0); + *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0); + + return b; +} + +static int dino_pcihost_init(SysBusDevice *dev) +{ + return 0; +} + +static void dino_pcihost_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + k->init = dino_pcihost_init; + dc->vmsd = &vmstate_dino; +} + +static const TypeInfo dino_pcihost_info = { + .name = TYPE_DINO_PCI_HOST_BRIDGE, + .parent = TYPE_PCI_HOST_BRIDGE, + .instance_size = sizeof(DinoState), + .class_init = dino_pcihost_class_init, +}; + +static void dino_register_types(void) +{ + type_register_static(&dino_pcihost_info); +} + +type_init(dino_register_types) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 79958da18f..2b66298af5 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -16,20 +16,264 @@ #include "hw/ide.h" #include "hw/timer/i8254.h" #include "hw/char/serial.h" +#include "hw/hppa/hppa_sys.h" #include "qemu/cutils.h" #include "qapi/error.h" +#define MAX_IDE_BUS 2 + +static ISABus *hppa_isa_bus(void) +{ + ISABus *isa_bus; + qemu_irq *isa_irqs; + MemoryRegion *isa_region; + + isa_region = g_new(MemoryRegion, 1); + memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops, + NULL, "isa-io", 0x800); + memory_region_add_subregion(get_system_memory(), IDE_HPA, + isa_region); + + isa_bus = isa_bus_new(NULL, get_system_memory(), isa_region, + &error_abort); + isa_irqs = i8259_init(isa_bus, + /* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */ + NULL); + isa_bus_irqs(isa_bus, isa_irqs); + + return isa_bus; +} + +static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr) +{ + addr &= (0x10000000 - 1); + return addr; +} + +static HPPACPU *cpu[HPPA_MAX_CPUS]; +static uint64_t firmware_entry; static void machine_hppa_init(MachineState *machine) { + const char *kernel_filename = machine->kernel_filename; + const char *kernel_cmdline = machine->kernel_cmdline; + const char *initrd_filename = machine->initrd_filename; + PCIBus *pci_bus; + ISABus *isa_bus; + qemu_irq rtc_irq, serial_irq; + char *firmware_filename; + uint64_t firmware_low, firmware_high; + long size; + uint64_t kernel_entry = 0, kernel_low, kernel_high; + MemoryRegion *addr_space = get_system_memory(); + MemoryRegion *rom_region; + MemoryRegion *ram_region; + MemoryRegion *cpu_region; + long i; + + ram_size = machine->ram_size; + + /* Create CPUs. */ + for (i = 0; i < smp_cpus; i++) { + cpu[i] = HPPA_CPU(cpu_create(machine->cpu_type)); + + cpu_region = g_new(MemoryRegion, 1); + memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops, + cpu[i], g_strdup_printf("cpu%ld-io-eir", i), 4); + memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000, + cpu_region); + } + + /* Limit main memory. */ + if (ram_size > FIRMWARE_START) { + machine->ram_size = ram_size = FIRMWARE_START; + } + + /* Main memory region. */ + ram_region = g_new(MemoryRegion, 1); + memory_region_allocate_system_memory(ram_region, OBJECT(machine), + "ram", ram_size); + memory_region_add_subregion(addr_space, 0, ram_region); + + /* Init Dino (PCI host bus chip). */ + pci_bus = dino_init(addr_space, &rtc_irq, &serial_irq); + assert(pci_bus); + + /* Create ISA bus. */ + isa_bus = hppa_isa_bus(); + assert(isa_bus); + + /* Realtime clock, used by firmware for PDC_TOD call. */ + mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + /* Serial code setup. */ + if (serial_hds[0]) { + uint32_t addr = DINO_UART_HPA + 0x800; + serial_mm_init(addr_space, addr, 0, serial_irq, + 115200, serial_hds[0], DEVICE_BIG_ENDIAN); + fprintf(stderr, "Serial port created at 0x%x\n", addr); + } + + /* SCSI disk setup. */ + lsi53c895a_create(pci_bus); + + /* Network setup. e1000 is good enough, failing Tulip support. */ + for (i = 0; i < nb_nics; i++) { + pci_nic_init_nofail(&nd_table[i], pci_bus, "e1000", NULL); + } + + /* Load firmware. Given that this is not "real" firmware, + but one explicitly written for the emulation, we might as + well load it directly from an ELF image. */ + firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, + bios_name ? bios_name : + "hppa-firmware.img"); + if (firmware_filename == NULL) { + error_report("no firmware provided"); + exit(1); + } + + size = load_elf(firmware_filename, NULL, + NULL, &firmware_entry, &firmware_low, &firmware_high, + true, EM_PARISC, 0, 0); + + /* Unfortunately, load_elf sign-extends reading elf32. */ + firmware_entry = (target_ureg)firmware_entry; + firmware_low = (target_ureg)firmware_low; + firmware_high = (target_ureg)firmware_high; + + if (size < 0) { + error_report("could not load firmware '%s'", firmware_filename); + exit(1); + } + fprintf(stderr, "Firmware loaded at 0x%08lx-0x%08lx, entry at 0x%08lx.\n", + firmware_low, firmware_high, firmware_entry); + if (firmware_low < ram_size || firmware_high >= FIRMWARE_END) { + error_report("Firmware overlaps with memory or IO space"); + exit(1); + } + g_free(firmware_filename); + + rom_region = g_new(MemoryRegion, 1); + memory_region_allocate_system_memory(rom_region, OBJECT(machine), + "firmware", + (FIRMWARE_END - FIRMWARE_START)); + memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region); + + /* Load kernel */ + if (kernel_filename) { + fprintf(stderr, "LOADING kernel '%s'\n", kernel_filename); + size = load_elf(kernel_filename, &cpu_hppa_to_phys, + NULL, &kernel_entry, &kernel_low, &kernel_high, + true, EM_PARISC, 0, 0); + + /* Unfortunately, load_elf sign-extends reading elf32. */ + kernel_entry = (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry); + kernel_low = (target_ureg)kernel_low; + kernel_high = (target_ureg)kernel_high; + + if (size < 0) { + error_report("could not load kernel '%s'", kernel_filename); + exit(1); + } + + fprintf(stderr, "Kernel loaded at 0x%08lx-0x%08lx, entry at 0x%08lx, " + "size %ld kB.\n", + kernel_low, kernel_high, kernel_entry, size / 1024); + + if (kernel_cmdline) { + cpu[0]->env.gr[24] = 0x4000; + pstrcpy_targphys("cmdline", cpu[0]->env.gr[24], + TARGET_PAGE_SIZE, kernel_cmdline); + } + + if (initrd_filename) { + ram_addr_t initrd_base; + long initrd_size; + + initrd_size = get_image_size(initrd_filename); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + initrd_filename); + exit(1); + } + + /* Load the initrd image high in memory. + Mirror the algorithm used by palo: + (1) Due to sign-extension problems and PDC, + put the initrd no higher than 1G. + (2) Reserve 64k for stack. */ + initrd_base = MIN(ram_size, 1024 * 1024 * 1024); + initrd_base = initrd_base - 64 * 1024; + initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK; + + if (initrd_base < kernel_high) { + error_report("kernel and initial ram disk too large!"); + exit(1); + } + + load_image_targphys(initrd_filename, initrd_base, initrd_size); + cpu[0]->env.gr[23] = initrd_base; + cpu[0]->env.gr[22] = initrd_base + initrd_size; + } + } + + if (!kernel_entry) { + /* When booting via firmware, tell firmware if we want interactive + * mode (kernel_entry=1), and to boot from CD (gr[24]='d') + * or hard disc * (gr[24]='c'). + */ + kernel_entry = boot_menu ? 1 : 0; + cpu[0]->env.gr[24] = machine->boot_order[0]; + } + + /* We jump to the firmware entry routine and pass the + * various parameters in registers. After firmware initialization, + * firmware will start the Linux kernel with ramdisk and cmdline. + */ + cpu[0]->env.gr[26] = ram_size; + cpu[0]->env.gr[25] = kernel_entry; + + /* tell firmware how many SMP CPUs to present in inventory table */ + cpu[0]->env.gr[21] = smp_cpus; } +static void hppa_machine_reset(void) +{ + int i; + + qemu_devices_reset(); + + /* Start all CPUs at the firmware entry point. + * Monarch CPU will initialize firmware, secondary CPUs + * will enter a small idle look and wait for rendevouz. */ + for (i = 0; i < smp_cpus; i++) { + cpu_set_pc(CPU(cpu[i]), firmware_entry); + cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000; + } + + /* already initialized by machine_hppa_init()? */ + if (cpu[0]->env.gr[26] == ram_size) { + return; + } + + cpu[0]->env.gr[26] = ram_size; + cpu[0]->env.gr[25] = 0; /* no firmware boot menu */ + cpu[0]->env.gr[24] = 'c'; + /* gr22/gr23 unused, no initrd while reboot. */ + cpu[0]->env.gr[21] = smp_cpus; +} + + static void machine_hppa_machine_init(MachineClass *mc) { mc->desc = "HPPA generic machine"; + mc->default_cpu_type = TYPE_HPPA_CPU; mc->init = machine_hppa_init; + mc->reset = hppa_machine_reset; mc->block_default_type = IF_SCSI; - mc->max_cpus = 1; + mc->max_cpus = HPPA_MAX_CPUS; + mc->default_cpus = 1; mc->is_default = 1; mc->default_ram_size = 512 * M_BYTE; mc->default_boot_order = "cd"; diff --git a/hw/hppa/pci.c b/hw/hppa/pci.c new file mode 100644 index 0000000000..766420254e --- /dev/null +++ b/hw/hppa/pci.c @@ -0,0 +1,90 @@ +/* + * QEMU HP-PARISC PCI support functions. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hppa_sys.h" +#include "qemu/log.h" +#include "sysemu/sysemu.h" +#include "trace.h" + + +/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ + +static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0; +} + +static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) +{ +} + +const MemoryRegionOps hppa_pci_ignore_ops = { + .read = ignore_read, + .write = ignore_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 8, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 8, + }, +}; + + +/* PCI config space reads/writes, to byte-word addressable memory. */ +static uint64_t bw_conf1_read(void *opaque, hwaddr addr, + unsigned size) +{ + PCIBus *b = opaque; + return pci_data_read(b, addr, size); +} + +static void bw_conf1_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PCIBus *b = opaque; + pci_data_write(b, addr, val, size); +} + +const MemoryRegionOps hppa_pci_conf1_ops = { + .read = bw_conf1_read, + .write = bw_conf1_write, + .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +/* PCI/EISA Interrupt Acknowledge Cycle. */ + +static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) +{ + return pic_read_irq(isa_pic); +} + +static void special_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + trace_hppa_pci_iack_write(); +} + +const MemoryRegionOps hppa_pci_iack_ops = { + .read = iack_read, + .write = special_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; diff --git a/default-configs/hppa-softmmu.mak b/default-configs/hppa-softmmu.mak new file mode 100644 index 0000000000..013e5f046f --- /dev/null +++ b/default-configs/hppa-softmmu.mak @@ -0,0 +1,14 @@ +include pci.mak +include usb.mak +CONFIG_SERIAL=y +CONFIG_SERIAL_ISA=y +CONFIG_ISA_BUS=y +CONFIG_I8259=y +CONFIG_VIRTIO_PCI=$(CONFIG_PCI) +CONFIG_VIRTIO=y +CONFIG_E1000_PCI=y +CONFIG_IDE_ISA=y +CONFIG_IDE_CMD646=y +# CONFIG_IDE_MMIO=y +CONFIG_VIRTIO_VGA=y +CONFIG_MC146818RTC=y diff --git a/hw/hppa/Makefile.objs b/hw/hppa/Makefile.objs index 46b2ae18de..bef241ed25 100644 --- a/hw/hppa/Makefile.objs +++ b/hw/hppa/Makefile.objs @@ -1 +1 @@ -obj-y += machine.o +obj-y += machine.o pci.o dino.o diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events new file mode 100644 index 0000000000..14c67937e1 --- /dev/null +++ b/hw/hppa/trace-events @@ -0,0 +1,4 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/hppa/pci.c +hppa_pci_iack_write(void) "" From patchwork Wed Jan 24 23:26:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125746 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp740162ljf; Wed, 24 Jan 2018 15:48:15 -0800 (PST) X-Google-Smtp-Source: AH8x226uZKJeMgtMAb4UifUDT5i7hjk1I9KG1VsrP8e/Kw+OkEFaVQIsucYpcCxDR0iTAK1Y0YTd X-Received: by 10.13.254.193 with SMTP id o184mr5092102ywf.283.1516837695696; Wed, 24 Jan 2018 15:48:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837695; cv=none; d=google.com; s=arc-20160816; b=saPo/z1CZrSZ7QHoHRVV5k+nLTkW4TAHE3+aQepGIF4N/dRWAMcmN54WTnnacInxgT ZT0EE1wwuf5uAzslM2PfKL9Wc3KSI/6RdOYSvP8XqCwlJluN6ySYM1kYtN4KGldhHhlk ALjPiaeghZLthDCk1y5HC3LX5revCD9CKiozBvlf+HJAN7lPQUBc3TC2PRyGxZ2w5YsS MZB1MIPPF+FwlTIiSypMrFWYUhawd2KSqgrlqZmqenSZTRL7zpjWyk+Eq3R/2OrewE/V KpSYdo+BCapdi5XLsd95YUb/7gq9YPdnu9D45cmAOi9vsEUPXCYFEW7PWsjE7ofs/7SX j9EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=3qlGn/Cev9ZRnJ42AuM8l715MDL3FQWxgHiylJ1qML4=; b=LJfHlvTYFWqiuymjTblB7iNiY1JWswTGzAY3afx/9EBgpHbC3MELlpr7I4H/++IRiH zVTU1ufm9WPnHBTGENT05LdZ4atJBaztOdYmOkKh3cXc/O+ykbDudqxyhH0FOcOtR9lT UDKQU0PMqjjXQOEDVTRVjrBkkvuB/fVE1cs6AVGpkaBNwqJWjAGtK/j9mwc3WnJ3AswK tOCxdC/BcLdFHgsdtacGO0bwqi1YqrRV1iCGtNlZMlcMcW7Kpex7rULe5IPo9qULcSPP QiY7dPVY8FKatYIabk+L/qNr7xKvpzWx9UIZEKH8BDr5KNNCXl3B+tWLqlEVIk8EOQUz fuaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j1zTjPHH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:22 -0800 Message-Id: <20180124232625.30105-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: [Qemu-devel] [PATCH v3 42/45] pc-bios: Add hppa-firmware.img and git submodule X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- Makefile | 3 ++- .gitmodules | 3 +++ pc-bios/hppa-firmware.img | Bin 0 -> 461352 bytes roms/seabios-hppa | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) create mode 100755 pc-bios/hppa-firmware.img create mode 160000 roms/seabios-hppa -- 2.14.3 diff --git a/Makefile b/Makefile index d835bb92e7..5ffb7ed57f 100644 --- a/Makefile +++ b/Makefile @@ -649,7 +649,8 @@ s390-ccw.img s390-netboot.img \ spapr-rtas.bin slof.bin skiboot.lid \ palcode-clipper \ u-boot.e500 \ -qemu_vga.ndrv +qemu_vga.ndrv \ +hppa-firmware.img else BLOBS= endif diff --git a/.gitmodules b/.gitmodules index 1500579638..7a8282df46 100644 --- a/.gitmodules +++ b/.gitmodules @@ -40,3 +40,6 @@ [submodule "capstone"] path = capstone url = git://git.qemu.org/capstone.git +[submodule "roms/seabios-hppa"] + path = roms/seabios-hppa + url = git://github.com/hdeller/seabios-hppa.git diff --git a/pc-bios/hppa-firmware.img b/pc-bios/hppa-firmware.img new file mode 100755 index 0000000000000000000000000000000000000000..ae833437a73cb0955491b95f03cd42132d8d2e9c GIT binary patch literal 461352 zcmeFae|VJTo$vq5R zPuLD5K=>tKpanP7w3l>o&$_2QN>_XETdbm}wG9M_bhV{FwA1?SwRl>u#{GhPU+;Tn zFk0Q+v)})|*U5F|x}Uk9`{(EW+@Ig~{d{fKjk8^DSB{nab6bTxy3SixH)+%=$m_Q( zx0k1g<+5t6N-L!I{3j`6>ECkwgU@ou#`9Fbf1LmS@Lwt%{&UK*{@1+e*W5a1e&b&? z&6_tpGH+&MWcHn3x%;n|eq}|ZcK(W`Gv?epKXUs$U+EZctz5Ha)#|B#^;dV?xn|{k zw|#cmJ$L`r%H=EWx@*N({%ZA#rMKOA&+2Pdu3EL!id}QvHpIA4cZesm4 z%kH}8zU8;w_m$OaKD*|x?_9q8t`(pC@`^QPq``<~E#iM4|F7{sh5!5ce~SO%h}-ff zBDIB=qE$@#%1F|-+;Kb4y*Lu_yP{R@qpoLz@u(|y$@R-%+;WY&lR3TXnd_cwd4dVo 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 43/45] hw/hppa: Add MAINTAINERS entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) -- 2.14.3 diff --git a/MAINTAINERS b/MAINTAINERS index 753e7996ce..bee6b2bec7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -133,6 +133,7 @@ HPPA (PA-RISC) M: Richard Henderson S: Maintained F: target/hppa/ +F: hw/hppa/ F: disas/hppa.c LM32 From patchwork Wed Jan 24 23:26:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125762 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp749159ljf; Wed, 24 Jan 2018 16:08:25 -0800 (PST) X-Google-Smtp-Source: AH8x224CecrlFHinx4ECWlD0Cnmdto3NaHYgEwOiH63y/9Vw7wfF6ZDL6nV1HcbYxJtAjrMTxDcM X-Received: by 10.129.131.209 with SMTP id t200mr6746537ywf.403.1516838905764; Wed, 24 Jan 2018 16:08:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516838905; cv=none; d=google.com; s=arc-20160816; b=dbUNWHdMg8A1ukdAzYka3WNsDtmxSWDl4TMAxxVzisv6DzSxo1WcdualN63cflCp0h sih14FwJVXd9zvtSfym8AqVnHB90OGkkw6rbAiNnkas83aDPYcwDQh46DI5Yon3mxvIY MtSmjgf/AigVd3FSHQYiIwhhyH1I06DwmsCEvgE7KGiH7WClNKN4KJaHOYJZxMR23xRB frRXA67q7e8b0aTjvRBJCwr8h4ZrVrFuDvpF9fMZ9+wLwERb3BlcxUaLNJUK5kPLhYFs S+vdPhUqYWgwiQhWwqPwInNcHNVWcDgcZia/KhnZPWaGaKwiLCkwfzc5ZZ14WvDRZY3t ArBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=2tOlTE3fGONKVXMFT49Q6MX6S2UmKToc68yykLOO3mU=; b=b91Om6A0y/0Tv1m2dK6qtcTLO5Kp9PhTxTUEaRefN2QTF9JDywebGf6xOGP4u5Qob7 bpjsx9GYOhBtz8JRniCmoCRW86fL14pcQs9Bu3BSTOCRYSpQTxFQp3vG3hNMcuY+S32u 2cdYKLvReADybzbYiRSYde+TWcBqji/DpNIq0H83uSwMq414n6KGhz67T+zNZl3LbyMp 2QyDMtni7YbS4kFZha9Ppw9PgeZsbPOrpIbHH5SAX8ysrzDU0GsTOAaHn7UUhXe5ciht /69RKhEMbWrNScxLEFrdKMGzRZY+YrVWTBtT245VJXLyZ0ApDL7CQRGLg1Ix0CGR955L tg/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=E8ss0iRS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:24 -0800 Message-Id: <20180124232625.30105-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 44/45] target/hppa: Fix 32-bit operand masks for 0E FCVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b9b097acc9..c62ee72615 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4381,34 +4381,34 @@ static const DisasInsn table_float_0e[] = { /* floating point class one */ /* float/float */ { 0x38000a00, 0xfc1fffa0, FOP_WED = gen_helper_fcnv_d_s }, - { 0x38002200, 0xfc1fffc0, FOP_DEW = gen_helper_fcnv_s_d }, + { 0x38002200, 0xfc1fff60, FOP_DEW = gen_helper_fcnv_s_d }, /* int/float */ - { 0x38008200, 0xfc1ffe60, FOP_WEW = gen_helper_fcnv_w_s }, + { 0x38008200, 0xfc1ffe20, FOP_WEW = gen_helper_fcnv_w_s }, { 0x38008a00, 0xfc1fffa0, FOP_WED = gen_helper_fcnv_dw_s }, { 0x3800a200, 0xfc1fff60, FOP_DEW = gen_helper_fcnv_w_d }, { 0x3800aa00, 0xfc1fffe0, FOP_DED = gen_helper_fcnv_dw_d }, /* float/int */ - { 0x38010200, 0xfc1ffe60, FOP_WEW = gen_helper_fcnv_s_w }, + { 0x38010200, 0xfc1ffe20, FOP_WEW = gen_helper_fcnv_s_w }, { 0x38010a00, 0xfc1fffa0, FOP_WED = gen_helper_fcnv_d_w }, { 0x38012200, 0xfc1fff60, FOP_DEW = gen_helper_fcnv_s_dw }, { 0x38012a00, 0xfc1fffe0, FOP_DED = gen_helper_fcnv_d_dw }, /* float/int truncate */ - { 0x38018200, 0xfc1ffe60, FOP_WEW = gen_helper_fcnv_t_s_w }, + { 0x38018200, 0xfc1ffe20, FOP_WEW = gen_helper_fcnv_t_s_w }, { 0x38018a00, 0xfc1fffa0, FOP_WED = gen_helper_fcnv_t_d_w }, { 0x3801a200, 0xfc1fff60, FOP_DEW = gen_helper_fcnv_t_s_dw }, { 0x3801aa00, 0xfc1fffe0, FOP_DED = gen_helper_fcnv_t_d_dw }, /* uint/float */ - { 0x38028200, 0xfc1ffe60, FOP_WEW = gen_helper_fcnv_uw_s }, + { 0x38028200, 0xfc1ffe20, FOP_WEW = gen_helper_fcnv_uw_s }, { 0x38028a00, 0xfc1fffa0, FOP_WED = gen_helper_fcnv_udw_s }, { 0x3802a200, 0xfc1fff60, FOP_DEW = gen_helper_fcnv_uw_d }, { 0x3802aa00, 0xfc1fffe0, FOP_DED = gen_helper_fcnv_udw_d }, /* float/uint */ - { 0x38030200, 0xfc1ffe60, FOP_WEW = gen_helper_fcnv_s_uw }, + { 0x38030200, 0xfc1ffe20, FOP_WEW = gen_helper_fcnv_s_uw }, { 0x38030a00, 0xfc1fffa0, FOP_WED = gen_helper_fcnv_d_uw }, { 0x38032200, 0xfc1fff60, FOP_DEW = gen_helper_fcnv_s_udw }, { 0x38032a00, 0xfc1fffe0, FOP_DED = gen_helper_fcnv_d_udw }, /* float/uint truncate */ - { 0x38038200, 0xfc1ffe60, FOP_WEW = gen_helper_fcnv_t_s_uw }, + { 0x38038200, 0xfc1ffe20, FOP_WEW = gen_helper_fcnv_t_s_uw }, { 0x38038a00, 0xfc1fffa0, FOP_WED = gen_helper_fcnv_t_d_uw }, { 0x3803a200, 0xfc1fff60, FOP_DEW = gen_helper_fcnv_t_s_udw }, { 0x3803aa00, 0xfc1fffe0, FOP_DED = gen_helper_fcnv_t_d_udw }, From patchwork Wed Jan 24 23:26:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125740 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp738588ljf; Wed, 24 Jan 2018 15:45:17 -0800 (PST) X-Google-Smtp-Source: AH8x224onfIWlKOmKFfP2JtbyIGG9+cC7tUYzu+ktlKmNIWLQGEWpKMRfZAf6Hx9XX4o20AjAX+9 X-Received: by 10.37.79.130 with SMTP id d124mr6676420ybb.150.1516837517824; Wed, 24 Jan 2018 15:45:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516837517; cv=none; d=google.com; s=arc-20160816; b=NbVZCn6oB6wY6APsiHSKEhSsQKAlkicxRrk5zXOeR7CD6TVNhpJGLcBh8ORCMc0CwV OyzqhVo7Q4Me8NAHJfUTBCwbn9BCWvE+QAfLt35gWcVz8HPyEFZGf233mb/WtQoDk170 DTf5/mYY4uUT6J+GhLpEMmD9lsw26zr3PECDmkvajAqmSsjAVrE8ZriavPlSZ1NZyXXV Nld9BMghuii04yHKl2OTOPu9HvXrj5W/WNWcfEc6jTkEL6t7ad4f9OzTwd4NFqt7CnzD EqHaqbA5FMkh6ACa7fIr0igp81jFgxPaQGBbaFAqxRBdWYSLwPvkR6+5G0ML+KiKpko9 cSFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=bou4vMWC6c1I5NQcTnWp5K8e3ECnbVkjzlF5uw1WvYY=; b=MjM9buLUq5NbzxiSFyEpun67fNZ/wI+gBDZ+3A1obQkYhKCzC+0NCsPE6Rp67VDitp 2M/LMDJelpsSR8SJMkkXGRIpm+uq1O6f0WSsJK4y+cOawf3ciIMp1hRauQsFlDiUzEdT luZmjBLaX/J7y9CDLeNdq4OYgRDHZmZ3M7PAX8uReVdeA29qCkCD9gwheQ6Pylavrutn pfsIsehNxONMXYXq2Q/pxtO8hpj7sazfAW6UuQta2AI1OGAmfgpqvFDKxTnrCnrixBf4 B9IrKJeCt5qmW/lAa0Mri1NuKZEa0rzat8m1IQwhP0wR37kGl031vbnfWUZ/f88GJaM9 Okwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QPieKmJz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.34 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:25 -0800 Message-Id: <20180124232625.30105-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 45/45] target/hppa: Implement PROBE for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 3 +-- target/hppa/op_helper.c | 36 +++++++++++++++++++++++++----------- target/hppa/translate.c | 20 ++++++++++++++++---- 3 files changed, 42 insertions(+), 17 deletions(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 31320740da..51dc3f8b09 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -17,8 +17,7 @@ DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tr, tl) -DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tr, tl) +DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index c2eeced0e9..b386394bdf 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -160,21 +160,35 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, do_stby_e(env, addr, val, true); } -target_ureg HELPER(probe_r)(target_ulong addr) +target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr, + uint32_t level, uint32_t want) { #ifdef CONFIG_USER_ONLY - return page_check_range(addr, 1, PAGE_READ); + return page_check_range(addr, 1, want); #else - return 1; /* FIXME */ -#endif -} + int prot, excp; + hwaddr phys; -target_ureg HELPER(probe_w)(target_ulong addr) -{ -#ifdef CONFIG_USER_ONLY - return page_check_range(addr, 1, PAGE_WRITE); -#else - return 1; /* FIXME */ + /* Fail if the requested privilege level is higher than current. */ + if (level < (env->iaoq_f & 3)) { + return 0; + } + + /* Use MMU_DEBUG_LOAD to bypass TLB D/B/T bit checks. */ + excp = hppa_get_physical_address(env, addr, level, MMU_DEBUG_LOAD, + &phys, &prot); + if (excp >= 0) { + if (env->psw & PSW_Q) { + /* ??? Needs tweaking for hppa64. */ + env->cr[CR_IOR] = addr; + env->cr[CR_ISR] = addr >> 32; + } + if (excp == EXCP_DTLB_MISS) { + excp = EXCP_NA_DTLB_MISS; + } + hppa_dynamic_excp(env, excp, GETPC()); + } + return (want & prot) != 0; #endif } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c62ee72615..7c45b1706c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2380,21 +2380,33 @@ static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, { unsigned rt = extract32(insn, 0, 5); unsigned sp = extract32(insn, 14, 2); + unsigned rr = extract32(insn, 16, 5); unsigned rb = extract32(insn, 21, 5); unsigned is_write = extract32(insn, 6, 1); + unsigned is_imm = extract32(insn, 13, 1); TCGv_reg dest, ofs; + TCGv_i32 level, want; TCGv_tl addr; nullify_over(ctx); - /* ??? Do something with priv level operand. */ dest = dest_gpr(ctx, rt); form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false); - if (is_write) { - gen_helper_probe_w(dest, addr); + + if (is_imm) { + level = tcg_const_i32(extract32(insn, 16, 2)); } else { - gen_helper_probe_r(dest, addr); + level = tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(level, load_gpr(ctx, rr)); + tcg_gen_andi_i32(level, level, 3); } + want = tcg_const_i32(is_write ? PROT_WRITE : PROT_READ); + + gen_helper_probe(dest, cpu_env, addr, level, want); + + tcg_temp_free_i32(want); + tcg_temp_free_i32(level); + save_gpr(ctx, rt, dest); return nullify_end(ctx, DISAS_NEXT); }