From patchwork Wed Dec 2 14:06:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 336107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71ABDC83012 for ; Wed, 2 Dec 2020 14:07:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 32AD421D42 for ; Wed, 2 Dec 2020 14:07:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727392AbgLBOHE (ORCPT ); Wed, 2 Dec 2020 09:07:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727060AbgLBOHD (ORCPT ); Wed, 2 Dec 2020 09:07:03 -0500 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD70CC0617A6 for ; Wed, 2 Dec 2020 06:06:22 -0800 (PST) Received: by mail-ej1-x642.google.com with SMTP id bo9so4415205ejb.13 for ; Wed, 02 Dec 2020 06:06:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9fw0c1vN25O3p+wsWwRXMndS7i0G5WWG/KRE/RpibJE=; b=oNoI9O7sqt8AxEf9aQbniuMZTVMVkzdQm+4ld7zxACwP86n5QOf26HwsHZcHLvbuLo LpH/fGNUEPsS+G9TokdZAZpLjcF6JkoYnbouzZaOJimlj0kUzoFGq80FpvhRDmaMGAS6 eHD9zMKJnPn5UD1kY1LcU2V0EX2ZR24norGXsQfmH3M2wIlFfdbMOEstVvxkywKjYcvy Ozdu4yMHq4M3NYKURK38HH43AUZaF89xREF+goKFw+V9jKquv0t49xhDoEf/C9gwCrLa UMAXHgW6/ARlbmoidLjFWG5ov1B+E8zZCJWMO/+LlwQ70eXweuYIDXm/Faw36ReFFsKG tphQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9fw0c1vN25O3p+wsWwRXMndS7i0G5WWG/KRE/RpibJE=; b=Vd5xX2x2RY02dL5M+VgIsi0rCLKxZPLk/vCbcCD0zfDwZVUPn42oPzwFuze3uKh2aP UqtlKZ+bbiBeJNSEFuHtd7g5527uqoG7qg1iiFLZ01SXc2NdfJhtxjKQpcMlwv/Ebcxb Fvwx/9cGTSkM0pXc/fCQaHQ2clQYvGst1tg5zs6sa94j+GnbPLO44kXUDgtRH0gIvs+z pB4uFWccY525GVB2pwRTQ0xdkoW/JBd0UVEQuPh277Yd91Us9+x2d1K5xacH5ivjAUwP nIQwz/SfjCnhbqQpOuO80G2DnnAntbcNs9xd2i2E80lthqIrVoWEUJ5Us14YeZYWbP/V CMoQ== X-Gm-Message-State: AOAM5303dSYoCRi5HjXG3vDDcx2jH8eHcXuH3JLYlq3TtEw1UKivldpf dbxpHvaScDFJRE+CwoXOpOYUxg== X-Google-Smtp-Source: ABdhPJxLGUWNldyoyyGpA5ToxlYngiIh2OO2SeZyt9xreCYBTUSa60Dqz5S0QUfA7HKWxgSqgS1Jyw== X-Received: by 2002:a17:906:ee2:: with SMTP id x2mr2542193eji.326.1606917981519; Wed, 02 Dec 2020 06:06:21 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id x16sm313775ejo.104.2020.12.02.06.06.20 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:20 -0800 (PST) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Anurag Kumar Vulisha , Krzysztof Kozlowski , Rajan Vaja , Rob Herring , Venkatesh Yadav Abbarapu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/12] arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 Date: Wed, 2 Dec 2020 15:06:02 +0100 Message-Id: <679a09c15babcc6c209e5e6466a9fa76d1e2c271.1606917949.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable si5341 driver is the main chip for providing preprogrammed clocks for the whole platform. # cat /sys/kernel/debug/clk/clk_summary ... refhdmi 1 1 0 114285000 0 0 50000 xtal_0 0 0 0 114285000 0 0 50000 pll_0 0 0 0 40731174000000 0 0 50000 clk1_0 0 0 0 27000000 0 0 50000 clk0_0 0 0 0 27000000 0 0 50000 ref48M 1 2 0 48000000 0 0 50000 si5341 0 4 0 14000000 0 0 50000 clock-generator.N4 0 0 0 0 0 0 50000 clock-generator.N3 0 1 0 733260000 0 0 50000 clock-generator.9 0 1 0 33330000 0 0 50000 clock-generator.N2 0 1 0 104000000 0 0 50000 clock-generator.2 0 1 0 26000000 0 0 50000 clock-generator.N1 0 2 0 594000000 0 0 50000 clock-generator.7 0 1 0 74250000 0 0 50000 clock-generator.0 0 1 0 27000000 0 0 50000 clock-generator.N0 0 4 0 1000000000 0 0 50000 clock-generator.8 0 0 0 0 0 0 50000 clock-generator.6 0 1 0 125000000 0 0 50000 clock-generator.5 0 1 0 100000000 0 0 50000 clock-generator.4 0 1 0 100000000 0 0 50000 clock-generator.3 0 1 0 125000000 0 0 50000 clock-generator.1 0 0 0 0 0 0 50000 ... Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 56 ++++++++++++++++++- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 45 +++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 46 ++++++++++++++- 3 files changed, 145 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5ff7ab665374..68c2ad30d62d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -133,6 +133,13 @@ ina226-u75 { io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; @@ -489,9 +496,56 @@ i2c@1 { #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ + compatible = "silabs,si5341"; reg = <0x36>; - }; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_4: out@4 { + /* refclk4 for PS-GT, used for PCIE slot */ + reg = <4>; + always-on; + }; + si5341_5: out@5 { + /* refclk5 for PS-GT, used for PCIE */ + reg = <5>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_7: out@7 { + /* refclk7 PL CLK74 */ + reg = <7>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; + }; }; i2c@2 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7910ac125101..a29ff20090ce 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -133,6 +133,13 @@ ina226-u75 { io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; @@ -488,7 +495,45 @@ i2c@1 { #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_7: out@7 { + /* refclk7 PL CLK74 */ + reg = <7>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d9a8fdbbcae8..92b3cee62d11 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -116,6 +116,13 @@ ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; &dcc { @@ -374,9 +381,46 @@ i2c@1 { #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_5: out@5 { + /* refclk5 PL CLK100 */ + reg = <5>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; }; - }; i2c@2 { #address-cells = <1>; From patchwork Wed Dec 2 14:06:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 336105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5015DC83016 for ; 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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id t8sm431538eju.69.2020.12.02.06.06.26 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:26 -0800 (PST) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Kalyani Akula , Krzysztof Kozlowski , Laurent Pinchart , Manish Narani , Rajan Vaja , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/12] arm64: dts: zynqmp: Add label for zynqmp_ipi Date: Wed, 2 Dec 2020 15:06:05 +0100 Message-Id: <272e23e0123f02c559bfa4ada9de73eb197aced8.1606917949.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add label which is used by bootloader for adding bootloader specific flag. Signed-off-by: Michal Simek --- U-Boot needs to add u-boot,dm-pre-reloc; property --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 4fa820f78d76..8e9b54b5e70c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -99,7 +99,7 @@ opp03 { }; }; - zynqmp_ipi { + zynqmp_ipi: zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; From patchwork Wed Dec 2 14:06:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 336106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8D09C83013 for ; Wed, 2 Dec 2020 14:07:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F1D6221FA for ; Wed, 2 Dec 2020 14:07:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388836AbgLBOHu (ORCPT ); Wed, 2 Dec 2020 09:07:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728986AbgLBOHp (ORCPT ); Wed, 2 Dec 2020 09:07:45 -0500 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B599C061A4F for ; Wed, 2 Dec 2020 06:06:30 -0800 (PST) Received: by mail-ej1-x642.google.com with SMTP id m19so4426558ejj.11 for ; Wed, 02 Dec 2020 06:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VViFxFAQk/Dkx4vjvV9oGNxK0PemXCTJcyLmBlIKKyA=; b=cL47bNhqpa3x5USkIcigZLKjV6p4UO236MRU5j/jpNIUbe72FhOmFeglcCDhruhmgd O8sRNLdcDXlY+1JiVphnRhQ7jfuZzOXJoEPb+OiZlN6GsWAdEPxR3+wPC/JCZwBAXh8P +kPyjQhoCgRU5fSJ8vZnNQ2WNGL0K+WH5exPUnjQrGDdRhJaThgdD8tAWlbcDkHbayJH 0g6SQyvu6lK6oL/UacYDKiWoAKyPF9km/oBLOY8Q5+jBm+bEOoUIHPEZLHhdsfctFjgh aEddtvV2AXPu6YLLuzIxnRspskC/BdBX/WGcYgQ6Y0FeplRn/q20H24MzFG5gLxS6yXQ GFOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VViFxFAQk/Dkx4vjvV9oGNxK0PemXCTJcyLmBlIKKyA=; b=frdtlYv5poPIuRQjCZAmGxa2OjZHag92/NeNpXZXOy2MycwCFT2gk0rL2EXecHqVw7 UCOr6X6hB6Pns9phRsRRkuUfoRoNcMBcyAnhVB0pvd1nQPS62UO83oI4dlemnJPLl67E 1PqSum9XM2TwycJRveSo85FeqQLT5Lkzgkw6JufCaUAC/tQS5lxLYYPtzuHotlBHl7lm E5l5l1syc982X/aK/EvWbtRVttEZh0c2U8w/lDfVbnIYsK/I2FQXejoJVqpa4PZI+aKq U/LAVHx8EpOk4RHAHhYkjorGtMDQBDmlWQV7OmoQIrti1CmpJy0BwP7NIROp00zhIdC2 87Kg== X-Gm-Message-State: AOAM530nrId403wNCjs3ivvxsfIsvJByPA//wqF0K47d4M2z3ijrV0e5 7rZDfj4NaWH6gKxEc/8Xtc6ueA== X-Google-Smtp-Source: ABdhPJzMLWC1zUilMeaUt+2C44lMS+bj//KaUelctZALEzJ6jI6HHccAyxryF32ur16l0qmPZft9Fg== X-Received: by 2002:a17:907:a96:: with SMTP id by22mr2371741ejc.171.1606917988872; Wed, 02 Dec 2020 06:06:28 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id q19sm1285936ejz.90.2020.12.02.06.06.28 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:28 -0800 (PST) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Anurag Kumar Vulisha , Krzysztof Kozlowski , Rajan Vaja , Rob Herring , Venkatesh Yadav Abbarapu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/12] arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis Date: Wed, 2 Dec 2020 15:06:06 +0100 Message-Id: <67301f9bf40028a223ebf81a9dfd35deb4098e11.1606917949.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with 0 value to have it listed in case that files are copied to different projects where default case doesn't need to be handled in the same way. That's why explicitly list them too. Signed-off-by: Michal Simek --- Based on dt binding fix: https://lore.kernel.org/r/5fa17dfe4b42abefd84b4cbb7b8bcd4d31398f40.1606914986.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 + 5 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 68ecd0f7b2f2..71ebcaadb7c8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -233,11 +233,13 @@ &sdhci0 { status = "okay"; no-1-8-v; disable-wp; + xlnx,mio-bank = <0>; }; &sdhci1 { status = "okay"; bus-width = <0x4>; + xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index d92698ffbf8c..9abd10f6785a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -694,6 +694,7 @@ &sata { &sdhci1 { status = "okay"; no-1-8-v; + xlnx,mio-bank = <1>; }; &uart0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 5e2be9abc175..8ede619fea52 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -203,6 +203,7 @@ &sata { &sdhci1 { status = "okay"; no-1-8-v; + xlnx,mio-bank = <1>; disable-wp; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 4ec6715abab7..d60a30787022 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -689,6 +689,7 @@ &sata { &sdhci1 { status = "okay"; no-1-8-v; + xlnx,mio-bank = <1>; }; &uart0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 2969c4b71384..758de05c4a4b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -572,6 +572,7 @@ &sata { &sdhci1 { status = "okay"; no-1-8-v; + xlnx,mio-bank = <1>; }; &uart0 { From patchwork Wed Dec 2 14:06:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 336104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE108C64E7C for ; Wed, 2 Dec 2020 14:08:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 61F69221FA for ; Wed, 2 Dec 2020 14:08:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387451AbgLBOIY (ORCPT ); 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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id da9sm26813edb.13.2020.12.02.06.06.29 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:30 -0800 (PST) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Kalyani Akula , Krzysztof Kozlowski , Laurent Pinchart , Manish Narani , Rajan Vaja , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/12] arm64: dts: zynqmp: Wire arasan nand controller Date: Wed, 2 Dec 2020 15:06:07 +0100 Message-Id: <96d84568afbbe97e3520b71d8e3e1da7ef10dc66.1606917949.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing arasan controller with clocks. Disable it by default. Every board can enable it with specifying others properties. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index c94c3bb67edc..7af57619436d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -116,6 +116,10 @@ &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; +&nand0 { + clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 8e9b54b5e70c..fa7ea7f56299 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -461,6 +461,18 @@ mc: memory-controller@fd070000 { interrupts = <0 112 4>; }; + nand0: nand-controller@ff100000 { + compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; + status = "disabled"; + reg = <0x0 0xff100000 0x0 0x1000>; + clock-names = "controller", "bus"; + interrupt-parent = <&gic>; + interrupts = <0 14 4>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_NAND>; + }; + gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; From patchwork Wed Dec 2 14:06:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 336102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21D18C71156 for ; Wed, 2 Dec 2020 14:08:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C330A221FA for ; Wed, 2 Dec 2020 14:08:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388887AbgLBOIZ (ORCPT ); Wed, 2 Dec 2020 09:08:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388779AbgLBOIZ (ORCPT ); Wed, 2 Dec 2020 09:08:25 -0500 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD6EAC08E85E for ; Wed, 2 Dec 2020 06:06:38 -0800 (PST) Received: by mail-ej1-x630.google.com with SMTP id a16so4493483ejj.5 for ; Wed, 02 Dec 2020 06:06:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j2JtlLp4w1Z1giGmdmjx5S9UgA6z7cseKVrEi8bWQG4=; b=OImXmOsA4pg0SUS/a/BG+be5IQ+DHkJQdC404Vt81CIJ9nxaGxv7B6PxS5goj81sjG F1WuhU/Gib+bajvJoA5cavcNou9wHv4HKAgWSEaLdCjniEcyT2WhrQPlAYFXxOBuH0ax OLoQiX7QRCm1l1QQqevgRFePsjBfD29qC7NjzM8p8YuH5sDSaHFA6PbHRvVLrYjOWQkM 0z1Y9zxntwwUlaD7Umc+uv6AtOJY6RLDxPx4IYROLCmxWTtQcYHekg5PFBGUmJeVg2FI rFL91zcWi9rm/ryskzaK4oleo7lhWurD+2F6zAaDVmDlvkis8x8TxDvTe3Db3lQ5pkjN 4DXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=j2JtlLp4w1Z1giGmdmjx5S9UgA6z7cseKVrEi8bWQG4=; b=cadi1efV8H42bbGfBIvFRH4SMxBHjSjhHFANzC9rcoBKBZEv49x1rQ0RWzk+R/RVkp 4Px5ltSy1zqXEegZlK8jm+Tpb8d0ZICVtI7P9KFu+h3hkaRgsQBkyoozuAQvPnR7FKAy cTLGdw4kgPaYO0nBUMu71Uvjom/eom0Vum/aWtfLQPpihLPAUxwUbkiA2i6wn5/QTuJS Zd93CtHdEILKTo2toNja8X3qKd4b3uf+tro74K0A0OfIFv2hiqmWyvBy5EcQBiwDMd5S i9CM6fGnl9gTfcmjB8QvWGjtYUJnZeC0NYMcOPSjLQvj5rO90cvB3tYvpdFoMvCcoTN9 BgZQ== X-Gm-Message-State: AOAM5338GToALjDVj4HHkbuzFCHB8phH3XONtikkGnfXGAmkY4/UjRTL tLNq5o9XsKP4/4yef8DlK6SdKg== X-Google-Smtp-Source: ABdhPJwdnxMGJt6ac+bc3IyHxOVRZJe6Ppipm16wStzecL3j8bl+7oMKGpohjUM1sV8aaWWWUyTmWw== X-Received: by 2002:a17:906:1151:: with SMTP id i17mr1791190eja.250.1606917997323; Wed, 02 Dec 2020 06:06:37 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id y24sm27171edt.15.2020.12.02.06.06.36 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:36 -0800 (PST) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Kalyani Akula , Krzysztof Kozlowski , Laurent Pinchart , Manish Narani , Rajan Vaja , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 11/12] arm64: dts: zynqmp: Add missing iommu IDs Date: Wed, 2 Dec 2020 15:06:10 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing iommu IDs to all IPs which have IDs assigned. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 52 ++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 704696811116..14a2e69cf98b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -270,6 +270,8 @@ fpd_dma_chan1: dma@fd500000 { interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -281,6 +283,8 @@ fpd_dma_chan2: dma@fd510000 { interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -292,6 +296,8 @@ fpd_dma_chan3: dma@fd520000 { interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -303,6 +309,8 @@ fpd_dma_chan4: dma@fd530000 { interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -314,6 +322,8 @@ fpd_dma_chan5: dma@fd540000 { interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -325,6 +335,8 @@ fpd_dma_chan6: dma@fd550000 { interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -336,6 +348,8 @@ fpd_dma_chan7: dma@fd560000 { interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -347,6 +361,8 @@ fpd_dma_chan8: dma@fd570000 { interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -374,6 +390,8 @@ lpd_dma_chan1: dma@ffa80000 { interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -385,6 +403,8 @@ lpd_dma_chan2: dma@ffa90000 { interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -396,6 +416,8 @@ lpd_dma_chan3: dma@ffaa0000 { interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -407,6 +429,8 @@ lpd_dma_chan4: dma@ffab0000 { interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -418,6 +442,8 @@ lpd_dma_chan5: dma@ffac0000 { interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -429,6 +455,8 @@ lpd_dma_chan6: dma@ffad0000 { interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -440,6 +468,8 @@ lpd_dma_chan7: dma@ffae0000 { interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -451,6 +481,8 @@ lpd_dma_chan8: dma@ffaf0000 { interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -470,6 +502,8 @@ nand0: nand-controller@ff100000 { interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -482,6 +516,8 @@ gem0: ethernet@ff0b0000 { clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; @@ -496,6 +532,8 @@ gem1: ethernet@ff0c0000 { clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; @@ -510,6 +548,8 @@ gem2: ethernet@ff0d0000 { clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; @@ -524,6 +564,8 @@ gem3: ethernet@ff0e0000 { clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; @@ -618,6 +660,8 @@ qspi: spi@ff0f0000 { <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -647,6 +691,9 @@ sata: ahci@fd0c0000 { interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; + #stream-id-cells = <4>; + iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, + <&smmu 0x4c2>, <&smmu 0x4c3>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; reset-names = "sata_rst"; }; @@ -658,6 +705,8 @@ sdhci0: mmc@ff160000 { interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; + #stream-id-cells = <1>; + iommus = <&smmu 0x870>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -670,6 +719,8 @@ sdhci1: mmc@ff170000 { interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; + #stream-id-cells = <1>; + iommus = <&smmu 0x871>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -678,6 +729,7 @@ sdhci1: mmc@ff170000 { smmu: iommu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; + #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; From patchwork Wed Dec 2 14:06:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 336103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F7DC83013 for ; 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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id d14sm22091edn.31.2020.12.02.06.06.38 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:38 -0800 (PST) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Anurag Kumar Vulisha , Rajan Vaja , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/12] arm64: dts: zynqmp: Add description for zcu104 revC Date: Wed, 2 Dec 2020 15:06:11 +0100 Message-Id: <5b670099adb67b06ec0a7d1b04ed9f4076e520c1.1606917949.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c structure compare to revA. The rest of the board is the same from software perspective. Also enable DMAs and QSPI. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/Makefile | 1 + .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 282 ++++++++++++++++++ 2 files changed, 283 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 60f5443f3ef4..11fb4fd3ebd4 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts new file mode 100644 index 000000000000..414f98f1831e --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU104 + * + * (C) Copyright 2017 - 2020, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include +#include + +/ { + model = "ZynqMP ZCU104 RevC"; + compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ina226 { + compatible = "iio-hwmon"; + io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; + }; + + clock_8t49n287_5: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clock_8t49n287_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_8t49n287_3: clk27 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: ethernet-phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - IRPS5401_ALERT_B + * 1 - HDMI_8T49N241_INT_ALM + * 2 - MAX6643_OT_B + * 3 - MAX6643_FANFAIL_B + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7 - FMC_LPC_PRSNT_M2C_B + * 4, 10 - 17 - not connected + */ + }; + + /* Another connection to this bus via PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ + reg = <0x6c>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x43>; /* pmbus / i2c 0x13 */ + }; + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ + compatible = "infineon,irps5401"; + reg = <0x44>; /* pmbus / i2c 0x14 */ + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + u183: ina226@40 { /* u183 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x40>; + shunt-resistor = <5000>; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + /* 4, 6 not connected */ + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + }; +}; + +&rtc { + status = "okay"; +}; + +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio-bank = <1>; + disable-wp; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&watchdog0 { + status = "okay"; +};