From patchwork Thu Dec 3 14:20:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 337095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98F40C00130 for ; Thu, 3 Dec 2020 14:22:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D382207A9 for ; Thu, 3 Dec 2020 14:22:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726880AbgLCOVx (ORCPT ); Thu, 3 Dec 2020 09:21:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727822AbgLCOVx (ORCPT ); Thu, 3 Dec 2020 09:21:53 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F861C061A52 for ; Thu, 3 Dec 2020 06:21:12 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id t6so2915241lfl.13 for ; Thu, 03 Dec 2020 06:21:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/6wim9Ub2SwtjYj9niGLBRd7nsut6yLKYnhevmwWC/o=; b=Z9Rhg57g1DCSc0KWSEzs5Wt7vqrE+dqRvw1SDOx7OeWPYDwUhpqWJ/LvEEYRloQ3P9 XrfguVhNYmcRz/tXD8mzhWTso2hzMWmG2KYxN3I7xmx12myGplRet1CW4GO8UUmxYk+p vn3+k6bgAJyK4xi5kWJIOePqoMbXPXLopxVRp9pQXbRpyjn3ASoBfpfW6yAJYKk6gCYq 8UAfqvGTzotTY9jcgsBOB2VZ6eIRzrHx6NhJbux6o+LaQt2nxnRsdYFE6zuqPy8plaug +x6qTmOM6onFHFmsDI/1uami3AkZnwIh+QyC9MqtRa2D7dEdA31Zd0Gb+Ux6U/DjJBaW aW7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/6wim9Ub2SwtjYj9niGLBRd7nsut6yLKYnhevmwWC/o=; b=aobknz9/PgSJU0dzdyYYt/tF2zBJ2Pk3g52e/gjGYnPIOQs+3QBgAVbZjS5Wr86QCb dr+Dgj2OgqkAl2bWp+GLAoq5jWAs7T8764qCWMRH2oGc2HLh9b+SjutivQbng/XF5UwL YVl0m5yfTXPkZjTiKhAhsXKol+R3YrRc+7azhi0cMI1s8zRgyUykxiBx/YdVpeaNDpsR yMmCtgKoHLuu2LBHKhQCWP2ZKo2F5cjAxH0IZBDq8YnThYMoFK1qIGi1efUgGFcagyRP DXgKOyJNuCz/jitRU1Gs3o5KH1BhJR+K0f4wwI8afTUsaGXVRrxVFutM8EUpYxLIJ3bv 6QuQ== X-Gm-Message-State: AOAM532iJV1nKiaif/LHvhIEWoQQ5rtXN8RqFtRYuulzjuCQ6Nikrtfr B1rKEHVZcpQAI4ke3TjMc6j1GQ== X-Google-Smtp-Source: ABdhPJwMOaXURcIM7Hz6a2IkaKB8mAu5cSQEgKWbKie6fQH5GaTmEZzS/nEgTIFbX+Af76CM+jxoyA== X-Received: by 2002:a19:c94:: with SMTP id 142mr1445563lfm.284.1607005270838; Thu, 03 Dec 2020 06:21:10 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.117]) by smtp.gmail.com with ESMTPSA id k185sm575716lfd.294.2020.12.03.06.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 06:21:10 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Date: Thu, 3 Dec 2020 17:20:59 +0300 Message-Id: <20201203142105.841666-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> References: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree nodes for mdss, mdp, dsi0/1. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 302 ++++++++++++++++++++++++++- 1 file changed, 295 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..f4cae2b82e2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 { }; gpu: gpu@3d00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ compatible = "qcom,adreno-650.2", - "qcom,adreno", - "amd,imageon"; + "qcom,adreno"; #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; @@ -1803,6 +1799,298 @@ usb_2_dwc3: dwc3@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, + <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <460000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8250-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "dptx2_phy_pll_link_clk", + "dptx2_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; From patchwork Thu Dec 3 14:21:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 336937 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp332737ilb; Thu, 3 Dec 2020 06:23:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJzsKnf2yDSJWuf3Qy0edJ2gvtf9nCDa/atp9SYiAmp26VzygxXBGrA7xxukT9mM2i3750Ib X-Received: by 2002:a17:906:1b04:: with SMTP id o4mr2717228ejg.531.1607005403011; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index ce9d98e2d856..22c1953f4e63 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -430,6 +430,13 @@ &dsi0_phy { vdds-supply = <&vreg_l5a_0p88>; }; +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sm8250/a650_zap.mbn"; + }; +}; + /* LS-I2C0 */ &i2c4 { status = "okay"; From patchwork Thu Dec 3 14:21:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 336938 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp332758ilb; Thu, 3 Dec 2020 06:23:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJwkMVu4ZV/6QoPaAXtQOIWB5rtToyw1+m22KN0HOtcJwoXeo06wEqEpoo8Ib4PrtwaFFgFK X-Received: by 2002:a17:906:7d91:: with SMTP id v17mr2791424ejo.522.1607005404599; Thu, 03 Dec 2020 06:23:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607005404; cv=none; d=google.com; s=arc-20160816; b=WU44hUXNwZ4cA5m7s5UKJfUNkjXS/kI4jdQzZ7cprT5dIfzi4bd6sI+pffgTPh17FG RhH0o7hFhlfzqlPHrqiWnkQuSEnDM5asPMW6/Od7fpEuDYfmUL8PIzsmN/Jtv9rtvwj8 Z19jHTPIxM9TcViSN/SgqWL6FPZ6b3GT7zR5s71aYzzowi7o4wSS95pdDF5GgrcOkylA sVHu75TNyOzCgDraF919dsPRMn6uEcOwuG5EAqQXWwWZ1/yemsTEVQDq+7KroUTezP1F kDsQYNvmrp5xz6KVPhGO0r5bBnzBaMDuqhlTDKgfkfO1GJ/q2UCBqBDuKAzicVqTDRI6 HfQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fC2x1NrmgFex/ZuI50LsbjTePisKBDjpo1XKmPIWh2s=; b=f+nlqkNlqH4QECjNu2JV0ep1v6nVesqFMqMK1nlbzvLa3TidAbOqlJeDlK+9X+HKRy AxHpolHq980GbN3esfMXgrV7lL9VHFzNVPLIef/nfVklWYtQ+DogQiQ9zZHC8YmdBO4I 403Ta3Ow/kcwXy+Ea/jqrkHP66xlyCNtk0raYENCclcDvt7RUp/DWjNcrLXY1k3buAu4 +YuhNxS4YUXbbROMFAUNmQOEIpC5pwmdVmoiDNtE1YfS4C5bZtRwLFBWI7s6xH9QWTwK 2uqEUqmCvbCtE2fQ5JJpX+cwmINpDo/8M0r/F86im6cnYoNy+qnOhonUKNXXex168Qcl 0NhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FLRFO2A+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index dea00f19711d..865b6b587843 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -358,6 +358,13 @@ &cdsp { firmware-name = "qcom/sm8250/cdsp.mbn"; }; +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sm8250/a650_zap.mbn"; + }; +}; + &i2c1 { status = "okay"; clock-frequency = <1000000>; From patchwork Thu Dec 3 14:21:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 336939 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp332796ilb; Thu, 3 Dec 2020 06:23:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJxMztC8ham+Vz45lYgj0BVB0Lt7djKwW4XVAOUaS6Q7DaG3Zb7jPpV/+Ar8Uh/EN5xV3LZC X-Received: by 2002:a50:c19a:: with SMTP id m26mr3035632edf.302.1607005406875; Thu, 03 Dec 2020 06:23:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607005406; cv=none; d=google.com; s=arc-20160816; b=w39cGTvxVMFdG5797TwO5HS1UQ/Qovfu1lQD0+Yy7qDmLhjtO56dVn6HTNJ3wAEKN5 mlse30YqcKm9/qy3dVFeGu67Z1qkFvK/RS+ispC31H9C6sb3+SqmIMfe0oWfDUjLYdG4 rW0xinxCdQO79rDZCR+z2ikK1ptUZRKa+agHfIS8Bp47Z7OLgQ1u0ghTv1ApEoIv6rrB xo64JGYwhSO0kobRYbasB4GE4rgAN/y0v3ySrQRy63O6yMpQDdPHR9cFGEF+fNc7pXHo gdvwjruCdoRvYCTQpSaxrLvV+hlzBg4g9nOlsOGss/xej/0hGgDPNjxJskgUH+QPjPol 3g2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KcRu/X3xJaaLM+ngoS1QVEM2mbS7z453C1cW9cVO+24=; b=l7tjBNlAH86hDxSj63gQ/Cvly23b/l+9irIFk2W54Rc1n96rxUiBXYhF5cmV1tWpaW nkNB3UV8diReHJLE6e5/Vmh3gsPAAnD2NkCSSMpokzXRZSCjpBokjtSm5Qwqxi5kdjML HMyZpQsafId3Nd1MZlF5mQLZWCANOmfiee7tryPTuG51hMAW+HTBAhwgkB+YrDFUZ0EB 0gdf1oLBGx68ZRMFQ3dxnLtw8JBq+Px/1pBcdJpOuwvI8xB0LUyOtvISuoYhycD0D9WI CsKSj5MqHb9gy+o5Xre40sgkDUNf9JKz7rIDraJ91L+XXg9rZ2Kx6mhgXxM0VXlV9kRW Wgjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jxALDj5S; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 97 +++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 94d95dff48c4..1ade62d98f98 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -40,6 +40,17 @@ dc12v: dc12v-regulator { regulator-always-on; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -66,6 +77,26 @@ bt { }; + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + lt9611_3v3: lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -418,7 +449,7 @@ &dsi0 { ports { port@1 { endpoint { - //remote-endpoint = <<9611_a>; + remote-endpoint = <<9611_a>; data-lanes = <0 1 2 3>; }; }; @@ -444,6 +475,55 @@ &i2c4 { &i2c5 { status = "okay"; + clock-frequency = <400000>; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + +#if 0 + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; +#endif + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + }; + }; }; /* LS-I2C1 */ @@ -504,6 +584,15 @@ &pm8150l_gpios { "PM_GPIO-B", "NC", "PM3003A_MODE"; + + lt9611_rst_pin: lt9611-rst-pin { + pins = "gpio5"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; }; &pm8150_rtc { @@ -735,6 +824,12 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + lt9611_irq_pin: lt9611-irq { + pins = "gpio63"; + function = "gpio"; + bias-disable; + }; + sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; From patchwork Thu Dec 3 14:21:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 336941 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp332850ilb; Thu, 3 Dec 2020 06:23:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJxAMTRk5Z0YbYEGLNyoB93lJPTuwMOjqI/siHaL8hLLojkPigkUm/eGgNlyR4eP/ZMuTpU4 X-Received: by 2002:a05:6402:1c9b:: with SMTP id cy27mr2998222edb.253.1607005409631; Thu, 03 Dec 2020 06:23:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607005409; cv=none; d=google.com; s=arc-20160816; b=ZlLytQ5WP9VL5NIlm3yRhlevmOQdZfRKjDNwhUvbnT5YHuYE/hsmHMNsxPyCM+izid hTlH6PcaguZZM+IR8jwlZJDj2yggvjC9m2BVA29qQoZXNyK3lMFEsbOScydHESWxY2HK sngPANmk7tXwqC2HIrO4eseFynYtEHD8psddKeEuci1YqPgqyTN9MCifG4vSxoFgUt6y 5K3arUli3GMaFlFczDw9Ve0aLR5V8KSBpPZ9rORjhxVLyNtfQ6X3eILs9D0eg+L2SCwv cFt372HQlnDotWxZ7i/f0dbBBnIFIO+C8Ow7QD5qDfJMxcfwWROyhlCl2m+rF0EBKe+s C5Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kW9Z+5MdERH4UOzelJv9hwVH2KR54qJRrBP7D3NwCS0=; b=XefqCxS+9qiEda8rG9IcTaAUHF0RnMys0YIhg6k+vBRqdvh0B+Irz910K2JhpZl7pr YdkiKJG0HSF6ZKBDqqmhBIilSeb23KvBgCQT5607eExCWqmPEgpFAwuFRJU/emwUmSRN hOawOHl0FGeaxF7HxUVamKhnQKRXi27WTJJJFAKR9IzFQJgx4lkNgPNq0lDym3QgHVz9 3y5Zo70aUnVMteB24ghouNCH1VOD5m3NBw06xvR6mmmgXVC/4ThnXwCr+GiI8CgfyW7P SyfPkh9ySYJ051Vc6ILjeN0ltLa8BybvZHBJiSDJfFNbUxl/pE+mKkytZpFbIEVmc2nC gvBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eKJI8a9D; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f4cae2b82e2a..0c7986bf60d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -216,6 +216,13 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + mmcx_reg: mmcx-reg { + compatible = "regulator-fixed-domain"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + regulator-name = "MMCX"; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2058,6 +2065,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x20000>; + mmcx-supply = <&mmcx_reg>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>,