From patchwork Fri Dec 4 20:32:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 337866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BECAC433FE for ; Fri, 4 Dec 2020 20:49:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB69E22CF6 for ; Fri, 4 Dec 2020 20:49:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730332AbgLDUtp (ORCPT ); Fri, 4 Dec 2020 15:49:45 -0500 Received: from mickerik.phytec.de ([195.145.39.210]:56224 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730241AbgLDUtm (ORCPT ); Fri, 4 Dec 2020 15:49:42 -0500 X-Greylist: delayed 941 seconds by postgrey-1.27 at vger.kernel.org; Fri, 04 Dec 2020 15:49:25 EST DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1607113983; x=1609705983; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=c5KOTTMHIHJYediZAqawgmWmdRhYpqG2gVgOgM7+P+g=; b=EG7XJYMxa7wnjI46AesWZf05oSssGeeefGw24bB6hMi2m7746/w7szFDYQYWccon hq4298LcYJAK+ZXPAVsf8FHr30xFnDG+UnMfM9DqDdPOLyjyi1MLfMIcn7U3HLNJ HZdm86xiIFks+8/twMh6oDQw2Q8RnCe9IRT0b63FiKs=; X-AuditID: c39127d2-981ff70000006435-71-5fca9cff8978 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 63.74.25653.FFC9ACF5; Fri, 4 Dec 2020 21:33:03 +0100 (CET) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020120421330292-920466 ; Fri, 4 Dec 2020 21:33:02 +0100 From: Teresa Remmet To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [PATCH 1/4] arm64: defconfig: Enable rv3028 i2c rtc driver Date: Fri, 4 Dec 2020 21:32:59 +0100 Message-Id: <1607113982-109524-2-git-send-email-t.remmet@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> References: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize complete at 04.12.2020 21:33:03 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprELMWRmVeSWpSXmKPExsWyRoCBS/f/nFPxBjPeclu8X9bDaDH/yDlW i4dX/S02Pb7GatG69wi7xd/tm1gsXmwRd2D3WDNvDaPHzll32T02repk89i8pN6j/6+Bx+dN cgFsUVw2Kak5mWWpRfp2CVwZ0yb/YSn4xlKxbM4m5gbGJSxdjJwcEgImEj+6JzN2MXJxCAls ZZR49HIhC4RzjlHixtLvbCBVbAIaEk9XnGYCsUUEXCQ6H6wDK2IW2M0osefzOlaQhLCAs8T+ BU/BilgEVCT2Xj3BDGLzAsVv7pvNDLFOTuLmuU4wmxNo0PF73xhBbCGgmv+rv4MNlRBoZJI4 sWkvG0SDkMTpxWeZJzDyLWBkWMUolJuZnJ1alJmtV5BRWZKarJeSuokRGG6HJ6pf2sHYN8fj ECMTB+MhRgkOZiUR3ljVk/FCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeTfwloQJCaQnlqRmp6YW pBbBZJk4OKUaGHuDvyc6Xv4kkvBu0S03XluFHRayfM55Mm/vqTJq7jos8KIgo22/6c/AKyLq xarrVzyL2S595Gnp7CuLNi1KbOLZY7bwWVcDz32B5P1WchxvJ1T+fHbeViggNnTChCKJma6s kTvknkkmZgsq3zIIWj3NKXrjowrme/bH/599ufvdgpPbpZutpyqxFGckGmoxFxUnAgBI5kp+ JQIAAA== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable rv3028 i2c rtc driver populated on phyBOARD-Pollux-i.MX8M Plus. Signed-off-by: Teresa Remmet --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5cfe3cf6f2ac..2034fefb3f44 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -818,6 +818,7 @@ CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RV3028=y CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_DS3232=y From patchwork Fri Dec 4 20:33:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 338482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99207C4167B for ; Fri, 4 Dec 2020 20:50:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5750522CF7 for ; Fri, 4 Dec 2020 20:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387751AbgLDUuA (ORCPT ); Fri, 4 Dec 2020 15:50:00 -0500 Received: from mickerik.phytec.de ([195.145.39.210]:56224 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387533AbgLDUuA (ORCPT ); Fri, 4 Dec 2020 15:50:00 -0500 X-Greylist: delayed 941 seconds by postgrey-1.27 at vger.kernel.org; Fri, 04 Dec 2020 15:49:25 EST DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1607113983; x=1609705983; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=z8BRVrkebhW2w2n75AvXMmalfkQgGNF/lWpRdfTsBZo=; b=gKZLBLpI3O+NACPAx5qFD63cg6fmCJA/h5QMyV7xyLYmVtD8FADetWDIGc03mNDr bowaH9YAgc+3Hd3R/z5HnP+crcE0U1GBKMf0MsBPQ+JbBtzwveuh/MvflybEFSWl W+DNOLXu/ryAHpWzkwgUqjWpz2sabuqlIK9mvtH6iAM=; X-AuditID: c39127d2-96bff70000006435-72-5fca9cfffdc4 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id E3.74.25653.FFC9ACF5; Fri, 4 Dec 2020 21:33:03 +0100 (CET) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020120421330317-920467 ; Fri, 4 Dec 2020 21:33:03 +0100 From: Teresa Remmet To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [PATCH 2/4] arm64: defconfig: Enable PCA9532 support Date: Fri, 4 Dec 2020 21:33:00 +0100 Message-Id: <1607113982-109524-3-git-send-email-t.remmet@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> References: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize complete at 04.12.2020 21:33:03 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprILMWRmVeSWpSXmKPExsWyRoCBS/f/nFPxBgu3KVu8X9bDaDH/yDlW i4dX/S02Pb7GatG69wi7xd/tm1gsXmwRd2D3WDNvDaPHzll32T02repk89i8pN6j/6+Bx+dN cgFsUVw2Kak5mWWpRfp2CVwZW6ZfZyt4yVKx8+lK9gbGKSxdjJwcEgImElunfGDvYuTiEBLY yigxZfFBFgjnHKNE68VD7CBVbAIaEk9XnGYCsUUEXCQ6H6wDK2IW2M0osefzOlaQhLCArcTU ieeZuxg5OFgEVCSePBMBCfMKOEu8e9HIDLFNTuLmuU4wmxNozvF73xhBbCGgmv+rv4PNlBBo ZJI4sWkvG0SDkMTpxWeZJzDyLWBkWMUolJuZnJ1alJmtV5BRWZKarJeSuokRGGyHJ6pf2sHY N8fjECMTB+MhRgkOZiUR3ljVk/FCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeTfwloQJCaQnlqRm p6YWpBbBZJk4OKUaGN2M7DXerxfv97sX6RIUv/v5Co/MzgWeiVsWdiovnXz9qPl39ePLzzia rUzefERh3d4c5dRerZX8oRV1+ecWSn+eVNSZ+S+f9eLp/ujFiU8DT1em6L45rF1dFhh2ilP7 TKbuJ6bGs+vuTeLRKN8b9i+5OjmX298nwjm9/aXb8sc8D/foNEvtVmIpzkg01GIuKk4EAK5x 2N0kAgAA Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable i2c led expander PCA9532 module support populated on phyBOARD-Pollux-i.MX8M Plus. Signed-off-by: Teresa Remmet Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2034fefb3f44..14b0a83d8d3f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -801,6 +801,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_PCA9532=m CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y From patchwork Fri Dec 4 20:33:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 337865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9B20C0018C for ; Fri, 4 Dec 2020 20:50:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A7C0A22CF7 for ; Fri, 4 Dec 2020 20:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388019AbgLDUuQ (ORCPT ); Fri, 4 Dec 2020 15:50:16 -0500 Received: from mickerik.phytec.de ([195.145.39.210]:56224 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387781AbgLDUuQ (ORCPT ); Fri, 4 Dec 2020 15:50:16 -0500 X-Greylist: delayed 941 seconds by postgrey-1.27 at vger.kernel.org; Fri, 04 Dec 2020 15:49:25 EST DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1607113983; x=1609705983; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=Og/b+KuaiCrFr7z7+ktku+KZgIrWu02KxpK97xIRG4g=; b=HVE5sBZsgli8ddDE7pOA2wNbDKXdIp6b9ErZuOWyD+AbgnYHWaqR81g7xDwmys4U 9iMys2Iaw0eTrIhttT8b+H+lJmwf3/9/oIfnQRa9RF3S7ZwoZX1cYIM/BeGOTOYK 0Y1u3or7t4k5QDM3kUqP/bSPwF3qgqa4iBpEAVpQS1s=; X-AuditID: c39127d2-981ff70000006435-73-5fca9cff7579 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 64.74.25653.FFC9ACF5; Fri, 4 Dec 2020 21:33:03 +0100 (CET) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020120421330345-920468 ; Fri, 4 Dec 2020 21:33:03 +0100 From: Teresa Remmet To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [PATCH 3/4] bindings: arm: fsl: Add PHYTEC i.MX8MP devicetree bindings Date: Fri, 4 Dec 2020 21:33:01 +0100 Message-Id: <1607113982-109524-4-git-send-email-t.remmet@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> References: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize complete at 04.12.2020 21:33:03 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprELMWRmVeSWpSXmKPExsWyRoCBS/f/nFPxBrM26Vm8X9bDaDH/yDlW i4dX/S02Pb7GatG69wi7xd/tm1gsXmwRd2D3WDNvDaPHzll32T02repk89i8pN6j/6+Bx+dN cgFsUVw2Kak5mWWpRfp2CVwZv1o3MxZ8Yq9YcPssUwPjF9YuRk4OCQETif+z9rN0MXJxCAls ZZR4/e8dO4RzjlHiwMzJYFVsAhoST1ecZgKxRQRcJDofrAPrYBbYzSix5/M6sCJhAX+JG9+v gNksAioSza2dYA28As4Sk2+shlonJ3HzXCcziM0JNOj4vW+MILYQUM3/1d/BhkoINDJJnNi0 lw2iQUji9OKzzBMY+RYwMqxiFMrNTM5OLcrM1ivIqCxJTdZLSd3ECAy3wxPVL+1g7JvjcYiR iYPxEKMEB7OSCG+s6sl4Id6UxMqq1KL8+KLSnNTiQ4zSHCxK4rwbeEvChATSE0tSs1NTC1KL YLJMHJxSDYwbDk31fS6wwUSqdruIdYDDVqfaPz1+Rt+dXznIiDNkf//daDy3+UXNtIRaC7P7 u15aN988KZD6kCt0/bX/H8VlKi782/ErX8Ot+cTX2UJWMz0CJ+889MrF4Yul0qvbTluUtfO+ M/6qbb1UKBXfdIKJU2oyY/l3ztr8s/tmn/yZmZj6rm9XK6MSS3FGoqEWc1FxIgDI2SH5JQIA AA== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree bindings for i.MX8MP based phyCORE-i.MX8MP and phyBOARD-Pollux RDK. Signed-off-by: Teresa Remmet --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 934289446abb..880d93092f37 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -433,6 +433,13 @@ properties: - fsl,imx8mp-evk # i.MX8MP EVK Board - const: fsl,imx8mp + - description: PHYTEC phyCORE-i.MX8MP SoM based boards + items: + - enum: + - phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM + - phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK + - const: fsl,imx8mp + - description: i.MX8MQ based Boards items: - enum: From patchwork Fri Dec 4 20:33:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 338481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55768C4361A for ; Fri, 4 Dec 2020 20:50:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD32422CE3 for ; Fri, 4 Dec 2020 20:50:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388023AbgLDUue (ORCPT ); Fri, 4 Dec 2020 15:50:34 -0500 Received: from mickerik.phytec.de ([195.145.39.210]:56224 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387781AbgLDUue (ORCPT ); Fri, 4 Dec 2020 15:50:34 -0500 X-Greylist: delayed 941 seconds by postgrey-1.27 at vger.kernel.org; Fri, 04 Dec 2020 15:49:25 EST DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1607113983; x=1609705983; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=ieqoD5+0S5L1S016fJVbHNsskgDWKBYlt8VW0lha8dk=; b=kUBEhEbvNJxwsVFV2GJx1jZ6GBOgxWcKzRQ2mQZGOGRpoHxjlUn0nS6PzDYVIUZn 23PQq0Rx36tgBWS6FAWiQEpaNCtVYH1IsEyl+DbN5ncHcfzR48gOWPxR5I8yGx2V vFOroJknup3s1CRvJDkWBljxlGKV47riEFlU3Q+x//Q=; X-AuditID: c39127d2-96bff70000006435-74-5fca9cff99a7 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id E4.74.25653.FFC9ACF5; Fri, 4 Dec 2020 21:33:03 +0100 (CET) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020120421330371-920469 ; Fri, 4 Dec 2020 21:33:03 +0100 From: Teresa Remmet To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [PATCH 4/4] arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP Date: Fri, 4 Dec 2020 21:33:02 +0100 Message-Id: <1607113982-109524-5-git-send-email-t.remmet@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> References: <1607113982-109524-1-git-send-email-t.remmet@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 04.12.2020 21:33:03, Serialize complete at 04.12.2020 21:33:03 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprILMWRmVeSWpSXmKPExsWyRoCBS/f/nFPxBq/nGVu8X9bDaDH/yDlW i4dX/S02Pb7GatG69wi7xd/tm1gsXmwRd2D3WDNvDaPHzll32T02repk89i8pN6j/6+Bx+dN cgFsUVw2Kak5mWWpRfp2CVwZe693shS8Lq7YMqWJtYHxYFwXIweHhICJxJFXjl2MXBxCAlsZ Jbbf3c0C4ZxjlGj4s4Wpi5GTg01AQ+LpitNgtoiAi0Tng3VgRcwCuxkl9nxexwqSEBYIltjU 9ZUNxGYRUJF4te0LM4jNK+AsseXFKhYQW0JATuLmuU6wOCfQoOP3vjGC2EJANf9XfwcbKiHQ yCRxYtNeNogGIYnTi88yT2DkW8DIsIpRKDczOTu1KDNbryCjsiQ1WS8ldRMjMNgOT1S/tIOx b47HIUYmDsZDjBIczEoivLGqJ+OFeFMSK6tSi/Lji0pzUosPMUpzsCiJ827gLQkTEkhPLEnN Tk0tSC2CyTJxcEo1MHo6Wn1tEP4jsSttT/bjtQ9iFn6oXnVbRXCbrmX32nuKFr53XT68qJdp ljv7oS1g2hKNbwt7l/ZsmOqwWfPXYvmT8Y+u3ZRhCtMqWDKb55LoylSfbx4PZjx5c33fkcKw csPbXk/Wr8q4UCCq7eZQy6+9QeZhQ1ruf0Mbv7yd2QHWbDdl2z1XHlJiKc5INNRiLipOBADl lj7QJAIAAA== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial support for phyBOARD-Pollux-i.MX8MP. Supported basic features: * eMMC * i2c EEPROM * i2c RTC * i2c LED * PMIC * debug UART * SD card * 1Gbit Ethernet (fec) * watchdog Signed-off-by: Teresa Remmet --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 16 ++ .../boot/dts/freescale/imx8mp-phyboard-pollux.dtsi | 152 ++++++++++ .../boot/dts/freescale/imx8mp-phycore-som.dtsi | 319 +++++++++++++++++++++ 4 files changed, 488 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index acfb8af45912..a43b496678be 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts new file mode 100644 index 000000000000..dd64be32c99d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; + +#include "imx8mp-phycore-som.dtsi" +#include "imx8mp-phyboard-pollux.dtsi" + +/ { + model = "PHYTEC phyBOARD-Pollux i.MX8MP"; + compatible = "phytec,imx8mp-phyboard-pollux-rdk", + "phytec,imx8mp-phycore-som", "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux.dtsi new file mode 100644 index 000000000000..dbeaa27eb043 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + status = "okay"; + }; + + leddimmer@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + status = "okay"; + + led1 { + label = "red:user1"; + type = ; + }; + + led2 { + label = "green:user2"; + type = ; + }; + + led3 { + label = "blue:user3"; + type = ; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* debug console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_pins: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi new file mode 100644 index 000000000000..e1fdfebd8142 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include +#include "imx8mp.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX8MP"; + compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + rtcclkout: rv3028-clkout { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rv3028-clkout"; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +/* ethernet 1 */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,clk-output-sel = ; + enet-phy-lane-no-swap; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + buck1: BUCK1 { + reg = <0>; + regulator-compatible = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + reg = <1>; + regulator-compatible = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + reg = <3>; + regulator-compatible = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + reg = <4>; + regulator-compatible = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + reg = <5>; + regulator-compatible = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + reg = <6>; + regulator-compatible = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + reg = <7>; + regulator-compatible = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + reg = <8>; + regulator-compatible = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + reg = <9>; + regulator-compatible = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + reg = <10>; + regulator-compatible = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + status = "okay"; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + trickle-resistor-ohms = <1000>; + enable-level-switching-mode; + clocks = <&rtcclkout>; + status = "okay"; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 + >; + }; + + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +};